1 // SPDX-License-Identifier: GPL-2.0-or-later 2 /* 3 * Driver for sunxi SD/MMC host controllers 4 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 5 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 6 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 7 * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 8 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 9 * (C) Copyright 2017 Sootech SA 10 */ 11 12 #include <linux/clk.h> 13 #include <linux/clk/sunxi-ng.h> 14 #include <linux/delay.h> 15 #include <linux/device.h> 16 #include <linux/dma-mapping.h> 17 #include <linux/err.h> 18 #include <linux/interrupt.h> 19 #include <linux/io.h> 20 #include <linux/kernel.h> 21 #include <linux/mmc/card.h> 22 #include <linux/mmc/core.h> 23 #include <linux/mmc/host.h> 24 #include <linux/mmc/mmc.h> 25 #include <linux/mmc/sd.h> 26 #include <linux/mmc/sdio.h> 27 #include <linux/mmc/slot-gpio.h> 28 #include <linux/module.h> 29 #include <linux/mod_devicetable.h> 30 #include <linux/of_address.h> 31 #include <linux/of_platform.h> 32 #include <linux/platform_device.h> 33 #include <linux/pm_runtime.h> 34 #include <linux/regulator/consumer.h> 35 #include <linux/reset.h> 36 #include <linux/scatterlist.h> 37 #include <linux/slab.h> 38 #include <linux/spinlock.h> 39 40 /* register offset definitions */ 41 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 42 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 43 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 44 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 45 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 46 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 47 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 48 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 49 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 50 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 51 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 52 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 53 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 54 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 55 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 56 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 57 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 58 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 59 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 60 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 61 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 62 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 63 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 64 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 65 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 66 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 67 #define SDXC_REG_CHDA (0x90) 68 #define SDXC_REG_CBDA (0x94) 69 70 /* New registers introduced in A64 */ 71 #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 72 #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 73 #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 74 #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 75 #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 76 77 #define mmc_readl(host, reg) \ 78 readl((host)->reg_base + SDXC_##reg) 79 #define mmc_writel(host, reg, value) \ 80 writel((value), (host)->reg_base + SDXC_##reg) 81 82 /* global control register bits */ 83 #define SDXC_SOFT_RESET BIT(0) 84 #define SDXC_FIFO_RESET BIT(1) 85 #define SDXC_DMA_RESET BIT(2) 86 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 87 #define SDXC_DMA_ENABLE_BIT BIT(5) 88 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 89 #define SDXC_POSEDGE_LATCH_DATA BIT(9) 90 #define SDXC_DDR_MODE BIT(10) 91 #define SDXC_MEMORY_ACCESS_DONE BIT(29) 92 #define SDXC_ACCESS_DONE_DIRECT BIT(30) 93 #define SDXC_ACCESS_BY_AHB BIT(31) 94 #define SDXC_ACCESS_BY_DMA (0 << 31) 95 #define SDXC_HARDWARE_RESET \ 96 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 97 98 /* clock control bits */ 99 #define SDXC_MASK_DATA0 BIT(31) 100 #define SDXC_CARD_CLOCK_ON BIT(16) 101 #define SDXC_LOW_POWER_ON BIT(17) 102 103 /* bus width */ 104 #define SDXC_WIDTH1 0 105 #define SDXC_WIDTH4 1 106 #define SDXC_WIDTH8 2 107 108 /* smc command bits */ 109 #define SDXC_RESP_EXPIRE BIT(6) 110 #define SDXC_LONG_RESPONSE BIT(7) 111 #define SDXC_CHECK_RESPONSE_CRC BIT(8) 112 #define SDXC_DATA_EXPIRE BIT(9) 113 #define SDXC_WRITE BIT(10) 114 #define SDXC_SEQUENCE_MODE BIT(11) 115 #define SDXC_SEND_AUTO_STOP BIT(12) 116 #define SDXC_WAIT_PRE_OVER BIT(13) 117 #define SDXC_STOP_ABORT_CMD BIT(14) 118 #define SDXC_SEND_INIT_SEQUENCE BIT(15) 119 #define SDXC_UPCLK_ONLY BIT(21) 120 #define SDXC_READ_CEATA_DEV BIT(22) 121 #define SDXC_CCS_EXPIRE BIT(23) 122 #define SDXC_ENABLE_BIT_BOOT BIT(24) 123 #define SDXC_ALT_BOOT_OPTIONS BIT(25) 124 #define SDXC_BOOT_ACK_EXPIRE BIT(26) 125 #define SDXC_BOOT_ABORT BIT(27) 126 #define SDXC_VOLTAGE_SWITCH BIT(28) 127 #define SDXC_USE_HOLD_REGISTER BIT(29) 128 #define SDXC_START BIT(31) 129 130 /* interrupt bits */ 131 #define SDXC_RESP_ERROR BIT(1) 132 #define SDXC_COMMAND_DONE BIT(2) 133 #define SDXC_DATA_OVER BIT(3) 134 #define SDXC_TX_DATA_REQUEST BIT(4) 135 #define SDXC_RX_DATA_REQUEST BIT(5) 136 #define SDXC_RESP_CRC_ERROR BIT(6) 137 #define SDXC_DATA_CRC_ERROR BIT(7) 138 #define SDXC_RESP_TIMEOUT BIT(8) 139 #define SDXC_DATA_TIMEOUT BIT(9) 140 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 141 #define SDXC_FIFO_RUN_ERROR BIT(11) 142 #define SDXC_HARD_WARE_LOCKED BIT(12) 143 #define SDXC_START_BIT_ERROR BIT(13) 144 #define SDXC_AUTO_COMMAND_DONE BIT(14) 145 #define SDXC_END_BIT_ERROR BIT(15) 146 #define SDXC_SDIO_INTERRUPT BIT(16) 147 #define SDXC_CARD_INSERT BIT(30) 148 #define SDXC_CARD_REMOVE BIT(31) 149 #define SDXC_INTERRUPT_ERROR_BIT \ 150 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 151 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 152 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 153 #define SDXC_INTERRUPT_DONE_BIT \ 154 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 155 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 156 157 /* status */ 158 #define SDXC_RXWL_FLAG BIT(0) 159 #define SDXC_TXWL_FLAG BIT(1) 160 #define SDXC_FIFO_EMPTY BIT(2) 161 #define SDXC_FIFO_FULL BIT(3) 162 #define SDXC_CARD_PRESENT BIT(8) 163 #define SDXC_CARD_DATA_BUSY BIT(9) 164 #define SDXC_DATA_FSM_BUSY BIT(10) 165 #define SDXC_DMA_REQUEST BIT(31) 166 #define SDXC_FIFO_SIZE 16 167 168 /* Function select */ 169 #define SDXC_CEATA_ON (0xceaa << 16) 170 #define SDXC_SEND_IRQ_RESPONSE BIT(0) 171 #define SDXC_SDIO_READ_WAIT BIT(1) 172 #define SDXC_ABORT_READ_DATA BIT(2) 173 #define SDXC_SEND_CCSD BIT(8) 174 #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 175 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 176 177 /* IDMA controller bus mod bit field */ 178 #define SDXC_IDMAC_SOFT_RESET BIT(0) 179 #define SDXC_IDMAC_FIX_BURST BIT(1) 180 #define SDXC_IDMAC_IDMA_ON BIT(7) 181 #define SDXC_IDMAC_REFETCH_DES BIT(31) 182 183 /* IDMA status bit field */ 184 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 185 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 186 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 187 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 188 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 189 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 190 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 191 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 192 #define SDXC_IDMAC_IDLE (0 << 13) 193 #define SDXC_IDMAC_SUSPEND (1 << 13) 194 #define SDXC_IDMAC_DESC_READ (2 << 13) 195 #define SDXC_IDMAC_DESC_CHECK (3 << 13) 196 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 197 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 198 #define SDXC_IDMAC_READ (6 << 13) 199 #define SDXC_IDMAC_WRITE (7 << 13) 200 #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 201 202 /* 203 * If the idma-des-size-bits of property is ie 13, bufsize bits are: 204 * Bits 0-12: buf1 size 205 * Bits 13-25: buf2 size 206 * Bits 26-31: not used 207 * Since we only ever set buf1 size, we can simply store it directly. 208 */ 209 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 210 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 211 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 212 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 213 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 214 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 215 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 216 217 #define SDXC_CLK_400K 0 218 #define SDXC_CLK_25M 1 219 #define SDXC_CLK_50M 2 220 #define SDXC_CLK_50M_DDR 3 221 #define SDXC_CLK_50M_DDR_8BIT 4 222 223 #define SDXC_2X_TIMING_MODE BIT(31) 224 225 #define SDXC_CAL_START BIT(15) 226 #define SDXC_CAL_DONE BIT(14) 227 #define SDXC_CAL_DL_SHIFT 8 228 #define SDXC_CAL_DL_SW_EN BIT(7) 229 #define SDXC_CAL_DL_SW_SHIFT 0 230 #define SDXC_CAL_DL_MASK 0x3f 231 232 #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 233 234 struct sunxi_mmc_clk_delay { 235 u32 output; 236 u32 sample; 237 }; 238 239 struct sunxi_idma_des { 240 __le32 config; 241 __le32 buf_size; 242 __le32 buf_addr_ptr1; 243 __le32 buf_addr_ptr2; 244 }; 245 246 struct sunxi_mmc_cfg { 247 u32 idma_des_size_bits; 248 u32 idma_des_shift; 249 const struct sunxi_mmc_clk_delay *clk_delays; 250 251 /* does the IP block support autocalibration? */ 252 bool can_calibrate; 253 254 /* Does DATA0 needs to be masked while the clock is updated */ 255 bool mask_data0; 256 257 /* 258 * hardware only supports new timing mode, either due to lack of 259 * a mode switch in the clock controller, or the mmc controller 260 * is permanently configured in the new timing mode, without the 261 * NTSR mode switch. 262 */ 263 bool needs_new_timings; 264 265 /* clock hardware can switch between old and new timing modes */ 266 bool ccu_has_timings_switch; 267 }; 268 269 struct sunxi_mmc_host { 270 struct device *dev; 271 struct mmc_host *mmc; 272 struct reset_control *reset; 273 const struct sunxi_mmc_cfg *cfg; 274 275 /* IO mapping base */ 276 void __iomem *reg_base; 277 278 /* clock management */ 279 struct clk *clk_ahb; 280 struct clk *clk_mmc; 281 struct clk *clk_sample; 282 struct clk *clk_output; 283 284 /* irq */ 285 spinlock_t lock; 286 int irq; 287 u32 int_sum; 288 u32 sdio_imask; 289 290 /* dma */ 291 dma_addr_t sg_dma; 292 void *sg_cpu; 293 bool wait_dma; 294 295 struct mmc_request *mrq; 296 struct mmc_request *manual_stop_mrq; 297 int ferror; 298 299 /* vqmmc */ 300 bool vqmmc_enabled; 301 302 /* timings */ 303 bool use_new_timings; 304 }; 305 306 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 307 { 308 unsigned long expire = jiffies + msecs_to_jiffies(250); 309 u32 rval; 310 311 mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 312 do { 313 rval = mmc_readl(host, REG_GCTRL); 314 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 315 316 if (rval & SDXC_HARDWARE_RESET) { 317 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 318 return -EIO; 319 } 320 321 return 0; 322 } 323 324 static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) 325 { 326 u32 rval; 327 328 if (sunxi_mmc_reset_host(host)) 329 return -EIO; 330 331 /* 332 * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 333 * 334 * TODO: sun9i has a larger FIFO and supports higher trigger values 335 */ 336 mmc_writel(host, REG_FTRGL, 0x20070008); 337 /* Maximum timeout value */ 338 mmc_writel(host, REG_TMOUT, 0xffffffff); 339 /* Unmask SDIO interrupt if needed */ 340 mmc_writel(host, REG_IMASK, host->sdio_imask); 341 /* Clear all pending interrupts */ 342 mmc_writel(host, REG_RINTR, 0xffffffff); 343 /* Debug register? undocumented */ 344 mmc_writel(host, REG_DBGC, 0xdeb); 345 /* Enable CEATA support */ 346 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 347 /* Set DMA descriptor list base address */ 348 mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift); 349 350 rval = mmc_readl(host, REG_GCTRL); 351 rval |= SDXC_INTERRUPT_ENABLE_BIT; 352 /* Undocumented, but found in Allwinner code */ 353 rval &= ~SDXC_ACCESS_DONE_DIRECT; 354 mmc_writel(host, REG_GCTRL, rval); 355 356 return 0; 357 } 358 359 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 360 struct mmc_data *data) 361 { 362 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 363 dma_addr_t next_desc = host->sg_dma; 364 int i, max_len = (1 << host->cfg->idma_des_size_bits); 365 366 for (i = 0; i < data->sg_len; i++) { 367 pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 368 SDXC_IDMAC_DES0_OWN | 369 SDXC_IDMAC_DES0_DIC); 370 371 if (data->sg[i].length == max_len) 372 pdes[i].buf_size = 0; /* 0 == max_len */ 373 else 374 pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 375 376 next_desc += sizeof(struct sunxi_idma_des); 377 pdes[i].buf_addr_ptr1 = 378 cpu_to_le32(sg_dma_address(&data->sg[i]) >> 379 host->cfg->idma_des_shift); 380 pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc >> 381 host->cfg->idma_des_shift); 382 } 383 384 pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 385 pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 386 SDXC_IDMAC_DES0_ER); 387 pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 388 pdes[i - 1].buf_addr_ptr2 = 0; 389 390 /* 391 * Avoid the io-store starting the idmac hitting io-mem before the 392 * descriptors hit the main-mem. 393 */ 394 wmb(); 395 } 396 397 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 398 struct mmc_data *data) 399 { 400 u32 i, dma_len; 401 struct scatterlist *sg; 402 403 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 404 mmc_get_dma_dir(data)); 405 if (dma_len == 0) { 406 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 407 return -ENOMEM; 408 } 409 410 for_each_sg(data->sg, sg, data->sg_len, i) { 411 if (sg->offset & 3 || sg->length & 3) { 412 dev_err(mmc_dev(host->mmc), 413 "unaligned scatterlist: os %x length %d\n", 414 sg->offset, sg->length); 415 return -EINVAL; 416 } 417 } 418 419 return 0; 420 } 421 422 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 423 struct mmc_data *data) 424 { 425 u32 rval; 426 427 sunxi_mmc_init_idma_des(host, data); 428 429 rval = mmc_readl(host, REG_GCTRL); 430 rval |= SDXC_DMA_ENABLE_BIT; 431 mmc_writel(host, REG_GCTRL, rval); 432 rval |= SDXC_DMA_RESET; 433 mmc_writel(host, REG_GCTRL, rval); 434 435 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 436 437 if (!(data->flags & MMC_DATA_WRITE)) 438 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 439 440 mmc_writel(host, REG_DMAC, 441 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 442 } 443 444 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 445 struct mmc_request *req) 446 { 447 u32 arg, cmd_val, ri; 448 unsigned long expire = jiffies + msecs_to_jiffies(1000); 449 450 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 451 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 452 453 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 454 cmd_val |= SD_IO_RW_DIRECT; 455 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 456 ((req->cmd->arg >> 28) & 0x7); 457 } else { 458 cmd_val |= MMC_STOP_TRANSMISSION; 459 arg = 0; 460 } 461 462 mmc_writel(host, REG_CARG, arg); 463 mmc_writel(host, REG_CMDR, cmd_val); 464 465 do { 466 ri = mmc_readl(host, REG_RINTR); 467 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 468 time_before(jiffies, expire)); 469 470 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 471 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 472 if (req->stop) 473 req->stop->resp[0] = -ETIMEDOUT; 474 } else { 475 if (req->stop) 476 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 477 } 478 479 mmc_writel(host, REG_RINTR, 0xffff); 480 } 481 482 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 483 { 484 struct mmc_command *cmd = host->mrq->cmd; 485 struct mmc_data *data = host->mrq->data; 486 487 /* For some cmds timeout is normal with sd/mmc cards */ 488 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 489 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 490 cmd->opcode == SD_IO_RW_DIRECT)) 491 return; 492 493 dev_dbg(mmc_dev(host->mmc), 494 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 495 host->mmc->index, cmd->opcode, 496 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 497 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 498 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 499 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 500 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 501 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 502 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 503 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 504 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 505 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 506 ); 507 } 508 509 /* Called in interrupt context! */ 510 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 511 { 512 struct mmc_request *mrq = host->mrq; 513 struct mmc_data *data = mrq->data; 514 u32 rval; 515 516 mmc_writel(host, REG_IMASK, host->sdio_imask); 517 mmc_writel(host, REG_IDIE, 0); 518 519 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 520 sunxi_mmc_dump_errinfo(host); 521 mrq->cmd->error = -ETIMEDOUT; 522 523 if (data) { 524 data->error = -ETIMEDOUT; 525 host->manual_stop_mrq = mrq; 526 } 527 528 if (mrq->stop) 529 mrq->stop->error = -ETIMEDOUT; 530 } else { 531 if (mrq->cmd->flags & MMC_RSP_136) { 532 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 533 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 534 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 535 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 536 } else { 537 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 538 } 539 540 if (data) 541 data->bytes_xfered = data->blocks * data->blksz; 542 } 543 544 if (data) { 545 mmc_writel(host, REG_IDST, 0x337); 546 mmc_writel(host, REG_DMAC, 0); 547 rval = mmc_readl(host, REG_GCTRL); 548 rval |= SDXC_DMA_RESET; 549 mmc_writel(host, REG_GCTRL, rval); 550 rval &= ~SDXC_DMA_ENABLE_BIT; 551 mmc_writel(host, REG_GCTRL, rval); 552 rval |= SDXC_FIFO_RESET; 553 mmc_writel(host, REG_GCTRL, rval); 554 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 555 mmc_get_dma_dir(data)); 556 } 557 558 mmc_writel(host, REG_RINTR, 0xffff); 559 560 host->mrq = NULL; 561 host->int_sum = 0; 562 host->wait_dma = false; 563 564 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 565 } 566 567 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 568 { 569 struct sunxi_mmc_host *host = dev_id; 570 struct mmc_request *mrq; 571 u32 msk_int, idma_int; 572 bool finalize = false; 573 bool sdio_int = false; 574 irqreturn_t ret = IRQ_HANDLED; 575 576 spin_lock(&host->lock); 577 578 idma_int = mmc_readl(host, REG_IDST); 579 msk_int = mmc_readl(host, REG_MISTA); 580 581 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 582 host->mrq, msk_int, idma_int); 583 584 mrq = host->mrq; 585 if (mrq) { 586 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 587 host->wait_dma = false; 588 589 host->int_sum |= msk_int; 590 591 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 592 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 593 !(host->int_sum & SDXC_COMMAND_DONE)) 594 mmc_writel(host, REG_IMASK, 595 host->sdio_imask | SDXC_COMMAND_DONE); 596 /* Don't wait for dma on error */ 597 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 598 finalize = true; 599 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 600 !host->wait_dma) 601 finalize = true; 602 } 603 604 if (msk_int & SDXC_SDIO_INTERRUPT) 605 sdio_int = true; 606 607 mmc_writel(host, REG_RINTR, msk_int); 608 mmc_writel(host, REG_IDST, idma_int); 609 610 if (finalize) 611 ret = sunxi_mmc_finalize_request(host); 612 613 spin_unlock(&host->lock); 614 615 if (finalize && ret == IRQ_HANDLED) 616 mmc_request_done(host->mmc, mrq); 617 618 if (sdio_int) 619 mmc_signal_sdio_irq(host->mmc); 620 621 return ret; 622 } 623 624 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 625 { 626 struct sunxi_mmc_host *host = dev_id; 627 struct mmc_request *mrq; 628 unsigned long iflags; 629 630 spin_lock_irqsave(&host->lock, iflags); 631 mrq = host->manual_stop_mrq; 632 spin_unlock_irqrestore(&host->lock, iflags); 633 634 if (!mrq) { 635 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 636 return IRQ_HANDLED; 637 } 638 639 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 640 641 /* 642 * We will never have more than one outstanding request, 643 * and we do not complete the request until after 644 * we've cleared host->manual_stop_mrq so we do not need to 645 * spin lock this function. 646 * Additionally we have wait states within this function 647 * so having it in a lock is a very bad idea. 648 */ 649 sunxi_mmc_send_manual_stop(host, mrq); 650 651 spin_lock_irqsave(&host->lock, iflags); 652 host->manual_stop_mrq = NULL; 653 spin_unlock_irqrestore(&host->lock, iflags); 654 655 mmc_request_done(host->mmc, mrq); 656 657 return IRQ_HANDLED; 658 } 659 660 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 661 { 662 unsigned long expire = jiffies + msecs_to_jiffies(750); 663 u32 rval; 664 665 dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 666 oclk_en ? "en" : "dis"); 667 668 rval = mmc_readl(host, REG_CLKCR); 669 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 670 671 if (oclk_en) 672 rval |= SDXC_CARD_CLOCK_ON; 673 if (host->cfg->mask_data0) 674 rval |= SDXC_MASK_DATA0; 675 676 mmc_writel(host, REG_CLKCR, rval); 677 678 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 679 mmc_writel(host, REG_CMDR, rval); 680 681 do { 682 rval = mmc_readl(host, REG_CMDR); 683 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 684 685 /* clear irq status bits set by the command */ 686 mmc_writel(host, REG_RINTR, 687 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 688 689 if (rval & SDXC_START) { 690 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 691 return -EIO; 692 } 693 694 if (host->cfg->mask_data0) { 695 rval = mmc_readl(host, REG_CLKCR); 696 mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 697 } 698 699 return 0; 700 } 701 702 static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 703 { 704 if (!host->cfg->can_calibrate) 705 return 0; 706 707 /* 708 * FIXME: 709 * This is not clear how the calibration is supposed to work 710 * yet. The best rate have been obtained by simply setting the 711 * delay to 0, as Allwinner does in its BSP. 712 * 713 * The only mode that doesn't have such a delay is HS400, that 714 * is in itself a TODO. 715 */ 716 writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 717 718 return 0; 719 } 720 721 static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 722 struct mmc_ios *ios, u32 rate) 723 { 724 int index; 725 726 /* clk controller delays not used under new timings mode */ 727 if (host->use_new_timings) 728 return 0; 729 730 /* some old controllers don't support delays */ 731 if (!host->cfg->clk_delays) 732 return 0; 733 734 /* determine delays */ 735 if (rate <= 400000) { 736 index = SDXC_CLK_400K; 737 } else if (rate <= 25000000) { 738 index = SDXC_CLK_25M; 739 } else if (rate <= 52000000) { 740 if (ios->timing != MMC_TIMING_UHS_DDR50 && 741 ios->timing != MMC_TIMING_MMC_DDR52) { 742 index = SDXC_CLK_50M; 743 } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 744 index = SDXC_CLK_50M_DDR_8BIT; 745 } else { 746 index = SDXC_CLK_50M_DDR; 747 } 748 } else { 749 dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 750 return -EINVAL; 751 } 752 753 clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 754 clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 755 756 return 0; 757 } 758 759 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 760 struct mmc_ios *ios) 761 { 762 struct mmc_host *mmc = host->mmc; 763 long rate; 764 u32 rval, clock = ios->clock, div = 1; 765 int ret; 766 767 ret = sunxi_mmc_oclk_onoff(host, 0); 768 if (ret) 769 return ret; 770 771 /* Our clock is gated now */ 772 mmc->actual_clock = 0; 773 774 if (!ios->clock) 775 return 0; 776 777 /* 778 * Under the old timing mode, 8 bit DDR requires the module 779 * clock to be double the card clock. Under the new timing 780 * mode, all DDR modes require a doubled module clock. 781 * 782 * We currently only support the standard MMC DDR52 mode. 783 * This block should be updated once support for other DDR 784 * modes is added. 785 */ 786 if (ios->timing == MMC_TIMING_MMC_DDR52 && 787 (host->use_new_timings || 788 ios->bus_width == MMC_BUS_WIDTH_8)) { 789 div = 2; 790 clock <<= 1; 791 } 792 793 if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { 794 ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 795 if (ret) { 796 dev_err(mmc_dev(mmc), 797 "error setting new timing mode\n"); 798 return ret; 799 } 800 } 801 802 rate = clk_round_rate(host->clk_mmc, clock); 803 if (rate < 0) { 804 dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 805 clock, rate); 806 return rate; 807 } 808 dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 809 clock, rate); 810 811 /* setting clock rate */ 812 ret = clk_set_rate(host->clk_mmc, rate); 813 if (ret) { 814 dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 815 rate, ret); 816 return ret; 817 } 818 819 /* set internal divider */ 820 rval = mmc_readl(host, REG_CLKCR); 821 rval &= ~0xff; 822 rval |= div - 1; 823 mmc_writel(host, REG_CLKCR, rval); 824 825 /* update card clock rate to account for internal divider */ 826 rate /= div; 827 828 /* 829 * Configure the controller to use the new timing mode if needed. 830 * On controllers that only support the new timing mode, such as 831 * the eMMC controller on the A64, this register does not exist, 832 * and any writes to it are ignored. 833 */ 834 if (host->use_new_timings) { 835 /* Don't touch the delay bits */ 836 rval = mmc_readl(host, REG_SD_NTSR); 837 rval |= SDXC_2X_TIMING_MODE; 838 mmc_writel(host, REG_SD_NTSR, rval); 839 } 840 841 /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 842 ret = sunxi_mmc_clk_set_phase(host, ios, rate); 843 if (ret) 844 return ret; 845 846 ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 847 if (ret) 848 return ret; 849 850 /* 851 * FIXME: 852 * 853 * In HS400 we'll also need to calibrate the data strobe 854 * signal. This should only happen on the MMC2 controller (at 855 * least on the A64). 856 */ 857 858 ret = sunxi_mmc_oclk_onoff(host, 1); 859 if (ret) 860 return ret; 861 862 /* And we just enabled our clock back */ 863 mmc->actual_clock = rate; 864 865 return 0; 866 } 867 868 static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, 869 unsigned char width) 870 { 871 switch (width) { 872 case MMC_BUS_WIDTH_1: 873 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 874 break; 875 case MMC_BUS_WIDTH_4: 876 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 877 break; 878 case MMC_BUS_WIDTH_8: 879 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 880 break; 881 } 882 } 883 884 static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) 885 { 886 u32 rval; 887 888 /* set ddr mode */ 889 rval = mmc_readl(host, REG_GCTRL); 890 if (ios->timing == MMC_TIMING_UHS_DDR50 || 891 ios->timing == MMC_TIMING_MMC_DDR52) 892 rval |= SDXC_DDR_MODE; 893 else 894 rval &= ~SDXC_DDR_MODE; 895 mmc_writel(host, REG_GCTRL, rval); 896 897 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 898 /* Android code had a usleep_range(50000, 55000); here */ 899 } 900 901 static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, 902 struct mmc_ios *ios) 903 { 904 struct mmc_host *mmc = host->mmc; 905 906 switch (ios->power_mode) { 907 case MMC_POWER_UP: 908 dev_dbg(mmc_dev(mmc), "Powering card up\n"); 909 910 if (!IS_ERR(mmc->supply.vmmc)) { 911 host->ferror = mmc_regulator_set_ocr(mmc, 912 mmc->supply.vmmc, 913 ios->vdd); 914 if (host->ferror) 915 return; 916 } 917 918 if (!IS_ERR(mmc->supply.vqmmc)) { 919 host->ferror = regulator_enable(mmc->supply.vqmmc); 920 if (host->ferror) { 921 dev_err(mmc_dev(mmc), 922 "failed to enable vqmmc\n"); 923 return; 924 } 925 host->vqmmc_enabled = true; 926 } 927 break; 928 929 case MMC_POWER_OFF: 930 dev_dbg(mmc_dev(mmc), "Powering card off\n"); 931 932 if (!IS_ERR(mmc->supply.vmmc)) 933 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 934 935 if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 936 regulator_disable(mmc->supply.vqmmc); 937 938 host->vqmmc_enabled = false; 939 break; 940 941 default: 942 dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n"); 943 break; 944 } 945 } 946 947 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 948 { 949 struct sunxi_mmc_host *host = mmc_priv(mmc); 950 951 sunxi_mmc_card_power(host, ios); 952 sunxi_mmc_set_bus_width(host, ios->bus_width); 953 sunxi_mmc_set_clk(host, ios); 954 } 955 956 static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 957 { 958 int ret; 959 960 /* vqmmc regulator is available */ 961 if (!IS_ERR(mmc->supply.vqmmc)) { 962 ret = mmc_regulator_set_vqmmc(mmc, ios); 963 return ret < 0 ? ret : 0; 964 } 965 966 /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 967 if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 968 return 0; 969 970 return -EINVAL; 971 } 972 973 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 974 { 975 struct sunxi_mmc_host *host = mmc_priv(mmc); 976 unsigned long flags; 977 u32 imask; 978 979 if (enable) 980 pm_runtime_get_noresume(host->dev); 981 982 spin_lock_irqsave(&host->lock, flags); 983 984 imask = mmc_readl(host, REG_IMASK); 985 if (enable) { 986 host->sdio_imask = SDXC_SDIO_INTERRUPT; 987 imask |= SDXC_SDIO_INTERRUPT; 988 } else { 989 host->sdio_imask = 0; 990 imask &= ~SDXC_SDIO_INTERRUPT; 991 } 992 mmc_writel(host, REG_IMASK, imask); 993 spin_unlock_irqrestore(&host->lock, flags); 994 995 if (!enable) 996 pm_runtime_put_noidle(host->mmc->parent); 997 } 998 999 static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 1000 { 1001 struct sunxi_mmc_host *host = mmc_priv(mmc); 1002 mmc_writel(host, REG_HWRST, 0); 1003 udelay(10); 1004 mmc_writel(host, REG_HWRST, 1); 1005 udelay(300); 1006 } 1007 1008 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 1009 { 1010 struct sunxi_mmc_host *host = mmc_priv(mmc); 1011 struct mmc_command *cmd = mrq->cmd; 1012 struct mmc_data *data = mrq->data; 1013 unsigned long iflags; 1014 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 1015 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 1016 bool wait_dma = host->wait_dma; 1017 int ret; 1018 1019 /* Check for set_ios errors (should never happen) */ 1020 if (host->ferror) { 1021 mrq->cmd->error = host->ferror; 1022 mmc_request_done(mmc, mrq); 1023 return; 1024 } 1025 1026 if (data) { 1027 ret = sunxi_mmc_map_dma(host, data); 1028 if (ret < 0) { 1029 dev_err(mmc_dev(mmc), "map DMA failed\n"); 1030 cmd->error = ret; 1031 data->error = ret; 1032 mmc_request_done(mmc, mrq); 1033 return; 1034 } 1035 } 1036 1037 if (cmd->opcode == MMC_GO_IDLE_STATE) { 1038 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 1039 imask |= SDXC_COMMAND_DONE; 1040 } 1041 1042 if (cmd->flags & MMC_RSP_PRESENT) { 1043 cmd_val |= SDXC_RESP_EXPIRE; 1044 if (cmd->flags & MMC_RSP_136) 1045 cmd_val |= SDXC_LONG_RESPONSE; 1046 if (cmd->flags & MMC_RSP_CRC) 1047 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 1048 1049 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 1050 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 1051 1052 if (cmd->data->stop) { 1053 imask |= SDXC_AUTO_COMMAND_DONE; 1054 cmd_val |= SDXC_SEND_AUTO_STOP; 1055 } else { 1056 imask |= SDXC_DATA_OVER; 1057 } 1058 1059 if (cmd->data->flags & MMC_DATA_WRITE) 1060 cmd_val |= SDXC_WRITE; 1061 else 1062 wait_dma = true; 1063 } else { 1064 imask |= SDXC_COMMAND_DONE; 1065 } 1066 } else { 1067 imask |= SDXC_COMMAND_DONE; 1068 } 1069 1070 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 1071 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 1072 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 1073 1074 spin_lock_irqsave(&host->lock, iflags); 1075 1076 if (host->mrq || host->manual_stop_mrq) { 1077 spin_unlock_irqrestore(&host->lock, iflags); 1078 1079 if (data) 1080 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1081 mmc_get_dma_dir(data)); 1082 1083 dev_err(mmc_dev(mmc), "request already pending\n"); 1084 mrq->cmd->error = -EBUSY; 1085 mmc_request_done(mmc, mrq); 1086 return; 1087 } 1088 1089 if (data) { 1090 mmc_writel(host, REG_BLKSZ, data->blksz); 1091 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 1092 sunxi_mmc_start_dma(host, data); 1093 } 1094 1095 host->mrq = mrq; 1096 host->wait_dma = wait_dma; 1097 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 1098 mmc_writel(host, REG_CARG, cmd->arg); 1099 mmc_writel(host, REG_CMDR, cmd_val); 1100 1101 spin_unlock_irqrestore(&host->lock, iflags); 1102 } 1103 1104 static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1105 { 1106 struct sunxi_mmc_host *host = mmc_priv(mmc); 1107 1108 return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1109 } 1110 1111 static const struct mmc_host_ops sunxi_mmc_ops = { 1112 .request = sunxi_mmc_request, 1113 .set_ios = sunxi_mmc_set_ios, 1114 .get_ro = mmc_gpio_get_ro, 1115 .get_cd = mmc_gpio_get_cd, 1116 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1117 .start_signal_voltage_switch = sunxi_mmc_volt_switch, 1118 .hw_reset = sunxi_mmc_hw_reset, 1119 .card_busy = sunxi_mmc_card_busy, 1120 }; 1121 1122 static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 1123 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1124 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1125 [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 1126 [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 1127 /* Value from A83T "new timing mode". Works but might not be right. */ 1128 [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 1129 }; 1130 1131 static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 1132 [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 1133 [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 1134 [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 1135 [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 1136 [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 1137 }; 1138 1139 static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 1140 .idma_des_size_bits = 13, 1141 .clk_delays = NULL, 1142 .can_calibrate = false, 1143 }; 1144 1145 static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 1146 .idma_des_size_bits = 16, 1147 .clk_delays = NULL, 1148 .can_calibrate = false, 1149 }; 1150 1151 static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1152 .idma_des_size_bits = 16, 1153 .clk_delays = sunxi_mmc_clk_delays, 1154 .can_calibrate = false, 1155 }; 1156 1157 static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1158 .idma_des_size_bits = 16, 1159 .clk_delays = sunxi_mmc_clk_delays, 1160 .can_calibrate = false, 1161 .ccu_has_timings_switch = true, 1162 }; 1163 1164 static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 1165 .idma_des_size_bits = 16, 1166 .clk_delays = sun9i_mmc_clk_delays, 1167 .can_calibrate = false, 1168 }; 1169 1170 static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1171 .idma_des_size_bits = 16, 1172 .clk_delays = NULL, 1173 .can_calibrate = true, 1174 .mask_data0 = true, 1175 .needs_new_timings = true, 1176 }; 1177 1178 static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 1179 .idma_des_size_bits = 13, 1180 .clk_delays = NULL, 1181 .can_calibrate = true, 1182 .needs_new_timings = true, 1183 }; 1184 1185 static const struct sunxi_mmc_cfg sun50i_a100_cfg = { 1186 .idma_des_size_bits = 16, 1187 .idma_des_shift = 2, 1188 .clk_delays = NULL, 1189 .can_calibrate = true, 1190 .mask_data0 = true, 1191 .needs_new_timings = true, 1192 }; 1193 1194 static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = { 1195 .idma_des_size_bits = 13, 1196 .idma_des_shift = 2, 1197 .clk_delays = NULL, 1198 .can_calibrate = true, 1199 .needs_new_timings = true, 1200 }; 1201 1202 static const struct of_device_id sunxi_mmc_of_match[] = { 1203 { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 1204 { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1205 { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1206 { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 1207 { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1208 { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 1209 { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 1210 { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg }, 1211 { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg }, 1212 { /* sentinel */ } 1213 }; 1214 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 1215 1216 static int sunxi_mmc_enable(struct sunxi_mmc_host *host) 1217 { 1218 int ret; 1219 1220 if (!IS_ERR(host->reset)) { 1221 ret = reset_control_reset(host->reset); 1222 if (ret) { 1223 dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", 1224 ret); 1225 return ret; 1226 } 1227 } 1228 1229 ret = clk_prepare_enable(host->clk_ahb); 1230 if (ret) { 1231 dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); 1232 goto error_assert_reset; 1233 } 1234 1235 ret = clk_prepare_enable(host->clk_mmc); 1236 if (ret) { 1237 dev_err(host->dev, "Enable mmc clk err %d\n", ret); 1238 goto error_disable_clk_ahb; 1239 } 1240 1241 ret = clk_prepare_enable(host->clk_output); 1242 if (ret) { 1243 dev_err(host->dev, "Enable output clk err %d\n", ret); 1244 goto error_disable_clk_mmc; 1245 } 1246 1247 ret = clk_prepare_enable(host->clk_sample); 1248 if (ret) { 1249 dev_err(host->dev, "Enable sample clk err %d\n", ret); 1250 goto error_disable_clk_output; 1251 } 1252 1253 /* 1254 * Sometimes the controller asserts the irq on boot for some reason, 1255 * make sure the controller is in a sane state before enabling irqs. 1256 */ 1257 ret = sunxi_mmc_reset_host(host); 1258 if (ret) 1259 goto error_disable_clk_sample; 1260 1261 return 0; 1262 1263 error_disable_clk_sample: 1264 clk_disable_unprepare(host->clk_sample); 1265 error_disable_clk_output: 1266 clk_disable_unprepare(host->clk_output); 1267 error_disable_clk_mmc: 1268 clk_disable_unprepare(host->clk_mmc); 1269 error_disable_clk_ahb: 1270 clk_disable_unprepare(host->clk_ahb); 1271 error_assert_reset: 1272 if (!IS_ERR(host->reset)) 1273 reset_control_assert(host->reset); 1274 return ret; 1275 } 1276 1277 static void sunxi_mmc_disable(struct sunxi_mmc_host *host) 1278 { 1279 sunxi_mmc_reset_host(host); 1280 1281 clk_disable_unprepare(host->clk_sample); 1282 clk_disable_unprepare(host->clk_output); 1283 clk_disable_unprepare(host->clk_mmc); 1284 clk_disable_unprepare(host->clk_ahb); 1285 1286 if (!IS_ERR(host->reset)) 1287 reset_control_assert(host->reset); 1288 } 1289 1290 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 1291 struct platform_device *pdev) 1292 { 1293 int ret; 1294 1295 host->cfg = of_device_get_match_data(&pdev->dev); 1296 if (!host->cfg) 1297 return -EINVAL; 1298 1299 ret = mmc_regulator_get_supply(host->mmc); 1300 if (ret) 1301 return ret; 1302 1303 host->reg_base = devm_platform_ioremap_resource(pdev, 0); 1304 if (IS_ERR(host->reg_base)) 1305 return PTR_ERR(host->reg_base); 1306 1307 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 1308 if (IS_ERR(host->clk_ahb)) { 1309 dev_err(&pdev->dev, "Could not get ahb clock\n"); 1310 return PTR_ERR(host->clk_ahb); 1311 } 1312 1313 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 1314 if (IS_ERR(host->clk_mmc)) { 1315 dev_err(&pdev->dev, "Could not get mmc clock\n"); 1316 return PTR_ERR(host->clk_mmc); 1317 } 1318 1319 if (host->cfg->clk_delays) { 1320 host->clk_output = devm_clk_get(&pdev->dev, "output"); 1321 if (IS_ERR(host->clk_output)) { 1322 dev_err(&pdev->dev, "Could not get output clock\n"); 1323 return PTR_ERR(host->clk_output); 1324 } 1325 1326 host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 1327 if (IS_ERR(host->clk_sample)) { 1328 dev_err(&pdev->dev, "Could not get sample clock\n"); 1329 return PTR_ERR(host->clk_sample); 1330 } 1331 } 1332 1333 host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 1334 "ahb"); 1335 if (PTR_ERR(host->reset) == -EPROBE_DEFER) 1336 return PTR_ERR(host->reset); 1337 1338 ret = sunxi_mmc_enable(host); 1339 if (ret) 1340 return ret; 1341 1342 host->irq = platform_get_irq(pdev, 0); 1343 if (host->irq <= 0) { 1344 ret = -EINVAL; 1345 goto error_disable_mmc; 1346 } 1347 1348 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 1349 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 1350 1351 error_disable_mmc: 1352 sunxi_mmc_disable(host); 1353 return ret; 1354 } 1355 1356 static int sunxi_mmc_probe(struct platform_device *pdev) 1357 { 1358 struct sunxi_mmc_host *host; 1359 struct mmc_host *mmc; 1360 int ret; 1361 1362 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 1363 if (!mmc) { 1364 dev_err(&pdev->dev, "mmc alloc host failed\n"); 1365 return -ENOMEM; 1366 } 1367 platform_set_drvdata(pdev, mmc); 1368 1369 host = mmc_priv(mmc); 1370 host->dev = &pdev->dev; 1371 host->mmc = mmc; 1372 spin_lock_init(&host->lock); 1373 1374 ret = sunxi_mmc_resource_request(host, pdev); 1375 if (ret) 1376 goto error_free_host; 1377 1378 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 1379 &host->sg_dma, GFP_KERNEL); 1380 if (!host->sg_cpu) { 1381 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 1382 ret = -ENOMEM; 1383 goto error_free_host; 1384 } 1385 1386 if (host->cfg->ccu_has_timings_switch) { 1387 /* 1388 * Supports both old and new timing modes. 1389 * Try setting the clk to new timing mode. 1390 */ 1391 sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1392 1393 /* And check the result */ 1394 ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1395 if (ret < 0) { 1396 /* 1397 * For whatever reason we were not able to get 1398 * the current active mode. Default to old mode. 1399 */ 1400 dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1401 host->use_new_timings = false; 1402 } else { 1403 host->use_new_timings = !!ret; 1404 } 1405 } else if (host->cfg->needs_new_timings) { 1406 /* Supports new timing mode only */ 1407 host->use_new_timings = true; 1408 } 1409 1410 mmc->ops = &sunxi_mmc_ops; 1411 mmc->max_blk_count = 8192; 1412 mmc->max_blk_size = 4096; 1413 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 1414 mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 1415 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 1416 /* 400kHz ~ 52MHz */ 1417 mmc->f_min = 400000; 1418 mmc->f_max = 52000000; 1419 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1420 MMC_CAP_SDIO_IRQ; 1421 1422 /* 1423 * Some H5 devices do not have signal traces precise enough to 1424 * use HS DDR mode for their eMMC chips. 1425 * 1426 * We still enable HS DDR modes for all the other controller 1427 * variants that support them. 1428 */ 1429 if ((host->cfg->clk_delays || host->use_new_timings) && 1430 !of_device_is_compatible(pdev->dev.of_node, 1431 "allwinner,sun50i-h5-emmc")) 1432 mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1433 1434 ret = mmc_of_parse(mmc); 1435 if (ret) 1436 goto error_free_dma; 1437 1438 /* 1439 * If we don't support delay chains in the SoC, we can't use any 1440 * of the higher speed modes. Mask them out in case the device 1441 * tree specifies the properties for them, which gets added to 1442 * the caps by mmc_of_parse() above. 1443 */ 1444 if (!(host->cfg->clk_delays || host->use_new_timings)) { 1445 mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | 1446 MMC_CAP_1_2V_DDR | MMC_CAP_UHS); 1447 mmc->caps2 &= ~MMC_CAP2_HS200; 1448 } 1449 1450 /* TODO: This driver doesn't support HS400 mode yet */ 1451 mmc->caps2 &= ~MMC_CAP2_HS400; 1452 1453 ret = sunxi_mmc_init_host(host); 1454 if (ret) 1455 goto error_free_dma; 1456 1457 pm_runtime_set_active(&pdev->dev); 1458 pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 1459 pm_runtime_use_autosuspend(&pdev->dev); 1460 pm_runtime_enable(&pdev->dev); 1461 1462 ret = mmc_add_host(mmc); 1463 if (ret) 1464 goto error_free_dma; 1465 1466 dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n", 1467 mmc->max_req_size >> 10, 1468 host->use_new_timings ? ", uses new timings mode" : ""); 1469 1470 return 0; 1471 1472 error_free_dma: 1473 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1474 error_free_host: 1475 mmc_free_host(mmc); 1476 return ret; 1477 } 1478 1479 static int sunxi_mmc_remove(struct platform_device *pdev) 1480 { 1481 struct mmc_host *mmc = platform_get_drvdata(pdev); 1482 struct sunxi_mmc_host *host = mmc_priv(mmc); 1483 1484 mmc_remove_host(mmc); 1485 pm_runtime_force_suspend(&pdev->dev); 1486 disable_irq(host->irq); 1487 sunxi_mmc_disable(host); 1488 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1489 mmc_free_host(mmc); 1490 1491 return 0; 1492 } 1493 1494 #ifdef CONFIG_PM 1495 static int sunxi_mmc_runtime_resume(struct device *dev) 1496 { 1497 struct mmc_host *mmc = dev_get_drvdata(dev); 1498 struct sunxi_mmc_host *host = mmc_priv(mmc); 1499 int ret; 1500 1501 ret = sunxi_mmc_enable(host); 1502 if (ret) 1503 return ret; 1504 1505 sunxi_mmc_init_host(host); 1506 sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); 1507 sunxi_mmc_set_clk(host, &mmc->ios); 1508 enable_irq(host->irq); 1509 1510 return 0; 1511 } 1512 1513 static int sunxi_mmc_runtime_suspend(struct device *dev) 1514 { 1515 struct mmc_host *mmc = dev_get_drvdata(dev); 1516 struct sunxi_mmc_host *host = mmc_priv(mmc); 1517 1518 /* 1519 * When clocks are off, it's possible receiving 1520 * fake interrupts, which will stall the system. 1521 * Disabling the irq will prevent this. 1522 */ 1523 disable_irq(host->irq); 1524 sunxi_mmc_reset_host(host); 1525 sunxi_mmc_disable(host); 1526 1527 return 0; 1528 } 1529 #endif 1530 1531 static const struct dev_pm_ops sunxi_mmc_pm_ops = { 1532 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1533 pm_runtime_force_resume) 1534 SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend, 1535 sunxi_mmc_runtime_resume, 1536 NULL) 1537 }; 1538 1539 static struct platform_driver sunxi_mmc_driver = { 1540 .driver = { 1541 .name = "sunxi-mmc", 1542 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1543 .of_match_table = sunxi_mmc_of_match, 1544 .pm = &sunxi_mmc_pm_ops, 1545 }, 1546 .probe = sunxi_mmc_probe, 1547 .remove = sunxi_mmc_remove, 1548 }; 1549 module_platform_driver(sunxi_mmc_driver); 1550 1551 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1552 MODULE_LICENSE("GPL v2"); 1553 MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 1554 MODULE_ALIAS("platform:sunxi-mmc"); 1555