1 /* 2 * Driver for sunxi SD/MMC host controllers 3 * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 4 * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 5 * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 6 * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch> 7 * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 */ 14 15 #include <linux/kernel.h> 16 #include <linux/module.h> 17 #include <linux/io.h> 18 #include <linux/device.h> 19 #include <linux/interrupt.h> 20 #include <linux/delay.h> 21 #include <linux/err.h> 22 23 #include <linux/clk.h> 24 #include <linux/clk-private.h> 25 #include <linux/clk/sunxi.h> 26 27 #include <linux/gpio.h> 28 #include <linux/platform_device.h> 29 #include <linux/spinlock.h> 30 #include <linux/scatterlist.h> 31 #include <linux/dma-mapping.h> 32 #include <linux/slab.h> 33 #include <linux/reset.h> 34 35 #include <linux/of_address.h> 36 #include <linux/of_gpio.h> 37 #include <linux/of_platform.h> 38 39 #include <linux/mmc/host.h> 40 #include <linux/mmc/sd.h> 41 #include <linux/mmc/sdio.h> 42 #include <linux/mmc/mmc.h> 43 #include <linux/mmc/core.h> 44 #include <linux/mmc/card.h> 45 #include <linux/mmc/slot-gpio.h> 46 47 /* register offset definitions */ 48 #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 49 #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 50 #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 51 #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 52 #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 53 #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 54 #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 55 #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 56 #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 57 #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 58 #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 59 #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 60 #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 61 #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 62 #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 63 #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 64 #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 65 #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 66 #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 67 #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 68 #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 69 #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 70 #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 71 #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 72 #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 73 #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 74 #define SDXC_REG_CHDA (0x90) 75 #define SDXC_REG_CBDA (0x94) 76 77 #define mmc_readl(host, reg) \ 78 readl((host)->reg_base + SDXC_##reg) 79 #define mmc_writel(host, reg, value) \ 80 writel((value), (host)->reg_base + SDXC_##reg) 81 82 /* global control register bits */ 83 #define SDXC_SOFT_RESET BIT(0) 84 #define SDXC_FIFO_RESET BIT(1) 85 #define SDXC_DMA_RESET BIT(2) 86 #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 87 #define SDXC_DMA_ENABLE_BIT BIT(5) 88 #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 89 #define SDXC_POSEDGE_LATCH_DATA BIT(9) 90 #define SDXC_DDR_MODE BIT(10) 91 #define SDXC_MEMORY_ACCESS_DONE BIT(29) 92 #define SDXC_ACCESS_DONE_DIRECT BIT(30) 93 #define SDXC_ACCESS_BY_AHB BIT(31) 94 #define SDXC_ACCESS_BY_DMA (0 << 31) 95 #define SDXC_HARDWARE_RESET \ 96 (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 97 98 /* clock control bits */ 99 #define SDXC_CARD_CLOCK_ON BIT(16) 100 #define SDXC_LOW_POWER_ON BIT(17) 101 102 /* bus width */ 103 #define SDXC_WIDTH1 0 104 #define SDXC_WIDTH4 1 105 #define SDXC_WIDTH8 2 106 107 /* smc command bits */ 108 #define SDXC_RESP_EXPIRE BIT(6) 109 #define SDXC_LONG_RESPONSE BIT(7) 110 #define SDXC_CHECK_RESPONSE_CRC BIT(8) 111 #define SDXC_DATA_EXPIRE BIT(9) 112 #define SDXC_WRITE BIT(10) 113 #define SDXC_SEQUENCE_MODE BIT(11) 114 #define SDXC_SEND_AUTO_STOP BIT(12) 115 #define SDXC_WAIT_PRE_OVER BIT(13) 116 #define SDXC_STOP_ABORT_CMD BIT(14) 117 #define SDXC_SEND_INIT_SEQUENCE BIT(15) 118 #define SDXC_UPCLK_ONLY BIT(21) 119 #define SDXC_READ_CEATA_DEV BIT(22) 120 #define SDXC_CCS_EXPIRE BIT(23) 121 #define SDXC_ENABLE_BIT_BOOT BIT(24) 122 #define SDXC_ALT_BOOT_OPTIONS BIT(25) 123 #define SDXC_BOOT_ACK_EXPIRE BIT(26) 124 #define SDXC_BOOT_ABORT BIT(27) 125 #define SDXC_VOLTAGE_SWITCH BIT(28) 126 #define SDXC_USE_HOLD_REGISTER BIT(29) 127 #define SDXC_START BIT(31) 128 129 /* interrupt bits */ 130 #define SDXC_RESP_ERROR BIT(1) 131 #define SDXC_COMMAND_DONE BIT(2) 132 #define SDXC_DATA_OVER BIT(3) 133 #define SDXC_TX_DATA_REQUEST BIT(4) 134 #define SDXC_RX_DATA_REQUEST BIT(5) 135 #define SDXC_RESP_CRC_ERROR BIT(6) 136 #define SDXC_DATA_CRC_ERROR BIT(7) 137 #define SDXC_RESP_TIMEOUT BIT(8) 138 #define SDXC_DATA_TIMEOUT BIT(9) 139 #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 140 #define SDXC_FIFO_RUN_ERROR BIT(11) 141 #define SDXC_HARD_WARE_LOCKED BIT(12) 142 #define SDXC_START_BIT_ERROR BIT(13) 143 #define SDXC_AUTO_COMMAND_DONE BIT(14) 144 #define SDXC_END_BIT_ERROR BIT(15) 145 #define SDXC_SDIO_INTERRUPT BIT(16) 146 #define SDXC_CARD_INSERT BIT(30) 147 #define SDXC_CARD_REMOVE BIT(31) 148 #define SDXC_INTERRUPT_ERROR_BIT \ 149 (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 150 SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 151 SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 152 #define SDXC_INTERRUPT_DONE_BIT \ 153 (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 154 SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 155 156 /* status */ 157 #define SDXC_RXWL_FLAG BIT(0) 158 #define SDXC_TXWL_FLAG BIT(1) 159 #define SDXC_FIFO_EMPTY BIT(2) 160 #define SDXC_FIFO_FULL BIT(3) 161 #define SDXC_CARD_PRESENT BIT(8) 162 #define SDXC_CARD_DATA_BUSY BIT(9) 163 #define SDXC_DATA_FSM_BUSY BIT(10) 164 #define SDXC_DMA_REQUEST BIT(31) 165 #define SDXC_FIFO_SIZE 16 166 167 /* Function select */ 168 #define SDXC_CEATA_ON (0xceaa << 16) 169 #define SDXC_SEND_IRQ_RESPONSE BIT(0) 170 #define SDXC_SDIO_READ_WAIT BIT(1) 171 #define SDXC_ABORT_READ_DATA BIT(2) 172 #define SDXC_SEND_CCSD BIT(8) 173 #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 174 #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 175 176 /* IDMA controller bus mod bit field */ 177 #define SDXC_IDMAC_SOFT_RESET BIT(0) 178 #define SDXC_IDMAC_FIX_BURST BIT(1) 179 #define SDXC_IDMAC_IDMA_ON BIT(7) 180 #define SDXC_IDMAC_REFETCH_DES BIT(31) 181 182 /* IDMA status bit field */ 183 #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 184 #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 185 #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 186 #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 187 #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 188 #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 189 #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 190 #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 191 #define SDXC_IDMAC_IDLE (0 << 13) 192 #define SDXC_IDMAC_SUSPEND (1 << 13) 193 #define SDXC_IDMAC_DESC_READ (2 << 13) 194 #define SDXC_IDMAC_DESC_CHECK (3 << 13) 195 #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 196 #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 197 #define SDXC_IDMAC_READ (6 << 13) 198 #define SDXC_IDMAC_WRITE (7 << 13) 199 #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 200 201 /* 202 * If the idma-des-size-bits of property is ie 13, bufsize bits are: 203 * Bits 0-12: buf1 size 204 * Bits 13-25: buf2 size 205 * Bits 26-31: not used 206 * Since we only ever set buf1 size, we can simply store it directly. 207 */ 208 #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 209 #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 210 #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 211 #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 212 #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 213 #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 214 #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 215 216 struct sunxi_idma_des { 217 u32 config; 218 u32 buf_size; 219 u32 buf_addr_ptr1; 220 u32 buf_addr_ptr2; 221 }; 222 223 struct sunxi_mmc_host { 224 struct mmc_host *mmc; 225 struct reset_control *reset; 226 227 /* IO mapping base */ 228 void __iomem *reg_base; 229 230 /* clock management */ 231 struct clk *clk_ahb; 232 struct clk *clk_mmc; 233 234 /* irq */ 235 spinlock_t lock; 236 int irq; 237 u32 int_sum; 238 u32 sdio_imask; 239 240 /* dma */ 241 u32 idma_des_size_bits; 242 dma_addr_t sg_dma; 243 void *sg_cpu; 244 bool wait_dma; 245 246 struct mmc_request *mrq; 247 struct mmc_request *manual_stop_mrq; 248 int ferror; 249 }; 250 251 static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 252 { 253 unsigned long expire = jiffies + msecs_to_jiffies(250); 254 u32 rval; 255 256 mmc_writel(host, REG_CMDR, SDXC_HARDWARE_RESET); 257 do { 258 rval = mmc_readl(host, REG_GCTRL); 259 } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 260 261 if (rval & SDXC_HARDWARE_RESET) { 262 dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 263 return -EIO; 264 } 265 266 return 0; 267 } 268 269 static int sunxi_mmc_init_host(struct mmc_host *mmc) 270 { 271 u32 rval; 272 struct sunxi_mmc_host *host = mmc_priv(mmc); 273 274 if (sunxi_mmc_reset_host(host)) 275 return -EIO; 276 277 mmc_writel(host, REG_FTRGL, 0x20070008); 278 mmc_writel(host, REG_TMOUT, 0xffffffff); 279 mmc_writel(host, REG_IMASK, host->sdio_imask); 280 mmc_writel(host, REG_RINTR, 0xffffffff); 281 mmc_writel(host, REG_DBGC, 0xdeb); 282 mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 283 mmc_writel(host, REG_DLBA, host->sg_dma); 284 285 rval = mmc_readl(host, REG_GCTRL); 286 rval |= SDXC_INTERRUPT_ENABLE_BIT; 287 rval &= ~SDXC_ACCESS_DONE_DIRECT; 288 mmc_writel(host, REG_GCTRL, rval); 289 290 return 0; 291 } 292 293 static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 294 struct mmc_data *data) 295 { 296 struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 297 struct sunxi_idma_des *pdes_pa = (struct sunxi_idma_des *)host->sg_dma; 298 int i, max_len = (1 << host->idma_des_size_bits); 299 300 for (i = 0; i < data->sg_len; i++) { 301 pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN | 302 SDXC_IDMAC_DES0_DIC; 303 304 if (data->sg[i].length == max_len) 305 pdes[i].buf_size = 0; /* 0 == max_len */ 306 else 307 pdes[i].buf_size = data->sg[i].length; 308 309 pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]); 310 pdes[i].buf_addr_ptr2 = (u32)&pdes_pa[i + 1]; 311 } 312 313 pdes[0].config |= SDXC_IDMAC_DES0_FD; 314 pdes[i - 1].config = SDXC_IDMAC_DES0_OWN | SDXC_IDMAC_DES0_LD; 315 316 /* 317 * Avoid the io-store starting the idmac hitting io-mem before the 318 * descriptors hit the main-mem. 319 */ 320 wmb(); 321 } 322 323 static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data) 324 { 325 if (data->flags & MMC_DATA_WRITE) 326 return DMA_TO_DEVICE; 327 else 328 return DMA_FROM_DEVICE; 329 } 330 331 static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 332 struct mmc_data *data) 333 { 334 u32 i, dma_len; 335 struct scatterlist *sg; 336 337 dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 338 sunxi_mmc_get_dma_dir(data)); 339 if (dma_len == 0) { 340 dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 341 return -ENOMEM; 342 } 343 344 for_each_sg(data->sg, sg, data->sg_len, i) { 345 if (sg->offset & 3 || sg->length & 3) { 346 dev_err(mmc_dev(host->mmc), 347 "unaligned scatterlist: os %x length %d\n", 348 sg->offset, sg->length); 349 return -EINVAL; 350 } 351 } 352 353 return 0; 354 } 355 356 static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 357 struct mmc_data *data) 358 { 359 u32 rval; 360 361 sunxi_mmc_init_idma_des(host, data); 362 363 rval = mmc_readl(host, REG_GCTRL); 364 rval |= SDXC_DMA_ENABLE_BIT; 365 mmc_writel(host, REG_GCTRL, rval); 366 rval |= SDXC_DMA_RESET; 367 mmc_writel(host, REG_GCTRL, rval); 368 369 mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 370 371 if (!(data->flags & MMC_DATA_WRITE)) 372 mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 373 374 mmc_writel(host, REG_DMAC, 375 SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 376 } 377 378 static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 379 struct mmc_request *req) 380 { 381 u32 arg, cmd_val, ri; 382 unsigned long expire = jiffies + msecs_to_jiffies(1000); 383 384 cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 385 SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 386 387 if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 388 cmd_val |= SD_IO_RW_DIRECT; 389 arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 390 ((req->cmd->arg >> 28) & 0x7); 391 } else { 392 cmd_val |= MMC_STOP_TRANSMISSION; 393 arg = 0; 394 } 395 396 mmc_writel(host, REG_CARG, arg); 397 mmc_writel(host, REG_CMDR, cmd_val); 398 399 do { 400 ri = mmc_readl(host, REG_RINTR); 401 } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 402 time_before(jiffies, expire)); 403 404 if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 405 dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 406 if (req->stop) 407 req->stop->resp[0] = -ETIMEDOUT; 408 } else { 409 if (req->stop) 410 req->stop->resp[0] = mmc_readl(host, REG_RESP0); 411 } 412 413 mmc_writel(host, REG_RINTR, 0xffff); 414 } 415 416 static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 417 { 418 struct mmc_command *cmd = host->mrq->cmd; 419 struct mmc_data *data = host->mrq->data; 420 421 /* For some cmds timeout is normal with sd/mmc cards */ 422 if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 423 SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 424 cmd->opcode == SD_IO_RW_DIRECT)) 425 return; 426 427 dev_err(mmc_dev(host->mmc), 428 "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 429 host->mmc->index, cmd->opcode, 430 data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 431 host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 432 host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 433 host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 434 host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 435 host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 436 host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 437 host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 438 host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 439 host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 440 ); 441 } 442 443 /* Called in interrupt context! */ 444 static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 445 { 446 struct mmc_request *mrq = host->mrq; 447 struct mmc_data *data = mrq->data; 448 u32 rval; 449 450 mmc_writel(host, REG_IMASK, host->sdio_imask); 451 mmc_writel(host, REG_IDIE, 0); 452 453 if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 454 sunxi_mmc_dump_errinfo(host); 455 mrq->cmd->error = -ETIMEDOUT; 456 457 if (data) { 458 data->error = -ETIMEDOUT; 459 host->manual_stop_mrq = mrq; 460 } 461 462 if (mrq->stop) 463 mrq->stop->error = -ETIMEDOUT; 464 } else { 465 if (mrq->cmd->flags & MMC_RSP_136) { 466 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 467 mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 468 mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 469 mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 470 } else { 471 mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 472 } 473 474 if (data) 475 data->bytes_xfered = data->blocks * data->blksz; 476 } 477 478 if (data) { 479 mmc_writel(host, REG_IDST, 0x337); 480 mmc_writel(host, REG_DMAC, 0); 481 rval = mmc_readl(host, REG_GCTRL); 482 rval |= SDXC_DMA_RESET; 483 mmc_writel(host, REG_GCTRL, rval); 484 rval &= ~SDXC_DMA_ENABLE_BIT; 485 mmc_writel(host, REG_GCTRL, rval); 486 rval |= SDXC_FIFO_RESET; 487 mmc_writel(host, REG_GCTRL, rval); 488 dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 489 sunxi_mmc_get_dma_dir(data)); 490 } 491 492 mmc_writel(host, REG_RINTR, 0xffff); 493 494 host->mrq = NULL; 495 host->int_sum = 0; 496 host->wait_dma = false; 497 498 return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 499 } 500 501 static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 502 { 503 struct sunxi_mmc_host *host = dev_id; 504 struct mmc_request *mrq; 505 u32 msk_int, idma_int; 506 bool finalize = false; 507 bool sdio_int = false; 508 irqreturn_t ret = IRQ_HANDLED; 509 510 spin_lock(&host->lock); 511 512 idma_int = mmc_readl(host, REG_IDST); 513 msk_int = mmc_readl(host, REG_MISTA); 514 515 dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 516 host->mrq, msk_int, idma_int); 517 518 mrq = host->mrq; 519 if (mrq) { 520 if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 521 host->wait_dma = false; 522 523 host->int_sum |= msk_int; 524 525 /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 526 if ((host->int_sum & SDXC_RESP_TIMEOUT) && 527 !(host->int_sum & SDXC_COMMAND_DONE)) 528 mmc_writel(host, REG_IMASK, 529 host->sdio_imask | SDXC_COMMAND_DONE); 530 /* Don't wait for dma on error */ 531 else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 532 finalize = true; 533 else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 534 !host->wait_dma) 535 finalize = true; 536 } 537 538 if (msk_int & SDXC_SDIO_INTERRUPT) 539 sdio_int = true; 540 541 mmc_writel(host, REG_RINTR, msk_int); 542 mmc_writel(host, REG_IDST, idma_int); 543 544 if (finalize) 545 ret = sunxi_mmc_finalize_request(host); 546 547 spin_unlock(&host->lock); 548 549 if (finalize && ret == IRQ_HANDLED) 550 mmc_request_done(host->mmc, mrq); 551 552 if (sdio_int) 553 mmc_signal_sdio_irq(host->mmc); 554 555 return ret; 556 } 557 558 static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 559 { 560 struct sunxi_mmc_host *host = dev_id; 561 struct mmc_request *mrq; 562 unsigned long iflags; 563 564 spin_lock_irqsave(&host->lock, iflags); 565 mrq = host->manual_stop_mrq; 566 spin_unlock_irqrestore(&host->lock, iflags); 567 568 if (!mrq) { 569 dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 570 return IRQ_HANDLED; 571 } 572 573 dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 574 sunxi_mmc_send_manual_stop(host, mrq); 575 576 spin_lock_irqsave(&host->lock, iflags); 577 host->manual_stop_mrq = NULL; 578 spin_unlock_irqrestore(&host->lock, iflags); 579 580 mmc_request_done(host->mmc, mrq); 581 582 return IRQ_HANDLED; 583 } 584 585 static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 586 { 587 unsigned long expire = jiffies + msecs_to_jiffies(250); 588 u32 rval; 589 590 rval = mmc_readl(host, REG_CLKCR); 591 rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON); 592 593 if (oclk_en) 594 rval |= SDXC_CARD_CLOCK_ON; 595 596 mmc_writel(host, REG_CLKCR, rval); 597 598 rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 599 mmc_writel(host, REG_CMDR, rval); 600 601 do { 602 rval = mmc_readl(host, REG_CMDR); 603 } while (time_before(jiffies, expire) && (rval & SDXC_START)); 604 605 /* clear irq status bits set by the command */ 606 mmc_writel(host, REG_RINTR, 607 mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 608 609 if (rval & SDXC_START) { 610 dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 611 return -EIO; 612 } 613 614 return 0; 615 } 616 617 static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 618 struct mmc_ios *ios) 619 { 620 u32 rate, oclk_dly, rval, sclk_dly, src_clk; 621 int ret; 622 623 rate = clk_round_rate(host->clk_mmc, ios->clock); 624 dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n", 625 ios->clock, rate); 626 627 /* setting clock rate */ 628 ret = clk_set_rate(host->clk_mmc, rate); 629 if (ret) { 630 dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n", 631 rate, ret); 632 return ret; 633 } 634 635 ret = sunxi_mmc_oclk_onoff(host, 0); 636 if (ret) 637 return ret; 638 639 /* clear internal divider */ 640 rval = mmc_readl(host, REG_CLKCR); 641 rval &= ~0xff; 642 mmc_writel(host, REG_CLKCR, rval); 643 644 /* determine delays */ 645 if (rate <= 400000) { 646 oclk_dly = 0; 647 sclk_dly = 7; 648 } else if (rate <= 25000000) { 649 oclk_dly = 0; 650 sclk_dly = 5; 651 } else if (rate <= 50000000) { 652 if (ios->timing == MMC_TIMING_UHS_DDR50) { 653 oclk_dly = 2; 654 sclk_dly = 4; 655 } else { 656 oclk_dly = 3; 657 sclk_dly = 5; 658 } 659 } else { 660 /* rate > 50000000 */ 661 oclk_dly = 2; 662 sclk_dly = 4; 663 } 664 665 src_clk = clk_get_rate(clk_get_parent(host->clk_mmc)); 666 if (src_clk >= 300000000 && src_clk <= 400000000) { 667 if (oclk_dly) 668 oclk_dly--; 669 if (sclk_dly) 670 sclk_dly--; 671 } 672 673 clk_sunxi_mmc_phase_control(host->clk_mmc, sclk_dly, oclk_dly); 674 675 return sunxi_mmc_oclk_onoff(host, 1); 676 } 677 678 static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 679 { 680 struct sunxi_mmc_host *host = mmc_priv(mmc); 681 u32 rval; 682 683 /* Set the power state */ 684 switch (ios->power_mode) { 685 case MMC_POWER_ON: 686 break; 687 688 case MMC_POWER_UP: 689 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 690 691 host->ferror = sunxi_mmc_init_host(mmc); 692 if (host->ferror) 693 return; 694 695 dev_dbg(mmc_dev(mmc), "power on!\n"); 696 break; 697 698 case MMC_POWER_OFF: 699 dev_dbg(mmc_dev(mmc), "power off!\n"); 700 sunxi_mmc_reset_host(host); 701 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 702 break; 703 } 704 705 /* set bus width */ 706 switch (ios->bus_width) { 707 case MMC_BUS_WIDTH_1: 708 mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 709 break; 710 case MMC_BUS_WIDTH_4: 711 mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 712 break; 713 case MMC_BUS_WIDTH_8: 714 mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 715 break; 716 } 717 718 /* set ddr mode */ 719 rval = mmc_readl(host, REG_GCTRL); 720 if (ios->timing == MMC_TIMING_UHS_DDR50) 721 rval |= SDXC_DDR_MODE; 722 else 723 rval &= ~SDXC_DDR_MODE; 724 mmc_writel(host, REG_GCTRL, rval); 725 726 /* set up clock */ 727 if (ios->clock && ios->power_mode) { 728 host->ferror = sunxi_mmc_clk_set_rate(host, ios); 729 /* Android code had a usleep_range(50000, 55000); here */ 730 } 731 } 732 733 static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 734 { 735 struct sunxi_mmc_host *host = mmc_priv(mmc); 736 unsigned long flags; 737 u32 imask; 738 739 spin_lock_irqsave(&host->lock, flags); 740 741 imask = mmc_readl(host, REG_IMASK); 742 if (enable) { 743 host->sdio_imask = SDXC_SDIO_INTERRUPT; 744 imask |= SDXC_SDIO_INTERRUPT; 745 } else { 746 host->sdio_imask = 0; 747 imask &= ~SDXC_SDIO_INTERRUPT; 748 } 749 mmc_writel(host, REG_IMASK, imask); 750 spin_unlock_irqrestore(&host->lock, flags); 751 } 752 753 static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 754 { 755 struct sunxi_mmc_host *host = mmc_priv(mmc); 756 mmc_writel(host, REG_HWRST, 0); 757 udelay(10); 758 mmc_writel(host, REG_HWRST, 1); 759 udelay(300); 760 } 761 762 static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 763 { 764 struct sunxi_mmc_host *host = mmc_priv(mmc); 765 struct mmc_command *cmd = mrq->cmd; 766 struct mmc_data *data = mrq->data; 767 unsigned long iflags; 768 u32 imask = SDXC_INTERRUPT_ERROR_BIT; 769 u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 770 int ret; 771 772 /* Check for set_ios errors (should never happen) */ 773 if (host->ferror) { 774 mrq->cmd->error = host->ferror; 775 mmc_request_done(mmc, mrq); 776 return; 777 } 778 779 if (data) { 780 ret = sunxi_mmc_map_dma(host, data); 781 if (ret < 0) { 782 dev_err(mmc_dev(mmc), "map DMA failed\n"); 783 cmd->error = ret; 784 data->error = ret; 785 mmc_request_done(mmc, mrq); 786 return; 787 } 788 } 789 790 if (cmd->opcode == MMC_GO_IDLE_STATE) { 791 cmd_val |= SDXC_SEND_INIT_SEQUENCE; 792 imask |= SDXC_COMMAND_DONE; 793 } 794 795 if (cmd->flags & MMC_RSP_PRESENT) { 796 cmd_val |= SDXC_RESP_EXPIRE; 797 if (cmd->flags & MMC_RSP_136) 798 cmd_val |= SDXC_LONG_RESPONSE; 799 if (cmd->flags & MMC_RSP_CRC) 800 cmd_val |= SDXC_CHECK_RESPONSE_CRC; 801 802 if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 803 cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 804 if (cmd->data->flags & MMC_DATA_STREAM) { 805 imask |= SDXC_AUTO_COMMAND_DONE; 806 cmd_val |= SDXC_SEQUENCE_MODE | 807 SDXC_SEND_AUTO_STOP; 808 } 809 810 if (cmd->data->stop) { 811 imask |= SDXC_AUTO_COMMAND_DONE; 812 cmd_val |= SDXC_SEND_AUTO_STOP; 813 } else { 814 imask |= SDXC_DATA_OVER; 815 } 816 817 if (cmd->data->flags & MMC_DATA_WRITE) 818 cmd_val |= SDXC_WRITE; 819 else 820 host->wait_dma = true; 821 } else { 822 imask |= SDXC_COMMAND_DONE; 823 } 824 } else { 825 imask |= SDXC_COMMAND_DONE; 826 } 827 828 dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 829 cmd_val & 0x3f, cmd_val, cmd->arg, imask, 830 mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 831 832 spin_lock_irqsave(&host->lock, iflags); 833 834 if (host->mrq || host->manual_stop_mrq) { 835 spin_unlock_irqrestore(&host->lock, iflags); 836 837 if (data) 838 dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 839 sunxi_mmc_get_dma_dir(data)); 840 841 dev_err(mmc_dev(mmc), "request already pending\n"); 842 mrq->cmd->error = -EBUSY; 843 mmc_request_done(mmc, mrq); 844 return; 845 } 846 847 if (data) { 848 mmc_writel(host, REG_BLKSZ, data->blksz); 849 mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 850 sunxi_mmc_start_dma(host, data); 851 } 852 853 host->mrq = mrq; 854 mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 855 mmc_writel(host, REG_CARG, cmd->arg); 856 mmc_writel(host, REG_CMDR, cmd_val); 857 858 spin_unlock_irqrestore(&host->lock, iflags); 859 } 860 861 static const struct of_device_id sunxi_mmc_of_match[] = { 862 { .compatible = "allwinner,sun4i-a10-mmc", }, 863 { .compatible = "allwinner,sun5i-a13-mmc", }, 864 { /* sentinel */ } 865 }; 866 MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 867 868 static struct mmc_host_ops sunxi_mmc_ops = { 869 .request = sunxi_mmc_request, 870 .set_ios = sunxi_mmc_set_ios, 871 .get_ro = mmc_gpio_get_ro, 872 .get_cd = mmc_gpio_get_cd, 873 .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 874 .hw_reset = sunxi_mmc_hw_reset, 875 }; 876 877 static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 878 struct platform_device *pdev) 879 { 880 struct device_node *np = pdev->dev.of_node; 881 int ret; 882 883 if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc")) 884 host->idma_des_size_bits = 13; 885 else 886 host->idma_des_size_bits = 16; 887 888 ret = mmc_regulator_get_supply(host->mmc); 889 if (ret) { 890 if (ret != -EPROBE_DEFER) 891 dev_err(&pdev->dev, "Could not get vmmc supply\n"); 892 return ret; 893 } 894 895 host->reg_base = devm_ioremap_resource(&pdev->dev, 896 platform_get_resource(pdev, IORESOURCE_MEM, 0)); 897 if (IS_ERR(host->reg_base)) 898 return PTR_ERR(host->reg_base); 899 900 host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 901 if (IS_ERR(host->clk_ahb)) { 902 dev_err(&pdev->dev, "Could not get ahb clock\n"); 903 return PTR_ERR(host->clk_ahb); 904 } 905 906 host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 907 if (IS_ERR(host->clk_mmc)) { 908 dev_err(&pdev->dev, "Could not get mmc clock\n"); 909 return PTR_ERR(host->clk_mmc); 910 } 911 912 host->reset = devm_reset_control_get(&pdev->dev, "ahb"); 913 914 ret = clk_prepare_enable(host->clk_ahb); 915 if (ret) { 916 dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret); 917 return ret; 918 } 919 920 ret = clk_prepare_enable(host->clk_mmc); 921 if (ret) { 922 dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret); 923 goto error_disable_clk_ahb; 924 } 925 926 if (!IS_ERR(host->reset)) { 927 ret = reset_control_deassert(host->reset); 928 if (ret) { 929 dev_err(&pdev->dev, "reset err %d\n", ret); 930 goto error_disable_clk_mmc; 931 } 932 } 933 934 /* 935 * Sometimes the controller asserts the irq on boot for some reason, 936 * make sure the controller is in a sane state before enabling irqs. 937 */ 938 ret = sunxi_mmc_reset_host(host); 939 if (ret) 940 goto error_assert_reset; 941 942 host->irq = platform_get_irq(pdev, 0); 943 return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 944 sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 945 946 error_assert_reset: 947 if (!IS_ERR(host->reset)) 948 reset_control_assert(host->reset); 949 error_disable_clk_mmc: 950 clk_disable_unprepare(host->clk_mmc); 951 error_disable_clk_ahb: 952 clk_disable_unprepare(host->clk_ahb); 953 return ret; 954 } 955 956 static int sunxi_mmc_probe(struct platform_device *pdev) 957 { 958 struct sunxi_mmc_host *host; 959 struct mmc_host *mmc; 960 int ret; 961 962 mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 963 if (!mmc) { 964 dev_err(&pdev->dev, "mmc alloc host failed\n"); 965 return -ENOMEM; 966 } 967 968 host = mmc_priv(mmc); 969 host->mmc = mmc; 970 spin_lock_init(&host->lock); 971 972 ret = sunxi_mmc_resource_request(host, pdev); 973 if (ret) 974 goto error_free_host; 975 976 host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 977 &host->sg_dma, GFP_KERNEL); 978 if (!host->sg_cpu) { 979 dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 980 ret = -ENOMEM; 981 goto error_free_host; 982 } 983 984 mmc->ops = &sunxi_mmc_ops; 985 mmc->max_blk_count = 8192; 986 mmc->max_blk_size = 4096; 987 mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 988 mmc->max_seg_size = (1 << host->idma_des_size_bits); 989 mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 990 /* 400kHz ~ 50MHz */ 991 mmc->f_min = 400000; 992 mmc->f_max = 50000000; 993 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED; 994 995 ret = mmc_of_parse(mmc); 996 if (ret) 997 goto error_free_dma; 998 999 ret = mmc_add_host(mmc); 1000 if (ret) 1001 goto error_free_dma; 1002 1003 dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); 1004 platform_set_drvdata(pdev, mmc); 1005 return 0; 1006 1007 error_free_dma: 1008 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1009 error_free_host: 1010 mmc_free_host(mmc); 1011 return ret; 1012 } 1013 1014 static int sunxi_mmc_remove(struct platform_device *pdev) 1015 { 1016 struct mmc_host *mmc = platform_get_drvdata(pdev); 1017 struct sunxi_mmc_host *host = mmc_priv(mmc); 1018 1019 mmc_remove_host(mmc); 1020 disable_irq(host->irq); 1021 sunxi_mmc_reset_host(host); 1022 1023 if (!IS_ERR(host->reset)) 1024 reset_control_assert(host->reset); 1025 1026 clk_disable_unprepare(host->clk_mmc); 1027 clk_disable_unprepare(host->clk_ahb); 1028 1029 dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 1030 mmc_free_host(mmc); 1031 1032 return 0; 1033 } 1034 1035 static struct platform_driver sunxi_mmc_driver = { 1036 .driver = { 1037 .name = "sunxi-mmc", 1038 .owner = THIS_MODULE, 1039 .of_match_table = of_match_ptr(sunxi_mmc_of_match), 1040 }, 1041 .probe = sunxi_mmc_probe, 1042 .remove = sunxi_mmc_remove, 1043 }; 1044 module_platform_driver(sunxi_mmc_driver); 1045 1046 MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 1047 MODULE_LICENSE("GPL v2"); 1048 MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>"); 1049 MODULE_ALIAS("platform:sunxi-mmc"); 1050