13cbcb160SDavid Lanzendörfer /* 23cbcb160SDavid Lanzendörfer * Driver for sunxi SD/MMC host controllers 33cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 43cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 53cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 61907e386SAdam Borowski * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 73cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 84fb3ce07SMaxime Ripard * (C) Copyright 2017 Sootech SA 93cbcb160SDavid Lanzendörfer * 103cbcb160SDavid Lanzendörfer * This program is free software; you can redistribute it and/or 113cbcb160SDavid Lanzendörfer * modify it under the terms of the GNU General Public License as 123cbcb160SDavid Lanzendörfer * published by the Free Software Foundation; either version 2 of 133cbcb160SDavid Lanzendörfer * the License, or (at your option) any later version. 143cbcb160SDavid Lanzendörfer */ 153cbcb160SDavid Lanzendörfer 163cbcb160SDavid Lanzendörfer #include <linux/clk.h> 17ff39e7f7SChen-Yu Tsai #include <linux/clk/sunxi-ng.h> 18743b819eSMaxime Ripard #include <linux/delay.h> 19743b819eSMaxime Ripard #include <linux/device.h> 203cbcb160SDavid Lanzendörfer #include <linux/dma-mapping.h> 21743b819eSMaxime Ripard #include <linux/err.h> 22743b819eSMaxime Ripard #include <linux/gpio.h> 23743b819eSMaxime Ripard #include <linux/interrupt.h> 24743b819eSMaxime Ripard #include <linux/io.h> 25743b819eSMaxime Ripard #include <linux/kernel.h> 26743b819eSMaxime Ripard #include <linux/mmc/card.h> 27743b819eSMaxime Ripard #include <linux/mmc/core.h> 28743b819eSMaxime Ripard #include <linux/mmc/host.h> 29743b819eSMaxime Ripard #include <linux/mmc/mmc.h> 30743b819eSMaxime Ripard #include <linux/mmc/sd.h> 31743b819eSMaxime Ripard #include <linux/mmc/sdio.h> 32743b819eSMaxime Ripard #include <linux/mmc/slot-gpio.h> 33743b819eSMaxime Ripard #include <linux/module.h> 343cbcb160SDavid Lanzendörfer #include <linux/of_address.h> 353cbcb160SDavid Lanzendörfer #include <linux/of_gpio.h> 363cbcb160SDavid Lanzendörfer #include <linux/of_platform.h> 37743b819eSMaxime Ripard #include <linux/platform_device.h> 389a8e1e8cSMaxime Ripard #include <linux/pm_runtime.h> 39743b819eSMaxime Ripard #include <linux/regulator/consumer.h> 40743b819eSMaxime Ripard #include <linux/reset.h> 41743b819eSMaxime Ripard #include <linux/scatterlist.h> 42743b819eSMaxime Ripard #include <linux/slab.h> 43743b819eSMaxime Ripard #include <linux/spinlock.h> 443cbcb160SDavid Lanzendörfer 453cbcb160SDavid Lanzendörfer /* register offset definitions */ 463cbcb160SDavid Lanzendörfer #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 473cbcb160SDavid Lanzendörfer #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 483cbcb160SDavid Lanzendörfer #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 493cbcb160SDavid Lanzendörfer #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 503cbcb160SDavid Lanzendörfer #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 513cbcb160SDavid Lanzendörfer #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 523cbcb160SDavid Lanzendörfer #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 533cbcb160SDavid Lanzendörfer #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 543cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 553cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 563cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 573cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 583cbcb160SDavid Lanzendörfer #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 593cbcb160SDavid Lanzendörfer #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 603cbcb160SDavid Lanzendörfer #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 613cbcb160SDavid Lanzendörfer #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 623cbcb160SDavid Lanzendörfer #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 633cbcb160SDavid Lanzendörfer #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 643cbcb160SDavid Lanzendörfer #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 653cbcb160SDavid Lanzendörfer #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 663cbcb160SDavid Lanzendörfer #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 673cbcb160SDavid Lanzendörfer #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 683cbcb160SDavid Lanzendörfer #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 693cbcb160SDavid Lanzendörfer #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 703cbcb160SDavid Lanzendörfer #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 713cbcb160SDavid Lanzendörfer #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 723cbcb160SDavid Lanzendörfer #define SDXC_REG_CHDA (0x90) 733cbcb160SDavid Lanzendörfer #define SDXC_REG_CBDA (0x94) 743cbcb160SDavid Lanzendörfer 75e1b8dfd1SIcenowy Zheng /* New registers introduced in A64 */ 76e1b8dfd1SIcenowy Zheng #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 77e1b8dfd1SIcenowy Zheng #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 78e1b8dfd1SIcenowy Zheng #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 79e1b8dfd1SIcenowy Zheng #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 80e1b8dfd1SIcenowy Zheng #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 81e1b8dfd1SIcenowy Zheng 823cbcb160SDavid Lanzendörfer #define mmc_readl(host, reg) \ 833cbcb160SDavid Lanzendörfer readl((host)->reg_base + SDXC_##reg) 843cbcb160SDavid Lanzendörfer #define mmc_writel(host, reg, value) \ 853cbcb160SDavid Lanzendörfer writel((value), (host)->reg_base + SDXC_##reg) 863cbcb160SDavid Lanzendörfer 873cbcb160SDavid Lanzendörfer /* global control register bits */ 883cbcb160SDavid Lanzendörfer #define SDXC_SOFT_RESET BIT(0) 893cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RESET BIT(1) 903cbcb160SDavid Lanzendörfer #define SDXC_DMA_RESET BIT(2) 913cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 923cbcb160SDavid Lanzendörfer #define SDXC_DMA_ENABLE_BIT BIT(5) 933cbcb160SDavid Lanzendörfer #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 943cbcb160SDavid Lanzendörfer #define SDXC_POSEDGE_LATCH_DATA BIT(9) 953cbcb160SDavid Lanzendörfer #define SDXC_DDR_MODE BIT(10) 963cbcb160SDavid Lanzendörfer #define SDXC_MEMORY_ACCESS_DONE BIT(29) 973cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_DONE_DIRECT BIT(30) 983cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_AHB BIT(31) 993cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_DMA (0 << 31) 1003cbcb160SDavid Lanzendörfer #define SDXC_HARDWARE_RESET \ 1013cbcb160SDavid Lanzendörfer (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 1023cbcb160SDavid Lanzendörfer 1033cbcb160SDavid Lanzendörfer /* clock control bits */ 10416e821e3SMaxime Ripard #define SDXC_MASK_DATA0 BIT(31) 1053cbcb160SDavid Lanzendörfer #define SDXC_CARD_CLOCK_ON BIT(16) 1063cbcb160SDavid Lanzendörfer #define SDXC_LOW_POWER_ON BIT(17) 1073cbcb160SDavid Lanzendörfer 1083cbcb160SDavid Lanzendörfer /* bus width */ 1093cbcb160SDavid Lanzendörfer #define SDXC_WIDTH1 0 1103cbcb160SDavid Lanzendörfer #define SDXC_WIDTH4 1 1113cbcb160SDavid Lanzendörfer #define SDXC_WIDTH8 2 1123cbcb160SDavid Lanzendörfer 1133cbcb160SDavid Lanzendörfer /* smc command bits */ 1143cbcb160SDavid Lanzendörfer #define SDXC_RESP_EXPIRE BIT(6) 1153cbcb160SDavid Lanzendörfer #define SDXC_LONG_RESPONSE BIT(7) 1163cbcb160SDavid Lanzendörfer #define SDXC_CHECK_RESPONSE_CRC BIT(8) 1173cbcb160SDavid Lanzendörfer #define SDXC_DATA_EXPIRE BIT(9) 1183cbcb160SDavid Lanzendörfer #define SDXC_WRITE BIT(10) 1193cbcb160SDavid Lanzendörfer #define SDXC_SEQUENCE_MODE BIT(11) 1203cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOP BIT(12) 1213cbcb160SDavid Lanzendörfer #define SDXC_WAIT_PRE_OVER BIT(13) 1223cbcb160SDavid Lanzendörfer #define SDXC_STOP_ABORT_CMD BIT(14) 1233cbcb160SDavid Lanzendörfer #define SDXC_SEND_INIT_SEQUENCE BIT(15) 1243cbcb160SDavid Lanzendörfer #define SDXC_UPCLK_ONLY BIT(21) 1253cbcb160SDavid Lanzendörfer #define SDXC_READ_CEATA_DEV BIT(22) 1263cbcb160SDavid Lanzendörfer #define SDXC_CCS_EXPIRE BIT(23) 1273cbcb160SDavid Lanzendörfer #define SDXC_ENABLE_BIT_BOOT BIT(24) 1283cbcb160SDavid Lanzendörfer #define SDXC_ALT_BOOT_OPTIONS BIT(25) 1293cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ACK_EXPIRE BIT(26) 1303cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ABORT BIT(27) 1313cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_SWITCH BIT(28) 1323cbcb160SDavid Lanzendörfer #define SDXC_USE_HOLD_REGISTER BIT(29) 1333cbcb160SDavid Lanzendörfer #define SDXC_START BIT(31) 1343cbcb160SDavid Lanzendörfer 1353cbcb160SDavid Lanzendörfer /* interrupt bits */ 1363cbcb160SDavid Lanzendörfer #define SDXC_RESP_ERROR BIT(1) 1373cbcb160SDavid Lanzendörfer #define SDXC_COMMAND_DONE BIT(2) 1383cbcb160SDavid Lanzendörfer #define SDXC_DATA_OVER BIT(3) 1393cbcb160SDavid Lanzendörfer #define SDXC_TX_DATA_REQUEST BIT(4) 1403cbcb160SDavid Lanzendörfer #define SDXC_RX_DATA_REQUEST BIT(5) 1413cbcb160SDavid Lanzendörfer #define SDXC_RESP_CRC_ERROR BIT(6) 1423cbcb160SDavid Lanzendörfer #define SDXC_DATA_CRC_ERROR BIT(7) 1433cbcb160SDavid Lanzendörfer #define SDXC_RESP_TIMEOUT BIT(8) 1443cbcb160SDavid Lanzendörfer #define SDXC_DATA_TIMEOUT BIT(9) 1453cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 1463cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RUN_ERROR BIT(11) 1473cbcb160SDavid Lanzendörfer #define SDXC_HARD_WARE_LOCKED BIT(12) 1483cbcb160SDavid Lanzendörfer #define SDXC_START_BIT_ERROR BIT(13) 1493cbcb160SDavid Lanzendörfer #define SDXC_AUTO_COMMAND_DONE BIT(14) 1503cbcb160SDavid Lanzendörfer #define SDXC_END_BIT_ERROR BIT(15) 1513cbcb160SDavid Lanzendörfer #define SDXC_SDIO_INTERRUPT BIT(16) 1523cbcb160SDavid Lanzendörfer #define SDXC_CARD_INSERT BIT(30) 1533cbcb160SDavid Lanzendörfer #define SDXC_CARD_REMOVE BIT(31) 1543cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ERROR_BIT \ 1553cbcb160SDavid Lanzendörfer (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 1563cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 1573cbcb160SDavid Lanzendörfer SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 1583cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_DONE_BIT \ 1593cbcb160SDavid Lanzendörfer (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 1603cbcb160SDavid Lanzendörfer SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 1613cbcb160SDavid Lanzendörfer 1623cbcb160SDavid Lanzendörfer /* status */ 1633cbcb160SDavid Lanzendörfer #define SDXC_RXWL_FLAG BIT(0) 1643cbcb160SDavid Lanzendörfer #define SDXC_TXWL_FLAG BIT(1) 1653cbcb160SDavid Lanzendörfer #define SDXC_FIFO_EMPTY BIT(2) 1663cbcb160SDavid Lanzendörfer #define SDXC_FIFO_FULL BIT(3) 1673cbcb160SDavid Lanzendörfer #define SDXC_CARD_PRESENT BIT(8) 1683cbcb160SDavid Lanzendörfer #define SDXC_CARD_DATA_BUSY BIT(9) 1693cbcb160SDavid Lanzendörfer #define SDXC_DATA_FSM_BUSY BIT(10) 1703cbcb160SDavid Lanzendörfer #define SDXC_DMA_REQUEST BIT(31) 1713cbcb160SDavid Lanzendörfer #define SDXC_FIFO_SIZE 16 1723cbcb160SDavid Lanzendörfer 1733cbcb160SDavid Lanzendörfer /* Function select */ 1743cbcb160SDavid Lanzendörfer #define SDXC_CEATA_ON (0xceaa << 16) 1753cbcb160SDavid Lanzendörfer #define SDXC_SEND_IRQ_RESPONSE BIT(0) 1763cbcb160SDavid Lanzendörfer #define SDXC_SDIO_READ_WAIT BIT(1) 1773cbcb160SDavid Lanzendörfer #define SDXC_ABORT_READ_DATA BIT(2) 1783cbcb160SDavid Lanzendörfer #define SDXC_SEND_CCSD BIT(8) 1793cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 1803cbcb160SDavid Lanzendörfer #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 1813cbcb160SDavid Lanzendörfer 1823cbcb160SDavid Lanzendörfer /* IDMA controller bus mod bit field */ 1833cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SOFT_RESET BIT(0) 1843cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FIX_BURST BIT(1) 1853cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDMA_ON BIT(7) 1863cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_REFETCH_DES BIT(31) 1873cbcb160SDavid Lanzendörfer 1883cbcb160SDavid Lanzendörfer /* IDMA status bit field */ 1893cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 1903cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 1913cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 1923cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 1933cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 1943cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 1953cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 1963cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 1973cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDLE (0 << 13) 1983cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SUSPEND (1 << 13) 1993cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_READ (2 << 13) 2003cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CHECK (3 << 13) 2013cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 2023cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 2033cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ (6 << 13) 2043cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE (7 << 13) 2053cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 2063cbcb160SDavid Lanzendörfer 2073cbcb160SDavid Lanzendörfer /* 2083cbcb160SDavid Lanzendörfer * If the idma-des-size-bits of property is ie 13, bufsize bits are: 2093cbcb160SDavid Lanzendörfer * Bits 0-12: buf1 size 2103cbcb160SDavid Lanzendörfer * Bits 13-25: buf2 size 2113cbcb160SDavid Lanzendörfer * Bits 26-31: not used 2123cbcb160SDavid Lanzendörfer * Since we only ever set buf1 size, we can simply store it directly. 2133cbcb160SDavid Lanzendörfer */ 2143cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 2153cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 2163cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 2173cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 2183cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 2193cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 2203cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 2213cbcb160SDavid Lanzendörfer 22251424b28SHans de Goede #define SDXC_CLK_400K 0 22351424b28SHans de Goede #define SDXC_CLK_25M 1 22451424b28SHans de Goede #define SDXC_CLK_50M 2 22551424b28SHans de Goede #define SDXC_CLK_50M_DDR 3 2262a7aa63aSChen-Yu Tsai #define SDXC_CLK_50M_DDR_8BIT 4 22751424b28SHans de Goede 228e1b8dfd1SIcenowy Zheng #define SDXC_2X_TIMING_MODE BIT(31) 229e1b8dfd1SIcenowy Zheng 230e1b8dfd1SIcenowy Zheng #define SDXC_CAL_START BIT(15) 231e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DONE BIT(14) 232e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SHIFT 8 233e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_EN BIT(7) 234e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_SHIFT 0 235e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_MASK 0x3f 236e1b8dfd1SIcenowy Zheng 237e1b8dfd1SIcenowy Zheng #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 238e1b8dfd1SIcenowy Zheng 23951424b28SHans de Goede struct sunxi_mmc_clk_delay { 24051424b28SHans de Goede u32 output; 24151424b28SHans de Goede u32 sample; 24251424b28SHans de Goede }; 24351424b28SHans de Goede 2443cbcb160SDavid Lanzendörfer struct sunxi_idma_des { 2452dd110b2SMichael Weiser __le32 config; 2462dd110b2SMichael Weiser __le32 buf_size; 2472dd110b2SMichael Weiser __le32 buf_addr_ptr1; 2482dd110b2SMichael Weiser __le32 buf_addr_ptr2; 2493cbcb160SDavid Lanzendörfer }; 2503cbcb160SDavid Lanzendörfer 25186a93317SHans de Goede struct sunxi_mmc_cfg { 25286a93317SHans de Goede u32 idma_des_size_bits; 25386a93317SHans de Goede const struct sunxi_mmc_clk_delay *clk_delays; 254e1b8dfd1SIcenowy Zheng 255e1b8dfd1SIcenowy Zheng /* does the IP block support autocalibration? */ 256e1b8dfd1SIcenowy Zheng bool can_calibrate; 2579a37e53eSMaxime Ripard 25816e821e3SMaxime Ripard /* Does DATA0 needs to be masked while the clock is updated */ 25916e821e3SMaxime Ripard bool mask_data0; 26016e821e3SMaxime Ripard 2611ff9cabdSChen-Yu Tsai /* 2621ff9cabdSChen-Yu Tsai * hardware only supports new timing mode, either due to lack of 2631ff9cabdSChen-Yu Tsai * a mode switch in the clock controller, or the mmc controller 2641ff9cabdSChen-Yu Tsai * is permanently configured in the new timing mode, without the 2651ff9cabdSChen-Yu Tsai * NTSR mode switch. 2661ff9cabdSChen-Yu Tsai */ 2679a37e53eSMaxime Ripard bool needs_new_timings; 268ff39e7f7SChen-Yu Tsai 2691ff9cabdSChen-Yu Tsai /* clock hardware can switch between old and new timing modes */ 2701ff9cabdSChen-Yu Tsai bool ccu_has_timings_switch; 27186a93317SHans de Goede }; 27286a93317SHans de Goede 2733cbcb160SDavid Lanzendörfer struct sunxi_mmc_host { 274774c0103SMaxime Ripard struct device *dev; 2753cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 2763cbcb160SDavid Lanzendörfer struct reset_control *reset; 27786a93317SHans de Goede const struct sunxi_mmc_cfg *cfg; 2783cbcb160SDavid Lanzendörfer 2793cbcb160SDavid Lanzendörfer /* IO mapping base */ 2803cbcb160SDavid Lanzendörfer void __iomem *reg_base; 2813cbcb160SDavid Lanzendörfer 2823cbcb160SDavid Lanzendörfer /* clock management */ 2833cbcb160SDavid Lanzendörfer struct clk *clk_ahb; 2843cbcb160SDavid Lanzendörfer struct clk *clk_mmc; 2856c09bb85SMaxime Ripard struct clk *clk_sample; 2866c09bb85SMaxime Ripard struct clk *clk_output; 2873cbcb160SDavid Lanzendörfer 2883cbcb160SDavid Lanzendörfer /* irq */ 2893cbcb160SDavid Lanzendörfer spinlock_t lock; 2903cbcb160SDavid Lanzendörfer int irq; 2913cbcb160SDavid Lanzendörfer u32 int_sum; 2923cbcb160SDavid Lanzendörfer u32 sdio_imask; 2933cbcb160SDavid Lanzendörfer 2943cbcb160SDavid Lanzendörfer /* dma */ 2953cbcb160SDavid Lanzendörfer dma_addr_t sg_dma; 2963cbcb160SDavid Lanzendörfer void *sg_cpu; 2973cbcb160SDavid Lanzendörfer bool wait_dma; 2983cbcb160SDavid Lanzendörfer 2993cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 3003cbcb160SDavid Lanzendörfer struct mmc_request *manual_stop_mrq; 3013cbcb160SDavid Lanzendörfer int ferror; 302f771f6e8SChen-Yu Tsai 303f771f6e8SChen-Yu Tsai /* vqmmc */ 304f771f6e8SChen-Yu Tsai bool vqmmc_enabled; 305ff39e7f7SChen-Yu Tsai 306ff39e7f7SChen-Yu Tsai /* timings */ 307ff39e7f7SChen-Yu Tsai bool use_new_timings; 3083cbcb160SDavid Lanzendörfer }; 3093cbcb160SDavid Lanzendörfer 3103cbcb160SDavid Lanzendörfer static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 3113cbcb160SDavid Lanzendörfer { 3123cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(250); 3133cbcb160SDavid Lanzendörfer u32 rval; 3143cbcb160SDavid Lanzendörfer 3150f0fcd37SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 3163cbcb160SDavid Lanzendörfer do { 3173cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3183cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 3193cbcb160SDavid Lanzendörfer 3203cbcb160SDavid Lanzendörfer if (rval & SDXC_HARDWARE_RESET) { 3213cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 3223cbcb160SDavid Lanzendörfer return -EIO; 3233cbcb160SDavid Lanzendörfer } 3243cbcb160SDavid Lanzendörfer 3253cbcb160SDavid Lanzendörfer return 0; 3263cbcb160SDavid Lanzendörfer } 3273cbcb160SDavid Lanzendörfer 3280fc4c61fSMaxime Ripard static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) 3293cbcb160SDavid Lanzendörfer { 3303cbcb160SDavid Lanzendörfer u32 rval; 3313cbcb160SDavid Lanzendörfer 3323cbcb160SDavid Lanzendörfer if (sunxi_mmc_reset_host(host)) 3333cbcb160SDavid Lanzendörfer return -EIO; 3343cbcb160SDavid Lanzendörfer 3350314cbd4SChen-Yu Tsai /* 3360314cbd4SChen-Yu Tsai * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 3370314cbd4SChen-Yu Tsai * 3380314cbd4SChen-Yu Tsai * TODO: sun9i has a larger FIFO and supports higher trigger values 3390314cbd4SChen-Yu Tsai */ 3403cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FTRGL, 0x20070008); 3410314cbd4SChen-Yu Tsai /* Maximum timeout value */ 3423cbcb160SDavid Lanzendörfer mmc_writel(host, REG_TMOUT, 0xffffffff); 3430314cbd4SChen-Yu Tsai /* Unmask SDIO interrupt if needed */ 3443cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 3450314cbd4SChen-Yu Tsai /* Clear all pending interrupts */ 3463cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffffffff); 3470314cbd4SChen-Yu Tsai /* Debug register? undocumented */ 3483cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DBGC, 0xdeb); 3490314cbd4SChen-Yu Tsai /* Enable CEATA support */ 3503cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 3510314cbd4SChen-Yu Tsai /* Set DMA descriptor list base address */ 3523cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DLBA, host->sg_dma); 3533cbcb160SDavid Lanzendörfer 3543cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3553cbcb160SDavid Lanzendörfer rval |= SDXC_INTERRUPT_ENABLE_BIT; 3560314cbd4SChen-Yu Tsai /* Undocumented, but found in Allwinner code */ 3573cbcb160SDavid Lanzendörfer rval &= ~SDXC_ACCESS_DONE_DIRECT; 3583cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 3593cbcb160SDavid Lanzendörfer 3603cbcb160SDavid Lanzendörfer return 0; 3613cbcb160SDavid Lanzendörfer } 3623cbcb160SDavid Lanzendörfer 3633cbcb160SDavid Lanzendörfer static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 3643cbcb160SDavid Lanzendörfer struct mmc_data *data) 3653cbcb160SDavid Lanzendörfer { 3663cbcb160SDavid Lanzendörfer struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 367d34712d2SArnd Bergmann dma_addr_t next_desc = host->sg_dma; 36886a93317SHans de Goede int i, max_len = (1 << host->cfg->idma_des_size_bits); 3693cbcb160SDavid Lanzendörfer 3703cbcb160SDavid Lanzendörfer for (i = 0; i < data->sg_len; i++) { 3712dd110b2SMichael Weiser pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 3722dd110b2SMichael Weiser SDXC_IDMAC_DES0_OWN | 3732dd110b2SMichael Weiser SDXC_IDMAC_DES0_DIC); 3743cbcb160SDavid Lanzendörfer 3753cbcb160SDavid Lanzendörfer if (data->sg[i].length == max_len) 3763cbcb160SDavid Lanzendörfer pdes[i].buf_size = 0; /* 0 == max_len */ 3773cbcb160SDavid Lanzendörfer else 3782dd110b2SMichael Weiser pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 3793cbcb160SDavid Lanzendörfer 380d34712d2SArnd Bergmann next_desc += sizeof(struct sunxi_idma_des); 3812dd110b2SMichael Weiser pdes[i].buf_addr_ptr1 = 3822dd110b2SMichael Weiser cpu_to_le32(sg_dma_address(&data->sg[i])); 3832dd110b2SMichael Weiser pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); 3843cbcb160SDavid Lanzendörfer } 3853cbcb160SDavid Lanzendörfer 3862dd110b2SMichael Weiser pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 3872dd110b2SMichael Weiser pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 3882dd110b2SMichael Weiser SDXC_IDMAC_DES0_ER); 3892dd110b2SMichael Weiser pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 390e8a59049SHans de Goede pdes[i - 1].buf_addr_ptr2 = 0; 3913cbcb160SDavid Lanzendörfer 3923cbcb160SDavid Lanzendörfer /* 3933cbcb160SDavid Lanzendörfer * Avoid the io-store starting the idmac hitting io-mem before the 3943cbcb160SDavid Lanzendörfer * descriptors hit the main-mem. 3953cbcb160SDavid Lanzendörfer */ 3963cbcb160SDavid Lanzendörfer wmb(); 3973cbcb160SDavid Lanzendörfer } 3983cbcb160SDavid Lanzendörfer 3993cbcb160SDavid Lanzendörfer static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 4003cbcb160SDavid Lanzendörfer struct mmc_data *data) 4013cbcb160SDavid Lanzendörfer { 4023cbcb160SDavid Lanzendörfer u32 i, dma_len; 4033cbcb160SDavid Lanzendörfer struct scatterlist *sg; 4043cbcb160SDavid Lanzendörfer 4053cbcb160SDavid Lanzendörfer dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 406feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 4073cbcb160SDavid Lanzendörfer if (dma_len == 0) { 4083cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 4093cbcb160SDavid Lanzendörfer return -ENOMEM; 4103cbcb160SDavid Lanzendörfer } 4113cbcb160SDavid Lanzendörfer 4123cbcb160SDavid Lanzendörfer for_each_sg(data->sg, sg, data->sg_len, i) { 4133cbcb160SDavid Lanzendörfer if (sg->offset & 3 || sg->length & 3) { 4143cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), 4153cbcb160SDavid Lanzendörfer "unaligned scatterlist: os %x length %d\n", 4163cbcb160SDavid Lanzendörfer sg->offset, sg->length); 4173cbcb160SDavid Lanzendörfer return -EINVAL; 4183cbcb160SDavid Lanzendörfer } 4193cbcb160SDavid Lanzendörfer } 4203cbcb160SDavid Lanzendörfer 4213cbcb160SDavid Lanzendörfer return 0; 4223cbcb160SDavid Lanzendörfer } 4233cbcb160SDavid Lanzendörfer 4243cbcb160SDavid Lanzendörfer static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 4253cbcb160SDavid Lanzendörfer struct mmc_data *data) 4263cbcb160SDavid Lanzendörfer { 4273cbcb160SDavid Lanzendörfer u32 rval; 4283cbcb160SDavid Lanzendörfer 4293cbcb160SDavid Lanzendörfer sunxi_mmc_init_idma_des(host, data); 4303cbcb160SDavid Lanzendörfer 4313cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 4323cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_ENABLE_BIT; 4333cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4343cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 4353cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4363cbcb160SDavid Lanzendörfer 4373cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 4383cbcb160SDavid Lanzendörfer 4393cbcb160SDavid Lanzendörfer if (!(data->flags & MMC_DATA_WRITE)) 4403cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 4413cbcb160SDavid Lanzendörfer 4423cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 4433cbcb160SDavid Lanzendörfer SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 4443cbcb160SDavid Lanzendörfer } 4453cbcb160SDavid Lanzendörfer 4463cbcb160SDavid Lanzendörfer static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 4473cbcb160SDavid Lanzendörfer struct mmc_request *req) 4483cbcb160SDavid Lanzendörfer { 4493cbcb160SDavid Lanzendörfer u32 arg, cmd_val, ri; 4503cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(1000); 4513cbcb160SDavid Lanzendörfer 4523cbcb160SDavid Lanzendörfer cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 4533cbcb160SDavid Lanzendörfer SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 4543cbcb160SDavid Lanzendörfer 4553cbcb160SDavid Lanzendörfer if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 4563cbcb160SDavid Lanzendörfer cmd_val |= SD_IO_RW_DIRECT; 4573cbcb160SDavid Lanzendörfer arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 4583cbcb160SDavid Lanzendörfer ((req->cmd->arg >> 28) & 0x7); 4593cbcb160SDavid Lanzendörfer } else { 4603cbcb160SDavid Lanzendörfer cmd_val |= MMC_STOP_TRANSMISSION; 4613cbcb160SDavid Lanzendörfer arg = 0; 4623cbcb160SDavid Lanzendörfer } 4633cbcb160SDavid Lanzendörfer 4643cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, arg); 4653cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 4663cbcb160SDavid Lanzendörfer 4673cbcb160SDavid Lanzendörfer do { 4683cbcb160SDavid Lanzendörfer ri = mmc_readl(host, REG_RINTR); 4693cbcb160SDavid Lanzendörfer } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 4703cbcb160SDavid Lanzendörfer time_before(jiffies, expire)); 4713cbcb160SDavid Lanzendörfer 4723cbcb160SDavid Lanzendörfer if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 4733cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 4743cbcb160SDavid Lanzendörfer if (req->stop) 4753cbcb160SDavid Lanzendörfer req->stop->resp[0] = -ETIMEDOUT; 4763cbcb160SDavid Lanzendörfer } else { 4773cbcb160SDavid Lanzendörfer if (req->stop) 4783cbcb160SDavid Lanzendörfer req->stop->resp[0] = mmc_readl(host, REG_RESP0); 4793cbcb160SDavid Lanzendörfer } 4803cbcb160SDavid Lanzendörfer 4813cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 4823cbcb160SDavid Lanzendörfer } 4833cbcb160SDavid Lanzendörfer 4843cbcb160SDavid Lanzendörfer static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 4853cbcb160SDavid Lanzendörfer { 4863cbcb160SDavid Lanzendörfer struct mmc_command *cmd = host->mrq->cmd; 4873cbcb160SDavid Lanzendörfer struct mmc_data *data = host->mrq->data; 4883cbcb160SDavid Lanzendörfer 4893cbcb160SDavid Lanzendörfer /* For some cmds timeout is normal with sd/mmc cards */ 4903cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 4913cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 4923cbcb160SDavid Lanzendörfer cmd->opcode == SD_IO_RW_DIRECT)) 4933cbcb160SDavid Lanzendörfer return; 4943cbcb160SDavid Lanzendörfer 495bd675698SIcenowy Zheng dev_dbg(mmc_dev(host->mmc), 4963cbcb160SDavid Lanzendörfer "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 4973cbcb160SDavid Lanzendörfer host->mmc->index, cmd->opcode, 4983cbcb160SDavid Lanzendörfer data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 4993cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 5003cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 5013cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 5023cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 5033cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 5043cbcb160SDavid Lanzendörfer host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 5053cbcb160SDavid Lanzendörfer host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 5063cbcb160SDavid Lanzendörfer host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 5073cbcb160SDavid Lanzendörfer host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 5083cbcb160SDavid Lanzendörfer ); 5093cbcb160SDavid Lanzendörfer } 5103cbcb160SDavid Lanzendörfer 5113cbcb160SDavid Lanzendörfer /* Called in interrupt context! */ 5123cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 5133cbcb160SDavid Lanzendörfer { 5143cbcb160SDavid Lanzendörfer struct mmc_request *mrq = host->mrq; 5153cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 5163cbcb160SDavid Lanzendörfer u32 rval; 5173cbcb160SDavid Lanzendörfer 5183cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 5193cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, 0); 5203cbcb160SDavid Lanzendörfer 5213cbcb160SDavid Lanzendörfer if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 5223cbcb160SDavid Lanzendörfer sunxi_mmc_dump_errinfo(host); 5233cbcb160SDavid Lanzendörfer mrq->cmd->error = -ETIMEDOUT; 5243cbcb160SDavid Lanzendörfer 5253cbcb160SDavid Lanzendörfer if (data) { 5263cbcb160SDavid Lanzendörfer data->error = -ETIMEDOUT; 5273cbcb160SDavid Lanzendörfer host->manual_stop_mrq = mrq; 5283cbcb160SDavid Lanzendörfer } 5293cbcb160SDavid Lanzendörfer 5303cbcb160SDavid Lanzendörfer if (mrq->stop) 5313cbcb160SDavid Lanzendörfer mrq->stop->error = -ETIMEDOUT; 5323cbcb160SDavid Lanzendörfer } else { 5333cbcb160SDavid Lanzendörfer if (mrq->cmd->flags & MMC_RSP_136) { 5343cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 5353cbcb160SDavid Lanzendörfer mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 5363cbcb160SDavid Lanzendörfer mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 5373cbcb160SDavid Lanzendörfer mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 5383cbcb160SDavid Lanzendörfer } else { 5393cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 5403cbcb160SDavid Lanzendörfer } 5413cbcb160SDavid Lanzendörfer 5423cbcb160SDavid Lanzendörfer if (data) 5433cbcb160SDavid Lanzendörfer data->bytes_xfered = data->blocks * data->blksz; 5443cbcb160SDavid Lanzendörfer } 5453cbcb160SDavid Lanzendörfer 5463cbcb160SDavid Lanzendörfer if (data) { 5473cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, 0x337); 5483cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 0); 5493cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 5503cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 5513cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5523cbcb160SDavid Lanzendörfer rval &= ~SDXC_DMA_ENABLE_BIT; 5533cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5543cbcb160SDavid Lanzendörfer rval |= SDXC_FIFO_RESET; 5553cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5563cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 557feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 5583cbcb160SDavid Lanzendörfer } 5593cbcb160SDavid Lanzendörfer 5603cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 5613cbcb160SDavid Lanzendörfer 5623cbcb160SDavid Lanzendörfer host->mrq = NULL; 5633cbcb160SDavid Lanzendörfer host->int_sum = 0; 5643cbcb160SDavid Lanzendörfer host->wait_dma = false; 5653cbcb160SDavid Lanzendörfer 5663cbcb160SDavid Lanzendörfer return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 5673cbcb160SDavid Lanzendörfer } 5683cbcb160SDavid Lanzendörfer 5693cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 5703cbcb160SDavid Lanzendörfer { 5713cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 5723cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 5733cbcb160SDavid Lanzendörfer u32 msk_int, idma_int; 5743cbcb160SDavid Lanzendörfer bool finalize = false; 5753cbcb160SDavid Lanzendörfer bool sdio_int = false; 5763cbcb160SDavid Lanzendörfer irqreturn_t ret = IRQ_HANDLED; 5773cbcb160SDavid Lanzendörfer 5783cbcb160SDavid Lanzendörfer spin_lock(&host->lock); 5793cbcb160SDavid Lanzendörfer 5803cbcb160SDavid Lanzendörfer idma_int = mmc_readl(host, REG_IDST); 5813cbcb160SDavid Lanzendörfer msk_int = mmc_readl(host, REG_MISTA); 5823cbcb160SDavid Lanzendörfer 5833cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 5843cbcb160SDavid Lanzendörfer host->mrq, msk_int, idma_int); 5853cbcb160SDavid Lanzendörfer 5863cbcb160SDavid Lanzendörfer mrq = host->mrq; 5873cbcb160SDavid Lanzendörfer if (mrq) { 5883cbcb160SDavid Lanzendörfer if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 5893cbcb160SDavid Lanzendörfer host->wait_dma = false; 5903cbcb160SDavid Lanzendörfer 5913cbcb160SDavid Lanzendörfer host->int_sum |= msk_int; 5923cbcb160SDavid Lanzendörfer 5933cbcb160SDavid Lanzendörfer /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 5943cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_RESP_TIMEOUT) && 5953cbcb160SDavid Lanzendörfer !(host->int_sum & SDXC_COMMAND_DONE)) 5963cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, 5973cbcb160SDavid Lanzendörfer host->sdio_imask | SDXC_COMMAND_DONE); 5983cbcb160SDavid Lanzendörfer /* Don't wait for dma on error */ 5993cbcb160SDavid Lanzendörfer else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 6003cbcb160SDavid Lanzendörfer finalize = true; 6013cbcb160SDavid Lanzendörfer else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 6023cbcb160SDavid Lanzendörfer !host->wait_dma) 6033cbcb160SDavid Lanzendörfer finalize = true; 6043cbcb160SDavid Lanzendörfer } 6053cbcb160SDavid Lanzendörfer 6063cbcb160SDavid Lanzendörfer if (msk_int & SDXC_SDIO_INTERRUPT) 6073cbcb160SDavid Lanzendörfer sdio_int = true; 6083cbcb160SDavid Lanzendörfer 6093cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, msk_int); 6103cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, idma_int); 6113cbcb160SDavid Lanzendörfer 6123cbcb160SDavid Lanzendörfer if (finalize) 6133cbcb160SDavid Lanzendörfer ret = sunxi_mmc_finalize_request(host); 6143cbcb160SDavid Lanzendörfer 6153cbcb160SDavid Lanzendörfer spin_unlock(&host->lock); 6163cbcb160SDavid Lanzendörfer 6173cbcb160SDavid Lanzendörfer if (finalize && ret == IRQ_HANDLED) 6183cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6193cbcb160SDavid Lanzendörfer 6203cbcb160SDavid Lanzendörfer if (sdio_int) 6213cbcb160SDavid Lanzendörfer mmc_signal_sdio_irq(host->mmc); 6223cbcb160SDavid Lanzendörfer 6233cbcb160SDavid Lanzendörfer return ret; 6243cbcb160SDavid Lanzendörfer } 6253cbcb160SDavid Lanzendörfer 6263cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 6273cbcb160SDavid Lanzendörfer { 6283cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 6293cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 6303cbcb160SDavid Lanzendörfer unsigned long iflags; 6313cbcb160SDavid Lanzendörfer 6323cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6333cbcb160SDavid Lanzendörfer mrq = host->manual_stop_mrq; 6343cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6353cbcb160SDavid Lanzendörfer 6363cbcb160SDavid Lanzendörfer if (!mrq) { 6373cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 6383cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6393cbcb160SDavid Lanzendörfer } 6403cbcb160SDavid Lanzendörfer 6413cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 642dd9b3803SDavid Lanzendörfer 643dd9b3803SDavid Lanzendörfer /* 644dd9b3803SDavid Lanzendörfer * We will never have more than one outstanding request, 645dd9b3803SDavid Lanzendörfer * and we do not complete the request until after 646dd9b3803SDavid Lanzendörfer * we've cleared host->manual_stop_mrq so we do not need to 647dd9b3803SDavid Lanzendörfer * spin lock this function. 648dd9b3803SDavid Lanzendörfer * Additionally we have wait states within this function 649dd9b3803SDavid Lanzendörfer * so having it in a lock is a very bad idea. 650dd9b3803SDavid Lanzendörfer */ 6513cbcb160SDavid Lanzendörfer sunxi_mmc_send_manual_stop(host, mrq); 6523cbcb160SDavid Lanzendörfer 6533cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6543cbcb160SDavid Lanzendörfer host->manual_stop_mrq = NULL; 6553cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6563cbcb160SDavid Lanzendörfer 6573cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6583cbcb160SDavid Lanzendörfer 6593cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6603cbcb160SDavid Lanzendörfer } 6613cbcb160SDavid Lanzendörfer 6623cbcb160SDavid Lanzendörfer static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 6633cbcb160SDavid Lanzendörfer { 6647bb9c244SMichal Suchanek unsigned long expire = jiffies + msecs_to_jiffies(750); 6653cbcb160SDavid Lanzendörfer u32 rval; 6663cbcb160SDavid Lanzendörfer 66743c15e96SMaxime Ripard dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 66843c15e96SMaxime Ripard oclk_en ? "en" : "dis"); 66943c15e96SMaxime Ripard 6703cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 67116e821e3SMaxime Ripard rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 6723cbcb160SDavid Lanzendörfer 6733cbcb160SDavid Lanzendörfer if (oclk_en) 6743cbcb160SDavid Lanzendörfer rval |= SDXC_CARD_CLOCK_ON; 67516e821e3SMaxime Ripard if (host->cfg->mask_data0) 67616e821e3SMaxime Ripard rval |= SDXC_MASK_DATA0; 6773cbcb160SDavid Lanzendörfer 6783cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 6793cbcb160SDavid Lanzendörfer 6803cbcb160SDavid Lanzendörfer rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 6813cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, rval); 6823cbcb160SDavid Lanzendörfer 6833cbcb160SDavid Lanzendörfer do { 6843cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CMDR); 6853cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_START)); 6863cbcb160SDavid Lanzendörfer 6873cbcb160SDavid Lanzendörfer /* clear irq status bits set by the command */ 6883cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 6893cbcb160SDavid Lanzendörfer mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 6903cbcb160SDavid Lanzendörfer 6913cbcb160SDavid Lanzendörfer if (rval & SDXC_START) { 6923cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 6933cbcb160SDavid Lanzendörfer return -EIO; 6943cbcb160SDavid Lanzendörfer } 6953cbcb160SDavid Lanzendörfer 69616e821e3SMaxime Ripard if (host->cfg->mask_data0) { 69716e821e3SMaxime Ripard rval = mmc_readl(host, REG_CLKCR); 69816e821e3SMaxime Ripard mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 69916e821e3SMaxime Ripard } 70016e821e3SMaxime Ripard 7013cbcb160SDavid Lanzendörfer return 0; 7023cbcb160SDavid Lanzendörfer } 7033cbcb160SDavid Lanzendörfer 704e1b8dfd1SIcenowy Zheng static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 705e1b8dfd1SIcenowy Zheng { 706e1b8dfd1SIcenowy Zheng if (!host->cfg->can_calibrate) 707e1b8dfd1SIcenowy Zheng return 0; 708e1b8dfd1SIcenowy Zheng 709860fdf89SMaxime Ripard /* 710860fdf89SMaxime Ripard * FIXME: 711860fdf89SMaxime Ripard * This is not clear how the calibration is supposed to work 712860fdf89SMaxime Ripard * yet. The best rate have been obtained by simply setting the 713860fdf89SMaxime Ripard * delay to 0, as Allwinner does in its BSP. 714860fdf89SMaxime Ripard * 715860fdf89SMaxime Ripard * The only mode that doesn't have such a delay is HS400, that 716860fdf89SMaxime Ripard * is in itself a TODO. 717860fdf89SMaxime Ripard */ 718860fdf89SMaxime Ripard writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 719e1b8dfd1SIcenowy Zheng 720e1b8dfd1SIcenowy Zheng return 0; 721e1b8dfd1SIcenowy Zheng } 722e1b8dfd1SIcenowy Zheng 723f2cecb70SHans de Goede static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 724f2cecb70SHans de Goede struct mmc_ios *ios, u32 rate) 725f2cecb70SHans de Goede { 726f2cecb70SHans de Goede int index; 727f2cecb70SHans de Goede 728a6461134SChen-Yu Tsai /* clk controller delays not used under new timings mode */ 729ff39e7f7SChen-Yu Tsai if (host->use_new_timings) 730b465646eSHans de Goede return 0; 731b465646eSHans de Goede 732a6461134SChen-Yu Tsai /* some old controllers don't support delays */ 733a6461134SChen-Yu Tsai if (!host->cfg->clk_delays) 734a6461134SChen-Yu Tsai return 0; 735a6461134SChen-Yu Tsai 736f2cecb70SHans de Goede /* determine delays */ 737f2cecb70SHans de Goede if (rate <= 400000) { 738f2cecb70SHans de Goede index = SDXC_CLK_400K; 739f2cecb70SHans de Goede } else if (rate <= 25000000) { 740f2cecb70SHans de Goede index = SDXC_CLK_25M; 741f2cecb70SHans de Goede } else if (rate <= 52000000) { 742f2cecb70SHans de Goede if (ios->timing != MMC_TIMING_UHS_DDR50 && 743f2cecb70SHans de Goede ios->timing != MMC_TIMING_MMC_DDR52) { 744f2cecb70SHans de Goede index = SDXC_CLK_50M; 745f2cecb70SHans de Goede } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 746f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR_8BIT; 747f2cecb70SHans de Goede } else { 748f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR; 749f2cecb70SHans de Goede } 750f2cecb70SHans de Goede } else { 75143c15e96SMaxime Ripard dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 752f2cecb70SHans de Goede return -EINVAL; 753f2cecb70SHans de Goede } 754f2cecb70SHans de Goede 755f2cecb70SHans de Goede clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 756f2cecb70SHans de Goede clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 757f2cecb70SHans de Goede 758f2cecb70SHans de Goede return 0; 759f2cecb70SHans de Goede } 760f2cecb70SHans de Goede 7613cbcb160SDavid Lanzendörfer static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 7623cbcb160SDavid Lanzendörfer struct mmc_ios *ios) 7633cbcb160SDavid Lanzendörfer { 76443c15e96SMaxime Ripard struct mmc_host *mmc = host->mmc; 76563311becSJean-Francois Moine long rate; 766c903a2aeSChen-Yu Tsai u32 rval, clock = ios->clock, div = 1; 7673cbcb160SDavid Lanzendörfer int ret; 7683cbcb160SDavid Lanzendörfer 76939cc281fSMaxime Ripard ret = sunxi_mmc_oclk_onoff(host, 0); 77039cc281fSMaxime Ripard if (ret) 77139cc281fSMaxime Ripard return ret; 77239cc281fSMaxime Ripard 77343c15e96SMaxime Ripard /* Our clock is gated now */ 77443c15e96SMaxime Ripard mmc->actual_clock = 0; 77543c15e96SMaxime Ripard 7769479074eSMaxime Ripard if (!ios->clock) 7779479074eSMaxime Ripard return 0; 7789479074eSMaxime Ripard 779c903a2aeSChen-Yu Tsai /* 780c903a2aeSChen-Yu Tsai * Under the old timing mode, 8 bit DDR requires the module 781c903a2aeSChen-Yu Tsai * clock to be double the card clock. Under the new timing 782c903a2aeSChen-Yu Tsai * mode, all DDR modes require a doubled module clock. 783c903a2aeSChen-Yu Tsai * 784c903a2aeSChen-Yu Tsai * We currently only support the standard MMC DDR52 mode. 785c903a2aeSChen-Yu Tsai * This block should be updated once support for other DDR 786c903a2aeSChen-Yu Tsai * modes is added. 787c903a2aeSChen-Yu Tsai */ 7882a7aa63aSChen-Yu Tsai if (ios->timing == MMC_TIMING_MMC_DDR52 && 789c903a2aeSChen-Yu Tsai (host->use_new_timings || 790c903a2aeSChen-Yu Tsai ios->bus_width == MMC_BUS_WIDTH_8)) { 791c903a2aeSChen-Yu Tsai div = 2; 7922a7aa63aSChen-Yu Tsai clock <<= 1; 793c903a2aeSChen-Yu Tsai } 7942a7aa63aSChen-Yu Tsai 7951ff9cabdSChen-Yu Tsai if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { 796ff39e7f7SChen-Yu Tsai ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 797ff39e7f7SChen-Yu Tsai if (ret) { 798ff39e7f7SChen-Yu Tsai dev_err(mmc_dev(mmc), 799ff39e7f7SChen-Yu Tsai "error setting new timing mode\n"); 800ff39e7f7SChen-Yu Tsai return ret; 801ff39e7f7SChen-Yu Tsai } 802ff39e7f7SChen-Yu Tsai } 803ff39e7f7SChen-Yu Tsai 8042a7aa63aSChen-Yu Tsai rate = clk_round_rate(host->clk_mmc, clock); 80563311becSJean-Francois Moine if (rate < 0) { 80643c15e96SMaxime Ripard dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 80763311becSJean-Francois Moine clock, rate); 80863311becSJean-Francois Moine return rate; 80963311becSJean-Francois Moine } 81043c15e96SMaxime Ripard dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 8112a7aa63aSChen-Yu Tsai clock, rate); 8123cbcb160SDavid Lanzendörfer 8133cbcb160SDavid Lanzendörfer /* setting clock rate */ 8143cbcb160SDavid Lanzendörfer ret = clk_set_rate(host->clk_mmc, rate); 8153cbcb160SDavid Lanzendörfer if (ret) { 81643c15e96SMaxime Ripard dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 8173cbcb160SDavid Lanzendörfer rate, ret); 8183cbcb160SDavid Lanzendörfer return ret; 8193cbcb160SDavid Lanzendörfer } 8203cbcb160SDavid Lanzendörfer 821c903a2aeSChen-Yu Tsai /* set internal divider */ 8223cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 8233cbcb160SDavid Lanzendörfer rval &= ~0xff; 824c903a2aeSChen-Yu Tsai rval |= div - 1; 8253cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 8263cbcb160SDavid Lanzendörfer 827082bb85fSChen-Yu Tsai /* update card clock rate to account for internal divider */ 828082bb85fSChen-Yu Tsai rate /= div; 829082bb85fSChen-Yu Tsai 8301ff9cabdSChen-Yu Tsai /* 8311ff9cabdSChen-Yu Tsai * Configure the controller to use the new timing mode if needed. 8321ff9cabdSChen-Yu Tsai * On controllers that only support the new timing mode, such as 8331ff9cabdSChen-Yu Tsai * the eMMC controller on the A64, this register does not exist, 8341ff9cabdSChen-Yu Tsai * and any writes to it are ignored. 8351ff9cabdSChen-Yu Tsai */ 836ff39e7f7SChen-Yu Tsai if (host->use_new_timings) { 83726cb2be4SChen-Yu Tsai /* Don't touch the delay bits */ 83826cb2be4SChen-Yu Tsai rval = mmc_readl(host, REG_SD_NTSR); 83926cb2be4SChen-Yu Tsai rval |= SDXC_2X_TIMING_MODE; 84026cb2be4SChen-Yu Tsai mmc_writel(host, REG_SD_NTSR, rval); 84126cb2be4SChen-Yu Tsai } 8429a37e53eSMaxime Ripard 843082bb85fSChen-Yu Tsai /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 844f2cecb70SHans de Goede ret = sunxi_mmc_clk_set_phase(host, ios, rate); 845f2cecb70SHans de Goede if (ret) 846f2cecb70SHans de Goede return ret; 8473cbcb160SDavid Lanzendörfer 848e1b8dfd1SIcenowy Zheng ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 849e1b8dfd1SIcenowy Zheng if (ret) 850e1b8dfd1SIcenowy Zheng return ret; 851e1b8dfd1SIcenowy Zheng 852860fdf89SMaxime Ripard /* 853860fdf89SMaxime Ripard * FIXME: 854860fdf89SMaxime Ripard * 855860fdf89SMaxime Ripard * In HS400 we'll also need to calibrate the data strobe 856860fdf89SMaxime Ripard * signal. This should only happen on the MMC2 controller (at 857860fdf89SMaxime Ripard * least on the A64). 858860fdf89SMaxime Ripard */ 859e1b8dfd1SIcenowy Zheng 86043c15e96SMaxime Ripard ret = sunxi_mmc_oclk_onoff(host, 1); 86143c15e96SMaxime Ripard if (ret) 86243c15e96SMaxime Ripard return ret; 86343c15e96SMaxime Ripard 86443c15e96SMaxime Ripard /* And we just enabled our clock back */ 865082bb85fSChen-Yu Tsai mmc->actual_clock = rate; 86643c15e96SMaxime Ripard 86743c15e96SMaxime Ripard return 0; 8683cbcb160SDavid Lanzendörfer } 8693cbcb160SDavid Lanzendörfer 8703f6c808eSMaxime Ripard static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, 8713f6c808eSMaxime Ripard unsigned char width) 8723f6c808eSMaxime Ripard { 8733f6c808eSMaxime Ripard switch (width) { 8743f6c808eSMaxime Ripard case MMC_BUS_WIDTH_1: 8753f6c808eSMaxime Ripard mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 8763f6c808eSMaxime Ripard break; 8773f6c808eSMaxime Ripard case MMC_BUS_WIDTH_4: 8783f6c808eSMaxime Ripard mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 8793f6c808eSMaxime Ripard break; 8803f6c808eSMaxime Ripard case MMC_BUS_WIDTH_8: 8813f6c808eSMaxime Ripard mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 8823f6c808eSMaxime Ripard break; 8833f6c808eSMaxime Ripard } 8843f6c808eSMaxime Ripard } 8853f6c808eSMaxime Ripard 886ad04d955SMaxime Ripard static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) 887ad04d955SMaxime Ripard { 888ad04d955SMaxime Ripard u32 rval; 889ad04d955SMaxime Ripard 890ad04d955SMaxime Ripard /* set ddr mode */ 891ad04d955SMaxime Ripard rval = mmc_readl(host, REG_GCTRL); 892ad04d955SMaxime Ripard if (ios->timing == MMC_TIMING_UHS_DDR50 || 893ad04d955SMaxime Ripard ios->timing == MMC_TIMING_MMC_DDR52) 894ad04d955SMaxime Ripard rval |= SDXC_DDR_MODE; 895ad04d955SMaxime Ripard else 896ad04d955SMaxime Ripard rval &= ~SDXC_DDR_MODE; 897ad04d955SMaxime Ripard mmc_writel(host, REG_GCTRL, rval); 898ad04d955SMaxime Ripard 899ad04d955SMaxime Ripard host->ferror = sunxi_mmc_clk_set_rate(host, ios); 900ad04d955SMaxime Ripard /* Android code had a usleep_range(50000, 55000); here */ 901ad04d955SMaxime Ripard } 902ad04d955SMaxime Ripard 903e27e1f3dSMaxime Ripard static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, 904e27e1f3dSMaxime Ripard struct mmc_ios *ios) 9053cbcb160SDavid Lanzendörfer { 906e27e1f3dSMaxime Ripard struct mmc_host *mmc = host->mmc; 9073cbcb160SDavid Lanzendörfer 9083cbcb160SDavid Lanzendörfer switch (ios->power_mode) { 9093cbcb160SDavid Lanzendörfer case MMC_POWER_UP: 910e27e1f3dSMaxime Ripard dev_dbg(mmc_dev(mmc), "Powering card up\n"); 911e27e1f3dSMaxime Ripard 912424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) { 913424feb59SMaxime Ripard host->ferror = mmc_regulator_set_ocr(mmc, 914424feb59SMaxime Ripard mmc->supply.vmmc, 9154159215aSChen-Yu Tsai ios->vdd); 9164159215aSChen-Yu Tsai if (host->ferror) 9174159215aSChen-Yu Tsai return; 918424feb59SMaxime Ripard } 9193cbcb160SDavid Lanzendörfer 920f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc)) { 921f771f6e8SChen-Yu Tsai host->ferror = regulator_enable(mmc->supply.vqmmc); 922f771f6e8SChen-Yu Tsai if (host->ferror) { 923f771f6e8SChen-Yu Tsai dev_err(mmc_dev(mmc), 924f771f6e8SChen-Yu Tsai "failed to enable vqmmc\n"); 925f771f6e8SChen-Yu Tsai return; 926f771f6e8SChen-Yu Tsai } 927f771f6e8SChen-Yu Tsai host->vqmmc_enabled = true; 928f771f6e8SChen-Yu Tsai } 9293cbcb160SDavid Lanzendörfer break; 9303cbcb160SDavid Lanzendörfer 9313cbcb160SDavid Lanzendörfer case MMC_POWER_OFF: 932e27e1f3dSMaxime Ripard dev_dbg(mmc_dev(mmc), "Powering card off\n"); 933e27e1f3dSMaxime Ripard 934424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) 9353cbcb160SDavid Lanzendörfer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 936424feb59SMaxime Ripard 937f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 938f771f6e8SChen-Yu Tsai regulator_disable(mmc->supply.vqmmc); 939e27e1f3dSMaxime Ripard 940f771f6e8SChen-Yu Tsai host->vqmmc_enabled = false; 9413cbcb160SDavid Lanzendörfer break; 942e27e1f3dSMaxime Ripard 943e27e1f3dSMaxime Ripard default: 944e27e1f3dSMaxime Ripard dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n"); 945e27e1f3dSMaxime Ripard break; 9463cbcb160SDavid Lanzendörfer } 947e27e1f3dSMaxime Ripard } 948e27e1f3dSMaxime Ripard 949e27e1f3dSMaxime Ripard static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 950e27e1f3dSMaxime Ripard { 951e27e1f3dSMaxime Ripard struct sunxi_mmc_host *host = mmc_priv(mmc); 952e27e1f3dSMaxime Ripard 953e27e1f3dSMaxime Ripard sunxi_mmc_card_power(host, ios); 9543f6c808eSMaxime Ripard sunxi_mmc_set_bus_width(host, ios->bus_width); 955ad04d955SMaxime Ripard sunxi_mmc_set_clk(host, ios); 9563cbcb160SDavid Lanzendörfer } 9573cbcb160SDavid Lanzendörfer 958f771f6e8SChen-Yu Tsai static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 959f771f6e8SChen-Yu Tsai { 960f771f6e8SChen-Yu Tsai /* vqmmc regulator is available */ 961f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc)) 962f771f6e8SChen-Yu Tsai return mmc_regulator_set_vqmmc(mmc, ios); 963f771f6e8SChen-Yu Tsai 964f771f6e8SChen-Yu Tsai /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 965f771f6e8SChen-Yu Tsai if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 966f771f6e8SChen-Yu Tsai return 0; 967f771f6e8SChen-Yu Tsai 968f771f6e8SChen-Yu Tsai return -EINVAL; 969f771f6e8SChen-Yu Tsai } 970f771f6e8SChen-Yu Tsai 9713cbcb160SDavid Lanzendörfer static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 9723cbcb160SDavid Lanzendörfer { 9733cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 9743cbcb160SDavid Lanzendörfer unsigned long flags; 9753cbcb160SDavid Lanzendörfer u32 imask; 9763cbcb160SDavid Lanzendörfer 9779a8e1e8cSMaxime Ripard if (enable) 9789a8e1e8cSMaxime Ripard pm_runtime_get_noresume(host->dev); 9799a8e1e8cSMaxime Ripard 9803cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, flags); 9813cbcb160SDavid Lanzendörfer 9823cbcb160SDavid Lanzendörfer imask = mmc_readl(host, REG_IMASK); 9833cbcb160SDavid Lanzendörfer if (enable) { 9843cbcb160SDavid Lanzendörfer host->sdio_imask = SDXC_SDIO_INTERRUPT; 9853cbcb160SDavid Lanzendörfer imask |= SDXC_SDIO_INTERRUPT; 9863cbcb160SDavid Lanzendörfer } else { 9873cbcb160SDavid Lanzendörfer host->sdio_imask = 0; 9883cbcb160SDavid Lanzendörfer imask &= ~SDXC_SDIO_INTERRUPT; 9893cbcb160SDavid Lanzendörfer } 9903cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, imask); 9913cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, flags); 9929a8e1e8cSMaxime Ripard 9939a8e1e8cSMaxime Ripard if (!enable) 9949a8e1e8cSMaxime Ripard pm_runtime_put_noidle(host->mmc->parent); 9953cbcb160SDavid Lanzendörfer } 9963cbcb160SDavid Lanzendörfer 9973cbcb160SDavid Lanzendörfer static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 9983cbcb160SDavid Lanzendörfer { 9993cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 10003cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 0); 10013cbcb160SDavid Lanzendörfer udelay(10); 10023cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 1); 10033cbcb160SDavid Lanzendörfer udelay(300); 10043cbcb160SDavid Lanzendörfer } 10053cbcb160SDavid Lanzendörfer 10063cbcb160SDavid Lanzendörfer static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 10073cbcb160SDavid Lanzendörfer { 10083cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 10093cbcb160SDavid Lanzendörfer struct mmc_command *cmd = mrq->cmd; 10103cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 10113cbcb160SDavid Lanzendörfer unsigned long iflags; 10123cbcb160SDavid Lanzendörfer u32 imask = SDXC_INTERRUPT_ERROR_BIT; 10133cbcb160SDavid Lanzendörfer u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 1014dd9b3803SDavid Lanzendörfer bool wait_dma = host->wait_dma; 10153cbcb160SDavid Lanzendörfer int ret; 10163cbcb160SDavid Lanzendörfer 10173cbcb160SDavid Lanzendörfer /* Check for set_ios errors (should never happen) */ 10183cbcb160SDavid Lanzendörfer if (host->ferror) { 10193cbcb160SDavid Lanzendörfer mrq->cmd->error = host->ferror; 10203cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10213cbcb160SDavid Lanzendörfer return; 10223cbcb160SDavid Lanzendörfer } 10233cbcb160SDavid Lanzendörfer 10243cbcb160SDavid Lanzendörfer if (data) { 10253cbcb160SDavid Lanzendörfer ret = sunxi_mmc_map_dma(host, data); 10263cbcb160SDavid Lanzendörfer if (ret < 0) { 10273cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "map DMA failed\n"); 10283cbcb160SDavid Lanzendörfer cmd->error = ret; 10293cbcb160SDavid Lanzendörfer data->error = ret; 10303cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10313cbcb160SDavid Lanzendörfer return; 10323cbcb160SDavid Lanzendörfer } 10333cbcb160SDavid Lanzendörfer } 10343cbcb160SDavid Lanzendörfer 10353cbcb160SDavid Lanzendörfer if (cmd->opcode == MMC_GO_IDLE_STATE) { 10363cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_INIT_SEQUENCE; 10373cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10383cbcb160SDavid Lanzendörfer } 10393cbcb160SDavid Lanzendörfer 10403cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_PRESENT) { 10413cbcb160SDavid Lanzendörfer cmd_val |= SDXC_RESP_EXPIRE; 10423cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_136) 10433cbcb160SDavid Lanzendörfer cmd_val |= SDXC_LONG_RESPONSE; 10443cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_CRC) 10453cbcb160SDavid Lanzendörfer cmd_val |= SDXC_CHECK_RESPONSE_CRC; 10463cbcb160SDavid Lanzendörfer 10473cbcb160SDavid Lanzendörfer if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 10483cbcb160SDavid Lanzendörfer cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 10493cbcb160SDavid Lanzendörfer 10503cbcb160SDavid Lanzendörfer if (cmd->data->stop) { 10513cbcb160SDavid Lanzendörfer imask |= SDXC_AUTO_COMMAND_DONE; 10523cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_AUTO_STOP; 10533cbcb160SDavid Lanzendörfer } else { 10543cbcb160SDavid Lanzendörfer imask |= SDXC_DATA_OVER; 10553cbcb160SDavid Lanzendörfer } 10563cbcb160SDavid Lanzendörfer 10573cbcb160SDavid Lanzendörfer if (cmd->data->flags & MMC_DATA_WRITE) 10583cbcb160SDavid Lanzendörfer cmd_val |= SDXC_WRITE; 10593cbcb160SDavid Lanzendörfer else 1060dd9b3803SDavid Lanzendörfer wait_dma = true; 10613cbcb160SDavid Lanzendörfer } else { 10623cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10633cbcb160SDavid Lanzendörfer } 10643cbcb160SDavid Lanzendörfer } else { 10653cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10663cbcb160SDavid Lanzendörfer } 10673cbcb160SDavid Lanzendörfer 10683cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 10693cbcb160SDavid Lanzendörfer cmd_val & 0x3f, cmd_val, cmd->arg, imask, 10703cbcb160SDavid Lanzendörfer mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 10713cbcb160SDavid Lanzendörfer 10723cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 10733cbcb160SDavid Lanzendörfer 10743cbcb160SDavid Lanzendörfer if (host->mrq || host->manual_stop_mrq) { 10753cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 10763cbcb160SDavid Lanzendörfer 10773cbcb160SDavid Lanzendörfer if (data) 10783cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1079feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 10803cbcb160SDavid Lanzendörfer 10813cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "request already pending\n"); 10823cbcb160SDavid Lanzendörfer mrq->cmd->error = -EBUSY; 10833cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10843cbcb160SDavid Lanzendörfer return; 10853cbcb160SDavid Lanzendörfer } 10863cbcb160SDavid Lanzendörfer 10873cbcb160SDavid Lanzendörfer if (data) { 10883cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BLKSZ, data->blksz); 10893cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 10903cbcb160SDavid Lanzendörfer sunxi_mmc_start_dma(host, data); 10913cbcb160SDavid Lanzendörfer } 10923cbcb160SDavid Lanzendörfer 10933cbcb160SDavid Lanzendörfer host->mrq = mrq; 1094dd9b3803SDavid Lanzendörfer host->wait_dma = wait_dma; 10953cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 10963cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, cmd->arg); 10973cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 10983cbcb160SDavid Lanzendörfer 10993cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 11003cbcb160SDavid Lanzendörfer } 11013cbcb160SDavid Lanzendörfer 1102c1590dd8SHans de Goede static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1103c1590dd8SHans de Goede { 1104c1590dd8SHans de Goede struct sunxi_mmc_host *host = mmc_priv(mmc); 1105c1590dd8SHans de Goede 1106c1590dd8SHans de Goede return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1107c1590dd8SHans de Goede } 1108c1590dd8SHans de Goede 11091f8029c3SJulia Lawall static const struct mmc_host_ops sunxi_mmc_ops = { 11103cbcb160SDavid Lanzendörfer .request = sunxi_mmc_request, 11113cbcb160SDavid Lanzendörfer .set_ios = sunxi_mmc_set_ios, 11123cbcb160SDavid Lanzendörfer .get_ro = mmc_gpio_get_ro, 11133cbcb160SDavid Lanzendörfer .get_cd = mmc_gpio_get_cd, 11143cbcb160SDavid Lanzendörfer .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1115f771f6e8SChen-Yu Tsai .start_signal_voltage_switch = sunxi_mmc_volt_switch, 11163cbcb160SDavid Lanzendörfer .hw_reset = sunxi_mmc_hw_reset, 1117c1590dd8SHans de Goede .card_busy = sunxi_mmc_card_busy, 11183cbcb160SDavid Lanzendörfer }; 11193cbcb160SDavid Lanzendörfer 112051424b28SHans de Goede static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 112151424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 112251424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 112351424b28SHans de Goede [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 112451424b28SHans de Goede [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 11252a7aa63aSChen-Yu Tsai /* Value from A83T "new timing mode". Works but might not be right. */ 11262a7aa63aSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 112751424b28SHans de Goede }; 112851424b28SHans de Goede 112951424b28SHans de Goede static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 113051424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 113151424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 113251424b28SHans de Goede [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 11330175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 11340175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 113551424b28SHans de Goede }; 113651424b28SHans de Goede 113786a93317SHans de Goede static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 113886a93317SHans de Goede .idma_des_size_bits = 13, 1139b465646eSHans de Goede .clk_delays = NULL, 1140e1b8dfd1SIcenowy Zheng .can_calibrate = false, 114186a93317SHans de Goede }; 114286a93317SHans de Goede 114386a93317SHans de Goede static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 114486a93317SHans de Goede .idma_des_size_bits = 16, 1145b465646eSHans de Goede .clk_delays = NULL, 1146e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1147b465646eSHans de Goede }; 1148b465646eSHans de Goede 1149b465646eSHans de Goede static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1150b465646eSHans de Goede .idma_des_size_bits = 16, 115186a93317SHans de Goede .clk_delays = sunxi_mmc_clk_delays, 1152e1b8dfd1SIcenowy Zheng .can_calibrate = false, 115386a93317SHans de Goede }; 115486a93317SHans de Goede 1155ac98caefSChen-Yu Tsai static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1156ac98caefSChen-Yu Tsai .idma_des_size_bits = 16, 1157ac98caefSChen-Yu Tsai .clk_delays = sunxi_mmc_clk_delays, 1158ac98caefSChen-Yu Tsai .can_calibrate = false, 11591ff9cabdSChen-Yu Tsai .ccu_has_timings_switch = true, 1160ac98caefSChen-Yu Tsai }; 1161ac98caefSChen-Yu Tsai 116286a93317SHans de Goede static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 116386a93317SHans de Goede .idma_des_size_bits = 16, 116486a93317SHans de Goede .clk_delays = sun9i_mmc_clk_delays, 1165e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1166e1b8dfd1SIcenowy Zheng }; 1167e1b8dfd1SIcenowy Zheng 1168e1b8dfd1SIcenowy Zheng static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1169e1b8dfd1SIcenowy Zheng .idma_des_size_bits = 16, 1170e1b8dfd1SIcenowy Zheng .clk_delays = NULL, 1171e1b8dfd1SIcenowy Zheng .can_calibrate = true, 117216e821e3SMaxime Ripard .mask_data0 = true, 11739a37e53eSMaxime Ripard .needs_new_timings = true, 117486a93317SHans de Goede }; 117586a93317SHans de Goede 11764fb3ce07SMaxime Ripard static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 11774fb3ce07SMaxime Ripard .idma_des_size_bits = 13, 11784fb3ce07SMaxime Ripard .clk_delays = NULL, 11794fb3ce07SMaxime Ripard .can_calibrate = true, 118007bafc1eSChen-Yu Tsai .needs_new_timings = true, 11814fb3ce07SMaxime Ripard }; 11824fb3ce07SMaxime Ripard 118386a93317SHans de Goede static const struct of_device_id sunxi_mmc_of_match[] = { 118486a93317SHans de Goede { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 118586a93317SHans de Goede { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1186b465646eSHans de Goede { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1187ac98caefSChen-Yu Tsai { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 118886a93317SHans de Goede { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1189e1b8dfd1SIcenowy Zheng { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 11904fb3ce07SMaxime Ripard { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 119186a93317SHans de Goede { /* sentinel */ } 119286a93317SHans de Goede }; 119386a93317SHans de Goede MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 119486a93317SHans de Goede 1195774c0103SMaxime Ripard static int sunxi_mmc_enable(struct sunxi_mmc_host *host) 1196774c0103SMaxime Ripard { 1197774c0103SMaxime Ripard int ret; 1198774c0103SMaxime Ripard 1199d8181941SMaxime Ripard if (!IS_ERR(host->reset)) { 1200d8181941SMaxime Ripard ret = reset_control_reset(host->reset); 1201d8181941SMaxime Ripard if (ret) { 1202d8181941SMaxime Ripard dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", 1203d8181941SMaxime Ripard ret); 1204d8181941SMaxime Ripard return ret; 1205d8181941SMaxime Ripard } 1206d8181941SMaxime Ripard } 1207d8181941SMaxime Ripard 1208774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_ahb); 1209774c0103SMaxime Ripard if (ret) { 1210d8181941SMaxime Ripard dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); 1211d8181941SMaxime Ripard goto error_assert_reset; 1212774c0103SMaxime Ripard } 1213774c0103SMaxime Ripard 1214774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_mmc); 1215774c0103SMaxime Ripard if (ret) { 1216774c0103SMaxime Ripard dev_err(host->dev, "Enable mmc clk err %d\n", ret); 1217774c0103SMaxime Ripard goto error_disable_clk_ahb; 1218774c0103SMaxime Ripard } 1219774c0103SMaxime Ripard 1220774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_output); 1221774c0103SMaxime Ripard if (ret) { 1222774c0103SMaxime Ripard dev_err(host->dev, "Enable output clk err %d\n", ret); 1223774c0103SMaxime Ripard goto error_disable_clk_mmc; 1224774c0103SMaxime Ripard } 1225774c0103SMaxime Ripard 1226774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_sample); 1227774c0103SMaxime Ripard if (ret) { 1228774c0103SMaxime Ripard dev_err(host->dev, "Enable sample clk err %d\n", ret); 1229774c0103SMaxime Ripard goto error_disable_clk_output; 1230774c0103SMaxime Ripard } 1231774c0103SMaxime Ripard 1232774c0103SMaxime Ripard /* 1233774c0103SMaxime Ripard * Sometimes the controller asserts the irq on boot for some reason, 1234774c0103SMaxime Ripard * make sure the controller is in a sane state before enabling irqs. 1235774c0103SMaxime Ripard */ 1236774c0103SMaxime Ripard ret = sunxi_mmc_reset_host(host); 1237774c0103SMaxime Ripard if (ret) 1238d8181941SMaxime Ripard goto error_disable_clk_sample; 1239774c0103SMaxime Ripard 1240774c0103SMaxime Ripard return 0; 1241774c0103SMaxime Ripard 1242774c0103SMaxime Ripard error_disable_clk_sample: 1243774c0103SMaxime Ripard clk_disable_unprepare(host->clk_sample); 1244774c0103SMaxime Ripard error_disable_clk_output: 1245774c0103SMaxime Ripard clk_disable_unprepare(host->clk_output); 1246774c0103SMaxime Ripard error_disable_clk_mmc: 1247774c0103SMaxime Ripard clk_disable_unprepare(host->clk_mmc); 1248774c0103SMaxime Ripard error_disable_clk_ahb: 1249774c0103SMaxime Ripard clk_disable_unprepare(host->clk_ahb); 1250d8181941SMaxime Ripard error_assert_reset: 1251d8181941SMaxime Ripard if (!IS_ERR(host->reset)) 1252d8181941SMaxime Ripard reset_control_assert(host->reset); 1253774c0103SMaxime Ripard return ret; 1254774c0103SMaxime Ripard } 1255774c0103SMaxime Ripard 1256774c0103SMaxime Ripard static void sunxi_mmc_disable(struct sunxi_mmc_host *host) 1257774c0103SMaxime Ripard { 1258774c0103SMaxime Ripard sunxi_mmc_reset_host(host); 1259774c0103SMaxime Ripard 1260774c0103SMaxime Ripard clk_disable_unprepare(host->clk_sample); 1261774c0103SMaxime Ripard clk_disable_unprepare(host->clk_output); 1262774c0103SMaxime Ripard clk_disable_unprepare(host->clk_mmc); 1263774c0103SMaxime Ripard clk_disable_unprepare(host->clk_ahb); 1264d8181941SMaxime Ripard 1265d8181941SMaxime Ripard if (!IS_ERR(host->reset)) 1266d8181941SMaxime Ripard reset_control_assert(host->reset); 1267774c0103SMaxime Ripard } 1268774c0103SMaxime Ripard 12693cbcb160SDavid Lanzendörfer static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 12703cbcb160SDavid Lanzendörfer struct platform_device *pdev) 12713cbcb160SDavid Lanzendörfer { 12723cbcb160SDavid Lanzendörfer int ret; 12733cbcb160SDavid Lanzendörfer 127486a93317SHans de Goede host->cfg = of_device_get_match_data(&pdev->dev); 127586a93317SHans de Goede if (!host->cfg) 127686a93317SHans de Goede return -EINVAL; 127751424b28SHans de Goede 12783cbcb160SDavid Lanzendörfer ret = mmc_regulator_get_supply(host->mmc); 1279aaab3c46SWolfram Sang if (ret) 12803cbcb160SDavid Lanzendörfer return ret; 12813cbcb160SDavid Lanzendörfer 12823cbcb160SDavid Lanzendörfer host->reg_base = devm_ioremap_resource(&pdev->dev, 12833cbcb160SDavid Lanzendörfer platform_get_resource(pdev, IORESOURCE_MEM, 0)); 12843cbcb160SDavid Lanzendörfer if (IS_ERR(host->reg_base)) 12853cbcb160SDavid Lanzendörfer return PTR_ERR(host->reg_base); 12863cbcb160SDavid Lanzendörfer 12873cbcb160SDavid Lanzendörfer host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 12883cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_ahb)) { 12893cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get ahb clock\n"); 12903cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_ahb); 12913cbcb160SDavid Lanzendörfer } 12923cbcb160SDavid Lanzendörfer 12933cbcb160SDavid Lanzendörfer host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 12943cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_mmc)) { 12953cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get mmc clock\n"); 12963cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_mmc); 12973cbcb160SDavid Lanzendörfer } 12983cbcb160SDavid Lanzendörfer 1299b465646eSHans de Goede if (host->cfg->clk_delays) { 13006c09bb85SMaxime Ripard host->clk_output = devm_clk_get(&pdev->dev, "output"); 13016c09bb85SMaxime Ripard if (IS_ERR(host->clk_output)) { 13026c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get output clock\n"); 13036c09bb85SMaxime Ripard return PTR_ERR(host->clk_output); 13046c09bb85SMaxime Ripard } 13056c09bb85SMaxime Ripard 13066c09bb85SMaxime Ripard host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 13076c09bb85SMaxime Ripard if (IS_ERR(host->clk_sample)) { 13086c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get sample clock\n"); 13096c09bb85SMaxime Ripard return PTR_ERR(host->clk_sample); 13106c09bb85SMaxime Ripard } 1311b465646eSHans de Goede } 13126c09bb85SMaxime Ripard 13135e40ddacSPhilipp Zabel host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 13145e40ddacSPhilipp Zabel "ahb"); 13159e71c589SChen-Yu Tsai if (PTR_ERR(host->reset) == -EPROBE_DEFER) 13169e71c589SChen-Yu Tsai return PTR_ERR(host->reset); 13173cbcb160SDavid Lanzendörfer 1318774c0103SMaxime Ripard ret = sunxi_mmc_enable(host); 13193cbcb160SDavid Lanzendörfer if (ret) 1320774c0103SMaxime Ripard return ret; 13213cbcb160SDavid Lanzendörfer 13223cbcb160SDavid Lanzendörfer host->irq = platform_get_irq(pdev, 0); 13232408a085SArvind Yadav if (host->irq <= 0) { 13242408a085SArvind Yadav ret = -EINVAL; 1325774c0103SMaxime Ripard goto error_disable_mmc; 13262408a085SArvind Yadav } 13272408a085SArvind Yadav 13283cbcb160SDavid Lanzendörfer return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 13293cbcb160SDavid Lanzendörfer sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 13303cbcb160SDavid Lanzendörfer 1331774c0103SMaxime Ripard error_disable_mmc: 1332774c0103SMaxime Ripard sunxi_mmc_disable(host); 13333cbcb160SDavid Lanzendörfer return ret; 13343cbcb160SDavid Lanzendörfer } 13353cbcb160SDavid Lanzendörfer 13363cbcb160SDavid Lanzendörfer static int sunxi_mmc_probe(struct platform_device *pdev) 13373cbcb160SDavid Lanzendörfer { 13383cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host; 13393cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 13403cbcb160SDavid Lanzendörfer int ret; 13413cbcb160SDavid Lanzendörfer 13423cbcb160SDavid Lanzendörfer mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 13433cbcb160SDavid Lanzendörfer if (!mmc) { 13443cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "mmc alloc host failed\n"); 13453cbcb160SDavid Lanzendörfer return -ENOMEM; 13463cbcb160SDavid Lanzendörfer } 1347cb1214d2SMaxime Ripard platform_set_drvdata(pdev, mmc); 13483cbcb160SDavid Lanzendörfer 13493cbcb160SDavid Lanzendörfer host = mmc_priv(mmc); 1350774c0103SMaxime Ripard host->dev = &pdev->dev; 13513cbcb160SDavid Lanzendörfer host->mmc = mmc; 13523cbcb160SDavid Lanzendörfer spin_lock_init(&host->lock); 13533cbcb160SDavid Lanzendörfer 13543cbcb160SDavid Lanzendörfer ret = sunxi_mmc_resource_request(host, pdev); 13553cbcb160SDavid Lanzendörfer if (ret) 13563cbcb160SDavid Lanzendörfer goto error_free_host; 13573cbcb160SDavid Lanzendörfer 13583cbcb160SDavid Lanzendörfer host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 13593cbcb160SDavid Lanzendörfer &host->sg_dma, GFP_KERNEL); 13603cbcb160SDavid Lanzendörfer if (!host->sg_cpu) { 13613cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 13623cbcb160SDavid Lanzendörfer ret = -ENOMEM; 13633cbcb160SDavid Lanzendörfer goto error_free_host; 13643cbcb160SDavid Lanzendörfer } 13653cbcb160SDavid Lanzendörfer 13661ff9cabdSChen-Yu Tsai if (host->cfg->ccu_has_timings_switch) { 1367ff39e7f7SChen-Yu Tsai /* 1368ff39e7f7SChen-Yu Tsai * Supports both old and new timing modes. 1369ff39e7f7SChen-Yu Tsai * Try setting the clk to new timing mode. 1370ff39e7f7SChen-Yu Tsai */ 1371ff39e7f7SChen-Yu Tsai sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1372ff39e7f7SChen-Yu Tsai 1373ff39e7f7SChen-Yu Tsai /* And check the result */ 1374ff39e7f7SChen-Yu Tsai ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1375ff39e7f7SChen-Yu Tsai if (ret < 0) { 1376ff39e7f7SChen-Yu Tsai /* 1377ff39e7f7SChen-Yu Tsai * For whatever reason we were not able to get 1378ff39e7f7SChen-Yu Tsai * the current active mode. Default to old mode. 1379ff39e7f7SChen-Yu Tsai */ 1380ff39e7f7SChen-Yu Tsai dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1381ff39e7f7SChen-Yu Tsai host->use_new_timings = false; 1382ff39e7f7SChen-Yu Tsai } else { 1383ff39e7f7SChen-Yu Tsai host->use_new_timings = !!ret; 1384ff39e7f7SChen-Yu Tsai } 1385ff39e7f7SChen-Yu Tsai } else if (host->cfg->needs_new_timings) { 1386ff39e7f7SChen-Yu Tsai /* Supports new timing mode only */ 1387ff39e7f7SChen-Yu Tsai host->use_new_timings = true; 1388ff39e7f7SChen-Yu Tsai } 1389ff39e7f7SChen-Yu Tsai 13903cbcb160SDavid Lanzendörfer mmc->ops = &sunxi_mmc_ops; 13913cbcb160SDavid Lanzendörfer mmc->max_blk_count = 8192; 13923cbcb160SDavid Lanzendörfer mmc->max_blk_size = 4096; 13933cbcb160SDavid Lanzendörfer mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 139486a93317SHans de Goede mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 13953cbcb160SDavid Lanzendörfer mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 13962dcb305aSChen-Yu Tsai /* 400kHz ~ 52MHz */ 13973cbcb160SDavid Lanzendörfer mmc->f_min = 400000; 13982dcb305aSChen-Yu Tsai mmc->f_max = 52000000; 13993df01a93SChen-Yu Tsai mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1400a4101dcbSHans de Goede MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 14013cbcb160SDavid Lanzendörfer 1402d49d92acSChen-Yu Tsai /* 1403d49d92acSChen-Yu Tsai * Some H5 devices do not have signal traces precise enough to 1404d49d92acSChen-Yu Tsai * use HS DDR mode for their eMMC chips. 1405d49d92acSChen-Yu Tsai * 1406d49d92acSChen-Yu Tsai * We still enable HS DDR modes for all the other controller 1407d49d92acSChen-Yu Tsai * variants that support them. 1408d49d92acSChen-Yu Tsai */ 1409d49d92acSChen-Yu Tsai if ((host->cfg->clk_delays || host->use_new_timings) && 1410d49d92acSChen-Yu Tsai !of_device_is_compatible(pdev->dev.of_node, 1411d49d92acSChen-Yu Tsai "allwinner,sun50i-h5-emmc")) 141288023d43SIcenowy Zheng mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1413b465646eSHans de Goede 14143cbcb160SDavid Lanzendörfer ret = mmc_of_parse(mmc); 14153cbcb160SDavid Lanzendörfer if (ret) 14163cbcb160SDavid Lanzendörfer goto error_free_dma; 14173cbcb160SDavid Lanzendörfer 1418d6f11e7dSChen-Yu Tsai /* 1419d6f11e7dSChen-Yu Tsai * If we don't support delay chains in the SoC, we can't use any 1420d6f11e7dSChen-Yu Tsai * of the higher speed modes. Mask them out in case the device 1421d6f11e7dSChen-Yu Tsai * tree specifies the properties for them, which gets added to 1422d6f11e7dSChen-Yu Tsai * the caps by mmc_of_parse() above. 1423d6f11e7dSChen-Yu Tsai */ 1424d6f11e7dSChen-Yu Tsai if (!(host->cfg->clk_delays || host->use_new_timings)) { 1425d6f11e7dSChen-Yu Tsai mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | 1426d6f11e7dSChen-Yu Tsai MMC_CAP_1_2V_DDR | MMC_CAP_UHS); 1427d6f11e7dSChen-Yu Tsai mmc->caps2 &= ~MMC_CAP2_HS200; 1428d6f11e7dSChen-Yu Tsai } 1429d6f11e7dSChen-Yu Tsai 1430d6f11e7dSChen-Yu Tsai /* TODO: This driver doesn't support HS400 mode yet */ 1431d6f11e7dSChen-Yu Tsai mmc->caps2 &= ~MMC_CAP2_HS400; 1432d6f11e7dSChen-Yu Tsai 1433eef797acSMaxime Ripard ret = sunxi_mmc_init_host(host); 1434eef797acSMaxime Ripard if (ret) 1435eef797acSMaxime Ripard goto error_free_dma; 1436eef797acSMaxime Ripard 14379a8e1e8cSMaxime Ripard pm_runtime_set_active(&pdev->dev); 14389a8e1e8cSMaxime Ripard pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 14399a8e1e8cSMaxime Ripard pm_runtime_use_autosuspend(&pdev->dev); 14409a8e1e8cSMaxime Ripard pm_runtime_enable(&pdev->dev); 14419a8e1e8cSMaxime Ripard 14423cbcb160SDavid Lanzendörfer ret = mmc_add_host(mmc); 14433cbcb160SDavid Lanzendörfer if (ret) 14443cbcb160SDavid Lanzendörfer goto error_free_dma; 14453cbcb160SDavid Lanzendörfer 14461389690bSAndre Przywara dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n", 14471389690bSAndre Przywara mmc->max_req_size >> 10, 14481389690bSAndre Przywara host->use_new_timings ? ", uses new timings mode" : ""); 14491389690bSAndre Przywara 14503cbcb160SDavid Lanzendörfer return 0; 14513cbcb160SDavid Lanzendörfer 14523cbcb160SDavid Lanzendörfer error_free_dma: 14533cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 14543cbcb160SDavid Lanzendörfer error_free_host: 14553cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 14563cbcb160SDavid Lanzendörfer return ret; 14573cbcb160SDavid Lanzendörfer } 14583cbcb160SDavid Lanzendörfer 14593cbcb160SDavid Lanzendörfer static int sunxi_mmc_remove(struct platform_device *pdev) 14603cbcb160SDavid Lanzendörfer { 14613cbcb160SDavid Lanzendörfer struct mmc_host *mmc = platform_get_drvdata(pdev); 14623cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 14633cbcb160SDavid Lanzendörfer 14643cbcb160SDavid Lanzendörfer mmc_remove_host(mmc); 14659a8e1e8cSMaxime Ripard pm_runtime_force_suspend(&pdev->dev); 14663cbcb160SDavid Lanzendörfer disable_irq(host->irq); 1467774c0103SMaxime Ripard sunxi_mmc_disable(host); 14683cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 14693cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 14703cbcb160SDavid Lanzendörfer 14713cbcb160SDavid Lanzendörfer return 0; 14723cbcb160SDavid Lanzendörfer } 14733cbcb160SDavid Lanzendörfer 1474af6b8ff4SUlf Hansson #ifdef CONFIG_PM 1475af6b8ff4SUlf Hansson static int sunxi_mmc_runtime_resume(struct device *dev) 14769a8e1e8cSMaxime Ripard { 14779a8e1e8cSMaxime Ripard struct mmc_host *mmc = dev_get_drvdata(dev); 14789a8e1e8cSMaxime Ripard struct sunxi_mmc_host *host = mmc_priv(mmc); 14799a8e1e8cSMaxime Ripard int ret; 14809a8e1e8cSMaxime Ripard 14819a8e1e8cSMaxime Ripard ret = sunxi_mmc_enable(host); 14829a8e1e8cSMaxime Ripard if (ret) 14839a8e1e8cSMaxime Ripard return ret; 14849a8e1e8cSMaxime Ripard 14859a8e1e8cSMaxime Ripard sunxi_mmc_init_host(host); 14869a8e1e8cSMaxime Ripard sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); 14879a8e1e8cSMaxime Ripard sunxi_mmc_set_clk(host, &mmc->ios); 1488b8ba3578SStefan Mavrodiev enable_irq(host->irq); 14899a8e1e8cSMaxime Ripard 14909a8e1e8cSMaxime Ripard return 0; 14919a8e1e8cSMaxime Ripard } 14929a8e1e8cSMaxime Ripard 1493af6b8ff4SUlf Hansson static int sunxi_mmc_runtime_suspend(struct device *dev) 14949a8e1e8cSMaxime Ripard { 14959a8e1e8cSMaxime Ripard struct mmc_host *mmc = dev_get_drvdata(dev); 14969a8e1e8cSMaxime Ripard struct sunxi_mmc_host *host = mmc_priv(mmc); 14979a8e1e8cSMaxime Ripard 1498b8ba3578SStefan Mavrodiev /* 1499b8ba3578SStefan Mavrodiev * When clocks are off, it's possible receiving 1500b8ba3578SStefan Mavrodiev * fake interrupts, which will stall the system. 1501b8ba3578SStefan Mavrodiev * Disabling the irq will prevent this. 1502b8ba3578SStefan Mavrodiev */ 1503b8ba3578SStefan Mavrodiev disable_irq(host->irq); 15049a8e1e8cSMaxime Ripard sunxi_mmc_reset_host(host); 15059a8e1e8cSMaxime Ripard sunxi_mmc_disable(host); 15069a8e1e8cSMaxime Ripard 15079a8e1e8cSMaxime Ripard return 0; 15089a8e1e8cSMaxime Ripard } 1509af6b8ff4SUlf Hansson #endif 15109a8e1e8cSMaxime Ripard 15119a8e1e8cSMaxime Ripard static const struct dev_pm_ops sunxi_mmc_pm_ops = { 15129a8e1e8cSMaxime Ripard SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend, 15139a8e1e8cSMaxime Ripard sunxi_mmc_runtime_resume, 15149a8e1e8cSMaxime Ripard NULL) 15159a8e1e8cSMaxime Ripard }; 15169a8e1e8cSMaxime Ripard 15173cbcb160SDavid Lanzendörfer static struct platform_driver sunxi_mmc_driver = { 15183cbcb160SDavid Lanzendörfer .driver = { 15193cbcb160SDavid Lanzendörfer .name = "sunxi-mmc", 15203cbcb160SDavid Lanzendörfer .of_match_table = of_match_ptr(sunxi_mmc_of_match), 15219a8e1e8cSMaxime Ripard .pm = &sunxi_mmc_pm_ops, 15223cbcb160SDavid Lanzendörfer }, 15233cbcb160SDavid Lanzendörfer .probe = sunxi_mmc_probe, 15243cbcb160SDavid Lanzendörfer .remove = sunxi_mmc_remove, 15253cbcb160SDavid Lanzendörfer }; 15263cbcb160SDavid Lanzendörfer module_platform_driver(sunxi_mmc_driver); 15273cbcb160SDavid Lanzendörfer 15283cbcb160SDavid Lanzendörfer MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 15293cbcb160SDavid Lanzendörfer MODULE_LICENSE("GPL v2"); 15301907e386SAdam Borowski MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 15313cbcb160SDavid Lanzendörfer MODULE_ALIAS("platform:sunxi-mmc"); 1532