13cbcb160SDavid Lanzendörfer /* 23cbcb160SDavid Lanzendörfer * Driver for sunxi SD/MMC host controllers 33cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 43cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 53cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 63cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch> 73cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 83cbcb160SDavid Lanzendörfer * 93cbcb160SDavid Lanzendörfer * This program is free software; you can redistribute it and/or 103cbcb160SDavid Lanzendörfer * modify it under the terms of the GNU General Public License as 113cbcb160SDavid Lanzendörfer * published by the Free Software Foundation; either version 2 of 123cbcb160SDavid Lanzendörfer * the License, or (at your option) any later version. 133cbcb160SDavid Lanzendörfer */ 143cbcb160SDavid Lanzendörfer 153cbcb160SDavid Lanzendörfer #include <linux/kernel.h> 163cbcb160SDavid Lanzendörfer #include <linux/module.h> 173cbcb160SDavid Lanzendörfer #include <linux/io.h> 183cbcb160SDavid Lanzendörfer #include <linux/device.h> 193cbcb160SDavid Lanzendörfer #include <linux/interrupt.h> 203cbcb160SDavid Lanzendörfer #include <linux/delay.h> 213cbcb160SDavid Lanzendörfer #include <linux/err.h> 223cbcb160SDavid Lanzendörfer 233cbcb160SDavid Lanzendörfer #include <linux/clk.h> 243cbcb160SDavid Lanzendörfer #include <linux/gpio.h> 253cbcb160SDavid Lanzendörfer #include <linux/platform_device.h> 263cbcb160SDavid Lanzendörfer #include <linux/spinlock.h> 273cbcb160SDavid Lanzendörfer #include <linux/scatterlist.h> 283cbcb160SDavid Lanzendörfer #include <linux/dma-mapping.h> 293cbcb160SDavid Lanzendörfer #include <linux/slab.h> 303cbcb160SDavid Lanzendörfer #include <linux/reset.h> 313cbcb160SDavid Lanzendörfer 323cbcb160SDavid Lanzendörfer #include <linux/of_address.h> 333cbcb160SDavid Lanzendörfer #include <linux/of_gpio.h> 343cbcb160SDavid Lanzendörfer #include <linux/of_platform.h> 353cbcb160SDavid Lanzendörfer 363cbcb160SDavid Lanzendörfer #include <linux/mmc/host.h> 373cbcb160SDavid Lanzendörfer #include <linux/mmc/sd.h> 383cbcb160SDavid Lanzendörfer #include <linux/mmc/sdio.h> 393cbcb160SDavid Lanzendörfer #include <linux/mmc/mmc.h> 403cbcb160SDavid Lanzendörfer #include <linux/mmc/core.h> 413cbcb160SDavid Lanzendörfer #include <linux/mmc/card.h> 423cbcb160SDavid Lanzendörfer #include <linux/mmc/slot-gpio.h> 433cbcb160SDavid Lanzendörfer 443cbcb160SDavid Lanzendörfer /* register offset definitions */ 453cbcb160SDavid Lanzendörfer #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 463cbcb160SDavid Lanzendörfer #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 473cbcb160SDavid Lanzendörfer #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 483cbcb160SDavid Lanzendörfer #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 493cbcb160SDavid Lanzendörfer #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 503cbcb160SDavid Lanzendörfer #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 513cbcb160SDavid Lanzendörfer #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 523cbcb160SDavid Lanzendörfer #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 533cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 543cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 553cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 563cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 573cbcb160SDavid Lanzendörfer #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 583cbcb160SDavid Lanzendörfer #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 593cbcb160SDavid Lanzendörfer #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 603cbcb160SDavid Lanzendörfer #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 613cbcb160SDavid Lanzendörfer #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 623cbcb160SDavid Lanzendörfer #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 633cbcb160SDavid Lanzendörfer #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 643cbcb160SDavid Lanzendörfer #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 653cbcb160SDavid Lanzendörfer #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 663cbcb160SDavid Lanzendörfer #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 673cbcb160SDavid Lanzendörfer #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 683cbcb160SDavid Lanzendörfer #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 693cbcb160SDavid Lanzendörfer #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 703cbcb160SDavid Lanzendörfer #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 713cbcb160SDavid Lanzendörfer #define SDXC_REG_CHDA (0x90) 723cbcb160SDavid Lanzendörfer #define SDXC_REG_CBDA (0x94) 733cbcb160SDavid Lanzendörfer 743cbcb160SDavid Lanzendörfer #define mmc_readl(host, reg) \ 753cbcb160SDavid Lanzendörfer readl((host)->reg_base + SDXC_##reg) 763cbcb160SDavid Lanzendörfer #define mmc_writel(host, reg, value) \ 773cbcb160SDavid Lanzendörfer writel((value), (host)->reg_base + SDXC_##reg) 783cbcb160SDavid Lanzendörfer 793cbcb160SDavid Lanzendörfer /* global control register bits */ 803cbcb160SDavid Lanzendörfer #define SDXC_SOFT_RESET BIT(0) 813cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RESET BIT(1) 823cbcb160SDavid Lanzendörfer #define SDXC_DMA_RESET BIT(2) 833cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 843cbcb160SDavid Lanzendörfer #define SDXC_DMA_ENABLE_BIT BIT(5) 853cbcb160SDavid Lanzendörfer #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 863cbcb160SDavid Lanzendörfer #define SDXC_POSEDGE_LATCH_DATA BIT(9) 873cbcb160SDavid Lanzendörfer #define SDXC_DDR_MODE BIT(10) 883cbcb160SDavid Lanzendörfer #define SDXC_MEMORY_ACCESS_DONE BIT(29) 893cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_DONE_DIRECT BIT(30) 903cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_AHB BIT(31) 913cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_DMA (0 << 31) 923cbcb160SDavid Lanzendörfer #define SDXC_HARDWARE_RESET \ 933cbcb160SDavid Lanzendörfer (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 943cbcb160SDavid Lanzendörfer 953cbcb160SDavid Lanzendörfer /* clock control bits */ 963cbcb160SDavid Lanzendörfer #define SDXC_CARD_CLOCK_ON BIT(16) 973cbcb160SDavid Lanzendörfer #define SDXC_LOW_POWER_ON BIT(17) 983cbcb160SDavid Lanzendörfer 993cbcb160SDavid Lanzendörfer /* bus width */ 1003cbcb160SDavid Lanzendörfer #define SDXC_WIDTH1 0 1013cbcb160SDavid Lanzendörfer #define SDXC_WIDTH4 1 1023cbcb160SDavid Lanzendörfer #define SDXC_WIDTH8 2 1033cbcb160SDavid Lanzendörfer 1043cbcb160SDavid Lanzendörfer /* smc command bits */ 1053cbcb160SDavid Lanzendörfer #define SDXC_RESP_EXPIRE BIT(6) 1063cbcb160SDavid Lanzendörfer #define SDXC_LONG_RESPONSE BIT(7) 1073cbcb160SDavid Lanzendörfer #define SDXC_CHECK_RESPONSE_CRC BIT(8) 1083cbcb160SDavid Lanzendörfer #define SDXC_DATA_EXPIRE BIT(9) 1093cbcb160SDavid Lanzendörfer #define SDXC_WRITE BIT(10) 1103cbcb160SDavid Lanzendörfer #define SDXC_SEQUENCE_MODE BIT(11) 1113cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOP BIT(12) 1123cbcb160SDavid Lanzendörfer #define SDXC_WAIT_PRE_OVER BIT(13) 1133cbcb160SDavid Lanzendörfer #define SDXC_STOP_ABORT_CMD BIT(14) 1143cbcb160SDavid Lanzendörfer #define SDXC_SEND_INIT_SEQUENCE BIT(15) 1153cbcb160SDavid Lanzendörfer #define SDXC_UPCLK_ONLY BIT(21) 1163cbcb160SDavid Lanzendörfer #define SDXC_READ_CEATA_DEV BIT(22) 1173cbcb160SDavid Lanzendörfer #define SDXC_CCS_EXPIRE BIT(23) 1183cbcb160SDavid Lanzendörfer #define SDXC_ENABLE_BIT_BOOT BIT(24) 1193cbcb160SDavid Lanzendörfer #define SDXC_ALT_BOOT_OPTIONS BIT(25) 1203cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ACK_EXPIRE BIT(26) 1213cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ABORT BIT(27) 1223cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_SWITCH BIT(28) 1233cbcb160SDavid Lanzendörfer #define SDXC_USE_HOLD_REGISTER BIT(29) 1243cbcb160SDavid Lanzendörfer #define SDXC_START BIT(31) 1253cbcb160SDavid Lanzendörfer 1263cbcb160SDavid Lanzendörfer /* interrupt bits */ 1273cbcb160SDavid Lanzendörfer #define SDXC_RESP_ERROR BIT(1) 1283cbcb160SDavid Lanzendörfer #define SDXC_COMMAND_DONE BIT(2) 1293cbcb160SDavid Lanzendörfer #define SDXC_DATA_OVER BIT(3) 1303cbcb160SDavid Lanzendörfer #define SDXC_TX_DATA_REQUEST BIT(4) 1313cbcb160SDavid Lanzendörfer #define SDXC_RX_DATA_REQUEST BIT(5) 1323cbcb160SDavid Lanzendörfer #define SDXC_RESP_CRC_ERROR BIT(6) 1333cbcb160SDavid Lanzendörfer #define SDXC_DATA_CRC_ERROR BIT(7) 1343cbcb160SDavid Lanzendörfer #define SDXC_RESP_TIMEOUT BIT(8) 1353cbcb160SDavid Lanzendörfer #define SDXC_DATA_TIMEOUT BIT(9) 1363cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 1373cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RUN_ERROR BIT(11) 1383cbcb160SDavid Lanzendörfer #define SDXC_HARD_WARE_LOCKED BIT(12) 1393cbcb160SDavid Lanzendörfer #define SDXC_START_BIT_ERROR BIT(13) 1403cbcb160SDavid Lanzendörfer #define SDXC_AUTO_COMMAND_DONE BIT(14) 1413cbcb160SDavid Lanzendörfer #define SDXC_END_BIT_ERROR BIT(15) 1423cbcb160SDavid Lanzendörfer #define SDXC_SDIO_INTERRUPT BIT(16) 1433cbcb160SDavid Lanzendörfer #define SDXC_CARD_INSERT BIT(30) 1443cbcb160SDavid Lanzendörfer #define SDXC_CARD_REMOVE BIT(31) 1453cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ERROR_BIT \ 1463cbcb160SDavid Lanzendörfer (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 1473cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 1483cbcb160SDavid Lanzendörfer SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 1493cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_DONE_BIT \ 1503cbcb160SDavid Lanzendörfer (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 1513cbcb160SDavid Lanzendörfer SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 1523cbcb160SDavid Lanzendörfer 1533cbcb160SDavid Lanzendörfer /* status */ 1543cbcb160SDavid Lanzendörfer #define SDXC_RXWL_FLAG BIT(0) 1553cbcb160SDavid Lanzendörfer #define SDXC_TXWL_FLAG BIT(1) 1563cbcb160SDavid Lanzendörfer #define SDXC_FIFO_EMPTY BIT(2) 1573cbcb160SDavid Lanzendörfer #define SDXC_FIFO_FULL BIT(3) 1583cbcb160SDavid Lanzendörfer #define SDXC_CARD_PRESENT BIT(8) 1593cbcb160SDavid Lanzendörfer #define SDXC_CARD_DATA_BUSY BIT(9) 1603cbcb160SDavid Lanzendörfer #define SDXC_DATA_FSM_BUSY BIT(10) 1613cbcb160SDavid Lanzendörfer #define SDXC_DMA_REQUEST BIT(31) 1623cbcb160SDavid Lanzendörfer #define SDXC_FIFO_SIZE 16 1633cbcb160SDavid Lanzendörfer 1643cbcb160SDavid Lanzendörfer /* Function select */ 1653cbcb160SDavid Lanzendörfer #define SDXC_CEATA_ON (0xceaa << 16) 1663cbcb160SDavid Lanzendörfer #define SDXC_SEND_IRQ_RESPONSE BIT(0) 1673cbcb160SDavid Lanzendörfer #define SDXC_SDIO_READ_WAIT BIT(1) 1683cbcb160SDavid Lanzendörfer #define SDXC_ABORT_READ_DATA BIT(2) 1693cbcb160SDavid Lanzendörfer #define SDXC_SEND_CCSD BIT(8) 1703cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 1713cbcb160SDavid Lanzendörfer #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 1723cbcb160SDavid Lanzendörfer 1733cbcb160SDavid Lanzendörfer /* IDMA controller bus mod bit field */ 1743cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SOFT_RESET BIT(0) 1753cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FIX_BURST BIT(1) 1763cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDMA_ON BIT(7) 1773cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_REFETCH_DES BIT(31) 1783cbcb160SDavid Lanzendörfer 1793cbcb160SDavid Lanzendörfer /* IDMA status bit field */ 1803cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 1813cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 1823cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 1833cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 1843cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 1853cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 1863cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 1873cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 1883cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDLE (0 << 13) 1893cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SUSPEND (1 << 13) 1903cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_READ (2 << 13) 1913cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CHECK (3 << 13) 1923cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 1933cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 1943cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ (6 << 13) 1953cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE (7 << 13) 1963cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 1973cbcb160SDavid Lanzendörfer 1983cbcb160SDavid Lanzendörfer /* 1993cbcb160SDavid Lanzendörfer * If the idma-des-size-bits of property is ie 13, bufsize bits are: 2003cbcb160SDavid Lanzendörfer * Bits 0-12: buf1 size 2013cbcb160SDavid Lanzendörfer * Bits 13-25: buf2 size 2023cbcb160SDavid Lanzendörfer * Bits 26-31: not used 2033cbcb160SDavid Lanzendörfer * Since we only ever set buf1 size, we can simply store it directly. 2043cbcb160SDavid Lanzendörfer */ 2053cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 2063cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 2073cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 2083cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 2093cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 2103cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 2113cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 2123cbcb160SDavid Lanzendörfer 2133cbcb160SDavid Lanzendörfer struct sunxi_idma_des { 2143cbcb160SDavid Lanzendörfer u32 config; 2153cbcb160SDavid Lanzendörfer u32 buf_size; 2163cbcb160SDavid Lanzendörfer u32 buf_addr_ptr1; 2173cbcb160SDavid Lanzendörfer u32 buf_addr_ptr2; 2183cbcb160SDavid Lanzendörfer }; 2193cbcb160SDavid Lanzendörfer 2203cbcb160SDavid Lanzendörfer struct sunxi_mmc_host { 2213cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 2223cbcb160SDavid Lanzendörfer struct reset_control *reset; 2233cbcb160SDavid Lanzendörfer 2243cbcb160SDavid Lanzendörfer /* IO mapping base */ 2253cbcb160SDavid Lanzendörfer void __iomem *reg_base; 2263cbcb160SDavid Lanzendörfer 2273cbcb160SDavid Lanzendörfer /* clock management */ 2283cbcb160SDavid Lanzendörfer struct clk *clk_ahb; 2293cbcb160SDavid Lanzendörfer struct clk *clk_mmc; 2306c09bb85SMaxime Ripard struct clk *clk_sample; 2316c09bb85SMaxime Ripard struct clk *clk_output; 2323cbcb160SDavid Lanzendörfer 2333cbcb160SDavid Lanzendörfer /* irq */ 2343cbcb160SDavid Lanzendörfer spinlock_t lock; 2353cbcb160SDavid Lanzendörfer int irq; 2363cbcb160SDavid Lanzendörfer u32 int_sum; 2373cbcb160SDavid Lanzendörfer u32 sdio_imask; 2383cbcb160SDavid Lanzendörfer 2393cbcb160SDavid Lanzendörfer /* dma */ 2403cbcb160SDavid Lanzendörfer u32 idma_des_size_bits; 2413cbcb160SDavid Lanzendörfer dma_addr_t sg_dma; 2423cbcb160SDavid Lanzendörfer void *sg_cpu; 2433cbcb160SDavid Lanzendörfer bool wait_dma; 2443cbcb160SDavid Lanzendörfer 2453cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 2463cbcb160SDavid Lanzendörfer struct mmc_request *manual_stop_mrq; 2473cbcb160SDavid Lanzendörfer int ferror; 2483cbcb160SDavid Lanzendörfer }; 2493cbcb160SDavid Lanzendörfer 2503cbcb160SDavid Lanzendörfer static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 2513cbcb160SDavid Lanzendörfer { 2523cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(250); 2533cbcb160SDavid Lanzendörfer u32 rval; 2543cbcb160SDavid Lanzendörfer 2550f0fcd37SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 2563cbcb160SDavid Lanzendörfer do { 2573cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 2583cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 2593cbcb160SDavid Lanzendörfer 2603cbcb160SDavid Lanzendörfer if (rval & SDXC_HARDWARE_RESET) { 2613cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 2623cbcb160SDavid Lanzendörfer return -EIO; 2633cbcb160SDavid Lanzendörfer } 2643cbcb160SDavid Lanzendörfer 2653cbcb160SDavid Lanzendörfer return 0; 2663cbcb160SDavid Lanzendörfer } 2673cbcb160SDavid Lanzendörfer 2683cbcb160SDavid Lanzendörfer static int sunxi_mmc_init_host(struct mmc_host *mmc) 2693cbcb160SDavid Lanzendörfer { 2703cbcb160SDavid Lanzendörfer u32 rval; 2713cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 2723cbcb160SDavid Lanzendörfer 2733cbcb160SDavid Lanzendörfer if (sunxi_mmc_reset_host(host)) 2743cbcb160SDavid Lanzendörfer return -EIO; 2753cbcb160SDavid Lanzendörfer 2763cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FTRGL, 0x20070008); 2773cbcb160SDavid Lanzendörfer mmc_writel(host, REG_TMOUT, 0xffffffff); 2783cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 2793cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffffffff); 2803cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DBGC, 0xdeb); 2813cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 2823cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DLBA, host->sg_dma); 2833cbcb160SDavid Lanzendörfer 2843cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 2853cbcb160SDavid Lanzendörfer rval |= SDXC_INTERRUPT_ENABLE_BIT; 2863cbcb160SDavid Lanzendörfer rval &= ~SDXC_ACCESS_DONE_DIRECT; 2873cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 2883cbcb160SDavid Lanzendörfer 2893cbcb160SDavid Lanzendörfer return 0; 2903cbcb160SDavid Lanzendörfer } 2913cbcb160SDavid Lanzendörfer 2923cbcb160SDavid Lanzendörfer static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 2933cbcb160SDavid Lanzendörfer struct mmc_data *data) 2943cbcb160SDavid Lanzendörfer { 2953cbcb160SDavid Lanzendörfer struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 296d34712d2SArnd Bergmann dma_addr_t next_desc = host->sg_dma; 2973cbcb160SDavid Lanzendörfer int i, max_len = (1 << host->idma_des_size_bits); 2983cbcb160SDavid Lanzendörfer 2993cbcb160SDavid Lanzendörfer for (i = 0; i < data->sg_len; i++) { 3003cbcb160SDavid Lanzendörfer pdes[i].config = SDXC_IDMAC_DES0_CH | SDXC_IDMAC_DES0_OWN | 3013cbcb160SDavid Lanzendörfer SDXC_IDMAC_DES0_DIC; 3023cbcb160SDavid Lanzendörfer 3033cbcb160SDavid Lanzendörfer if (data->sg[i].length == max_len) 3043cbcb160SDavid Lanzendörfer pdes[i].buf_size = 0; /* 0 == max_len */ 3053cbcb160SDavid Lanzendörfer else 3063cbcb160SDavid Lanzendörfer pdes[i].buf_size = data->sg[i].length; 3073cbcb160SDavid Lanzendörfer 308d34712d2SArnd Bergmann next_desc += sizeof(struct sunxi_idma_des); 3093cbcb160SDavid Lanzendörfer pdes[i].buf_addr_ptr1 = sg_dma_address(&data->sg[i]); 310d34712d2SArnd Bergmann pdes[i].buf_addr_ptr2 = (u32)next_desc; 3113cbcb160SDavid Lanzendörfer } 3123cbcb160SDavid Lanzendörfer 3133cbcb160SDavid Lanzendörfer pdes[0].config |= SDXC_IDMAC_DES0_FD; 314e8a59049SHans de Goede pdes[i - 1].config |= SDXC_IDMAC_DES0_LD | SDXC_IDMAC_DES0_ER; 315e8a59049SHans de Goede pdes[i - 1].config &= ~SDXC_IDMAC_DES0_DIC; 316e8a59049SHans de Goede pdes[i - 1].buf_addr_ptr2 = 0; 3173cbcb160SDavid Lanzendörfer 3183cbcb160SDavid Lanzendörfer /* 3193cbcb160SDavid Lanzendörfer * Avoid the io-store starting the idmac hitting io-mem before the 3203cbcb160SDavid Lanzendörfer * descriptors hit the main-mem. 3213cbcb160SDavid Lanzendörfer */ 3223cbcb160SDavid Lanzendörfer wmb(); 3233cbcb160SDavid Lanzendörfer } 3243cbcb160SDavid Lanzendörfer 3253cbcb160SDavid Lanzendörfer static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data) 3263cbcb160SDavid Lanzendörfer { 3273cbcb160SDavid Lanzendörfer if (data->flags & MMC_DATA_WRITE) 3283cbcb160SDavid Lanzendörfer return DMA_TO_DEVICE; 3293cbcb160SDavid Lanzendörfer else 3303cbcb160SDavid Lanzendörfer return DMA_FROM_DEVICE; 3313cbcb160SDavid Lanzendörfer } 3323cbcb160SDavid Lanzendörfer 3333cbcb160SDavid Lanzendörfer static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 3343cbcb160SDavid Lanzendörfer struct mmc_data *data) 3353cbcb160SDavid Lanzendörfer { 3363cbcb160SDavid Lanzendörfer u32 i, dma_len; 3373cbcb160SDavid Lanzendörfer struct scatterlist *sg; 3383cbcb160SDavid Lanzendörfer 3393cbcb160SDavid Lanzendörfer dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 3403cbcb160SDavid Lanzendörfer sunxi_mmc_get_dma_dir(data)); 3413cbcb160SDavid Lanzendörfer if (dma_len == 0) { 3423cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 3433cbcb160SDavid Lanzendörfer return -ENOMEM; 3443cbcb160SDavid Lanzendörfer } 3453cbcb160SDavid Lanzendörfer 3463cbcb160SDavid Lanzendörfer for_each_sg(data->sg, sg, data->sg_len, i) { 3473cbcb160SDavid Lanzendörfer if (sg->offset & 3 || sg->length & 3) { 3483cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), 3493cbcb160SDavid Lanzendörfer "unaligned scatterlist: os %x length %d\n", 3503cbcb160SDavid Lanzendörfer sg->offset, sg->length); 3513cbcb160SDavid Lanzendörfer return -EINVAL; 3523cbcb160SDavid Lanzendörfer } 3533cbcb160SDavid Lanzendörfer } 3543cbcb160SDavid Lanzendörfer 3553cbcb160SDavid Lanzendörfer return 0; 3563cbcb160SDavid Lanzendörfer } 3573cbcb160SDavid Lanzendörfer 3583cbcb160SDavid Lanzendörfer static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 3593cbcb160SDavid Lanzendörfer struct mmc_data *data) 3603cbcb160SDavid Lanzendörfer { 3613cbcb160SDavid Lanzendörfer u32 rval; 3623cbcb160SDavid Lanzendörfer 3633cbcb160SDavid Lanzendörfer sunxi_mmc_init_idma_des(host, data); 3643cbcb160SDavid Lanzendörfer 3653cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3663cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_ENABLE_BIT; 3673cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 3683cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 3693cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 3703cbcb160SDavid Lanzendörfer 3713cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 3723cbcb160SDavid Lanzendörfer 3733cbcb160SDavid Lanzendörfer if (!(data->flags & MMC_DATA_WRITE)) 3743cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 3753cbcb160SDavid Lanzendörfer 3763cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 3773cbcb160SDavid Lanzendörfer SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 3783cbcb160SDavid Lanzendörfer } 3793cbcb160SDavid Lanzendörfer 3803cbcb160SDavid Lanzendörfer static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 3813cbcb160SDavid Lanzendörfer struct mmc_request *req) 3823cbcb160SDavid Lanzendörfer { 3833cbcb160SDavid Lanzendörfer u32 arg, cmd_val, ri; 3843cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(1000); 3853cbcb160SDavid Lanzendörfer 3863cbcb160SDavid Lanzendörfer cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 3873cbcb160SDavid Lanzendörfer SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 3883cbcb160SDavid Lanzendörfer 3893cbcb160SDavid Lanzendörfer if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 3903cbcb160SDavid Lanzendörfer cmd_val |= SD_IO_RW_DIRECT; 3913cbcb160SDavid Lanzendörfer arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 3923cbcb160SDavid Lanzendörfer ((req->cmd->arg >> 28) & 0x7); 3933cbcb160SDavid Lanzendörfer } else { 3943cbcb160SDavid Lanzendörfer cmd_val |= MMC_STOP_TRANSMISSION; 3953cbcb160SDavid Lanzendörfer arg = 0; 3963cbcb160SDavid Lanzendörfer } 3973cbcb160SDavid Lanzendörfer 3983cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, arg); 3993cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 4003cbcb160SDavid Lanzendörfer 4013cbcb160SDavid Lanzendörfer do { 4023cbcb160SDavid Lanzendörfer ri = mmc_readl(host, REG_RINTR); 4033cbcb160SDavid Lanzendörfer } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 4043cbcb160SDavid Lanzendörfer time_before(jiffies, expire)); 4053cbcb160SDavid Lanzendörfer 4063cbcb160SDavid Lanzendörfer if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 4073cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 4083cbcb160SDavid Lanzendörfer if (req->stop) 4093cbcb160SDavid Lanzendörfer req->stop->resp[0] = -ETIMEDOUT; 4103cbcb160SDavid Lanzendörfer } else { 4113cbcb160SDavid Lanzendörfer if (req->stop) 4123cbcb160SDavid Lanzendörfer req->stop->resp[0] = mmc_readl(host, REG_RESP0); 4133cbcb160SDavid Lanzendörfer } 4143cbcb160SDavid Lanzendörfer 4153cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 4163cbcb160SDavid Lanzendörfer } 4173cbcb160SDavid Lanzendörfer 4183cbcb160SDavid Lanzendörfer static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 4193cbcb160SDavid Lanzendörfer { 4203cbcb160SDavid Lanzendörfer struct mmc_command *cmd = host->mrq->cmd; 4213cbcb160SDavid Lanzendörfer struct mmc_data *data = host->mrq->data; 4223cbcb160SDavid Lanzendörfer 4233cbcb160SDavid Lanzendörfer /* For some cmds timeout is normal with sd/mmc cards */ 4243cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 4253cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 4263cbcb160SDavid Lanzendörfer cmd->opcode == SD_IO_RW_DIRECT)) 4273cbcb160SDavid Lanzendörfer return; 4283cbcb160SDavid Lanzendörfer 4293cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), 4303cbcb160SDavid Lanzendörfer "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 4313cbcb160SDavid Lanzendörfer host->mmc->index, cmd->opcode, 4323cbcb160SDavid Lanzendörfer data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 4333cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 4343cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 4353cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 4363cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 4373cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 4383cbcb160SDavid Lanzendörfer host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 4393cbcb160SDavid Lanzendörfer host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 4403cbcb160SDavid Lanzendörfer host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 4413cbcb160SDavid Lanzendörfer host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 4423cbcb160SDavid Lanzendörfer ); 4433cbcb160SDavid Lanzendörfer } 4443cbcb160SDavid Lanzendörfer 4453cbcb160SDavid Lanzendörfer /* Called in interrupt context! */ 4463cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 4473cbcb160SDavid Lanzendörfer { 4483cbcb160SDavid Lanzendörfer struct mmc_request *mrq = host->mrq; 4493cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 4503cbcb160SDavid Lanzendörfer u32 rval; 4513cbcb160SDavid Lanzendörfer 4523cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 4533cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, 0); 4543cbcb160SDavid Lanzendörfer 4553cbcb160SDavid Lanzendörfer if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 4563cbcb160SDavid Lanzendörfer sunxi_mmc_dump_errinfo(host); 4573cbcb160SDavid Lanzendörfer mrq->cmd->error = -ETIMEDOUT; 4583cbcb160SDavid Lanzendörfer 4593cbcb160SDavid Lanzendörfer if (data) { 4603cbcb160SDavid Lanzendörfer data->error = -ETIMEDOUT; 4613cbcb160SDavid Lanzendörfer host->manual_stop_mrq = mrq; 4623cbcb160SDavid Lanzendörfer } 4633cbcb160SDavid Lanzendörfer 4643cbcb160SDavid Lanzendörfer if (mrq->stop) 4653cbcb160SDavid Lanzendörfer mrq->stop->error = -ETIMEDOUT; 4663cbcb160SDavid Lanzendörfer } else { 4673cbcb160SDavid Lanzendörfer if (mrq->cmd->flags & MMC_RSP_136) { 4683cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 4693cbcb160SDavid Lanzendörfer mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 4703cbcb160SDavid Lanzendörfer mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 4713cbcb160SDavid Lanzendörfer mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 4723cbcb160SDavid Lanzendörfer } else { 4733cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 4743cbcb160SDavid Lanzendörfer } 4753cbcb160SDavid Lanzendörfer 4763cbcb160SDavid Lanzendörfer if (data) 4773cbcb160SDavid Lanzendörfer data->bytes_xfered = data->blocks * data->blksz; 4783cbcb160SDavid Lanzendörfer } 4793cbcb160SDavid Lanzendörfer 4803cbcb160SDavid Lanzendörfer if (data) { 4813cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, 0x337); 4823cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 0); 4833cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 4843cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 4853cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4863cbcb160SDavid Lanzendörfer rval &= ~SDXC_DMA_ENABLE_BIT; 4873cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4883cbcb160SDavid Lanzendörfer rval |= SDXC_FIFO_RESET; 4893cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4903cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 4913cbcb160SDavid Lanzendörfer sunxi_mmc_get_dma_dir(data)); 4923cbcb160SDavid Lanzendörfer } 4933cbcb160SDavid Lanzendörfer 4943cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 4953cbcb160SDavid Lanzendörfer 4963cbcb160SDavid Lanzendörfer host->mrq = NULL; 4973cbcb160SDavid Lanzendörfer host->int_sum = 0; 4983cbcb160SDavid Lanzendörfer host->wait_dma = false; 4993cbcb160SDavid Lanzendörfer 5003cbcb160SDavid Lanzendörfer return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 5013cbcb160SDavid Lanzendörfer } 5023cbcb160SDavid Lanzendörfer 5033cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 5043cbcb160SDavid Lanzendörfer { 5053cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 5063cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 5073cbcb160SDavid Lanzendörfer u32 msk_int, idma_int; 5083cbcb160SDavid Lanzendörfer bool finalize = false; 5093cbcb160SDavid Lanzendörfer bool sdio_int = false; 5103cbcb160SDavid Lanzendörfer irqreturn_t ret = IRQ_HANDLED; 5113cbcb160SDavid Lanzendörfer 5123cbcb160SDavid Lanzendörfer spin_lock(&host->lock); 5133cbcb160SDavid Lanzendörfer 5143cbcb160SDavid Lanzendörfer idma_int = mmc_readl(host, REG_IDST); 5153cbcb160SDavid Lanzendörfer msk_int = mmc_readl(host, REG_MISTA); 5163cbcb160SDavid Lanzendörfer 5173cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 5183cbcb160SDavid Lanzendörfer host->mrq, msk_int, idma_int); 5193cbcb160SDavid Lanzendörfer 5203cbcb160SDavid Lanzendörfer mrq = host->mrq; 5213cbcb160SDavid Lanzendörfer if (mrq) { 5223cbcb160SDavid Lanzendörfer if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 5233cbcb160SDavid Lanzendörfer host->wait_dma = false; 5243cbcb160SDavid Lanzendörfer 5253cbcb160SDavid Lanzendörfer host->int_sum |= msk_int; 5263cbcb160SDavid Lanzendörfer 5273cbcb160SDavid Lanzendörfer /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 5283cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_RESP_TIMEOUT) && 5293cbcb160SDavid Lanzendörfer !(host->int_sum & SDXC_COMMAND_DONE)) 5303cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, 5313cbcb160SDavid Lanzendörfer host->sdio_imask | SDXC_COMMAND_DONE); 5323cbcb160SDavid Lanzendörfer /* Don't wait for dma on error */ 5333cbcb160SDavid Lanzendörfer else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 5343cbcb160SDavid Lanzendörfer finalize = true; 5353cbcb160SDavid Lanzendörfer else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 5363cbcb160SDavid Lanzendörfer !host->wait_dma) 5373cbcb160SDavid Lanzendörfer finalize = true; 5383cbcb160SDavid Lanzendörfer } 5393cbcb160SDavid Lanzendörfer 5403cbcb160SDavid Lanzendörfer if (msk_int & SDXC_SDIO_INTERRUPT) 5413cbcb160SDavid Lanzendörfer sdio_int = true; 5423cbcb160SDavid Lanzendörfer 5433cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, msk_int); 5443cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, idma_int); 5453cbcb160SDavid Lanzendörfer 5463cbcb160SDavid Lanzendörfer if (finalize) 5473cbcb160SDavid Lanzendörfer ret = sunxi_mmc_finalize_request(host); 5483cbcb160SDavid Lanzendörfer 5493cbcb160SDavid Lanzendörfer spin_unlock(&host->lock); 5503cbcb160SDavid Lanzendörfer 5513cbcb160SDavid Lanzendörfer if (finalize && ret == IRQ_HANDLED) 5523cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 5533cbcb160SDavid Lanzendörfer 5543cbcb160SDavid Lanzendörfer if (sdio_int) 5553cbcb160SDavid Lanzendörfer mmc_signal_sdio_irq(host->mmc); 5563cbcb160SDavid Lanzendörfer 5573cbcb160SDavid Lanzendörfer return ret; 5583cbcb160SDavid Lanzendörfer } 5593cbcb160SDavid Lanzendörfer 5603cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 5613cbcb160SDavid Lanzendörfer { 5623cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 5633cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 5643cbcb160SDavid Lanzendörfer unsigned long iflags; 5653cbcb160SDavid Lanzendörfer 5663cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 5673cbcb160SDavid Lanzendörfer mrq = host->manual_stop_mrq; 5683cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 5693cbcb160SDavid Lanzendörfer 5703cbcb160SDavid Lanzendörfer if (!mrq) { 5713cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 5723cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 5733cbcb160SDavid Lanzendörfer } 5743cbcb160SDavid Lanzendörfer 5753cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 576dd9b3803SDavid Lanzendörfer 577dd9b3803SDavid Lanzendörfer /* 578dd9b3803SDavid Lanzendörfer * We will never have more than one outstanding request, 579dd9b3803SDavid Lanzendörfer * and we do not complete the request until after 580dd9b3803SDavid Lanzendörfer * we've cleared host->manual_stop_mrq so we do not need to 581dd9b3803SDavid Lanzendörfer * spin lock this function. 582dd9b3803SDavid Lanzendörfer * Additionally we have wait states within this function 583dd9b3803SDavid Lanzendörfer * so having it in a lock is a very bad idea. 584dd9b3803SDavid Lanzendörfer */ 5853cbcb160SDavid Lanzendörfer sunxi_mmc_send_manual_stop(host, mrq); 5863cbcb160SDavid Lanzendörfer 5873cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 5883cbcb160SDavid Lanzendörfer host->manual_stop_mrq = NULL; 5893cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 5903cbcb160SDavid Lanzendörfer 5913cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 5923cbcb160SDavid Lanzendörfer 5933cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 5943cbcb160SDavid Lanzendörfer } 5953cbcb160SDavid Lanzendörfer 5963cbcb160SDavid Lanzendörfer static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 5973cbcb160SDavid Lanzendörfer { 5983cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(250); 5993cbcb160SDavid Lanzendörfer u32 rval; 6003cbcb160SDavid Lanzendörfer 6013cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 6023cbcb160SDavid Lanzendörfer rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON); 6033cbcb160SDavid Lanzendörfer 6043cbcb160SDavid Lanzendörfer if (oclk_en) 6053cbcb160SDavid Lanzendörfer rval |= SDXC_CARD_CLOCK_ON; 6063cbcb160SDavid Lanzendörfer 6073cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 6083cbcb160SDavid Lanzendörfer 6093cbcb160SDavid Lanzendörfer rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 6103cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, rval); 6113cbcb160SDavid Lanzendörfer 6123cbcb160SDavid Lanzendörfer do { 6133cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CMDR); 6143cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_START)); 6153cbcb160SDavid Lanzendörfer 6163cbcb160SDavid Lanzendörfer /* clear irq status bits set by the command */ 6173cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 6183cbcb160SDavid Lanzendörfer mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 6193cbcb160SDavid Lanzendörfer 6203cbcb160SDavid Lanzendörfer if (rval & SDXC_START) { 6213cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 6223cbcb160SDavid Lanzendörfer return -EIO; 6233cbcb160SDavid Lanzendörfer } 6243cbcb160SDavid Lanzendörfer 6253cbcb160SDavid Lanzendörfer return 0; 6263cbcb160SDavid Lanzendörfer } 6273cbcb160SDavid Lanzendörfer 6283cbcb160SDavid Lanzendörfer static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 6293cbcb160SDavid Lanzendörfer struct mmc_ios *ios) 6303cbcb160SDavid Lanzendörfer { 631de0673cdSDavid Lanzendörfer u32 rate, oclk_dly, rval, sclk_dly; 6323cbcb160SDavid Lanzendörfer int ret; 6333cbcb160SDavid Lanzendörfer 6343cbcb160SDavid Lanzendörfer rate = clk_round_rate(host->clk_mmc, ios->clock); 6353cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %d\n", 6363cbcb160SDavid Lanzendörfer ios->clock, rate); 6373cbcb160SDavid Lanzendörfer 6383cbcb160SDavid Lanzendörfer /* setting clock rate */ 6393cbcb160SDavid Lanzendörfer ret = clk_set_rate(host->clk_mmc, rate); 6403cbcb160SDavid Lanzendörfer if (ret) { 6413cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "error setting clk to %d: %d\n", 6423cbcb160SDavid Lanzendörfer rate, ret); 6433cbcb160SDavid Lanzendörfer return ret; 6443cbcb160SDavid Lanzendörfer } 6453cbcb160SDavid Lanzendörfer 6463cbcb160SDavid Lanzendörfer ret = sunxi_mmc_oclk_onoff(host, 0); 6473cbcb160SDavid Lanzendörfer if (ret) 6483cbcb160SDavid Lanzendörfer return ret; 6493cbcb160SDavid Lanzendörfer 6503cbcb160SDavid Lanzendörfer /* clear internal divider */ 6513cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 6523cbcb160SDavid Lanzendörfer rval &= ~0xff; 6533cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 6543cbcb160SDavid Lanzendörfer 6553cbcb160SDavid Lanzendörfer /* determine delays */ 6563cbcb160SDavid Lanzendörfer if (rate <= 400000) { 6576c09bb85SMaxime Ripard oclk_dly = 180; 6586c09bb85SMaxime Ripard sclk_dly = 42; 6593cbcb160SDavid Lanzendörfer } else if (rate <= 25000000) { 6606c09bb85SMaxime Ripard oclk_dly = 180; 6616c09bb85SMaxime Ripard sclk_dly = 75; 6623cbcb160SDavid Lanzendörfer } else if (rate <= 50000000) { 6633cbcb160SDavid Lanzendörfer if (ios->timing == MMC_TIMING_UHS_DDR50) { 6646c09bb85SMaxime Ripard oclk_dly = 60; 6656c09bb85SMaxime Ripard sclk_dly = 120; 6663cbcb160SDavid Lanzendörfer } else { 6676c09bb85SMaxime Ripard oclk_dly = 90; 6686c09bb85SMaxime Ripard sclk_dly = 150; 6693cbcb160SDavid Lanzendörfer } 6706c09bb85SMaxime Ripard } else if (rate <= 100000000) { 6716c09bb85SMaxime Ripard oclk_dly = 6; 6726c09bb85SMaxime Ripard sclk_dly = 24; 6736c09bb85SMaxime Ripard } else if (rate <= 200000000) { 6743cbcb160SDavid Lanzendörfer oclk_dly = 3; 6756c09bb85SMaxime Ripard sclk_dly = 12; 6763cbcb160SDavid Lanzendörfer } else { 6776c09bb85SMaxime Ripard return -EINVAL; 6783cbcb160SDavid Lanzendörfer } 6793cbcb160SDavid Lanzendörfer 6806c09bb85SMaxime Ripard clk_set_phase(host->clk_sample, sclk_dly); 6816c09bb85SMaxime Ripard clk_set_phase(host->clk_output, oclk_dly); 6823cbcb160SDavid Lanzendörfer 6833cbcb160SDavid Lanzendörfer return sunxi_mmc_oclk_onoff(host, 1); 6843cbcb160SDavid Lanzendörfer } 6853cbcb160SDavid Lanzendörfer 6863cbcb160SDavid Lanzendörfer static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 6873cbcb160SDavid Lanzendörfer { 6883cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 6893cbcb160SDavid Lanzendörfer u32 rval; 6903cbcb160SDavid Lanzendörfer 6913cbcb160SDavid Lanzendörfer /* Set the power state */ 6923cbcb160SDavid Lanzendörfer switch (ios->power_mode) { 6933cbcb160SDavid Lanzendörfer case MMC_POWER_ON: 6943cbcb160SDavid Lanzendörfer break; 6953cbcb160SDavid Lanzendörfer 6963cbcb160SDavid Lanzendörfer case MMC_POWER_UP: 6973cbcb160SDavid Lanzendörfer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 6983cbcb160SDavid Lanzendörfer 6993cbcb160SDavid Lanzendörfer host->ferror = sunxi_mmc_init_host(mmc); 7003cbcb160SDavid Lanzendörfer if (host->ferror) 7013cbcb160SDavid Lanzendörfer return; 7023cbcb160SDavid Lanzendörfer 7033cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "power on!\n"); 7043cbcb160SDavid Lanzendörfer break; 7053cbcb160SDavid Lanzendörfer 7063cbcb160SDavid Lanzendörfer case MMC_POWER_OFF: 7073cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "power off!\n"); 7083cbcb160SDavid Lanzendörfer sunxi_mmc_reset_host(host); 7093cbcb160SDavid Lanzendörfer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 7103cbcb160SDavid Lanzendörfer break; 7113cbcb160SDavid Lanzendörfer } 7123cbcb160SDavid Lanzendörfer 7133cbcb160SDavid Lanzendörfer /* set bus width */ 7143cbcb160SDavid Lanzendörfer switch (ios->bus_width) { 7153cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_1: 7163cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 7173cbcb160SDavid Lanzendörfer break; 7183cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_4: 7193cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 7203cbcb160SDavid Lanzendörfer break; 7213cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_8: 7223cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 7233cbcb160SDavid Lanzendörfer break; 7243cbcb160SDavid Lanzendörfer } 7253cbcb160SDavid Lanzendörfer 7263cbcb160SDavid Lanzendörfer /* set ddr mode */ 7273cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 7283cbcb160SDavid Lanzendörfer if (ios->timing == MMC_TIMING_UHS_DDR50) 7293cbcb160SDavid Lanzendörfer rval |= SDXC_DDR_MODE; 7303cbcb160SDavid Lanzendörfer else 7313cbcb160SDavid Lanzendörfer rval &= ~SDXC_DDR_MODE; 7323cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 7333cbcb160SDavid Lanzendörfer 7343cbcb160SDavid Lanzendörfer /* set up clock */ 7353cbcb160SDavid Lanzendörfer if (ios->clock && ios->power_mode) { 7363cbcb160SDavid Lanzendörfer host->ferror = sunxi_mmc_clk_set_rate(host, ios); 7373cbcb160SDavid Lanzendörfer /* Android code had a usleep_range(50000, 55000); here */ 7383cbcb160SDavid Lanzendörfer } 7393cbcb160SDavid Lanzendörfer } 7403cbcb160SDavid Lanzendörfer 7413cbcb160SDavid Lanzendörfer static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 7423cbcb160SDavid Lanzendörfer { 7433cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 7443cbcb160SDavid Lanzendörfer unsigned long flags; 7453cbcb160SDavid Lanzendörfer u32 imask; 7463cbcb160SDavid Lanzendörfer 7473cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, flags); 7483cbcb160SDavid Lanzendörfer 7493cbcb160SDavid Lanzendörfer imask = mmc_readl(host, REG_IMASK); 7503cbcb160SDavid Lanzendörfer if (enable) { 7513cbcb160SDavid Lanzendörfer host->sdio_imask = SDXC_SDIO_INTERRUPT; 7523cbcb160SDavid Lanzendörfer imask |= SDXC_SDIO_INTERRUPT; 7533cbcb160SDavid Lanzendörfer } else { 7543cbcb160SDavid Lanzendörfer host->sdio_imask = 0; 7553cbcb160SDavid Lanzendörfer imask &= ~SDXC_SDIO_INTERRUPT; 7563cbcb160SDavid Lanzendörfer } 7573cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, imask); 7583cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, flags); 7593cbcb160SDavid Lanzendörfer } 7603cbcb160SDavid Lanzendörfer 7613cbcb160SDavid Lanzendörfer static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 7623cbcb160SDavid Lanzendörfer { 7633cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 7643cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 0); 7653cbcb160SDavid Lanzendörfer udelay(10); 7663cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 1); 7673cbcb160SDavid Lanzendörfer udelay(300); 7683cbcb160SDavid Lanzendörfer } 7693cbcb160SDavid Lanzendörfer 7703cbcb160SDavid Lanzendörfer static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 7713cbcb160SDavid Lanzendörfer { 7723cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 7733cbcb160SDavid Lanzendörfer struct mmc_command *cmd = mrq->cmd; 7743cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 7753cbcb160SDavid Lanzendörfer unsigned long iflags; 7763cbcb160SDavid Lanzendörfer u32 imask = SDXC_INTERRUPT_ERROR_BIT; 7773cbcb160SDavid Lanzendörfer u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 778dd9b3803SDavid Lanzendörfer bool wait_dma = host->wait_dma; 7793cbcb160SDavid Lanzendörfer int ret; 7803cbcb160SDavid Lanzendörfer 7813cbcb160SDavid Lanzendörfer /* Check for set_ios errors (should never happen) */ 7823cbcb160SDavid Lanzendörfer if (host->ferror) { 7833cbcb160SDavid Lanzendörfer mrq->cmd->error = host->ferror; 7843cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 7853cbcb160SDavid Lanzendörfer return; 7863cbcb160SDavid Lanzendörfer } 7873cbcb160SDavid Lanzendörfer 7883cbcb160SDavid Lanzendörfer if (data) { 7893cbcb160SDavid Lanzendörfer ret = sunxi_mmc_map_dma(host, data); 7903cbcb160SDavid Lanzendörfer if (ret < 0) { 7913cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "map DMA failed\n"); 7923cbcb160SDavid Lanzendörfer cmd->error = ret; 7933cbcb160SDavid Lanzendörfer data->error = ret; 7943cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 7953cbcb160SDavid Lanzendörfer return; 7963cbcb160SDavid Lanzendörfer } 7973cbcb160SDavid Lanzendörfer } 7983cbcb160SDavid Lanzendörfer 7993cbcb160SDavid Lanzendörfer if (cmd->opcode == MMC_GO_IDLE_STATE) { 8003cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_INIT_SEQUENCE; 8013cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 8023cbcb160SDavid Lanzendörfer } 8033cbcb160SDavid Lanzendörfer 8043cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_PRESENT) { 8053cbcb160SDavid Lanzendörfer cmd_val |= SDXC_RESP_EXPIRE; 8063cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_136) 8073cbcb160SDavid Lanzendörfer cmd_val |= SDXC_LONG_RESPONSE; 8083cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_CRC) 8093cbcb160SDavid Lanzendörfer cmd_val |= SDXC_CHECK_RESPONSE_CRC; 8103cbcb160SDavid Lanzendörfer 8113cbcb160SDavid Lanzendörfer if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 8123cbcb160SDavid Lanzendörfer cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 8133cbcb160SDavid Lanzendörfer if (cmd->data->flags & MMC_DATA_STREAM) { 8143cbcb160SDavid Lanzendörfer imask |= SDXC_AUTO_COMMAND_DONE; 8153cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEQUENCE_MODE | 8163cbcb160SDavid Lanzendörfer SDXC_SEND_AUTO_STOP; 8173cbcb160SDavid Lanzendörfer } 8183cbcb160SDavid Lanzendörfer 8193cbcb160SDavid Lanzendörfer if (cmd->data->stop) { 8203cbcb160SDavid Lanzendörfer imask |= SDXC_AUTO_COMMAND_DONE; 8213cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_AUTO_STOP; 8223cbcb160SDavid Lanzendörfer } else { 8233cbcb160SDavid Lanzendörfer imask |= SDXC_DATA_OVER; 8243cbcb160SDavid Lanzendörfer } 8253cbcb160SDavid Lanzendörfer 8263cbcb160SDavid Lanzendörfer if (cmd->data->flags & MMC_DATA_WRITE) 8273cbcb160SDavid Lanzendörfer cmd_val |= SDXC_WRITE; 8283cbcb160SDavid Lanzendörfer else 829dd9b3803SDavid Lanzendörfer wait_dma = true; 8303cbcb160SDavid Lanzendörfer } else { 8313cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 8323cbcb160SDavid Lanzendörfer } 8333cbcb160SDavid Lanzendörfer } else { 8343cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 8353cbcb160SDavid Lanzendörfer } 8363cbcb160SDavid Lanzendörfer 8373cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 8383cbcb160SDavid Lanzendörfer cmd_val & 0x3f, cmd_val, cmd->arg, imask, 8393cbcb160SDavid Lanzendörfer mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 8403cbcb160SDavid Lanzendörfer 8413cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 8423cbcb160SDavid Lanzendörfer 8433cbcb160SDavid Lanzendörfer if (host->mrq || host->manual_stop_mrq) { 8443cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 8453cbcb160SDavid Lanzendörfer 8463cbcb160SDavid Lanzendörfer if (data) 8473cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 8483cbcb160SDavid Lanzendörfer sunxi_mmc_get_dma_dir(data)); 8493cbcb160SDavid Lanzendörfer 8503cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "request already pending\n"); 8513cbcb160SDavid Lanzendörfer mrq->cmd->error = -EBUSY; 8523cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 8533cbcb160SDavid Lanzendörfer return; 8543cbcb160SDavid Lanzendörfer } 8553cbcb160SDavid Lanzendörfer 8563cbcb160SDavid Lanzendörfer if (data) { 8573cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BLKSZ, data->blksz); 8583cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 8593cbcb160SDavid Lanzendörfer sunxi_mmc_start_dma(host, data); 8603cbcb160SDavid Lanzendörfer } 8613cbcb160SDavid Lanzendörfer 8623cbcb160SDavid Lanzendörfer host->mrq = mrq; 863dd9b3803SDavid Lanzendörfer host->wait_dma = wait_dma; 8643cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 8653cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, cmd->arg); 8663cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 8673cbcb160SDavid Lanzendörfer 8683cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 8693cbcb160SDavid Lanzendörfer } 8703cbcb160SDavid Lanzendörfer 8713cbcb160SDavid Lanzendörfer static const struct of_device_id sunxi_mmc_of_match[] = { 8723cbcb160SDavid Lanzendörfer { .compatible = "allwinner,sun4i-a10-mmc", }, 8733cbcb160SDavid Lanzendörfer { .compatible = "allwinner,sun5i-a13-mmc", }, 8743cbcb160SDavid Lanzendörfer { /* sentinel */ } 8753cbcb160SDavid Lanzendörfer }; 8763cbcb160SDavid Lanzendörfer MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 8773cbcb160SDavid Lanzendörfer 8783cbcb160SDavid Lanzendörfer static struct mmc_host_ops sunxi_mmc_ops = { 8793cbcb160SDavid Lanzendörfer .request = sunxi_mmc_request, 8803cbcb160SDavid Lanzendörfer .set_ios = sunxi_mmc_set_ios, 8813cbcb160SDavid Lanzendörfer .get_ro = mmc_gpio_get_ro, 8823cbcb160SDavid Lanzendörfer .get_cd = mmc_gpio_get_cd, 8833cbcb160SDavid Lanzendörfer .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 8843cbcb160SDavid Lanzendörfer .hw_reset = sunxi_mmc_hw_reset, 8853cbcb160SDavid Lanzendörfer }; 8863cbcb160SDavid Lanzendörfer 8873cbcb160SDavid Lanzendörfer static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 8883cbcb160SDavid Lanzendörfer struct platform_device *pdev) 8893cbcb160SDavid Lanzendörfer { 8903cbcb160SDavid Lanzendörfer struct device_node *np = pdev->dev.of_node; 8913cbcb160SDavid Lanzendörfer int ret; 8923cbcb160SDavid Lanzendörfer 8933cbcb160SDavid Lanzendörfer if (of_device_is_compatible(np, "allwinner,sun4i-a10-mmc")) 8943cbcb160SDavid Lanzendörfer host->idma_des_size_bits = 13; 8953cbcb160SDavid Lanzendörfer else 8963cbcb160SDavid Lanzendörfer host->idma_des_size_bits = 16; 8973cbcb160SDavid Lanzendörfer 8983cbcb160SDavid Lanzendörfer ret = mmc_regulator_get_supply(host->mmc); 8993cbcb160SDavid Lanzendörfer if (ret) { 9003cbcb160SDavid Lanzendörfer if (ret != -EPROBE_DEFER) 9013cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get vmmc supply\n"); 9023cbcb160SDavid Lanzendörfer return ret; 9033cbcb160SDavid Lanzendörfer } 9043cbcb160SDavid Lanzendörfer 9053cbcb160SDavid Lanzendörfer host->reg_base = devm_ioremap_resource(&pdev->dev, 9063cbcb160SDavid Lanzendörfer platform_get_resource(pdev, IORESOURCE_MEM, 0)); 9073cbcb160SDavid Lanzendörfer if (IS_ERR(host->reg_base)) 9083cbcb160SDavid Lanzendörfer return PTR_ERR(host->reg_base); 9093cbcb160SDavid Lanzendörfer 9103cbcb160SDavid Lanzendörfer host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 9113cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_ahb)) { 9123cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get ahb clock\n"); 9133cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_ahb); 9143cbcb160SDavid Lanzendörfer } 9153cbcb160SDavid Lanzendörfer 9163cbcb160SDavid Lanzendörfer host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 9173cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_mmc)) { 9183cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get mmc clock\n"); 9193cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_mmc); 9203cbcb160SDavid Lanzendörfer } 9213cbcb160SDavid Lanzendörfer 9226c09bb85SMaxime Ripard host->clk_output = devm_clk_get(&pdev->dev, "output"); 9236c09bb85SMaxime Ripard if (IS_ERR(host->clk_output)) { 9246c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get output clock\n"); 9256c09bb85SMaxime Ripard return PTR_ERR(host->clk_output); 9266c09bb85SMaxime Ripard } 9276c09bb85SMaxime Ripard 9286c09bb85SMaxime Ripard host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 9296c09bb85SMaxime Ripard if (IS_ERR(host->clk_sample)) { 9306c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get sample clock\n"); 9316c09bb85SMaxime Ripard return PTR_ERR(host->clk_sample); 9326c09bb85SMaxime Ripard } 9336c09bb85SMaxime Ripard 9349e71c589SChen-Yu Tsai host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb"); 9359e71c589SChen-Yu Tsai if (PTR_ERR(host->reset) == -EPROBE_DEFER) 9369e71c589SChen-Yu Tsai return PTR_ERR(host->reset); 9373cbcb160SDavid Lanzendörfer 9383cbcb160SDavid Lanzendörfer ret = clk_prepare_enable(host->clk_ahb); 9393cbcb160SDavid Lanzendörfer if (ret) { 9403cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret); 9413cbcb160SDavid Lanzendörfer return ret; 9423cbcb160SDavid Lanzendörfer } 9433cbcb160SDavid Lanzendörfer 9443cbcb160SDavid Lanzendörfer ret = clk_prepare_enable(host->clk_mmc); 9453cbcb160SDavid Lanzendörfer if (ret) { 9463cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret); 9473cbcb160SDavid Lanzendörfer goto error_disable_clk_ahb; 9483cbcb160SDavid Lanzendörfer } 9493cbcb160SDavid Lanzendörfer 9506c09bb85SMaxime Ripard ret = clk_prepare_enable(host->clk_output); 9516c09bb85SMaxime Ripard if (ret) { 9526c09bb85SMaxime Ripard dev_err(&pdev->dev, "Enable output clk err %d\n", ret); 9536c09bb85SMaxime Ripard goto error_disable_clk_mmc; 9546c09bb85SMaxime Ripard } 9556c09bb85SMaxime Ripard 9566c09bb85SMaxime Ripard ret = clk_prepare_enable(host->clk_sample); 9576c09bb85SMaxime Ripard if (ret) { 9586c09bb85SMaxime Ripard dev_err(&pdev->dev, "Enable sample clk err %d\n", ret); 9596c09bb85SMaxime Ripard goto error_disable_clk_output; 9606c09bb85SMaxime Ripard } 9616c09bb85SMaxime Ripard 9623cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) { 9633cbcb160SDavid Lanzendörfer ret = reset_control_deassert(host->reset); 9643cbcb160SDavid Lanzendörfer if (ret) { 9653cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "reset err %d\n", ret); 9666c09bb85SMaxime Ripard goto error_disable_clk_sample; 9673cbcb160SDavid Lanzendörfer } 9683cbcb160SDavid Lanzendörfer } 9693cbcb160SDavid Lanzendörfer 9703cbcb160SDavid Lanzendörfer /* 9713cbcb160SDavid Lanzendörfer * Sometimes the controller asserts the irq on boot for some reason, 9723cbcb160SDavid Lanzendörfer * make sure the controller is in a sane state before enabling irqs. 9733cbcb160SDavid Lanzendörfer */ 9743cbcb160SDavid Lanzendörfer ret = sunxi_mmc_reset_host(host); 9753cbcb160SDavid Lanzendörfer if (ret) 9763cbcb160SDavid Lanzendörfer goto error_assert_reset; 9773cbcb160SDavid Lanzendörfer 9783cbcb160SDavid Lanzendörfer host->irq = platform_get_irq(pdev, 0); 9793cbcb160SDavid Lanzendörfer return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 9803cbcb160SDavid Lanzendörfer sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 9813cbcb160SDavid Lanzendörfer 9823cbcb160SDavid Lanzendörfer error_assert_reset: 9833cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) 9843cbcb160SDavid Lanzendörfer reset_control_assert(host->reset); 9856c09bb85SMaxime Ripard error_disable_clk_sample: 9866c09bb85SMaxime Ripard clk_disable_unprepare(host->clk_sample); 9876c09bb85SMaxime Ripard error_disable_clk_output: 9886c09bb85SMaxime Ripard clk_disable_unprepare(host->clk_output); 9893cbcb160SDavid Lanzendörfer error_disable_clk_mmc: 9903cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_mmc); 9913cbcb160SDavid Lanzendörfer error_disable_clk_ahb: 9923cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_ahb); 9933cbcb160SDavid Lanzendörfer return ret; 9943cbcb160SDavid Lanzendörfer } 9953cbcb160SDavid Lanzendörfer 9963cbcb160SDavid Lanzendörfer static int sunxi_mmc_probe(struct platform_device *pdev) 9973cbcb160SDavid Lanzendörfer { 9983cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host; 9993cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 10003cbcb160SDavid Lanzendörfer int ret; 10013cbcb160SDavid Lanzendörfer 10023cbcb160SDavid Lanzendörfer mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 10033cbcb160SDavid Lanzendörfer if (!mmc) { 10043cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "mmc alloc host failed\n"); 10053cbcb160SDavid Lanzendörfer return -ENOMEM; 10063cbcb160SDavid Lanzendörfer } 10073cbcb160SDavid Lanzendörfer 10083cbcb160SDavid Lanzendörfer host = mmc_priv(mmc); 10093cbcb160SDavid Lanzendörfer host->mmc = mmc; 10103cbcb160SDavid Lanzendörfer spin_lock_init(&host->lock); 10113cbcb160SDavid Lanzendörfer 10123cbcb160SDavid Lanzendörfer ret = sunxi_mmc_resource_request(host, pdev); 10133cbcb160SDavid Lanzendörfer if (ret) 10143cbcb160SDavid Lanzendörfer goto error_free_host; 10153cbcb160SDavid Lanzendörfer 10163cbcb160SDavid Lanzendörfer host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 10173cbcb160SDavid Lanzendörfer &host->sg_dma, GFP_KERNEL); 10183cbcb160SDavid Lanzendörfer if (!host->sg_cpu) { 10193cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 10203cbcb160SDavid Lanzendörfer ret = -ENOMEM; 10213cbcb160SDavid Lanzendörfer goto error_free_host; 10223cbcb160SDavid Lanzendörfer } 10233cbcb160SDavid Lanzendörfer 10243cbcb160SDavid Lanzendörfer mmc->ops = &sunxi_mmc_ops; 10253cbcb160SDavid Lanzendörfer mmc->max_blk_count = 8192; 10263cbcb160SDavid Lanzendörfer mmc->max_blk_size = 4096; 10273cbcb160SDavid Lanzendörfer mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 10283cbcb160SDavid Lanzendörfer mmc->max_seg_size = (1 << host->idma_des_size_bits); 10293cbcb160SDavid Lanzendörfer mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 10303cbcb160SDavid Lanzendörfer /* 400kHz ~ 50MHz */ 10313cbcb160SDavid Lanzendörfer mmc->f_min = 400000; 10323cbcb160SDavid Lanzendörfer mmc->f_max = 50000000; 10333df01a93SChen-Yu Tsai mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1034a4101dcbSHans de Goede MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 10353cbcb160SDavid Lanzendörfer 10363cbcb160SDavid Lanzendörfer ret = mmc_of_parse(mmc); 10373cbcb160SDavid Lanzendörfer if (ret) 10383cbcb160SDavid Lanzendörfer goto error_free_dma; 10393cbcb160SDavid Lanzendörfer 10403cbcb160SDavid Lanzendörfer ret = mmc_add_host(mmc); 10413cbcb160SDavid Lanzendörfer if (ret) 10423cbcb160SDavid Lanzendörfer goto error_free_dma; 10433cbcb160SDavid Lanzendörfer 10443cbcb160SDavid Lanzendörfer dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); 10453cbcb160SDavid Lanzendörfer platform_set_drvdata(pdev, mmc); 10463cbcb160SDavid Lanzendörfer return 0; 10473cbcb160SDavid Lanzendörfer 10483cbcb160SDavid Lanzendörfer error_free_dma: 10493cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 10503cbcb160SDavid Lanzendörfer error_free_host: 10513cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 10523cbcb160SDavid Lanzendörfer return ret; 10533cbcb160SDavid Lanzendörfer } 10543cbcb160SDavid Lanzendörfer 10553cbcb160SDavid Lanzendörfer static int sunxi_mmc_remove(struct platform_device *pdev) 10563cbcb160SDavid Lanzendörfer { 10573cbcb160SDavid Lanzendörfer struct mmc_host *mmc = platform_get_drvdata(pdev); 10583cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 10593cbcb160SDavid Lanzendörfer 10603cbcb160SDavid Lanzendörfer mmc_remove_host(mmc); 10613cbcb160SDavid Lanzendörfer disable_irq(host->irq); 10623cbcb160SDavid Lanzendörfer sunxi_mmc_reset_host(host); 10633cbcb160SDavid Lanzendörfer 10643cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) 10653cbcb160SDavid Lanzendörfer reset_control_assert(host->reset); 10663cbcb160SDavid Lanzendörfer 10673cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_mmc); 10683cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_ahb); 10693cbcb160SDavid Lanzendörfer 10703cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 10713cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 10723cbcb160SDavid Lanzendörfer 10733cbcb160SDavid Lanzendörfer return 0; 10743cbcb160SDavid Lanzendörfer } 10753cbcb160SDavid Lanzendörfer 10763cbcb160SDavid Lanzendörfer static struct platform_driver sunxi_mmc_driver = { 10773cbcb160SDavid Lanzendörfer .driver = { 10783cbcb160SDavid Lanzendörfer .name = "sunxi-mmc", 10793cbcb160SDavid Lanzendörfer .of_match_table = of_match_ptr(sunxi_mmc_of_match), 10803cbcb160SDavid Lanzendörfer }, 10813cbcb160SDavid Lanzendörfer .probe = sunxi_mmc_probe, 10823cbcb160SDavid Lanzendörfer .remove = sunxi_mmc_remove, 10833cbcb160SDavid Lanzendörfer }; 10843cbcb160SDavid Lanzendörfer module_platform_driver(sunxi_mmc_driver); 10853cbcb160SDavid Lanzendörfer 10863cbcb160SDavid Lanzendörfer MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 10873cbcb160SDavid Lanzendörfer MODULE_LICENSE("GPL v2"); 10883cbcb160SDavid Lanzendörfer MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>"); 10893cbcb160SDavid Lanzendörfer MODULE_ALIAS("platform:sunxi-mmc"); 1090