13cbcb160SDavid Lanzendörfer /* 23cbcb160SDavid Lanzendörfer * Driver for sunxi SD/MMC host controllers 33cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 43cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 53cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 63cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 David Lanzend�rfer <david.lanzendoerfer@o2s.ch> 73cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 83cbcb160SDavid Lanzendörfer * 93cbcb160SDavid Lanzendörfer * This program is free software; you can redistribute it and/or 103cbcb160SDavid Lanzendörfer * modify it under the terms of the GNU General Public License as 113cbcb160SDavid Lanzendörfer * published by the Free Software Foundation; either version 2 of 123cbcb160SDavid Lanzendörfer * the License, or (at your option) any later version. 133cbcb160SDavid Lanzendörfer */ 143cbcb160SDavid Lanzendörfer 153cbcb160SDavid Lanzendörfer #include <linux/kernel.h> 163cbcb160SDavid Lanzendörfer #include <linux/module.h> 173cbcb160SDavid Lanzendörfer #include <linux/io.h> 183cbcb160SDavid Lanzendörfer #include <linux/device.h> 193cbcb160SDavid Lanzendörfer #include <linux/interrupt.h> 203cbcb160SDavid Lanzendörfer #include <linux/delay.h> 213cbcb160SDavid Lanzendörfer #include <linux/err.h> 223cbcb160SDavid Lanzendörfer 233cbcb160SDavid Lanzendörfer #include <linux/clk.h> 243cbcb160SDavid Lanzendörfer #include <linux/gpio.h> 253cbcb160SDavid Lanzendörfer #include <linux/platform_device.h> 263cbcb160SDavid Lanzendörfer #include <linux/spinlock.h> 273cbcb160SDavid Lanzendörfer #include <linux/scatterlist.h> 283cbcb160SDavid Lanzendörfer #include <linux/dma-mapping.h> 293cbcb160SDavid Lanzendörfer #include <linux/slab.h> 303cbcb160SDavid Lanzendörfer #include <linux/reset.h> 31f771f6e8SChen-Yu Tsai #include <linux/regulator/consumer.h> 323cbcb160SDavid Lanzendörfer 333cbcb160SDavid Lanzendörfer #include <linux/of_address.h> 343cbcb160SDavid Lanzendörfer #include <linux/of_gpio.h> 353cbcb160SDavid Lanzendörfer #include <linux/of_platform.h> 363cbcb160SDavid Lanzendörfer 373cbcb160SDavid Lanzendörfer #include <linux/mmc/host.h> 383cbcb160SDavid Lanzendörfer #include <linux/mmc/sd.h> 393cbcb160SDavid Lanzendörfer #include <linux/mmc/sdio.h> 403cbcb160SDavid Lanzendörfer #include <linux/mmc/mmc.h> 413cbcb160SDavid Lanzendörfer #include <linux/mmc/core.h> 423cbcb160SDavid Lanzendörfer #include <linux/mmc/card.h> 433cbcb160SDavid Lanzendörfer #include <linux/mmc/slot-gpio.h> 443cbcb160SDavid Lanzendörfer 453cbcb160SDavid Lanzendörfer /* register offset definitions */ 463cbcb160SDavid Lanzendörfer #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 473cbcb160SDavid Lanzendörfer #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 483cbcb160SDavid Lanzendörfer #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 493cbcb160SDavid Lanzendörfer #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 503cbcb160SDavid Lanzendörfer #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 513cbcb160SDavid Lanzendörfer #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 523cbcb160SDavid Lanzendörfer #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 533cbcb160SDavid Lanzendörfer #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 543cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 553cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 563cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 573cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 583cbcb160SDavid Lanzendörfer #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 593cbcb160SDavid Lanzendörfer #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 603cbcb160SDavid Lanzendörfer #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 613cbcb160SDavid Lanzendörfer #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 623cbcb160SDavid Lanzendörfer #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 633cbcb160SDavid Lanzendörfer #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 643cbcb160SDavid Lanzendörfer #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 653cbcb160SDavid Lanzendörfer #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 663cbcb160SDavid Lanzendörfer #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 673cbcb160SDavid Lanzendörfer #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 683cbcb160SDavid Lanzendörfer #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 693cbcb160SDavid Lanzendörfer #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 703cbcb160SDavid Lanzendörfer #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 713cbcb160SDavid Lanzendörfer #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 723cbcb160SDavid Lanzendörfer #define SDXC_REG_CHDA (0x90) 733cbcb160SDavid Lanzendörfer #define SDXC_REG_CBDA (0x94) 743cbcb160SDavid Lanzendörfer 75e1b8dfd1SIcenowy Zheng /* New registers introduced in A64 */ 76e1b8dfd1SIcenowy Zheng #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 77e1b8dfd1SIcenowy Zheng #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 78e1b8dfd1SIcenowy Zheng #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 79e1b8dfd1SIcenowy Zheng #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 80e1b8dfd1SIcenowy Zheng #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 81e1b8dfd1SIcenowy Zheng 823cbcb160SDavid Lanzendörfer #define mmc_readl(host, reg) \ 833cbcb160SDavid Lanzendörfer readl((host)->reg_base + SDXC_##reg) 843cbcb160SDavid Lanzendörfer #define mmc_writel(host, reg, value) \ 853cbcb160SDavid Lanzendörfer writel((value), (host)->reg_base + SDXC_##reg) 863cbcb160SDavid Lanzendörfer 873cbcb160SDavid Lanzendörfer /* global control register bits */ 883cbcb160SDavid Lanzendörfer #define SDXC_SOFT_RESET BIT(0) 893cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RESET BIT(1) 903cbcb160SDavid Lanzendörfer #define SDXC_DMA_RESET BIT(2) 913cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 923cbcb160SDavid Lanzendörfer #define SDXC_DMA_ENABLE_BIT BIT(5) 933cbcb160SDavid Lanzendörfer #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 943cbcb160SDavid Lanzendörfer #define SDXC_POSEDGE_LATCH_DATA BIT(9) 953cbcb160SDavid Lanzendörfer #define SDXC_DDR_MODE BIT(10) 963cbcb160SDavid Lanzendörfer #define SDXC_MEMORY_ACCESS_DONE BIT(29) 973cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_DONE_DIRECT BIT(30) 983cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_AHB BIT(31) 993cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_DMA (0 << 31) 1003cbcb160SDavid Lanzendörfer #define SDXC_HARDWARE_RESET \ 1013cbcb160SDavid Lanzendörfer (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 1023cbcb160SDavid Lanzendörfer 1033cbcb160SDavid Lanzendörfer /* clock control bits */ 1043cbcb160SDavid Lanzendörfer #define SDXC_CARD_CLOCK_ON BIT(16) 1053cbcb160SDavid Lanzendörfer #define SDXC_LOW_POWER_ON BIT(17) 1063cbcb160SDavid Lanzendörfer 1073cbcb160SDavid Lanzendörfer /* bus width */ 1083cbcb160SDavid Lanzendörfer #define SDXC_WIDTH1 0 1093cbcb160SDavid Lanzendörfer #define SDXC_WIDTH4 1 1103cbcb160SDavid Lanzendörfer #define SDXC_WIDTH8 2 1113cbcb160SDavid Lanzendörfer 1123cbcb160SDavid Lanzendörfer /* smc command bits */ 1133cbcb160SDavid Lanzendörfer #define SDXC_RESP_EXPIRE BIT(6) 1143cbcb160SDavid Lanzendörfer #define SDXC_LONG_RESPONSE BIT(7) 1153cbcb160SDavid Lanzendörfer #define SDXC_CHECK_RESPONSE_CRC BIT(8) 1163cbcb160SDavid Lanzendörfer #define SDXC_DATA_EXPIRE BIT(9) 1173cbcb160SDavid Lanzendörfer #define SDXC_WRITE BIT(10) 1183cbcb160SDavid Lanzendörfer #define SDXC_SEQUENCE_MODE BIT(11) 1193cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOP BIT(12) 1203cbcb160SDavid Lanzendörfer #define SDXC_WAIT_PRE_OVER BIT(13) 1213cbcb160SDavid Lanzendörfer #define SDXC_STOP_ABORT_CMD BIT(14) 1223cbcb160SDavid Lanzendörfer #define SDXC_SEND_INIT_SEQUENCE BIT(15) 1233cbcb160SDavid Lanzendörfer #define SDXC_UPCLK_ONLY BIT(21) 1243cbcb160SDavid Lanzendörfer #define SDXC_READ_CEATA_DEV BIT(22) 1253cbcb160SDavid Lanzendörfer #define SDXC_CCS_EXPIRE BIT(23) 1263cbcb160SDavid Lanzendörfer #define SDXC_ENABLE_BIT_BOOT BIT(24) 1273cbcb160SDavid Lanzendörfer #define SDXC_ALT_BOOT_OPTIONS BIT(25) 1283cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ACK_EXPIRE BIT(26) 1293cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ABORT BIT(27) 1303cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_SWITCH BIT(28) 1313cbcb160SDavid Lanzendörfer #define SDXC_USE_HOLD_REGISTER BIT(29) 1323cbcb160SDavid Lanzendörfer #define SDXC_START BIT(31) 1333cbcb160SDavid Lanzendörfer 1343cbcb160SDavid Lanzendörfer /* interrupt bits */ 1353cbcb160SDavid Lanzendörfer #define SDXC_RESP_ERROR BIT(1) 1363cbcb160SDavid Lanzendörfer #define SDXC_COMMAND_DONE BIT(2) 1373cbcb160SDavid Lanzendörfer #define SDXC_DATA_OVER BIT(3) 1383cbcb160SDavid Lanzendörfer #define SDXC_TX_DATA_REQUEST BIT(4) 1393cbcb160SDavid Lanzendörfer #define SDXC_RX_DATA_REQUEST BIT(5) 1403cbcb160SDavid Lanzendörfer #define SDXC_RESP_CRC_ERROR BIT(6) 1413cbcb160SDavid Lanzendörfer #define SDXC_DATA_CRC_ERROR BIT(7) 1423cbcb160SDavid Lanzendörfer #define SDXC_RESP_TIMEOUT BIT(8) 1433cbcb160SDavid Lanzendörfer #define SDXC_DATA_TIMEOUT BIT(9) 1443cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 1453cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RUN_ERROR BIT(11) 1463cbcb160SDavid Lanzendörfer #define SDXC_HARD_WARE_LOCKED BIT(12) 1473cbcb160SDavid Lanzendörfer #define SDXC_START_BIT_ERROR BIT(13) 1483cbcb160SDavid Lanzendörfer #define SDXC_AUTO_COMMAND_DONE BIT(14) 1493cbcb160SDavid Lanzendörfer #define SDXC_END_BIT_ERROR BIT(15) 1503cbcb160SDavid Lanzendörfer #define SDXC_SDIO_INTERRUPT BIT(16) 1513cbcb160SDavid Lanzendörfer #define SDXC_CARD_INSERT BIT(30) 1523cbcb160SDavid Lanzendörfer #define SDXC_CARD_REMOVE BIT(31) 1533cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ERROR_BIT \ 1543cbcb160SDavid Lanzendörfer (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 1553cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 1563cbcb160SDavid Lanzendörfer SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 1573cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_DONE_BIT \ 1583cbcb160SDavid Lanzendörfer (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 1593cbcb160SDavid Lanzendörfer SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 1603cbcb160SDavid Lanzendörfer 1613cbcb160SDavid Lanzendörfer /* status */ 1623cbcb160SDavid Lanzendörfer #define SDXC_RXWL_FLAG BIT(0) 1633cbcb160SDavid Lanzendörfer #define SDXC_TXWL_FLAG BIT(1) 1643cbcb160SDavid Lanzendörfer #define SDXC_FIFO_EMPTY BIT(2) 1653cbcb160SDavid Lanzendörfer #define SDXC_FIFO_FULL BIT(3) 1663cbcb160SDavid Lanzendörfer #define SDXC_CARD_PRESENT BIT(8) 1673cbcb160SDavid Lanzendörfer #define SDXC_CARD_DATA_BUSY BIT(9) 1683cbcb160SDavid Lanzendörfer #define SDXC_DATA_FSM_BUSY BIT(10) 1693cbcb160SDavid Lanzendörfer #define SDXC_DMA_REQUEST BIT(31) 1703cbcb160SDavid Lanzendörfer #define SDXC_FIFO_SIZE 16 1713cbcb160SDavid Lanzendörfer 1723cbcb160SDavid Lanzendörfer /* Function select */ 1733cbcb160SDavid Lanzendörfer #define SDXC_CEATA_ON (0xceaa << 16) 1743cbcb160SDavid Lanzendörfer #define SDXC_SEND_IRQ_RESPONSE BIT(0) 1753cbcb160SDavid Lanzendörfer #define SDXC_SDIO_READ_WAIT BIT(1) 1763cbcb160SDavid Lanzendörfer #define SDXC_ABORT_READ_DATA BIT(2) 1773cbcb160SDavid Lanzendörfer #define SDXC_SEND_CCSD BIT(8) 1783cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 1793cbcb160SDavid Lanzendörfer #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 1803cbcb160SDavid Lanzendörfer 1813cbcb160SDavid Lanzendörfer /* IDMA controller bus mod bit field */ 1823cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SOFT_RESET BIT(0) 1833cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FIX_BURST BIT(1) 1843cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDMA_ON BIT(7) 1853cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_REFETCH_DES BIT(31) 1863cbcb160SDavid Lanzendörfer 1873cbcb160SDavid Lanzendörfer /* IDMA status bit field */ 1883cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 1893cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 1903cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 1913cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 1923cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 1933cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 1943cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 1953cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 1963cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDLE (0 << 13) 1973cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SUSPEND (1 << 13) 1983cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_READ (2 << 13) 1993cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CHECK (3 << 13) 2003cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 2013cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 2023cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ (6 << 13) 2033cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE (7 << 13) 2043cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 2053cbcb160SDavid Lanzendörfer 2063cbcb160SDavid Lanzendörfer /* 2073cbcb160SDavid Lanzendörfer * If the idma-des-size-bits of property is ie 13, bufsize bits are: 2083cbcb160SDavid Lanzendörfer * Bits 0-12: buf1 size 2093cbcb160SDavid Lanzendörfer * Bits 13-25: buf2 size 2103cbcb160SDavid Lanzendörfer * Bits 26-31: not used 2113cbcb160SDavid Lanzendörfer * Since we only ever set buf1 size, we can simply store it directly. 2123cbcb160SDavid Lanzendörfer */ 2133cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 2143cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 2153cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 2163cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 2173cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 2183cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 2193cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 2203cbcb160SDavid Lanzendörfer 22151424b28SHans de Goede #define SDXC_CLK_400K 0 22251424b28SHans de Goede #define SDXC_CLK_25M 1 22351424b28SHans de Goede #define SDXC_CLK_50M 2 22451424b28SHans de Goede #define SDXC_CLK_50M_DDR 3 2252a7aa63aSChen-Yu Tsai #define SDXC_CLK_50M_DDR_8BIT 4 22651424b28SHans de Goede 227e1b8dfd1SIcenowy Zheng #define SDXC_2X_TIMING_MODE BIT(31) 228e1b8dfd1SIcenowy Zheng 229e1b8dfd1SIcenowy Zheng #define SDXC_CAL_START BIT(15) 230e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DONE BIT(14) 231e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SHIFT 8 232e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_EN BIT(7) 233e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_SHIFT 0 234e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_MASK 0x3f 235e1b8dfd1SIcenowy Zheng 236e1b8dfd1SIcenowy Zheng #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 237e1b8dfd1SIcenowy Zheng 23851424b28SHans de Goede struct sunxi_mmc_clk_delay { 23951424b28SHans de Goede u32 output; 24051424b28SHans de Goede u32 sample; 24151424b28SHans de Goede }; 24251424b28SHans de Goede 2433cbcb160SDavid Lanzendörfer struct sunxi_idma_des { 2442dd110b2SMichael Weiser __le32 config; 2452dd110b2SMichael Weiser __le32 buf_size; 2462dd110b2SMichael Weiser __le32 buf_addr_ptr1; 2472dd110b2SMichael Weiser __le32 buf_addr_ptr2; 2483cbcb160SDavid Lanzendörfer }; 2493cbcb160SDavid Lanzendörfer 25086a93317SHans de Goede struct sunxi_mmc_cfg { 25186a93317SHans de Goede u32 idma_des_size_bits; 25286a93317SHans de Goede const struct sunxi_mmc_clk_delay *clk_delays; 253e1b8dfd1SIcenowy Zheng 254e1b8dfd1SIcenowy Zheng /* does the IP block support autocalibration? */ 255e1b8dfd1SIcenowy Zheng bool can_calibrate; 2569a37e53eSMaxime Ripard 2579a37e53eSMaxime Ripard bool needs_new_timings; 25886a93317SHans de Goede }; 25986a93317SHans de Goede 2603cbcb160SDavid Lanzendörfer struct sunxi_mmc_host { 2613cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 2623cbcb160SDavid Lanzendörfer struct reset_control *reset; 26386a93317SHans de Goede const struct sunxi_mmc_cfg *cfg; 2643cbcb160SDavid Lanzendörfer 2653cbcb160SDavid Lanzendörfer /* IO mapping base */ 2663cbcb160SDavid Lanzendörfer void __iomem *reg_base; 2673cbcb160SDavid Lanzendörfer 2683cbcb160SDavid Lanzendörfer /* clock management */ 2693cbcb160SDavid Lanzendörfer struct clk *clk_ahb; 2703cbcb160SDavid Lanzendörfer struct clk *clk_mmc; 2716c09bb85SMaxime Ripard struct clk *clk_sample; 2726c09bb85SMaxime Ripard struct clk *clk_output; 2733cbcb160SDavid Lanzendörfer 2743cbcb160SDavid Lanzendörfer /* irq */ 2753cbcb160SDavid Lanzendörfer spinlock_t lock; 2763cbcb160SDavid Lanzendörfer int irq; 2773cbcb160SDavid Lanzendörfer u32 int_sum; 2783cbcb160SDavid Lanzendörfer u32 sdio_imask; 2793cbcb160SDavid Lanzendörfer 2803cbcb160SDavid Lanzendörfer /* dma */ 2813cbcb160SDavid Lanzendörfer dma_addr_t sg_dma; 2823cbcb160SDavid Lanzendörfer void *sg_cpu; 2833cbcb160SDavid Lanzendörfer bool wait_dma; 2843cbcb160SDavid Lanzendörfer 2853cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 2863cbcb160SDavid Lanzendörfer struct mmc_request *manual_stop_mrq; 2873cbcb160SDavid Lanzendörfer int ferror; 288f771f6e8SChen-Yu Tsai 289f771f6e8SChen-Yu Tsai /* vqmmc */ 290f771f6e8SChen-Yu Tsai bool vqmmc_enabled; 2913cbcb160SDavid Lanzendörfer }; 2923cbcb160SDavid Lanzendörfer 2933cbcb160SDavid Lanzendörfer static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 2943cbcb160SDavid Lanzendörfer { 2953cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(250); 2963cbcb160SDavid Lanzendörfer u32 rval; 2973cbcb160SDavid Lanzendörfer 2980f0fcd37SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 2993cbcb160SDavid Lanzendörfer do { 3003cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3013cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 3023cbcb160SDavid Lanzendörfer 3033cbcb160SDavid Lanzendörfer if (rval & SDXC_HARDWARE_RESET) { 3043cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 3053cbcb160SDavid Lanzendörfer return -EIO; 3063cbcb160SDavid Lanzendörfer } 3073cbcb160SDavid Lanzendörfer 3083cbcb160SDavid Lanzendörfer return 0; 3093cbcb160SDavid Lanzendörfer } 3103cbcb160SDavid Lanzendörfer 3113cbcb160SDavid Lanzendörfer static int sunxi_mmc_init_host(struct mmc_host *mmc) 3123cbcb160SDavid Lanzendörfer { 3133cbcb160SDavid Lanzendörfer u32 rval; 3143cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 3153cbcb160SDavid Lanzendörfer 3163cbcb160SDavid Lanzendörfer if (sunxi_mmc_reset_host(host)) 3173cbcb160SDavid Lanzendörfer return -EIO; 3183cbcb160SDavid Lanzendörfer 3190314cbd4SChen-Yu Tsai /* 3200314cbd4SChen-Yu Tsai * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 3210314cbd4SChen-Yu Tsai * 3220314cbd4SChen-Yu Tsai * TODO: sun9i has a larger FIFO and supports higher trigger values 3230314cbd4SChen-Yu Tsai */ 3243cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FTRGL, 0x20070008); 3250314cbd4SChen-Yu Tsai /* Maximum timeout value */ 3263cbcb160SDavid Lanzendörfer mmc_writel(host, REG_TMOUT, 0xffffffff); 3270314cbd4SChen-Yu Tsai /* Unmask SDIO interrupt if needed */ 3283cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 3290314cbd4SChen-Yu Tsai /* Clear all pending interrupts */ 3303cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffffffff); 3310314cbd4SChen-Yu Tsai /* Debug register? undocumented */ 3323cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DBGC, 0xdeb); 3330314cbd4SChen-Yu Tsai /* Enable CEATA support */ 3343cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 3350314cbd4SChen-Yu Tsai /* Set DMA descriptor list base address */ 3363cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DLBA, host->sg_dma); 3373cbcb160SDavid Lanzendörfer 3383cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3393cbcb160SDavid Lanzendörfer rval |= SDXC_INTERRUPT_ENABLE_BIT; 3400314cbd4SChen-Yu Tsai /* Undocumented, but found in Allwinner code */ 3413cbcb160SDavid Lanzendörfer rval &= ~SDXC_ACCESS_DONE_DIRECT; 3423cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 3433cbcb160SDavid Lanzendörfer 3443cbcb160SDavid Lanzendörfer return 0; 3453cbcb160SDavid Lanzendörfer } 3463cbcb160SDavid Lanzendörfer 3473cbcb160SDavid Lanzendörfer static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 3483cbcb160SDavid Lanzendörfer struct mmc_data *data) 3493cbcb160SDavid Lanzendörfer { 3503cbcb160SDavid Lanzendörfer struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 351d34712d2SArnd Bergmann dma_addr_t next_desc = host->sg_dma; 35286a93317SHans de Goede int i, max_len = (1 << host->cfg->idma_des_size_bits); 3533cbcb160SDavid Lanzendörfer 3543cbcb160SDavid Lanzendörfer for (i = 0; i < data->sg_len; i++) { 3552dd110b2SMichael Weiser pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 3562dd110b2SMichael Weiser SDXC_IDMAC_DES0_OWN | 3572dd110b2SMichael Weiser SDXC_IDMAC_DES0_DIC); 3583cbcb160SDavid Lanzendörfer 3593cbcb160SDavid Lanzendörfer if (data->sg[i].length == max_len) 3603cbcb160SDavid Lanzendörfer pdes[i].buf_size = 0; /* 0 == max_len */ 3613cbcb160SDavid Lanzendörfer else 3622dd110b2SMichael Weiser pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 3633cbcb160SDavid Lanzendörfer 364d34712d2SArnd Bergmann next_desc += sizeof(struct sunxi_idma_des); 3652dd110b2SMichael Weiser pdes[i].buf_addr_ptr1 = 3662dd110b2SMichael Weiser cpu_to_le32(sg_dma_address(&data->sg[i])); 3672dd110b2SMichael Weiser pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); 3683cbcb160SDavid Lanzendörfer } 3693cbcb160SDavid Lanzendörfer 3702dd110b2SMichael Weiser pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 3712dd110b2SMichael Weiser pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 3722dd110b2SMichael Weiser SDXC_IDMAC_DES0_ER); 3732dd110b2SMichael Weiser pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 374e8a59049SHans de Goede pdes[i - 1].buf_addr_ptr2 = 0; 3753cbcb160SDavid Lanzendörfer 3763cbcb160SDavid Lanzendörfer /* 3773cbcb160SDavid Lanzendörfer * Avoid the io-store starting the idmac hitting io-mem before the 3783cbcb160SDavid Lanzendörfer * descriptors hit the main-mem. 3793cbcb160SDavid Lanzendörfer */ 3803cbcb160SDavid Lanzendörfer wmb(); 3813cbcb160SDavid Lanzendörfer } 3823cbcb160SDavid Lanzendörfer 3833cbcb160SDavid Lanzendörfer static enum dma_data_direction sunxi_mmc_get_dma_dir(struct mmc_data *data) 3843cbcb160SDavid Lanzendörfer { 3853cbcb160SDavid Lanzendörfer if (data->flags & MMC_DATA_WRITE) 3863cbcb160SDavid Lanzendörfer return DMA_TO_DEVICE; 3873cbcb160SDavid Lanzendörfer else 3883cbcb160SDavid Lanzendörfer return DMA_FROM_DEVICE; 3893cbcb160SDavid Lanzendörfer } 3903cbcb160SDavid Lanzendörfer 3913cbcb160SDavid Lanzendörfer static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 3923cbcb160SDavid Lanzendörfer struct mmc_data *data) 3933cbcb160SDavid Lanzendörfer { 3943cbcb160SDavid Lanzendörfer u32 i, dma_len; 3953cbcb160SDavid Lanzendörfer struct scatterlist *sg; 3963cbcb160SDavid Lanzendörfer 3973cbcb160SDavid Lanzendörfer dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 3983cbcb160SDavid Lanzendörfer sunxi_mmc_get_dma_dir(data)); 3993cbcb160SDavid Lanzendörfer if (dma_len == 0) { 4003cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 4013cbcb160SDavid Lanzendörfer return -ENOMEM; 4023cbcb160SDavid Lanzendörfer } 4033cbcb160SDavid Lanzendörfer 4043cbcb160SDavid Lanzendörfer for_each_sg(data->sg, sg, data->sg_len, i) { 4053cbcb160SDavid Lanzendörfer if (sg->offset & 3 || sg->length & 3) { 4063cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), 4073cbcb160SDavid Lanzendörfer "unaligned scatterlist: os %x length %d\n", 4083cbcb160SDavid Lanzendörfer sg->offset, sg->length); 4093cbcb160SDavid Lanzendörfer return -EINVAL; 4103cbcb160SDavid Lanzendörfer } 4113cbcb160SDavid Lanzendörfer } 4123cbcb160SDavid Lanzendörfer 4133cbcb160SDavid Lanzendörfer return 0; 4143cbcb160SDavid Lanzendörfer } 4153cbcb160SDavid Lanzendörfer 4163cbcb160SDavid Lanzendörfer static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 4173cbcb160SDavid Lanzendörfer struct mmc_data *data) 4183cbcb160SDavid Lanzendörfer { 4193cbcb160SDavid Lanzendörfer u32 rval; 4203cbcb160SDavid Lanzendörfer 4213cbcb160SDavid Lanzendörfer sunxi_mmc_init_idma_des(host, data); 4223cbcb160SDavid Lanzendörfer 4233cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 4243cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_ENABLE_BIT; 4253cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4263cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 4273cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4283cbcb160SDavid Lanzendörfer 4293cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 4303cbcb160SDavid Lanzendörfer 4313cbcb160SDavid Lanzendörfer if (!(data->flags & MMC_DATA_WRITE)) 4323cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 4333cbcb160SDavid Lanzendörfer 4343cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 4353cbcb160SDavid Lanzendörfer SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 4363cbcb160SDavid Lanzendörfer } 4373cbcb160SDavid Lanzendörfer 4383cbcb160SDavid Lanzendörfer static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 4393cbcb160SDavid Lanzendörfer struct mmc_request *req) 4403cbcb160SDavid Lanzendörfer { 4413cbcb160SDavid Lanzendörfer u32 arg, cmd_val, ri; 4423cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(1000); 4433cbcb160SDavid Lanzendörfer 4443cbcb160SDavid Lanzendörfer cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 4453cbcb160SDavid Lanzendörfer SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 4463cbcb160SDavid Lanzendörfer 4473cbcb160SDavid Lanzendörfer if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 4483cbcb160SDavid Lanzendörfer cmd_val |= SD_IO_RW_DIRECT; 4493cbcb160SDavid Lanzendörfer arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 4503cbcb160SDavid Lanzendörfer ((req->cmd->arg >> 28) & 0x7); 4513cbcb160SDavid Lanzendörfer } else { 4523cbcb160SDavid Lanzendörfer cmd_val |= MMC_STOP_TRANSMISSION; 4533cbcb160SDavid Lanzendörfer arg = 0; 4543cbcb160SDavid Lanzendörfer } 4553cbcb160SDavid Lanzendörfer 4563cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, arg); 4573cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 4583cbcb160SDavid Lanzendörfer 4593cbcb160SDavid Lanzendörfer do { 4603cbcb160SDavid Lanzendörfer ri = mmc_readl(host, REG_RINTR); 4613cbcb160SDavid Lanzendörfer } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 4623cbcb160SDavid Lanzendörfer time_before(jiffies, expire)); 4633cbcb160SDavid Lanzendörfer 4643cbcb160SDavid Lanzendörfer if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 4653cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 4663cbcb160SDavid Lanzendörfer if (req->stop) 4673cbcb160SDavid Lanzendörfer req->stop->resp[0] = -ETIMEDOUT; 4683cbcb160SDavid Lanzendörfer } else { 4693cbcb160SDavid Lanzendörfer if (req->stop) 4703cbcb160SDavid Lanzendörfer req->stop->resp[0] = mmc_readl(host, REG_RESP0); 4713cbcb160SDavid Lanzendörfer } 4723cbcb160SDavid Lanzendörfer 4733cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 4743cbcb160SDavid Lanzendörfer } 4753cbcb160SDavid Lanzendörfer 4763cbcb160SDavid Lanzendörfer static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 4773cbcb160SDavid Lanzendörfer { 4783cbcb160SDavid Lanzendörfer struct mmc_command *cmd = host->mrq->cmd; 4793cbcb160SDavid Lanzendörfer struct mmc_data *data = host->mrq->data; 4803cbcb160SDavid Lanzendörfer 4813cbcb160SDavid Lanzendörfer /* For some cmds timeout is normal with sd/mmc cards */ 4823cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 4833cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 4843cbcb160SDavid Lanzendörfer cmd->opcode == SD_IO_RW_DIRECT)) 4853cbcb160SDavid Lanzendörfer return; 4863cbcb160SDavid Lanzendörfer 4873cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), 4883cbcb160SDavid Lanzendörfer "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 4893cbcb160SDavid Lanzendörfer host->mmc->index, cmd->opcode, 4903cbcb160SDavid Lanzendörfer data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 4913cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 4923cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 4933cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 4943cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 4953cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 4963cbcb160SDavid Lanzendörfer host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 4973cbcb160SDavid Lanzendörfer host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 4983cbcb160SDavid Lanzendörfer host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 4993cbcb160SDavid Lanzendörfer host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 5003cbcb160SDavid Lanzendörfer ); 5013cbcb160SDavid Lanzendörfer } 5023cbcb160SDavid Lanzendörfer 5033cbcb160SDavid Lanzendörfer /* Called in interrupt context! */ 5043cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 5053cbcb160SDavid Lanzendörfer { 5063cbcb160SDavid Lanzendörfer struct mmc_request *mrq = host->mrq; 5073cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 5083cbcb160SDavid Lanzendörfer u32 rval; 5093cbcb160SDavid Lanzendörfer 5103cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 5113cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, 0); 5123cbcb160SDavid Lanzendörfer 5133cbcb160SDavid Lanzendörfer if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 5143cbcb160SDavid Lanzendörfer sunxi_mmc_dump_errinfo(host); 5153cbcb160SDavid Lanzendörfer mrq->cmd->error = -ETIMEDOUT; 5163cbcb160SDavid Lanzendörfer 5173cbcb160SDavid Lanzendörfer if (data) { 5183cbcb160SDavid Lanzendörfer data->error = -ETIMEDOUT; 5193cbcb160SDavid Lanzendörfer host->manual_stop_mrq = mrq; 5203cbcb160SDavid Lanzendörfer } 5213cbcb160SDavid Lanzendörfer 5223cbcb160SDavid Lanzendörfer if (mrq->stop) 5233cbcb160SDavid Lanzendörfer mrq->stop->error = -ETIMEDOUT; 5243cbcb160SDavid Lanzendörfer } else { 5253cbcb160SDavid Lanzendörfer if (mrq->cmd->flags & MMC_RSP_136) { 5263cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 5273cbcb160SDavid Lanzendörfer mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 5283cbcb160SDavid Lanzendörfer mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 5293cbcb160SDavid Lanzendörfer mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 5303cbcb160SDavid Lanzendörfer } else { 5313cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 5323cbcb160SDavid Lanzendörfer } 5333cbcb160SDavid Lanzendörfer 5343cbcb160SDavid Lanzendörfer if (data) 5353cbcb160SDavid Lanzendörfer data->bytes_xfered = data->blocks * data->blksz; 5363cbcb160SDavid Lanzendörfer } 5373cbcb160SDavid Lanzendörfer 5383cbcb160SDavid Lanzendörfer if (data) { 5393cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, 0x337); 5403cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 0); 5413cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 5423cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 5433cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5443cbcb160SDavid Lanzendörfer rval &= ~SDXC_DMA_ENABLE_BIT; 5453cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5463cbcb160SDavid Lanzendörfer rval |= SDXC_FIFO_RESET; 5473cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5483cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 5493cbcb160SDavid Lanzendörfer sunxi_mmc_get_dma_dir(data)); 5503cbcb160SDavid Lanzendörfer } 5513cbcb160SDavid Lanzendörfer 5523cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 5533cbcb160SDavid Lanzendörfer 5543cbcb160SDavid Lanzendörfer host->mrq = NULL; 5553cbcb160SDavid Lanzendörfer host->int_sum = 0; 5563cbcb160SDavid Lanzendörfer host->wait_dma = false; 5573cbcb160SDavid Lanzendörfer 5583cbcb160SDavid Lanzendörfer return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 5593cbcb160SDavid Lanzendörfer } 5603cbcb160SDavid Lanzendörfer 5613cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 5623cbcb160SDavid Lanzendörfer { 5633cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 5643cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 5653cbcb160SDavid Lanzendörfer u32 msk_int, idma_int; 5663cbcb160SDavid Lanzendörfer bool finalize = false; 5673cbcb160SDavid Lanzendörfer bool sdio_int = false; 5683cbcb160SDavid Lanzendörfer irqreturn_t ret = IRQ_HANDLED; 5693cbcb160SDavid Lanzendörfer 5703cbcb160SDavid Lanzendörfer spin_lock(&host->lock); 5713cbcb160SDavid Lanzendörfer 5723cbcb160SDavid Lanzendörfer idma_int = mmc_readl(host, REG_IDST); 5733cbcb160SDavid Lanzendörfer msk_int = mmc_readl(host, REG_MISTA); 5743cbcb160SDavid Lanzendörfer 5753cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 5763cbcb160SDavid Lanzendörfer host->mrq, msk_int, idma_int); 5773cbcb160SDavid Lanzendörfer 5783cbcb160SDavid Lanzendörfer mrq = host->mrq; 5793cbcb160SDavid Lanzendörfer if (mrq) { 5803cbcb160SDavid Lanzendörfer if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 5813cbcb160SDavid Lanzendörfer host->wait_dma = false; 5823cbcb160SDavid Lanzendörfer 5833cbcb160SDavid Lanzendörfer host->int_sum |= msk_int; 5843cbcb160SDavid Lanzendörfer 5853cbcb160SDavid Lanzendörfer /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 5863cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_RESP_TIMEOUT) && 5873cbcb160SDavid Lanzendörfer !(host->int_sum & SDXC_COMMAND_DONE)) 5883cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, 5893cbcb160SDavid Lanzendörfer host->sdio_imask | SDXC_COMMAND_DONE); 5903cbcb160SDavid Lanzendörfer /* Don't wait for dma on error */ 5913cbcb160SDavid Lanzendörfer else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 5923cbcb160SDavid Lanzendörfer finalize = true; 5933cbcb160SDavid Lanzendörfer else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 5943cbcb160SDavid Lanzendörfer !host->wait_dma) 5953cbcb160SDavid Lanzendörfer finalize = true; 5963cbcb160SDavid Lanzendörfer } 5973cbcb160SDavid Lanzendörfer 5983cbcb160SDavid Lanzendörfer if (msk_int & SDXC_SDIO_INTERRUPT) 5993cbcb160SDavid Lanzendörfer sdio_int = true; 6003cbcb160SDavid Lanzendörfer 6013cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, msk_int); 6023cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, idma_int); 6033cbcb160SDavid Lanzendörfer 6043cbcb160SDavid Lanzendörfer if (finalize) 6053cbcb160SDavid Lanzendörfer ret = sunxi_mmc_finalize_request(host); 6063cbcb160SDavid Lanzendörfer 6073cbcb160SDavid Lanzendörfer spin_unlock(&host->lock); 6083cbcb160SDavid Lanzendörfer 6093cbcb160SDavid Lanzendörfer if (finalize && ret == IRQ_HANDLED) 6103cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6113cbcb160SDavid Lanzendörfer 6123cbcb160SDavid Lanzendörfer if (sdio_int) 6133cbcb160SDavid Lanzendörfer mmc_signal_sdio_irq(host->mmc); 6143cbcb160SDavid Lanzendörfer 6153cbcb160SDavid Lanzendörfer return ret; 6163cbcb160SDavid Lanzendörfer } 6173cbcb160SDavid Lanzendörfer 6183cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 6193cbcb160SDavid Lanzendörfer { 6203cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 6213cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 6223cbcb160SDavid Lanzendörfer unsigned long iflags; 6233cbcb160SDavid Lanzendörfer 6243cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6253cbcb160SDavid Lanzendörfer mrq = host->manual_stop_mrq; 6263cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6273cbcb160SDavid Lanzendörfer 6283cbcb160SDavid Lanzendörfer if (!mrq) { 6293cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 6303cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6313cbcb160SDavid Lanzendörfer } 6323cbcb160SDavid Lanzendörfer 6333cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 634dd9b3803SDavid Lanzendörfer 635dd9b3803SDavid Lanzendörfer /* 636dd9b3803SDavid Lanzendörfer * We will never have more than one outstanding request, 637dd9b3803SDavid Lanzendörfer * and we do not complete the request until after 638dd9b3803SDavid Lanzendörfer * we've cleared host->manual_stop_mrq so we do not need to 639dd9b3803SDavid Lanzendörfer * spin lock this function. 640dd9b3803SDavid Lanzendörfer * Additionally we have wait states within this function 641dd9b3803SDavid Lanzendörfer * so having it in a lock is a very bad idea. 642dd9b3803SDavid Lanzendörfer */ 6433cbcb160SDavid Lanzendörfer sunxi_mmc_send_manual_stop(host, mrq); 6443cbcb160SDavid Lanzendörfer 6453cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6463cbcb160SDavid Lanzendörfer host->manual_stop_mrq = NULL; 6473cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6483cbcb160SDavid Lanzendörfer 6493cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6503cbcb160SDavid Lanzendörfer 6513cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6523cbcb160SDavid Lanzendörfer } 6533cbcb160SDavid Lanzendörfer 6543cbcb160SDavid Lanzendörfer static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 6553cbcb160SDavid Lanzendörfer { 6567bb9c244SMichal Suchanek unsigned long expire = jiffies + msecs_to_jiffies(750); 6573cbcb160SDavid Lanzendörfer u32 rval; 6583cbcb160SDavid Lanzendörfer 6593cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 6603cbcb160SDavid Lanzendörfer rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON); 6613cbcb160SDavid Lanzendörfer 6623cbcb160SDavid Lanzendörfer if (oclk_en) 6633cbcb160SDavid Lanzendörfer rval |= SDXC_CARD_CLOCK_ON; 6643cbcb160SDavid Lanzendörfer 6653cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 6663cbcb160SDavid Lanzendörfer 6673cbcb160SDavid Lanzendörfer rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 6683cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, rval); 6693cbcb160SDavid Lanzendörfer 6703cbcb160SDavid Lanzendörfer do { 6713cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CMDR); 6723cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_START)); 6733cbcb160SDavid Lanzendörfer 6743cbcb160SDavid Lanzendörfer /* clear irq status bits set by the command */ 6753cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 6763cbcb160SDavid Lanzendörfer mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 6773cbcb160SDavid Lanzendörfer 6783cbcb160SDavid Lanzendörfer if (rval & SDXC_START) { 6793cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 6803cbcb160SDavid Lanzendörfer return -EIO; 6813cbcb160SDavid Lanzendörfer } 6823cbcb160SDavid Lanzendörfer 6833cbcb160SDavid Lanzendörfer return 0; 6843cbcb160SDavid Lanzendörfer } 6853cbcb160SDavid Lanzendörfer 686e1b8dfd1SIcenowy Zheng static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 687e1b8dfd1SIcenowy Zheng { 688e1b8dfd1SIcenowy Zheng if (!host->cfg->can_calibrate) 689e1b8dfd1SIcenowy Zheng return 0; 690e1b8dfd1SIcenowy Zheng 691860fdf89SMaxime Ripard /* 692860fdf89SMaxime Ripard * FIXME: 693860fdf89SMaxime Ripard * This is not clear how the calibration is supposed to work 694860fdf89SMaxime Ripard * yet. The best rate have been obtained by simply setting the 695860fdf89SMaxime Ripard * delay to 0, as Allwinner does in its BSP. 696860fdf89SMaxime Ripard * 697860fdf89SMaxime Ripard * The only mode that doesn't have such a delay is HS400, that 698860fdf89SMaxime Ripard * is in itself a TODO. 699860fdf89SMaxime Ripard */ 700860fdf89SMaxime Ripard writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 701e1b8dfd1SIcenowy Zheng 702e1b8dfd1SIcenowy Zheng return 0; 703e1b8dfd1SIcenowy Zheng } 704e1b8dfd1SIcenowy Zheng 705f2cecb70SHans de Goede static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 706f2cecb70SHans de Goede struct mmc_ios *ios, u32 rate) 707f2cecb70SHans de Goede { 708f2cecb70SHans de Goede int index; 709f2cecb70SHans de Goede 710b465646eSHans de Goede if (!host->cfg->clk_delays) 711b465646eSHans de Goede return 0; 712b465646eSHans de Goede 713f2cecb70SHans de Goede /* determine delays */ 714f2cecb70SHans de Goede if (rate <= 400000) { 715f2cecb70SHans de Goede index = SDXC_CLK_400K; 716f2cecb70SHans de Goede } else if (rate <= 25000000) { 717f2cecb70SHans de Goede index = SDXC_CLK_25M; 718f2cecb70SHans de Goede } else if (rate <= 52000000) { 719f2cecb70SHans de Goede if (ios->timing != MMC_TIMING_UHS_DDR50 && 720f2cecb70SHans de Goede ios->timing != MMC_TIMING_MMC_DDR52) { 721f2cecb70SHans de Goede index = SDXC_CLK_50M; 722f2cecb70SHans de Goede } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 723f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR_8BIT; 724f2cecb70SHans de Goede } else { 725f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR; 726f2cecb70SHans de Goede } 727f2cecb70SHans de Goede } else { 728f2cecb70SHans de Goede return -EINVAL; 729f2cecb70SHans de Goede } 730f2cecb70SHans de Goede 731f2cecb70SHans de Goede clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 732f2cecb70SHans de Goede clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 733f2cecb70SHans de Goede 734f2cecb70SHans de Goede return 0; 735f2cecb70SHans de Goede } 736f2cecb70SHans de Goede 7373cbcb160SDavid Lanzendörfer static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 7383cbcb160SDavid Lanzendörfer struct mmc_ios *ios) 7393cbcb160SDavid Lanzendörfer { 74063311becSJean-Francois Moine long rate; 74163311becSJean-Francois Moine u32 rval, clock = ios->clock; 7423cbcb160SDavid Lanzendörfer int ret; 7433cbcb160SDavid Lanzendörfer 74439cc281fSMaxime Ripard ret = sunxi_mmc_oclk_onoff(host, 0); 74539cc281fSMaxime Ripard if (ret) 74639cc281fSMaxime Ripard return ret; 74739cc281fSMaxime Ripard 7489479074eSMaxime Ripard if (!ios->clock) 7499479074eSMaxime Ripard return 0; 7509479074eSMaxime Ripard 7512a7aa63aSChen-Yu Tsai /* 8 bit DDR requires a higher module clock */ 7522a7aa63aSChen-Yu Tsai if (ios->timing == MMC_TIMING_MMC_DDR52 && 7532a7aa63aSChen-Yu Tsai ios->bus_width == MMC_BUS_WIDTH_8) 7542a7aa63aSChen-Yu Tsai clock <<= 1; 7552a7aa63aSChen-Yu Tsai 7562a7aa63aSChen-Yu Tsai rate = clk_round_rate(host->clk_mmc, clock); 75763311becSJean-Francois Moine if (rate < 0) { 75863311becSJean-Francois Moine dev_err(mmc_dev(host->mmc), "error rounding clk to %d: %ld\n", 75963311becSJean-Francois Moine clock, rate); 76063311becSJean-Francois Moine return rate; 76163311becSJean-Francois Moine } 76263311becSJean-Francois Moine dev_dbg(mmc_dev(host->mmc), "setting clk to %d, rounded %ld\n", 7632a7aa63aSChen-Yu Tsai clock, rate); 7643cbcb160SDavid Lanzendörfer 7653cbcb160SDavid Lanzendörfer /* setting clock rate */ 7663cbcb160SDavid Lanzendörfer ret = clk_set_rate(host->clk_mmc, rate); 7673cbcb160SDavid Lanzendörfer if (ret) { 76863311becSJean-Francois Moine dev_err(mmc_dev(host->mmc), "error setting clk to %ld: %d\n", 7693cbcb160SDavid Lanzendörfer rate, ret); 7703cbcb160SDavid Lanzendörfer return ret; 7713cbcb160SDavid Lanzendörfer } 7723cbcb160SDavid Lanzendörfer 7733cbcb160SDavid Lanzendörfer /* clear internal divider */ 7743cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 7753cbcb160SDavid Lanzendörfer rval &= ~0xff; 7762a7aa63aSChen-Yu Tsai /* set internal divider for 8 bit eMMC DDR, so card clock is right */ 7772a7aa63aSChen-Yu Tsai if (ios->timing == MMC_TIMING_MMC_DDR52 && 7782a7aa63aSChen-Yu Tsai ios->bus_width == MMC_BUS_WIDTH_8) { 7792a7aa63aSChen-Yu Tsai rval |= 1; 7802a7aa63aSChen-Yu Tsai rate >>= 1; 7812a7aa63aSChen-Yu Tsai } 7823cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 7833cbcb160SDavid Lanzendörfer 7849a37e53eSMaxime Ripard if (host->cfg->needs_new_timings) 7859a37e53eSMaxime Ripard mmc_writel(host, REG_SD_NTSR, SDXC_2X_TIMING_MODE); 7869a37e53eSMaxime Ripard 787f2cecb70SHans de Goede ret = sunxi_mmc_clk_set_phase(host, ios, rate); 788f2cecb70SHans de Goede if (ret) 789f2cecb70SHans de Goede return ret; 7903cbcb160SDavid Lanzendörfer 791e1b8dfd1SIcenowy Zheng ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 792e1b8dfd1SIcenowy Zheng if (ret) 793e1b8dfd1SIcenowy Zheng return ret; 794e1b8dfd1SIcenowy Zheng 795860fdf89SMaxime Ripard /* 796860fdf89SMaxime Ripard * FIXME: 797860fdf89SMaxime Ripard * 798860fdf89SMaxime Ripard * In HS400 we'll also need to calibrate the data strobe 799860fdf89SMaxime Ripard * signal. This should only happen on the MMC2 controller (at 800860fdf89SMaxime Ripard * least on the A64). 801860fdf89SMaxime Ripard */ 802e1b8dfd1SIcenowy Zheng 8033cbcb160SDavid Lanzendörfer return sunxi_mmc_oclk_onoff(host, 1); 8043cbcb160SDavid Lanzendörfer } 8053cbcb160SDavid Lanzendörfer 8063cbcb160SDavid Lanzendörfer static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 8073cbcb160SDavid Lanzendörfer { 8083cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 8093cbcb160SDavid Lanzendörfer u32 rval; 8103cbcb160SDavid Lanzendörfer 8113cbcb160SDavid Lanzendörfer /* Set the power state */ 8123cbcb160SDavid Lanzendörfer switch (ios->power_mode) { 8133cbcb160SDavid Lanzendörfer case MMC_POWER_ON: 8143cbcb160SDavid Lanzendörfer break; 8153cbcb160SDavid Lanzendörfer 8163cbcb160SDavid Lanzendörfer case MMC_POWER_UP: 817424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) { 818424feb59SMaxime Ripard host->ferror = mmc_regulator_set_ocr(mmc, 819424feb59SMaxime Ripard mmc->supply.vmmc, 8204159215aSChen-Yu Tsai ios->vdd); 8214159215aSChen-Yu Tsai if (host->ferror) 8224159215aSChen-Yu Tsai return; 823424feb59SMaxime Ripard } 8243cbcb160SDavid Lanzendörfer 825f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc)) { 826f771f6e8SChen-Yu Tsai host->ferror = regulator_enable(mmc->supply.vqmmc); 827f771f6e8SChen-Yu Tsai if (host->ferror) { 828f771f6e8SChen-Yu Tsai dev_err(mmc_dev(mmc), 829f771f6e8SChen-Yu Tsai "failed to enable vqmmc\n"); 830f771f6e8SChen-Yu Tsai return; 831f771f6e8SChen-Yu Tsai } 832f771f6e8SChen-Yu Tsai host->vqmmc_enabled = true; 833f771f6e8SChen-Yu Tsai } 834f771f6e8SChen-Yu Tsai 8353cbcb160SDavid Lanzendörfer host->ferror = sunxi_mmc_init_host(mmc); 8363cbcb160SDavid Lanzendörfer if (host->ferror) 8373cbcb160SDavid Lanzendörfer return; 8383cbcb160SDavid Lanzendörfer 8393cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "power on!\n"); 8403cbcb160SDavid Lanzendörfer break; 8413cbcb160SDavid Lanzendörfer 8423cbcb160SDavid Lanzendörfer case MMC_POWER_OFF: 8433cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "power off!\n"); 8443cbcb160SDavid Lanzendörfer sunxi_mmc_reset_host(host); 845424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) 8463cbcb160SDavid Lanzendörfer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 847424feb59SMaxime Ripard 848f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 849f771f6e8SChen-Yu Tsai regulator_disable(mmc->supply.vqmmc); 850f771f6e8SChen-Yu Tsai host->vqmmc_enabled = false; 8513cbcb160SDavid Lanzendörfer break; 8523cbcb160SDavid Lanzendörfer } 8533cbcb160SDavid Lanzendörfer 8543cbcb160SDavid Lanzendörfer /* set bus width */ 8553cbcb160SDavid Lanzendörfer switch (ios->bus_width) { 8563cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_1: 8573cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 8583cbcb160SDavid Lanzendörfer break; 8593cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_4: 8603cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 8613cbcb160SDavid Lanzendörfer break; 8623cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_8: 8633cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 8643cbcb160SDavid Lanzendörfer break; 8653cbcb160SDavid Lanzendörfer } 8663cbcb160SDavid Lanzendörfer 8673cbcb160SDavid Lanzendörfer /* set ddr mode */ 8683cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 8692dcb305aSChen-Yu Tsai if (ios->timing == MMC_TIMING_UHS_DDR50 || 8702dcb305aSChen-Yu Tsai ios->timing == MMC_TIMING_MMC_DDR52) 8713cbcb160SDavid Lanzendörfer rval |= SDXC_DDR_MODE; 8723cbcb160SDavid Lanzendörfer else 8733cbcb160SDavid Lanzendörfer rval &= ~SDXC_DDR_MODE; 8743cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 8753cbcb160SDavid Lanzendörfer 8763cbcb160SDavid Lanzendörfer /* set up clock */ 8779479074eSMaxime Ripard if (ios->power_mode) { 8783cbcb160SDavid Lanzendörfer host->ferror = sunxi_mmc_clk_set_rate(host, ios); 8793cbcb160SDavid Lanzendörfer /* Android code had a usleep_range(50000, 55000); here */ 8803cbcb160SDavid Lanzendörfer } 8813cbcb160SDavid Lanzendörfer } 8823cbcb160SDavid Lanzendörfer 883f771f6e8SChen-Yu Tsai static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 884f771f6e8SChen-Yu Tsai { 885f771f6e8SChen-Yu Tsai /* vqmmc regulator is available */ 886f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc)) 887f771f6e8SChen-Yu Tsai return mmc_regulator_set_vqmmc(mmc, ios); 888f771f6e8SChen-Yu Tsai 889f771f6e8SChen-Yu Tsai /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 890f771f6e8SChen-Yu Tsai if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 891f771f6e8SChen-Yu Tsai return 0; 892f771f6e8SChen-Yu Tsai 893f771f6e8SChen-Yu Tsai return -EINVAL; 894f771f6e8SChen-Yu Tsai } 895f771f6e8SChen-Yu Tsai 8963cbcb160SDavid Lanzendörfer static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 8973cbcb160SDavid Lanzendörfer { 8983cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 8993cbcb160SDavid Lanzendörfer unsigned long flags; 9003cbcb160SDavid Lanzendörfer u32 imask; 9013cbcb160SDavid Lanzendörfer 9023cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, flags); 9033cbcb160SDavid Lanzendörfer 9043cbcb160SDavid Lanzendörfer imask = mmc_readl(host, REG_IMASK); 9053cbcb160SDavid Lanzendörfer if (enable) { 9063cbcb160SDavid Lanzendörfer host->sdio_imask = SDXC_SDIO_INTERRUPT; 9073cbcb160SDavid Lanzendörfer imask |= SDXC_SDIO_INTERRUPT; 9083cbcb160SDavid Lanzendörfer } else { 9093cbcb160SDavid Lanzendörfer host->sdio_imask = 0; 9103cbcb160SDavid Lanzendörfer imask &= ~SDXC_SDIO_INTERRUPT; 9113cbcb160SDavid Lanzendörfer } 9123cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, imask); 9133cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, flags); 9143cbcb160SDavid Lanzendörfer } 9153cbcb160SDavid Lanzendörfer 9163cbcb160SDavid Lanzendörfer static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 9173cbcb160SDavid Lanzendörfer { 9183cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 9193cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 0); 9203cbcb160SDavid Lanzendörfer udelay(10); 9213cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 1); 9223cbcb160SDavid Lanzendörfer udelay(300); 9233cbcb160SDavid Lanzendörfer } 9243cbcb160SDavid Lanzendörfer 9253cbcb160SDavid Lanzendörfer static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 9263cbcb160SDavid Lanzendörfer { 9273cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 9283cbcb160SDavid Lanzendörfer struct mmc_command *cmd = mrq->cmd; 9293cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 9303cbcb160SDavid Lanzendörfer unsigned long iflags; 9313cbcb160SDavid Lanzendörfer u32 imask = SDXC_INTERRUPT_ERROR_BIT; 9323cbcb160SDavid Lanzendörfer u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 933dd9b3803SDavid Lanzendörfer bool wait_dma = host->wait_dma; 9343cbcb160SDavid Lanzendörfer int ret; 9353cbcb160SDavid Lanzendörfer 9363cbcb160SDavid Lanzendörfer /* Check for set_ios errors (should never happen) */ 9373cbcb160SDavid Lanzendörfer if (host->ferror) { 9383cbcb160SDavid Lanzendörfer mrq->cmd->error = host->ferror; 9393cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 9403cbcb160SDavid Lanzendörfer return; 9413cbcb160SDavid Lanzendörfer } 9423cbcb160SDavid Lanzendörfer 9433cbcb160SDavid Lanzendörfer if (data) { 9443cbcb160SDavid Lanzendörfer ret = sunxi_mmc_map_dma(host, data); 9453cbcb160SDavid Lanzendörfer if (ret < 0) { 9463cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "map DMA failed\n"); 9473cbcb160SDavid Lanzendörfer cmd->error = ret; 9483cbcb160SDavid Lanzendörfer data->error = ret; 9493cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 9503cbcb160SDavid Lanzendörfer return; 9513cbcb160SDavid Lanzendörfer } 9523cbcb160SDavid Lanzendörfer } 9533cbcb160SDavid Lanzendörfer 9543cbcb160SDavid Lanzendörfer if (cmd->opcode == MMC_GO_IDLE_STATE) { 9553cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_INIT_SEQUENCE; 9563cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 9573cbcb160SDavid Lanzendörfer } 9583cbcb160SDavid Lanzendörfer 9593cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_PRESENT) { 9603cbcb160SDavid Lanzendörfer cmd_val |= SDXC_RESP_EXPIRE; 9613cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_136) 9623cbcb160SDavid Lanzendörfer cmd_val |= SDXC_LONG_RESPONSE; 9633cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_CRC) 9643cbcb160SDavid Lanzendörfer cmd_val |= SDXC_CHECK_RESPONSE_CRC; 9653cbcb160SDavid Lanzendörfer 9663cbcb160SDavid Lanzendörfer if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 9673cbcb160SDavid Lanzendörfer cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 9683cbcb160SDavid Lanzendörfer 9693cbcb160SDavid Lanzendörfer if (cmd->data->stop) { 9703cbcb160SDavid Lanzendörfer imask |= SDXC_AUTO_COMMAND_DONE; 9713cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_AUTO_STOP; 9723cbcb160SDavid Lanzendörfer } else { 9733cbcb160SDavid Lanzendörfer imask |= SDXC_DATA_OVER; 9743cbcb160SDavid Lanzendörfer } 9753cbcb160SDavid Lanzendörfer 9763cbcb160SDavid Lanzendörfer if (cmd->data->flags & MMC_DATA_WRITE) 9773cbcb160SDavid Lanzendörfer cmd_val |= SDXC_WRITE; 9783cbcb160SDavid Lanzendörfer else 979dd9b3803SDavid Lanzendörfer wait_dma = true; 9803cbcb160SDavid Lanzendörfer } else { 9813cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 9823cbcb160SDavid Lanzendörfer } 9833cbcb160SDavid Lanzendörfer } else { 9843cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 9853cbcb160SDavid Lanzendörfer } 9863cbcb160SDavid Lanzendörfer 9873cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 9883cbcb160SDavid Lanzendörfer cmd_val & 0x3f, cmd_val, cmd->arg, imask, 9893cbcb160SDavid Lanzendörfer mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 9903cbcb160SDavid Lanzendörfer 9913cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 9923cbcb160SDavid Lanzendörfer 9933cbcb160SDavid Lanzendörfer if (host->mrq || host->manual_stop_mrq) { 9943cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 9953cbcb160SDavid Lanzendörfer 9963cbcb160SDavid Lanzendörfer if (data) 9973cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 9983cbcb160SDavid Lanzendörfer sunxi_mmc_get_dma_dir(data)); 9993cbcb160SDavid Lanzendörfer 10003cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "request already pending\n"); 10013cbcb160SDavid Lanzendörfer mrq->cmd->error = -EBUSY; 10023cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10033cbcb160SDavid Lanzendörfer return; 10043cbcb160SDavid Lanzendörfer } 10053cbcb160SDavid Lanzendörfer 10063cbcb160SDavid Lanzendörfer if (data) { 10073cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BLKSZ, data->blksz); 10083cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 10093cbcb160SDavid Lanzendörfer sunxi_mmc_start_dma(host, data); 10103cbcb160SDavid Lanzendörfer } 10113cbcb160SDavid Lanzendörfer 10123cbcb160SDavid Lanzendörfer host->mrq = mrq; 1013dd9b3803SDavid Lanzendörfer host->wait_dma = wait_dma; 10143cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 10153cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, cmd->arg); 10163cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 10173cbcb160SDavid Lanzendörfer 10183cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 10193cbcb160SDavid Lanzendörfer } 10203cbcb160SDavid Lanzendörfer 1021c1590dd8SHans de Goede static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1022c1590dd8SHans de Goede { 1023c1590dd8SHans de Goede struct sunxi_mmc_host *host = mmc_priv(mmc); 1024c1590dd8SHans de Goede 1025c1590dd8SHans de Goede return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1026c1590dd8SHans de Goede } 1027c1590dd8SHans de Goede 10283cbcb160SDavid Lanzendörfer static struct mmc_host_ops sunxi_mmc_ops = { 10293cbcb160SDavid Lanzendörfer .request = sunxi_mmc_request, 10303cbcb160SDavid Lanzendörfer .set_ios = sunxi_mmc_set_ios, 10313cbcb160SDavid Lanzendörfer .get_ro = mmc_gpio_get_ro, 10323cbcb160SDavid Lanzendörfer .get_cd = mmc_gpio_get_cd, 10333cbcb160SDavid Lanzendörfer .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1034f771f6e8SChen-Yu Tsai .start_signal_voltage_switch = sunxi_mmc_volt_switch, 10353cbcb160SDavid Lanzendörfer .hw_reset = sunxi_mmc_hw_reset, 1036c1590dd8SHans de Goede .card_busy = sunxi_mmc_card_busy, 10373cbcb160SDavid Lanzendörfer }; 10383cbcb160SDavid Lanzendörfer 103951424b28SHans de Goede static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 104051424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 104151424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 104251424b28SHans de Goede [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 104351424b28SHans de Goede [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 10442a7aa63aSChen-Yu Tsai /* Value from A83T "new timing mode". Works but might not be right. */ 10452a7aa63aSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 104651424b28SHans de Goede }; 104751424b28SHans de Goede 104851424b28SHans de Goede static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 104951424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 105051424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 105151424b28SHans de Goede [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 10520175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 10530175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 105451424b28SHans de Goede }; 105551424b28SHans de Goede 105686a93317SHans de Goede static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 105786a93317SHans de Goede .idma_des_size_bits = 13, 1058b465646eSHans de Goede .clk_delays = NULL, 1059e1b8dfd1SIcenowy Zheng .can_calibrate = false, 106086a93317SHans de Goede }; 106186a93317SHans de Goede 106286a93317SHans de Goede static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 106386a93317SHans de Goede .idma_des_size_bits = 16, 1064b465646eSHans de Goede .clk_delays = NULL, 1065e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1066b465646eSHans de Goede }; 1067b465646eSHans de Goede 1068b465646eSHans de Goede static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1069b465646eSHans de Goede .idma_des_size_bits = 16, 107086a93317SHans de Goede .clk_delays = sunxi_mmc_clk_delays, 1071e1b8dfd1SIcenowy Zheng .can_calibrate = false, 107286a93317SHans de Goede }; 107386a93317SHans de Goede 107486a93317SHans de Goede static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 107586a93317SHans de Goede .idma_des_size_bits = 16, 107686a93317SHans de Goede .clk_delays = sun9i_mmc_clk_delays, 1077e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1078e1b8dfd1SIcenowy Zheng }; 1079e1b8dfd1SIcenowy Zheng 1080e1b8dfd1SIcenowy Zheng static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1081e1b8dfd1SIcenowy Zheng .idma_des_size_bits = 16, 1082e1b8dfd1SIcenowy Zheng .clk_delays = NULL, 1083e1b8dfd1SIcenowy Zheng .can_calibrate = true, 10849a37e53eSMaxime Ripard .needs_new_timings = true, 108586a93317SHans de Goede }; 108686a93317SHans de Goede 108786a93317SHans de Goede static const struct of_device_id sunxi_mmc_of_match[] = { 108886a93317SHans de Goede { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 108986a93317SHans de Goede { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1090b465646eSHans de Goede { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 109186a93317SHans de Goede { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1092e1b8dfd1SIcenowy Zheng { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 109386a93317SHans de Goede { /* sentinel */ } 109486a93317SHans de Goede }; 109586a93317SHans de Goede MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 109686a93317SHans de Goede 10973cbcb160SDavid Lanzendörfer static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 10983cbcb160SDavid Lanzendörfer struct platform_device *pdev) 10993cbcb160SDavid Lanzendörfer { 11003cbcb160SDavid Lanzendörfer int ret; 11013cbcb160SDavid Lanzendörfer 110286a93317SHans de Goede host->cfg = of_device_get_match_data(&pdev->dev); 110386a93317SHans de Goede if (!host->cfg) 110486a93317SHans de Goede return -EINVAL; 110551424b28SHans de Goede 11063cbcb160SDavid Lanzendörfer ret = mmc_regulator_get_supply(host->mmc); 11073cbcb160SDavid Lanzendörfer if (ret) { 11083cbcb160SDavid Lanzendörfer if (ret != -EPROBE_DEFER) 11093cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get vmmc supply\n"); 11103cbcb160SDavid Lanzendörfer return ret; 11113cbcb160SDavid Lanzendörfer } 11123cbcb160SDavid Lanzendörfer 11133cbcb160SDavid Lanzendörfer host->reg_base = devm_ioremap_resource(&pdev->dev, 11143cbcb160SDavid Lanzendörfer platform_get_resource(pdev, IORESOURCE_MEM, 0)); 11153cbcb160SDavid Lanzendörfer if (IS_ERR(host->reg_base)) 11163cbcb160SDavid Lanzendörfer return PTR_ERR(host->reg_base); 11173cbcb160SDavid Lanzendörfer 11183cbcb160SDavid Lanzendörfer host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 11193cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_ahb)) { 11203cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get ahb clock\n"); 11213cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_ahb); 11223cbcb160SDavid Lanzendörfer } 11233cbcb160SDavid Lanzendörfer 11243cbcb160SDavid Lanzendörfer host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 11253cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_mmc)) { 11263cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get mmc clock\n"); 11273cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_mmc); 11283cbcb160SDavid Lanzendörfer } 11293cbcb160SDavid Lanzendörfer 1130b465646eSHans de Goede if (host->cfg->clk_delays) { 11316c09bb85SMaxime Ripard host->clk_output = devm_clk_get(&pdev->dev, "output"); 11326c09bb85SMaxime Ripard if (IS_ERR(host->clk_output)) { 11336c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get output clock\n"); 11346c09bb85SMaxime Ripard return PTR_ERR(host->clk_output); 11356c09bb85SMaxime Ripard } 11366c09bb85SMaxime Ripard 11376c09bb85SMaxime Ripard host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 11386c09bb85SMaxime Ripard if (IS_ERR(host->clk_sample)) { 11396c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get sample clock\n"); 11406c09bb85SMaxime Ripard return PTR_ERR(host->clk_sample); 11416c09bb85SMaxime Ripard } 1142b465646eSHans de Goede } 11436c09bb85SMaxime Ripard 11449e71c589SChen-Yu Tsai host->reset = devm_reset_control_get_optional(&pdev->dev, "ahb"); 11459e71c589SChen-Yu Tsai if (PTR_ERR(host->reset) == -EPROBE_DEFER) 11469e71c589SChen-Yu Tsai return PTR_ERR(host->reset); 11473cbcb160SDavid Lanzendörfer 11483cbcb160SDavid Lanzendörfer ret = clk_prepare_enable(host->clk_ahb); 11493cbcb160SDavid Lanzendörfer if (ret) { 11503cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret); 11513cbcb160SDavid Lanzendörfer return ret; 11523cbcb160SDavid Lanzendörfer } 11533cbcb160SDavid Lanzendörfer 11543cbcb160SDavid Lanzendörfer ret = clk_prepare_enable(host->clk_mmc); 11553cbcb160SDavid Lanzendörfer if (ret) { 11563cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret); 11573cbcb160SDavid Lanzendörfer goto error_disable_clk_ahb; 11583cbcb160SDavid Lanzendörfer } 11593cbcb160SDavid Lanzendörfer 11606c09bb85SMaxime Ripard ret = clk_prepare_enable(host->clk_output); 11616c09bb85SMaxime Ripard if (ret) { 11626c09bb85SMaxime Ripard dev_err(&pdev->dev, "Enable output clk err %d\n", ret); 11636c09bb85SMaxime Ripard goto error_disable_clk_mmc; 11646c09bb85SMaxime Ripard } 11656c09bb85SMaxime Ripard 11666c09bb85SMaxime Ripard ret = clk_prepare_enable(host->clk_sample); 11676c09bb85SMaxime Ripard if (ret) { 11686c09bb85SMaxime Ripard dev_err(&pdev->dev, "Enable sample clk err %d\n", ret); 11696c09bb85SMaxime Ripard goto error_disable_clk_output; 11706c09bb85SMaxime Ripard } 11716c09bb85SMaxime Ripard 11723cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) { 11733cbcb160SDavid Lanzendörfer ret = reset_control_deassert(host->reset); 11743cbcb160SDavid Lanzendörfer if (ret) { 11753cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "reset err %d\n", ret); 11766c09bb85SMaxime Ripard goto error_disable_clk_sample; 11773cbcb160SDavid Lanzendörfer } 11783cbcb160SDavid Lanzendörfer } 11793cbcb160SDavid Lanzendörfer 11803cbcb160SDavid Lanzendörfer /* 11813cbcb160SDavid Lanzendörfer * Sometimes the controller asserts the irq on boot for some reason, 11823cbcb160SDavid Lanzendörfer * make sure the controller is in a sane state before enabling irqs. 11833cbcb160SDavid Lanzendörfer */ 11843cbcb160SDavid Lanzendörfer ret = sunxi_mmc_reset_host(host); 11853cbcb160SDavid Lanzendörfer if (ret) 11863cbcb160SDavid Lanzendörfer goto error_assert_reset; 11873cbcb160SDavid Lanzendörfer 11883cbcb160SDavid Lanzendörfer host->irq = platform_get_irq(pdev, 0); 11893cbcb160SDavid Lanzendörfer return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 11903cbcb160SDavid Lanzendörfer sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 11913cbcb160SDavid Lanzendörfer 11923cbcb160SDavid Lanzendörfer error_assert_reset: 11933cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) 11943cbcb160SDavid Lanzendörfer reset_control_assert(host->reset); 11956c09bb85SMaxime Ripard error_disable_clk_sample: 11966c09bb85SMaxime Ripard clk_disable_unprepare(host->clk_sample); 11976c09bb85SMaxime Ripard error_disable_clk_output: 11986c09bb85SMaxime Ripard clk_disable_unprepare(host->clk_output); 11993cbcb160SDavid Lanzendörfer error_disable_clk_mmc: 12003cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_mmc); 12013cbcb160SDavid Lanzendörfer error_disable_clk_ahb: 12023cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_ahb); 12033cbcb160SDavid Lanzendörfer return ret; 12043cbcb160SDavid Lanzendörfer } 12053cbcb160SDavid Lanzendörfer 12063cbcb160SDavid Lanzendörfer static int sunxi_mmc_probe(struct platform_device *pdev) 12073cbcb160SDavid Lanzendörfer { 12083cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host; 12093cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 12103cbcb160SDavid Lanzendörfer int ret; 12113cbcb160SDavid Lanzendörfer 12123cbcb160SDavid Lanzendörfer mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 12133cbcb160SDavid Lanzendörfer if (!mmc) { 12143cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "mmc alloc host failed\n"); 12153cbcb160SDavid Lanzendörfer return -ENOMEM; 12163cbcb160SDavid Lanzendörfer } 12173cbcb160SDavid Lanzendörfer 12183cbcb160SDavid Lanzendörfer host = mmc_priv(mmc); 12193cbcb160SDavid Lanzendörfer host->mmc = mmc; 12203cbcb160SDavid Lanzendörfer spin_lock_init(&host->lock); 12213cbcb160SDavid Lanzendörfer 12223cbcb160SDavid Lanzendörfer ret = sunxi_mmc_resource_request(host, pdev); 12233cbcb160SDavid Lanzendörfer if (ret) 12243cbcb160SDavid Lanzendörfer goto error_free_host; 12253cbcb160SDavid Lanzendörfer 12263cbcb160SDavid Lanzendörfer host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 12273cbcb160SDavid Lanzendörfer &host->sg_dma, GFP_KERNEL); 12283cbcb160SDavid Lanzendörfer if (!host->sg_cpu) { 12293cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 12303cbcb160SDavid Lanzendörfer ret = -ENOMEM; 12313cbcb160SDavid Lanzendörfer goto error_free_host; 12323cbcb160SDavid Lanzendörfer } 12333cbcb160SDavid Lanzendörfer 12343cbcb160SDavid Lanzendörfer mmc->ops = &sunxi_mmc_ops; 12353cbcb160SDavid Lanzendörfer mmc->max_blk_count = 8192; 12363cbcb160SDavid Lanzendörfer mmc->max_blk_size = 4096; 12373cbcb160SDavid Lanzendörfer mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 123886a93317SHans de Goede mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 12393cbcb160SDavid Lanzendörfer mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 12402dcb305aSChen-Yu Tsai /* 400kHz ~ 52MHz */ 12413cbcb160SDavid Lanzendörfer mmc->f_min = 400000; 12422dcb305aSChen-Yu Tsai mmc->f_max = 52000000; 12433df01a93SChen-Yu Tsai mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1244a4101dcbSHans de Goede MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 12453cbcb160SDavid Lanzendörfer 1246b465646eSHans de Goede if (host->cfg->clk_delays) 1247b465646eSHans de Goede mmc->caps |= MMC_CAP_1_8V_DDR; 1248b465646eSHans de Goede 12493cbcb160SDavid Lanzendörfer ret = mmc_of_parse(mmc); 12503cbcb160SDavid Lanzendörfer if (ret) 12513cbcb160SDavid Lanzendörfer goto error_free_dma; 12523cbcb160SDavid Lanzendörfer 12533cbcb160SDavid Lanzendörfer ret = mmc_add_host(mmc); 12543cbcb160SDavid Lanzendörfer if (ret) 12553cbcb160SDavid Lanzendörfer goto error_free_dma; 12563cbcb160SDavid Lanzendörfer 12573cbcb160SDavid Lanzendörfer dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); 12583cbcb160SDavid Lanzendörfer platform_set_drvdata(pdev, mmc); 12593cbcb160SDavid Lanzendörfer return 0; 12603cbcb160SDavid Lanzendörfer 12613cbcb160SDavid Lanzendörfer error_free_dma: 12623cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 12633cbcb160SDavid Lanzendörfer error_free_host: 12643cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 12653cbcb160SDavid Lanzendörfer return ret; 12663cbcb160SDavid Lanzendörfer } 12673cbcb160SDavid Lanzendörfer 12683cbcb160SDavid Lanzendörfer static int sunxi_mmc_remove(struct platform_device *pdev) 12693cbcb160SDavid Lanzendörfer { 12703cbcb160SDavid Lanzendörfer struct mmc_host *mmc = platform_get_drvdata(pdev); 12713cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 12723cbcb160SDavid Lanzendörfer 12733cbcb160SDavid Lanzendörfer mmc_remove_host(mmc); 12743cbcb160SDavid Lanzendörfer disable_irq(host->irq); 12753cbcb160SDavid Lanzendörfer sunxi_mmc_reset_host(host); 12763cbcb160SDavid Lanzendörfer 12773cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) 12783cbcb160SDavid Lanzendörfer reset_control_assert(host->reset); 12793cbcb160SDavid Lanzendörfer 12804c5f4bf4SHans de Goede clk_disable_unprepare(host->clk_sample); 12814c5f4bf4SHans de Goede clk_disable_unprepare(host->clk_output); 12823cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_mmc); 12833cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_ahb); 12843cbcb160SDavid Lanzendörfer 12853cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 12863cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 12873cbcb160SDavid Lanzendörfer 12883cbcb160SDavid Lanzendörfer return 0; 12893cbcb160SDavid Lanzendörfer } 12903cbcb160SDavid Lanzendörfer 12913cbcb160SDavid Lanzendörfer static struct platform_driver sunxi_mmc_driver = { 12923cbcb160SDavid Lanzendörfer .driver = { 12933cbcb160SDavid Lanzendörfer .name = "sunxi-mmc", 12943cbcb160SDavid Lanzendörfer .of_match_table = of_match_ptr(sunxi_mmc_of_match), 12953cbcb160SDavid Lanzendörfer }, 12963cbcb160SDavid Lanzendörfer .probe = sunxi_mmc_probe, 12973cbcb160SDavid Lanzendörfer .remove = sunxi_mmc_remove, 12983cbcb160SDavid Lanzendörfer }; 12993cbcb160SDavid Lanzendörfer module_platform_driver(sunxi_mmc_driver); 13003cbcb160SDavid Lanzendörfer 13013cbcb160SDavid Lanzendörfer MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 13023cbcb160SDavid Lanzendörfer MODULE_LICENSE("GPL v2"); 13033cbcb160SDavid Lanzendörfer MODULE_AUTHOR("David Lanzend�rfer <david.lanzendoerfer@o2s.ch>"); 13043cbcb160SDavid Lanzendörfer MODULE_ALIAS("platform:sunxi-mmc"); 1305