12874c5fdSThomas Gleixner // SPDX-License-Identifier: GPL-2.0-or-later 23cbcb160SDavid Lanzendörfer /* 33cbcb160SDavid Lanzendörfer * Driver for sunxi SD/MMC host controllers 43cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 53cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 63cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 71907e386SAdam Borowski * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 83cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 94fb3ce07SMaxime Ripard * (C) Copyright 2017 Sootech SA 103cbcb160SDavid Lanzendörfer */ 113cbcb160SDavid Lanzendörfer 123cbcb160SDavid Lanzendörfer #include <linux/clk.h> 13ff39e7f7SChen-Yu Tsai #include <linux/clk/sunxi-ng.h> 14743b819eSMaxime Ripard #include <linux/delay.h> 15743b819eSMaxime Ripard #include <linux/device.h> 163cbcb160SDavid Lanzendörfer #include <linux/dma-mapping.h> 17743b819eSMaxime Ripard #include <linux/err.h> 18743b819eSMaxime Ripard #include <linux/interrupt.h> 19743b819eSMaxime Ripard #include <linux/io.h> 20743b819eSMaxime Ripard #include <linux/kernel.h> 21743b819eSMaxime Ripard #include <linux/mmc/card.h> 22743b819eSMaxime Ripard #include <linux/mmc/core.h> 23743b819eSMaxime Ripard #include <linux/mmc/host.h> 24743b819eSMaxime Ripard #include <linux/mmc/mmc.h> 25743b819eSMaxime Ripard #include <linux/mmc/sd.h> 26743b819eSMaxime Ripard #include <linux/mmc/sdio.h> 27743b819eSMaxime Ripard #include <linux/mmc/slot-gpio.h> 28743b819eSMaxime Ripard #include <linux/module.h> 29b733775fSKrzysztof Kozlowski #include <linux/mod_devicetable.h> 303cbcb160SDavid Lanzendörfer #include <linux/of_address.h> 313cbcb160SDavid Lanzendörfer #include <linux/of_platform.h> 32743b819eSMaxime Ripard #include <linux/platform_device.h> 339a8e1e8cSMaxime Ripard #include <linux/pm_runtime.h> 34743b819eSMaxime Ripard #include <linux/regulator/consumer.h> 35743b819eSMaxime Ripard #include <linux/reset.h> 36743b819eSMaxime Ripard #include <linux/scatterlist.h> 37743b819eSMaxime Ripard #include <linux/slab.h> 38743b819eSMaxime Ripard #include <linux/spinlock.h> 393cbcb160SDavid Lanzendörfer 403cbcb160SDavid Lanzendörfer /* register offset definitions */ 413cbcb160SDavid Lanzendörfer #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 423cbcb160SDavid Lanzendörfer #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 433cbcb160SDavid Lanzendörfer #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 443cbcb160SDavid Lanzendörfer #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 453cbcb160SDavid Lanzendörfer #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 463cbcb160SDavid Lanzendörfer #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 473cbcb160SDavid Lanzendörfer #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 483cbcb160SDavid Lanzendörfer #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 493cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 503cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 513cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 523cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 533cbcb160SDavid Lanzendörfer #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 543cbcb160SDavid Lanzendörfer #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 553cbcb160SDavid Lanzendörfer #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 563cbcb160SDavid Lanzendörfer #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 573cbcb160SDavid Lanzendörfer #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 583cbcb160SDavid Lanzendörfer #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 593cbcb160SDavid Lanzendörfer #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 603cbcb160SDavid Lanzendörfer #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 613cbcb160SDavid Lanzendörfer #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 623cbcb160SDavid Lanzendörfer #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 633cbcb160SDavid Lanzendörfer #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 643cbcb160SDavid Lanzendörfer #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 653cbcb160SDavid Lanzendörfer #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 663cbcb160SDavid Lanzendörfer #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 673cbcb160SDavid Lanzendörfer #define SDXC_REG_CHDA (0x90) 683cbcb160SDavid Lanzendörfer #define SDXC_REG_CBDA (0x94) 693cbcb160SDavid Lanzendörfer 70e1b8dfd1SIcenowy Zheng /* New registers introduced in A64 */ 71e1b8dfd1SIcenowy Zheng #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 72e1b8dfd1SIcenowy Zheng #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 73e1b8dfd1SIcenowy Zheng #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 74e1b8dfd1SIcenowy Zheng #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 75e1b8dfd1SIcenowy Zheng #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 76e1b8dfd1SIcenowy Zheng 773cbcb160SDavid Lanzendörfer #define mmc_readl(host, reg) \ 783cbcb160SDavid Lanzendörfer readl((host)->reg_base + SDXC_##reg) 793cbcb160SDavid Lanzendörfer #define mmc_writel(host, reg, value) \ 803cbcb160SDavid Lanzendörfer writel((value), (host)->reg_base + SDXC_##reg) 813cbcb160SDavid Lanzendörfer 823cbcb160SDavid Lanzendörfer /* global control register bits */ 833cbcb160SDavid Lanzendörfer #define SDXC_SOFT_RESET BIT(0) 843cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RESET BIT(1) 853cbcb160SDavid Lanzendörfer #define SDXC_DMA_RESET BIT(2) 863cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 873cbcb160SDavid Lanzendörfer #define SDXC_DMA_ENABLE_BIT BIT(5) 883cbcb160SDavid Lanzendörfer #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 893cbcb160SDavid Lanzendörfer #define SDXC_POSEDGE_LATCH_DATA BIT(9) 903cbcb160SDavid Lanzendörfer #define SDXC_DDR_MODE BIT(10) 913cbcb160SDavid Lanzendörfer #define SDXC_MEMORY_ACCESS_DONE BIT(29) 923cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_DONE_DIRECT BIT(30) 933cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_AHB BIT(31) 943cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_DMA (0 << 31) 953cbcb160SDavid Lanzendörfer #define SDXC_HARDWARE_RESET \ 963cbcb160SDavid Lanzendörfer (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 973cbcb160SDavid Lanzendörfer 983cbcb160SDavid Lanzendörfer /* clock control bits */ 9916e821e3SMaxime Ripard #define SDXC_MASK_DATA0 BIT(31) 1003cbcb160SDavid Lanzendörfer #define SDXC_CARD_CLOCK_ON BIT(16) 1013cbcb160SDavid Lanzendörfer #define SDXC_LOW_POWER_ON BIT(17) 1023cbcb160SDavid Lanzendörfer 1033cbcb160SDavid Lanzendörfer /* bus width */ 1043cbcb160SDavid Lanzendörfer #define SDXC_WIDTH1 0 1053cbcb160SDavid Lanzendörfer #define SDXC_WIDTH4 1 1063cbcb160SDavid Lanzendörfer #define SDXC_WIDTH8 2 1073cbcb160SDavid Lanzendörfer 1083cbcb160SDavid Lanzendörfer /* smc command bits */ 1093cbcb160SDavid Lanzendörfer #define SDXC_RESP_EXPIRE BIT(6) 1103cbcb160SDavid Lanzendörfer #define SDXC_LONG_RESPONSE BIT(7) 1113cbcb160SDavid Lanzendörfer #define SDXC_CHECK_RESPONSE_CRC BIT(8) 1123cbcb160SDavid Lanzendörfer #define SDXC_DATA_EXPIRE BIT(9) 1133cbcb160SDavid Lanzendörfer #define SDXC_WRITE BIT(10) 1143cbcb160SDavid Lanzendörfer #define SDXC_SEQUENCE_MODE BIT(11) 1153cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOP BIT(12) 1163cbcb160SDavid Lanzendörfer #define SDXC_WAIT_PRE_OVER BIT(13) 1173cbcb160SDavid Lanzendörfer #define SDXC_STOP_ABORT_CMD BIT(14) 1183cbcb160SDavid Lanzendörfer #define SDXC_SEND_INIT_SEQUENCE BIT(15) 1193cbcb160SDavid Lanzendörfer #define SDXC_UPCLK_ONLY BIT(21) 1203cbcb160SDavid Lanzendörfer #define SDXC_READ_CEATA_DEV BIT(22) 1213cbcb160SDavid Lanzendörfer #define SDXC_CCS_EXPIRE BIT(23) 1223cbcb160SDavid Lanzendörfer #define SDXC_ENABLE_BIT_BOOT BIT(24) 1233cbcb160SDavid Lanzendörfer #define SDXC_ALT_BOOT_OPTIONS BIT(25) 1243cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ACK_EXPIRE BIT(26) 1253cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ABORT BIT(27) 1263cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_SWITCH BIT(28) 1273cbcb160SDavid Lanzendörfer #define SDXC_USE_HOLD_REGISTER BIT(29) 1283cbcb160SDavid Lanzendörfer #define SDXC_START BIT(31) 1293cbcb160SDavid Lanzendörfer 1303cbcb160SDavid Lanzendörfer /* interrupt bits */ 1313cbcb160SDavid Lanzendörfer #define SDXC_RESP_ERROR BIT(1) 1323cbcb160SDavid Lanzendörfer #define SDXC_COMMAND_DONE BIT(2) 1333cbcb160SDavid Lanzendörfer #define SDXC_DATA_OVER BIT(3) 1343cbcb160SDavid Lanzendörfer #define SDXC_TX_DATA_REQUEST BIT(4) 1353cbcb160SDavid Lanzendörfer #define SDXC_RX_DATA_REQUEST BIT(5) 1363cbcb160SDavid Lanzendörfer #define SDXC_RESP_CRC_ERROR BIT(6) 1373cbcb160SDavid Lanzendörfer #define SDXC_DATA_CRC_ERROR BIT(7) 1383cbcb160SDavid Lanzendörfer #define SDXC_RESP_TIMEOUT BIT(8) 1393cbcb160SDavid Lanzendörfer #define SDXC_DATA_TIMEOUT BIT(9) 1403cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 1413cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RUN_ERROR BIT(11) 1423cbcb160SDavid Lanzendörfer #define SDXC_HARD_WARE_LOCKED BIT(12) 1433cbcb160SDavid Lanzendörfer #define SDXC_START_BIT_ERROR BIT(13) 1443cbcb160SDavid Lanzendörfer #define SDXC_AUTO_COMMAND_DONE BIT(14) 1453cbcb160SDavid Lanzendörfer #define SDXC_END_BIT_ERROR BIT(15) 1463cbcb160SDavid Lanzendörfer #define SDXC_SDIO_INTERRUPT BIT(16) 1473cbcb160SDavid Lanzendörfer #define SDXC_CARD_INSERT BIT(30) 1483cbcb160SDavid Lanzendörfer #define SDXC_CARD_REMOVE BIT(31) 1493cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ERROR_BIT \ 1503cbcb160SDavid Lanzendörfer (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 1513cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 1523cbcb160SDavid Lanzendörfer SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 1533cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_DONE_BIT \ 1543cbcb160SDavid Lanzendörfer (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 1553cbcb160SDavid Lanzendörfer SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 1563cbcb160SDavid Lanzendörfer 1573cbcb160SDavid Lanzendörfer /* status */ 1583cbcb160SDavid Lanzendörfer #define SDXC_RXWL_FLAG BIT(0) 1593cbcb160SDavid Lanzendörfer #define SDXC_TXWL_FLAG BIT(1) 1603cbcb160SDavid Lanzendörfer #define SDXC_FIFO_EMPTY BIT(2) 1613cbcb160SDavid Lanzendörfer #define SDXC_FIFO_FULL BIT(3) 1623cbcb160SDavid Lanzendörfer #define SDXC_CARD_PRESENT BIT(8) 1633cbcb160SDavid Lanzendörfer #define SDXC_CARD_DATA_BUSY BIT(9) 1643cbcb160SDavid Lanzendörfer #define SDXC_DATA_FSM_BUSY BIT(10) 1653cbcb160SDavid Lanzendörfer #define SDXC_DMA_REQUEST BIT(31) 1663cbcb160SDavid Lanzendörfer #define SDXC_FIFO_SIZE 16 1673cbcb160SDavid Lanzendörfer 1683cbcb160SDavid Lanzendörfer /* Function select */ 1693cbcb160SDavid Lanzendörfer #define SDXC_CEATA_ON (0xceaa << 16) 1703cbcb160SDavid Lanzendörfer #define SDXC_SEND_IRQ_RESPONSE BIT(0) 1713cbcb160SDavid Lanzendörfer #define SDXC_SDIO_READ_WAIT BIT(1) 1723cbcb160SDavid Lanzendörfer #define SDXC_ABORT_READ_DATA BIT(2) 1733cbcb160SDavid Lanzendörfer #define SDXC_SEND_CCSD BIT(8) 1743cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 1753cbcb160SDavid Lanzendörfer #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 1763cbcb160SDavid Lanzendörfer 1773cbcb160SDavid Lanzendörfer /* IDMA controller bus mod bit field */ 1783cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SOFT_RESET BIT(0) 1793cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FIX_BURST BIT(1) 1803cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDMA_ON BIT(7) 1813cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_REFETCH_DES BIT(31) 1823cbcb160SDavid Lanzendörfer 1833cbcb160SDavid Lanzendörfer /* IDMA status bit field */ 1843cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 1853cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 1863cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 1873cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 1883cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 1893cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 1903cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 1913cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 1923cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDLE (0 << 13) 1933cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SUSPEND (1 << 13) 1943cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_READ (2 << 13) 1953cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CHECK (3 << 13) 1963cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 1973cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 1983cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ (6 << 13) 1993cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE (7 << 13) 2003cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 2013cbcb160SDavid Lanzendörfer 2023cbcb160SDavid Lanzendörfer /* 2033cbcb160SDavid Lanzendörfer * If the idma-des-size-bits of property is ie 13, bufsize bits are: 2043cbcb160SDavid Lanzendörfer * Bits 0-12: buf1 size 2053cbcb160SDavid Lanzendörfer * Bits 13-25: buf2 size 2063cbcb160SDavid Lanzendörfer * Bits 26-31: not used 2073cbcb160SDavid Lanzendörfer * Since we only ever set buf1 size, we can simply store it directly. 2083cbcb160SDavid Lanzendörfer */ 2093cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 2103cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 2113cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 2123cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 2133cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 2143cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 2153cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 2163cbcb160SDavid Lanzendörfer 21751424b28SHans de Goede #define SDXC_CLK_400K 0 21851424b28SHans de Goede #define SDXC_CLK_25M 1 21951424b28SHans de Goede #define SDXC_CLK_50M 2 22051424b28SHans de Goede #define SDXC_CLK_50M_DDR 3 2212a7aa63aSChen-Yu Tsai #define SDXC_CLK_50M_DDR_8BIT 4 22251424b28SHans de Goede 223e1b8dfd1SIcenowy Zheng #define SDXC_2X_TIMING_MODE BIT(31) 224e1b8dfd1SIcenowy Zheng 225e1b8dfd1SIcenowy Zheng #define SDXC_CAL_START BIT(15) 226e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DONE BIT(14) 227e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SHIFT 8 228e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_EN BIT(7) 229e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_SHIFT 0 230e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_MASK 0x3f 231e1b8dfd1SIcenowy Zheng 232e1b8dfd1SIcenowy Zheng #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 233e1b8dfd1SIcenowy Zheng 23451424b28SHans de Goede struct sunxi_mmc_clk_delay { 23551424b28SHans de Goede u32 output; 23651424b28SHans de Goede u32 sample; 23751424b28SHans de Goede }; 23851424b28SHans de Goede 2393cbcb160SDavid Lanzendörfer struct sunxi_idma_des { 2402dd110b2SMichael Weiser __le32 config; 2412dd110b2SMichael Weiser __le32 buf_size; 2422dd110b2SMichael Weiser __le32 buf_addr_ptr1; 2432dd110b2SMichael Weiser __le32 buf_addr_ptr2; 2443cbcb160SDavid Lanzendörfer }; 2453cbcb160SDavid Lanzendörfer 24686a93317SHans de Goede struct sunxi_mmc_cfg { 24786a93317SHans de Goede u32 idma_des_size_bits; 2483536b82eSYangtao Li u32 idma_des_shift; 24986a93317SHans de Goede const struct sunxi_mmc_clk_delay *clk_delays; 250e1b8dfd1SIcenowy Zheng 251e1b8dfd1SIcenowy Zheng /* does the IP block support autocalibration? */ 252e1b8dfd1SIcenowy Zheng bool can_calibrate; 2539a37e53eSMaxime Ripard 25416e821e3SMaxime Ripard /* Does DATA0 needs to be masked while the clock is updated */ 25516e821e3SMaxime Ripard bool mask_data0; 25616e821e3SMaxime Ripard 2571ff9cabdSChen-Yu Tsai /* 2581ff9cabdSChen-Yu Tsai * hardware only supports new timing mode, either due to lack of 2591ff9cabdSChen-Yu Tsai * a mode switch in the clock controller, or the mmc controller 2601ff9cabdSChen-Yu Tsai * is permanently configured in the new timing mode, without the 2611ff9cabdSChen-Yu Tsai * NTSR mode switch. 2621ff9cabdSChen-Yu Tsai */ 2639a37e53eSMaxime Ripard bool needs_new_timings; 264ff39e7f7SChen-Yu Tsai 2651ff9cabdSChen-Yu Tsai /* clock hardware can switch between old and new timing modes */ 2661ff9cabdSChen-Yu Tsai bool ccu_has_timings_switch; 26786a93317SHans de Goede }; 26886a93317SHans de Goede 2693cbcb160SDavid Lanzendörfer struct sunxi_mmc_host { 270774c0103SMaxime Ripard struct device *dev; 2713cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 2723cbcb160SDavid Lanzendörfer struct reset_control *reset; 27386a93317SHans de Goede const struct sunxi_mmc_cfg *cfg; 2743cbcb160SDavid Lanzendörfer 2753cbcb160SDavid Lanzendörfer /* IO mapping base */ 2763cbcb160SDavid Lanzendörfer void __iomem *reg_base; 2773cbcb160SDavid Lanzendörfer 2783cbcb160SDavid Lanzendörfer /* clock management */ 2793cbcb160SDavid Lanzendörfer struct clk *clk_ahb; 2803cbcb160SDavid Lanzendörfer struct clk *clk_mmc; 2816c09bb85SMaxime Ripard struct clk *clk_sample; 2826c09bb85SMaxime Ripard struct clk *clk_output; 2833cbcb160SDavid Lanzendörfer 2843cbcb160SDavid Lanzendörfer /* irq */ 2853cbcb160SDavid Lanzendörfer spinlock_t lock; 2863cbcb160SDavid Lanzendörfer int irq; 2873cbcb160SDavid Lanzendörfer u32 int_sum; 2883cbcb160SDavid Lanzendörfer u32 sdio_imask; 2893cbcb160SDavid Lanzendörfer 2903cbcb160SDavid Lanzendörfer /* dma */ 2913cbcb160SDavid Lanzendörfer dma_addr_t sg_dma; 2923cbcb160SDavid Lanzendörfer void *sg_cpu; 2933cbcb160SDavid Lanzendörfer bool wait_dma; 2943cbcb160SDavid Lanzendörfer 2953cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 2963cbcb160SDavid Lanzendörfer struct mmc_request *manual_stop_mrq; 2973cbcb160SDavid Lanzendörfer int ferror; 298f771f6e8SChen-Yu Tsai 299f771f6e8SChen-Yu Tsai /* vqmmc */ 300f771f6e8SChen-Yu Tsai bool vqmmc_enabled; 301ff39e7f7SChen-Yu Tsai 302ff39e7f7SChen-Yu Tsai /* timings */ 303ff39e7f7SChen-Yu Tsai bool use_new_timings; 3043cbcb160SDavid Lanzendörfer }; 3053cbcb160SDavid Lanzendörfer 3063cbcb160SDavid Lanzendörfer static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 3073cbcb160SDavid Lanzendörfer { 3083cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(250); 3093cbcb160SDavid Lanzendörfer u32 rval; 3103cbcb160SDavid Lanzendörfer 3110f0fcd37SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 3123cbcb160SDavid Lanzendörfer do { 3133cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3143cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 3153cbcb160SDavid Lanzendörfer 3163cbcb160SDavid Lanzendörfer if (rval & SDXC_HARDWARE_RESET) { 3173cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 3183cbcb160SDavid Lanzendörfer return -EIO; 3193cbcb160SDavid Lanzendörfer } 3203cbcb160SDavid Lanzendörfer 3213cbcb160SDavid Lanzendörfer return 0; 3223cbcb160SDavid Lanzendörfer } 3233cbcb160SDavid Lanzendörfer 3240fc4c61fSMaxime Ripard static int sunxi_mmc_init_host(struct sunxi_mmc_host *host) 3253cbcb160SDavid Lanzendörfer { 3263cbcb160SDavid Lanzendörfer u32 rval; 3273cbcb160SDavid Lanzendörfer 3283cbcb160SDavid Lanzendörfer if (sunxi_mmc_reset_host(host)) 3293cbcb160SDavid Lanzendörfer return -EIO; 3303cbcb160SDavid Lanzendörfer 3310314cbd4SChen-Yu Tsai /* 3320314cbd4SChen-Yu Tsai * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 3330314cbd4SChen-Yu Tsai * 3340314cbd4SChen-Yu Tsai * TODO: sun9i has a larger FIFO and supports higher trigger values 3350314cbd4SChen-Yu Tsai */ 3363cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FTRGL, 0x20070008); 3370314cbd4SChen-Yu Tsai /* Maximum timeout value */ 3383cbcb160SDavid Lanzendörfer mmc_writel(host, REG_TMOUT, 0xffffffff); 3390314cbd4SChen-Yu Tsai /* Unmask SDIO interrupt if needed */ 3403cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 3410314cbd4SChen-Yu Tsai /* Clear all pending interrupts */ 3423cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffffffff); 3430314cbd4SChen-Yu Tsai /* Debug register? undocumented */ 3443cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DBGC, 0xdeb); 3450314cbd4SChen-Yu Tsai /* Enable CEATA support */ 3463cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 3470314cbd4SChen-Yu Tsai /* Set DMA descriptor list base address */ 3483536b82eSYangtao Li mmc_writel(host, REG_DLBA, host->sg_dma >> host->cfg->idma_des_shift); 3493cbcb160SDavid Lanzendörfer 3503cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3513cbcb160SDavid Lanzendörfer rval |= SDXC_INTERRUPT_ENABLE_BIT; 3520314cbd4SChen-Yu Tsai /* Undocumented, but found in Allwinner code */ 3533cbcb160SDavid Lanzendörfer rval &= ~SDXC_ACCESS_DONE_DIRECT; 3543cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 3553cbcb160SDavid Lanzendörfer 3563cbcb160SDavid Lanzendörfer return 0; 3573cbcb160SDavid Lanzendörfer } 3583cbcb160SDavid Lanzendörfer 3593cbcb160SDavid Lanzendörfer static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 3603cbcb160SDavid Lanzendörfer struct mmc_data *data) 3613cbcb160SDavid Lanzendörfer { 3623cbcb160SDavid Lanzendörfer struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 363d34712d2SArnd Bergmann dma_addr_t next_desc = host->sg_dma; 36486a93317SHans de Goede int i, max_len = (1 << host->cfg->idma_des_size_bits); 3653cbcb160SDavid Lanzendörfer 3663cbcb160SDavid Lanzendörfer for (i = 0; i < data->sg_len; i++) { 3672dd110b2SMichael Weiser pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 3682dd110b2SMichael Weiser SDXC_IDMAC_DES0_OWN | 3692dd110b2SMichael Weiser SDXC_IDMAC_DES0_DIC); 3703cbcb160SDavid Lanzendörfer 3713cbcb160SDavid Lanzendörfer if (data->sg[i].length == max_len) 3723cbcb160SDavid Lanzendörfer pdes[i].buf_size = 0; /* 0 == max_len */ 3733cbcb160SDavid Lanzendörfer else 3742dd110b2SMichael Weiser pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 3753cbcb160SDavid Lanzendörfer 376d34712d2SArnd Bergmann next_desc += sizeof(struct sunxi_idma_des); 3772dd110b2SMichael Weiser pdes[i].buf_addr_ptr1 = 3783536b82eSYangtao Li cpu_to_le32(sg_dma_address(&data->sg[i]) >> 3793536b82eSYangtao Li host->cfg->idma_des_shift); 380e9f3fb52SSamuel Holland pdes[i].buf_addr_ptr2 = 381e9f3fb52SSamuel Holland cpu_to_le32(next_desc >> 3823536b82eSYangtao Li host->cfg->idma_des_shift); 3833cbcb160SDavid Lanzendörfer } 3843cbcb160SDavid Lanzendörfer 3852dd110b2SMichael Weiser pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 3862dd110b2SMichael Weiser pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 3872dd110b2SMichael Weiser SDXC_IDMAC_DES0_ER); 3882dd110b2SMichael Weiser pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 389e8a59049SHans de Goede pdes[i - 1].buf_addr_ptr2 = 0; 3903cbcb160SDavid Lanzendörfer 3913cbcb160SDavid Lanzendörfer /* 3923cbcb160SDavid Lanzendörfer * Avoid the io-store starting the idmac hitting io-mem before the 3933cbcb160SDavid Lanzendörfer * descriptors hit the main-mem. 3943cbcb160SDavid Lanzendörfer */ 3953cbcb160SDavid Lanzendörfer wmb(); 3963cbcb160SDavid Lanzendörfer } 3973cbcb160SDavid Lanzendörfer 3983cbcb160SDavid Lanzendörfer static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 3993cbcb160SDavid Lanzendörfer struct mmc_data *data) 4003cbcb160SDavid Lanzendörfer { 4013cbcb160SDavid Lanzendörfer u32 i, dma_len; 4023cbcb160SDavid Lanzendörfer struct scatterlist *sg; 4033cbcb160SDavid Lanzendörfer 4043cbcb160SDavid Lanzendörfer dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 405feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 4063cbcb160SDavid Lanzendörfer if (dma_len == 0) { 4073cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 4083cbcb160SDavid Lanzendörfer return -ENOMEM; 4093cbcb160SDavid Lanzendörfer } 4103cbcb160SDavid Lanzendörfer 4113cbcb160SDavid Lanzendörfer for_each_sg(data->sg, sg, data->sg_len, i) { 4123cbcb160SDavid Lanzendörfer if (sg->offset & 3 || sg->length & 3) { 4133cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), 4143cbcb160SDavid Lanzendörfer "unaligned scatterlist: os %x length %d\n", 4153cbcb160SDavid Lanzendörfer sg->offset, sg->length); 4163cbcb160SDavid Lanzendörfer return -EINVAL; 4173cbcb160SDavid Lanzendörfer } 4183cbcb160SDavid Lanzendörfer } 4193cbcb160SDavid Lanzendörfer 4203cbcb160SDavid Lanzendörfer return 0; 4213cbcb160SDavid Lanzendörfer } 4223cbcb160SDavid Lanzendörfer 4233cbcb160SDavid Lanzendörfer static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 4243cbcb160SDavid Lanzendörfer struct mmc_data *data) 4253cbcb160SDavid Lanzendörfer { 4263cbcb160SDavid Lanzendörfer u32 rval; 4273cbcb160SDavid Lanzendörfer 4283cbcb160SDavid Lanzendörfer sunxi_mmc_init_idma_des(host, data); 4293cbcb160SDavid Lanzendörfer 4303cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 4313cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_ENABLE_BIT; 4323cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4333cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 4343cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4353cbcb160SDavid Lanzendörfer 4363cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 4373cbcb160SDavid Lanzendörfer 4383cbcb160SDavid Lanzendörfer if (!(data->flags & MMC_DATA_WRITE)) 4393cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 4403cbcb160SDavid Lanzendörfer 4413cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 4423cbcb160SDavid Lanzendörfer SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 4433cbcb160SDavid Lanzendörfer } 4443cbcb160SDavid Lanzendörfer 4453cbcb160SDavid Lanzendörfer static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 4463cbcb160SDavid Lanzendörfer struct mmc_request *req) 4473cbcb160SDavid Lanzendörfer { 4483cbcb160SDavid Lanzendörfer u32 arg, cmd_val, ri; 4493cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(1000); 4503cbcb160SDavid Lanzendörfer 4513cbcb160SDavid Lanzendörfer cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 4523cbcb160SDavid Lanzendörfer SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 4533cbcb160SDavid Lanzendörfer 4543cbcb160SDavid Lanzendörfer if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 4553cbcb160SDavid Lanzendörfer cmd_val |= SD_IO_RW_DIRECT; 4563cbcb160SDavid Lanzendörfer arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 4573cbcb160SDavid Lanzendörfer ((req->cmd->arg >> 28) & 0x7); 4583cbcb160SDavid Lanzendörfer } else { 4593cbcb160SDavid Lanzendörfer cmd_val |= MMC_STOP_TRANSMISSION; 4603cbcb160SDavid Lanzendörfer arg = 0; 4613cbcb160SDavid Lanzendörfer } 4623cbcb160SDavid Lanzendörfer 4633cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, arg); 4643cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 4653cbcb160SDavid Lanzendörfer 4663cbcb160SDavid Lanzendörfer do { 4673cbcb160SDavid Lanzendörfer ri = mmc_readl(host, REG_RINTR); 4683cbcb160SDavid Lanzendörfer } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 4693cbcb160SDavid Lanzendörfer time_before(jiffies, expire)); 4703cbcb160SDavid Lanzendörfer 4713cbcb160SDavid Lanzendörfer if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 4723cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 4733cbcb160SDavid Lanzendörfer if (req->stop) 4743cbcb160SDavid Lanzendörfer req->stop->resp[0] = -ETIMEDOUT; 4753cbcb160SDavid Lanzendörfer } else { 4763cbcb160SDavid Lanzendörfer if (req->stop) 4773cbcb160SDavid Lanzendörfer req->stop->resp[0] = mmc_readl(host, REG_RESP0); 4783cbcb160SDavid Lanzendörfer } 4793cbcb160SDavid Lanzendörfer 4803cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 4813cbcb160SDavid Lanzendörfer } 4823cbcb160SDavid Lanzendörfer 4833cbcb160SDavid Lanzendörfer static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 4843cbcb160SDavid Lanzendörfer { 4853cbcb160SDavid Lanzendörfer struct mmc_command *cmd = host->mrq->cmd; 4863cbcb160SDavid Lanzendörfer struct mmc_data *data = host->mrq->data; 4873cbcb160SDavid Lanzendörfer 4883cbcb160SDavid Lanzendörfer /* For some cmds timeout is normal with sd/mmc cards */ 4893cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 4903cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 4913cbcb160SDavid Lanzendörfer cmd->opcode == SD_IO_RW_DIRECT)) 4923cbcb160SDavid Lanzendörfer return; 4933cbcb160SDavid Lanzendörfer 494bd675698SIcenowy Zheng dev_dbg(mmc_dev(host->mmc), 4953cbcb160SDavid Lanzendörfer "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 4963cbcb160SDavid Lanzendörfer host->mmc->index, cmd->opcode, 4973cbcb160SDavid Lanzendörfer data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 4983cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 4993cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 5003cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 5013cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 5023cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 5033cbcb160SDavid Lanzendörfer host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 5043cbcb160SDavid Lanzendörfer host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 5053cbcb160SDavid Lanzendörfer host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 5063cbcb160SDavid Lanzendörfer host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 5073cbcb160SDavid Lanzendörfer ); 5083cbcb160SDavid Lanzendörfer } 5093cbcb160SDavid Lanzendörfer 5103cbcb160SDavid Lanzendörfer /* Called in interrupt context! */ 5113cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 5123cbcb160SDavid Lanzendörfer { 5133cbcb160SDavid Lanzendörfer struct mmc_request *mrq = host->mrq; 5143cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 5153cbcb160SDavid Lanzendörfer u32 rval; 5163cbcb160SDavid Lanzendörfer 5173cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 5183cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, 0); 5193cbcb160SDavid Lanzendörfer 5203cbcb160SDavid Lanzendörfer if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 5213cbcb160SDavid Lanzendörfer sunxi_mmc_dump_errinfo(host); 5223cbcb160SDavid Lanzendörfer mrq->cmd->error = -ETIMEDOUT; 5233cbcb160SDavid Lanzendörfer 5243cbcb160SDavid Lanzendörfer if (data) { 5253cbcb160SDavid Lanzendörfer data->error = -ETIMEDOUT; 5263cbcb160SDavid Lanzendörfer host->manual_stop_mrq = mrq; 5273cbcb160SDavid Lanzendörfer } 5283cbcb160SDavid Lanzendörfer 5293cbcb160SDavid Lanzendörfer if (mrq->stop) 5303cbcb160SDavid Lanzendörfer mrq->stop->error = -ETIMEDOUT; 5313cbcb160SDavid Lanzendörfer } else { 5323cbcb160SDavid Lanzendörfer if (mrq->cmd->flags & MMC_RSP_136) { 5333cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 5343cbcb160SDavid Lanzendörfer mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 5353cbcb160SDavid Lanzendörfer mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 5363cbcb160SDavid Lanzendörfer mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 5373cbcb160SDavid Lanzendörfer } else { 5383cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 5393cbcb160SDavid Lanzendörfer } 5403cbcb160SDavid Lanzendörfer 5413cbcb160SDavid Lanzendörfer if (data) 5423cbcb160SDavid Lanzendörfer data->bytes_xfered = data->blocks * data->blksz; 5433cbcb160SDavid Lanzendörfer } 5443cbcb160SDavid Lanzendörfer 5453cbcb160SDavid Lanzendörfer if (data) { 5463cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, 0x337); 5473cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 0); 5483cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 5493cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 5503cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5513cbcb160SDavid Lanzendörfer rval &= ~SDXC_DMA_ENABLE_BIT; 5523cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5533cbcb160SDavid Lanzendörfer rval |= SDXC_FIFO_RESET; 5543cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5553cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 556feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 5573cbcb160SDavid Lanzendörfer } 5583cbcb160SDavid Lanzendörfer 5593cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 5603cbcb160SDavid Lanzendörfer 5613cbcb160SDavid Lanzendörfer host->mrq = NULL; 5623cbcb160SDavid Lanzendörfer host->int_sum = 0; 5633cbcb160SDavid Lanzendörfer host->wait_dma = false; 5643cbcb160SDavid Lanzendörfer 5653cbcb160SDavid Lanzendörfer return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 5663cbcb160SDavid Lanzendörfer } 5673cbcb160SDavid Lanzendörfer 5683cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 5693cbcb160SDavid Lanzendörfer { 5703cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 5713cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 5723cbcb160SDavid Lanzendörfer u32 msk_int, idma_int; 5733cbcb160SDavid Lanzendörfer bool finalize = false; 5743cbcb160SDavid Lanzendörfer bool sdio_int = false; 5753cbcb160SDavid Lanzendörfer irqreturn_t ret = IRQ_HANDLED; 5763cbcb160SDavid Lanzendörfer 5773cbcb160SDavid Lanzendörfer spin_lock(&host->lock); 5783cbcb160SDavid Lanzendörfer 5793cbcb160SDavid Lanzendörfer idma_int = mmc_readl(host, REG_IDST); 5803cbcb160SDavid Lanzendörfer msk_int = mmc_readl(host, REG_MISTA); 5813cbcb160SDavid Lanzendörfer 5823cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 5833cbcb160SDavid Lanzendörfer host->mrq, msk_int, idma_int); 5843cbcb160SDavid Lanzendörfer 5853cbcb160SDavid Lanzendörfer mrq = host->mrq; 5863cbcb160SDavid Lanzendörfer if (mrq) { 5873cbcb160SDavid Lanzendörfer if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 5883cbcb160SDavid Lanzendörfer host->wait_dma = false; 5893cbcb160SDavid Lanzendörfer 5903cbcb160SDavid Lanzendörfer host->int_sum |= msk_int; 5913cbcb160SDavid Lanzendörfer 5923cbcb160SDavid Lanzendörfer /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 5933cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_RESP_TIMEOUT) && 5943cbcb160SDavid Lanzendörfer !(host->int_sum & SDXC_COMMAND_DONE)) 5953cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, 5963cbcb160SDavid Lanzendörfer host->sdio_imask | SDXC_COMMAND_DONE); 5973cbcb160SDavid Lanzendörfer /* Don't wait for dma on error */ 5983cbcb160SDavid Lanzendörfer else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 5993cbcb160SDavid Lanzendörfer finalize = true; 6003cbcb160SDavid Lanzendörfer else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 6013cbcb160SDavid Lanzendörfer !host->wait_dma) 6023cbcb160SDavid Lanzendörfer finalize = true; 6033cbcb160SDavid Lanzendörfer } 6043cbcb160SDavid Lanzendörfer 6053cbcb160SDavid Lanzendörfer if (msk_int & SDXC_SDIO_INTERRUPT) 6063cbcb160SDavid Lanzendörfer sdio_int = true; 6073cbcb160SDavid Lanzendörfer 6083cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, msk_int); 6093cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, idma_int); 6103cbcb160SDavid Lanzendörfer 6113cbcb160SDavid Lanzendörfer if (finalize) 6123cbcb160SDavid Lanzendörfer ret = sunxi_mmc_finalize_request(host); 6133cbcb160SDavid Lanzendörfer 6143cbcb160SDavid Lanzendörfer spin_unlock(&host->lock); 6153cbcb160SDavid Lanzendörfer 6163cbcb160SDavid Lanzendörfer if (finalize && ret == IRQ_HANDLED) 6173cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6183cbcb160SDavid Lanzendörfer 6193cbcb160SDavid Lanzendörfer if (sdio_int) 6203cbcb160SDavid Lanzendörfer mmc_signal_sdio_irq(host->mmc); 6213cbcb160SDavid Lanzendörfer 6223cbcb160SDavid Lanzendörfer return ret; 6233cbcb160SDavid Lanzendörfer } 6243cbcb160SDavid Lanzendörfer 6253cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 6263cbcb160SDavid Lanzendörfer { 6273cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 6283cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 6293cbcb160SDavid Lanzendörfer unsigned long iflags; 6303cbcb160SDavid Lanzendörfer 6313cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6323cbcb160SDavid Lanzendörfer mrq = host->manual_stop_mrq; 6333cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6343cbcb160SDavid Lanzendörfer 6353cbcb160SDavid Lanzendörfer if (!mrq) { 6363cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 6373cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6383cbcb160SDavid Lanzendörfer } 6393cbcb160SDavid Lanzendörfer 6403cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 641dd9b3803SDavid Lanzendörfer 642dd9b3803SDavid Lanzendörfer /* 643dd9b3803SDavid Lanzendörfer * We will never have more than one outstanding request, 644dd9b3803SDavid Lanzendörfer * and we do not complete the request until after 645dd9b3803SDavid Lanzendörfer * we've cleared host->manual_stop_mrq so we do not need to 646dd9b3803SDavid Lanzendörfer * spin lock this function. 647dd9b3803SDavid Lanzendörfer * Additionally we have wait states within this function 648dd9b3803SDavid Lanzendörfer * so having it in a lock is a very bad idea. 649dd9b3803SDavid Lanzendörfer */ 6503cbcb160SDavid Lanzendörfer sunxi_mmc_send_manual_stop(host, mrq); 6513cbcb160SDavid Lanzendörfer 6523cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6533cbcb160SDavid Lanzendörfer host->manual_stop_mrq = NULL; 6543cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6553cbcb160SDavid Lanzendörfer 6563cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6573cbcb160SDavid Lanzendörfer 6583cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6593cbcb160SDavid Lanzendörfer } 6603cbcb160SDavid Lanzendörfer 6613cbcb160SDavid Lanzendörfer static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 6623cbcb160SDavid Lanzendörfer { 6637bb9c244SMichal Suchanek unsigned long expire = jiffies + msecs_to_jiffies(750); 6643cbcb160SDavid Lanzendörfer u32 rval; 6653cbcb160SDavid Lanzendörfer 66643c15e96SMaxime Ripard dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 66743c15e96SMaxime Ripard oclk_en ? "en" : "dis"); 66843c15e96SMaxime Ripard 6693cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 67016e821e3SMaxime Ripard rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 6713cbcb160SDavid Lanzendörfer 6723cbcb160SDavid Lanzendörfer if (oclk_en) 6733cbcb160SDavid Lanzendörfer rval |= SDXC_CARD_CLOCK_ON; 67416e821e3SMaxime Ripard if (host->cfg->mask_data0) 67516e821e3SMaxime Ripard rval |= SDXC_MASK_DATA0; 6763cbcb160SDavid Lanzendörfer 6773cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 6783cbcb160SDavid Lanzendörfer 6793cbcb160SDavid Lanzendörfer rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 6803cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, rval); 6813cbcb160SDavid Lanzendörfer 6823cbcb160SDavid Lanzendörfer do { 6833cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CMDR); 6843cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_START)); 6853cbcb160SDavid Lanzendörfer 6863cbcb160SDavid Lanzendörfer /* clear irq status bits set by the command */ 6873cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 6883cbcb160SDavid Lanzendörfer mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 6893cbcb160SDavid Lanzendörfer 6903cbcb160SDavid Lanzendörfer if (rval & SDXC_START) { 6913cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 6923cbcb160SDavid Lanzendörfer return -EIO; 6933cbcb160SDavid Lanzendörfer } 6943cbcb160SDavid Lanzendörfer 69516e821e3SMaxime Ripard if (host->cfg->mask_data0) { 69616e821e3SMaxime Ripard rval = mmc_readl(host, REG_CLKCR); 69716e821e3SMaxime Ripard mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 69816e821e3SMaxime Ripard } 69916e821e3SMaxime Ripard 7003cbcb160SDavid Lanzendörfer return 0; 7013cbcb160SDavid Lanzendörfer } 7023cbcb160SDavid Lanzendörfer 703e1b8dfd1SIcenowy Zheng static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 704e1b8dfd1SIcenowy Zheng { 705e1b8dfd1SIcenowy Zheng if (!host->cfg->can_calibrate) 706e1b8dfd1SIcenowy Zheng return 0; 707e1b8dfd1SIcenowy Zheng 708860fdf89SMaxime Ripard /* 709860fdf89SMaxime Ripard * FIXME: 710860fdf89SMaxime Ripard * This is not clear how the calibration is supposed to work 711860fdf89SMaxime Ripard * yet. The best rate have been obtained by simply setting the 712860fdf89SMaxime Ripard * delay to 0, as Allwinner does in its BSP. 713860fdf89SMaxime Ripard * 714860fdf89SMaxime Ripard * The only mode that doesn't have such a delay is HS400, that 715860fdf89SMaxime Ripard * is in itself a TODO. 716860fdf89SMaxime Ripard */ 717860fdf89SMaxime Ripard writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 718e1b8dfd1SIcenowy Zheng 719e1b8dfd1SIcenowy Zheng return 0; 720e1b8dfd1SIcenowy Zheng } 721e1b8dfd1SIcenowy Zheng 722f2cecb70SHans de Goede static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 723f2cecb70SHans de Goede struct mmc_ios *ios, u32 rate) 724f2cecb70SHans de Goede { 725f2cecb70SHans de Goede int index; 726f2cecb70SHans de Goede 727a6461134SChen-Yu Tsai /* clk controller delays not used under new timings mode */ 728ff39e7f7SChen-Yu Tsai if (host->use_new_timings) 729b465646eSHans de Goede return 0; 730b465646eSHans de Goede 731a6461134SChen-Yu Tsai /* some old controllers don't support delays */ 732a6461134SChen-Yu Tsai if (!host->cfg->clk_delays) 733a6461134SChen-Yu Tsai return 0; 734a6461134SChen-Yu Tsai 735f2cecb70SHans de Goede /* determine delays */ 736f2cecb70SHans de Goede if (rate <= 400000) { 737f2cecb70SHans de Goede index = SDXC_CLK_400K; 738f2cecb70SHans de Goede } else if (rate <= 25000000) { 739f2cecb70SHans de Goede index = SDXC_CLK_25M; 740f2cecb70SHans de Goede } else if (rate <= 52000000) { 741f2cecb70SHans de Goede if (ios->timing != MMC_TIMING_UHS_DDR50 && 742f2cecb70SHans de Goede ios->timing != MMC_TIMING_MMC_DDR52) { 743f2cecb70SHans de Goede index = SDXC_CLK_50M; 744f2cecb70SHans de Goede } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 745f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR_8BIT; 746f2cecb70SHans de Goede } else { 747f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR; 748f2cecb70SHans de Goede } 749f2cecb70SHans de Goede } else { 75043c15e96SMaxime Ripard dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 751f2cecb70SHans de Goede return -EINVAL; 752f2cecb70SHans de Goede } 753f2cecb70SHans de Goede 754f2cecb70SHans de Goede clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 755f2cecb70SHans de Goede clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 756f2cecb70SHans de Goede 757f2cecb70SHans de Goede return 0; 758f2cecb70SHans de Goede } 759f2cecb70SHans de Goede 7603cbcb160SDavid Lanzendörfer static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 7613cbcb160SDavid Lanzendörfer struct mmc_ios *ios) 7623cbcb160SDavid Lanzendörfer { 76343c15e96SMaxime Ripard struct mmc_host *mmc = host->mmc; 76463311becSJean-Francois Moine long rate; 765c903a2aeSChen-Yu Tsai u32 rval, clock = ios->clock, div = 1; 7663cbcb160SDavid Lanzendörfer int ret; 7673cbcb160SDavid Lanzendörfer 76839cc281fSMaxime Ripard ret = sunxi_mmc_oclk_onoff(host, 0); 76939cc281fSMaxime Ripard if (ret) 77039cc281fSMaxime Ripard return ret; 77139cc281fSMaxime Ripard 77243c15e96SMaxime Ripard /* Our clock is gated now */ 77343c15e96SMaxime Ripard mmc->actual_clock = 0; 77443c15e96SMaxime Ripard 7759479074eSMaxime Ripard if (!ios->clock) 7769479074eSMaxime Ripard return 0; 7779479074eSMaxime Ripard 778c903a2aeSChen-Yu Tsai /* 779c903a2aeSChen-Yu Tsai * Under the old timing mode, 8 bit DDR requires the module 780c903a2aeSChen-Yu Tsai * clock to be double the card clock. Under the new timing 781c903a2aeSChen-Yu Tsai * mode, all DDR modes require a doubled module clock. 782c903a2aeSChen-Yu Tsai * 783c903a2aeSChen-Yu Tsai * We currently only support the standard MMC DDR52 mode. 784c903a2aeSChen-Yu Tsai * This block should be updated once support for other DDR 785c903a2aeSChen-Yu Tsai * modes is added. 786c903a2aeSChen-Yu Tsai */ 7872a7aa63aSChen-Yu Tsai if (ios->timing == MMC_TIMING_MMC_DDR52 && 788c903a2aeSChen-Yu Tsai (host->use_new_timings || 789c903a2aeSChen-Yu Tsai ios->bus_width == MMC_BUS_WIDTH_8)) { 790c903a2aeSChen-Yu Tsai div = 2; 7912a7aa63aSChen-Yu Tsai clock <<= 1; 792c903a2aeSChen-Yu Tsai } 7932a7aa63aSChen-Yu Tsai 7941ff9cabdSChen-Yu Tsai if (host->use_new_timings && host->cfg->ccu_has_timings_switch) { 795ff39e7f7SChen-Yu Tsai ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 796ff39e7f7SChen-Yu Tsai if (ret) { 797ff39e7f7SChen-Yu Tsai dev_err(mmc_dev(mmc), 798ff39e7f7SChen-Yu Tsai "error setting new timing mode\n"); 799ff39e7f7SChen-Yu Tsai return ret; 800ff39e7f7SChen-Yu Tsai } 801ff39e7f7SChen-Yu Tsai } 802ff39e7f7SChen-Yu Tsai 8032a7aa63aSChen-Yu Tsai rate = clk_round_rate(host->clk_mmc, clock); 80463311becSJean-Francois Moine if (rate < 0) { 80543c15e96SMaxime Ripard dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 80663311becSJean-Francois Moine clock, rate); 80763311becSJean-Francois Moine return rate; 80863311becSJean-Francois Moine } 80943c15e96SMaxime Ripard dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 8102a7aa63aSChen-Yu Tsai clock, rate); 8113cbcb160SDavid Lanzendörfer 8123cbcb160SDavid Lanzendörfer /* setting clock rate */ 8133cbcb160SDavid Lanzendörfer ret = clk_set_rate(host->clk_mmc, rate); 8143cbcb160SDavid Lanzendörfer if (ret) { 81543c15e96SMaxime Ripard dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 8163cbcb160SDavid Lanzendörfer rate, ret); 8173cbcb160SDavid Lanzendörfer return ret; 8183cbcb160SDavid Lanzendörfer } 8193cbcb160SDavid Lanzendörfer 820c903a2aeSChen-Yu Tsai /* set internal divider */ 8213cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 8223cbcb160SDavid Lanzendörfer rval &= ~0xff; 823c903a2aeSChen-Yu Tsai rval |= div - 1; 8243cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 8253cbcb160SDavid Lanzendörfer 826082bb85fSChen-Yu Tsai /* update card clock rate to account for internal divider */ 827082bb85fSChen-Yu Tsai rate /= div; 828082bb85fSChen-Yu Tsai 8291ff9cabdSChen-Yu Tsai /* 8301ff9cabdSChen-Yu Tsai * Configure the controller to use the new timing mode if needed. 8311ff9cabdSChen-Yu Tsai * On controllers that only support the new timing mode, such as 8321ff9cabdSChen-Yu Tsai * the eMMC controller on the A64, this register does not exist, 8331ff9cabdSChen-Yu Tsai * and any writes to it are ignored. 8341ff9cabdSChen-Yu Tsai */ 835ff39e7f7SChen-Yu Tsai if (host->use_new_timings) { 83626cb2be4SChen-Yu Tsai /* Don't touch the delay bits */ 83726cb2be4SChen-Yu Tsai rval = mmc_readl(host, REG_SD_NTSR); 83826cb2be4SChen-Yu Tsai rval |= SDXC_2X_TIMING_MODE; 83926cb2be4SChen-Yu Tsai mmc_writel(host, REG_SD_NTSR, rval); 84026cb2be4SChen-Yu Tsai } 8419a37e53eSMaxime Ripard 842082bb85fSChen-Yu Tsai /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 843f2cecb70SHans de Goede ret = sunxi_mmc_clk_set_phase(host, ios, rate); 844f2cecb70SHans de Goede if (ret) 845f2cecb70SHans de Goede return ret; 8463cbcb160SDavid Lanzendörfer 847e1b8dfd1SIcenowy Zheng ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 848e1b8dfd1SIcenowy Zheng if (ret) 849e1b8dfd1SIcenowy Zheng return ret; 850e1b8dfd1SIcenowy Zheng 851860fdf89SMaxime Ripard /* 852860fdf89SMaxime Ripard * FIXME: 853860fdf89SMaxime Ripard * 854860fdf89SMaxime Ripard * In HS400 we'll also need to calibrate the data strobe 855860fdf89SMaxime Ripard * signal. This should only happen on the MMC2 controller (at 856860fdf89SMaxime Ripard * least on the A64). 857860fdf89SMaxime Ripard */ 858e1b8dfd1SIcenowy Zheng 85943c15e96SMaxime Ripard ret = sunxi_mmc_oclk_onoff(host, 1); 86043c15e96SMaxime Ripard if (ret) 86143c15e96SMaxime Ripard return ret; 86243c15e96SMaxime Ripard 86343c15e96SMaxime Ripard /* And we just enabled our clock back */ 864082bb85fSChen-Yu Tsai mmc->actual_clock = rate; 86543c15e96SMaxime Ripard 86643c15e96SMaxime Ripard return 0; 8673cbcb160SDavid Lanzendörfer } 8683cbcb160SDavid Lanzendörfer 8693f6c808eSMaxime Ripard static void sunxi_mmc_set_bus_width(struct sunxi_mmc_host *host, 8703f6c808eSMaxime Ripard unsigned char width) 8713f6c808eSMaxime Ripard { 8723f6c808eSMaxime Ripard switch (width) { 8733f6c808eSMaxime Ripard case MMC_BUS_WIDTH_1: 8743f6c808eSMaxime Ripard mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 8753f6c808eSMaxime Ripard break; 8763f6c808eSMaxime Ripard case MMC_BUS_WIDTH_4: 8773f6c808eSMaxime Ripard mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 8783f6c808eSMaxime Ripard break; 8793f6c808eSMaxime Ripard case MMC_BUS_WIDTH_8: 8803f6c808eSMaxime Ripard mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 8813f6c808eSMaxime Ripard break; 8823f6c808eSMaxime Ripard } 8833f6c808eSMaxime Ripard } 8843f6c808eSMaxime Ripard 885ad04d955SMaxime Ripard static void sunxi_mmc_set_clk(struct sunxi_mmc_host *host, struct mmc_ios *ios) 886ad04d955SMaxime Ripard { 887ad04d955SMaxime Ripard u32 rval; 888ad04d955SMaxime Ripard 889ad04d955SMaxime Ripard /* set ddr mode */ 890ad04d955SMaxime Ripard rval = mmc_readl(host, REG_GCTRL); 891ad04d955SMaxime Ripard if (ios->timing == MMC_TIMING_UHS_DDR50 || 892ad04d955SMaxime Ripard ios->timing == MMC_TIMING_MMC_DDR52) 893ad04d955SMaxime Ripard rval |= SDXC_DDR_MODE; 894ad04d955SMaxime Ripard else 895ad04d955SMaxime Ripard rval &= ~SDXC_DDR_MODE; 896ad04d955SMaxime Ripard mmc_writel(host, REG_GCTRL, rval); 897ad04d955SMaxime Ripard 898ad04d955SMaxime Ripard host->ferror = sunxi_mmc_clk_set_rate(host, ios); 899ad04d955SMaxime Ripard /* Android code had a usleep_range(50000, 55000); here */ 900ad04d955SMaxime Ripard } 901ad04d955SMaxime Ripard 902e27e1f3dSMaxime Ripard static void sunxi_mmc_card_power(struct sunxi_mmc_host *host, 903e27e1f3dSMaxime Ripard struct mmc_ios *ios) 9043cbcb160SDavid Lanzendörfer { 905e27e1f3dSMaxime Ripard struct mmc_host *mmc = host->mmc; 9063cbcb160SDavid Lanzendörfer 9073cbcb160SDavid Lanzendörfer switch (ios->power_mode) { 9083cbcb160SDavid Lanzendörfer case MMC_POWER_UP: 909e27e1f3dSMaxime Ripard dev_dbg(mmc_dev(mmc), "Powering card up\n"); 910e27e1f3dSMaxime Ripard 911424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) { 912424feb59SMaxime Ripard host->ferror = mmc_regulator_set_ocr(mmc, 913424feb59SMaxime Ripard mmc->supply.vmmc, 9144159215aSChen-Yu Tsai ios->vdd); 9154159215aSChen-Yu Tsai if (host->ferror) 9164159215aSChen-Yu Tsai return; 917424feb59SMaxime Ripard } 9183cbcb160SDavid Lanzendörfer 919f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc)) { 920f771f6e8SChen-Yu Tsai host->ferror = regulator_enable(mmc->supply.vqmmc); 921f771f6e8SChen-Yu Tsai if (host->ferror) { 922f771f6e8SChen-Yu Tsai dev_err(mmc_dev(mmc), 923f771f6e8SChen-Yu Tsai "failed to enable vqmmc\n"); 924f771f6e8SChen-Yu Tsai return; 925f771f6e8SChen-Yu Tsai } 926f771f6e8SChen-Yu Tsai host->vqmmc_enabled = true; 927f771f6e8SChen-Yu Tsai } 9283cbcb160SDavid Lanzendörfer break; 9293cbcb160SDavid Lanzendörfer 9303cbcb160SDavid Lanzendörfer case MMC_POWER_OFF: 931e27e1f3dSMaxime Ripard dev_dbg(mmc_dev(mmc), "Powering card off\n"); 932e27e1f3dSMaxime Ripard 933424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) 9343cbcb160SDavid Lanzendörfer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 935424feb59SMaxime Ripard 936f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 937f771f6e8SChen-Yu Tsai regulator_disable(mmc->supply.vqmmc); 938e27e1f3dSMaxime Ripard 939f771f6e8SChen-Yu Tsai host->vqmmc_enabled = false; 9403cbcb160SDavid Lanzendörfer break; 941e27e1f3dSMaxime Ripard 942e27e1f3dSMaxime Ripard default: 943e27e1f3dSMaxime Ripard dev_dbg(mmc_dev(mmc), "Ignoring unknown card power state\n"); 944e27e1f3dSMaxime Ripard break; 9453cbcb160SDavid Lanzendörfer } 946e27e1f3dSMaxime Ripard } 947e27e1f3dSMaxime Ripard 948e27e1f3dSMaxime Ripard static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 949e27e1f3dSMaxime Ripard { 950e27e1f3dSMaxime Ripard struct sunxi_mmc_host *host = mmc_priv(mmc); 951e27e1f3dSMaxime Ripard 952e27e1f3dSMaxime Ripard sunxi_mmc_card_power(host, ios); 9533f6c808eSMaxime Ripard sunxi_mmc_set_bus_width(host, ios->bus_width); 954ad04d955SMaxime Ripard sunxi_mmc_set_clk(host, ios); 9553cbcb160SDavid Lanzendörfer } 9563cbcb160SDavid Lanzendörfer 957f771f6e8SChen-Yu Tsai static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 958f771f6e8SChen-Yu Tsai { 9599cbe0fc8SMarek Vasut int ret; 9609cbe0fc8SMarek Vasut 961f771f6e8SChen-Yu Tsai /* vqmmc regulator is available */ 9629cbe0fc8SMarek Vasut if (!IS_ERR(mmc->supply.vqmmc)) { 9639cbe0fc8SMarek Vasut ret = mmc_regulator_set_vqmmc(mmc, ios); 9649cbe0fc8SMarek Vasut return ret < 0 ? ret : 0; 9659cbe0fc8SMarek Vasut } 966f771f6e8SChen-Yu Tsai 967f771f6e8SChen-Yu Tsai /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 968f771f6e8SChen-Yu Tsai if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 969f771f6e8SChen-Yu Tsai return 0; 970f771f6e8SChen-Yu Tsai 971f771f6e8SChen-Yu Tsai return -EINVAL; 972f771f6e8SChen-Yu Tsai } 973f771f6e8SChen-Yu Tsai 9743cbcb160SDavid Lanzendörfer static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 9753cbcb160SDavid Lanzendörfer { 9763cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 9773cbcb160SDavid Lanzendörfer unsigned long flags; 9783cbcb160SDavid Lanzendörfer u32 imask; 9793cbcb160SDavid Lanzendörfer 9809a8e1e8cSMaxime Ripard if (enable) 9819a8e1e8cSMaxime Ripard pm_runtime_get_noresume(host->dev); 9829a8e1e8cSMaxime Ripard 9833cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, flags); 9843cbcb160SDavid Lanzendörfer 9853cbcb160SDavid Lanzendörfer imask = mmc_readl(host, REG_IMASK); 9863cbcb160SDavid Lanzendörfer if (enable) { 9873cbcb160SDavid Lanzendörfer host->sdio_imask = SDXC_SDIO_INTERRUPT; 9883cbcb160SDavid Lanzendörfer imask |= SDXC_SDIO_INTERRUPT; 9893cbcb160SDavid Lanzendörfer } else { 9903cbcb160SDavid Lanzendörfer host->sdio_imask = 0; 9913cbcb160SDavid Lanzendörfer imask &= ~SDXC_SDIO_INTERRUPT; 9923cbcb160SDavid Lanzendörfer } 9933cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, imask); 9943cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, flags); 9959a8e1e8cSMaxime Ripard 9969a8e1e8cSMaxime Ripard if (!enable) 9979a8e1e8cSMaxime Ripard pm_runtime_put_noidle(host->mmc->parent); 9983cbcb160SDavid Lanzendörfer } 9993cbcb160SDavid Lanzendörfer 10003cbcb160SDavid Lanzendörfer static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 10013cbcb160SDavid Lanzendörfer { 10023cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 10033cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 0); 10043cbcb160SDavid Lanzendörfer udelay(10); 10053cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 1); 10063cbcb160SDavid Lanzendörfer udelay(300); 10073cbcb160SDavid Lanzendörfer } 10083cbcb160SDavid Lanzendörfer 10093cbcb160SDavid Lanzendörfer static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 10103cbcb160SDavid Lanzendörfer { 10113cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 10123cbcb160SDavid Lanzendörfer struct mmc_command *cmd = mrq->cmd; 10133cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 10143cbcb160SDavid Lanzendörfer unsigned long iflags; 10153cbcb160SDavid Lanzendörfer u32 imask = SDXC_INTERRUPT_ERROR_BIT; 10163cbcb160SDavid Lanzendörfer u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 1017dd9b3803SDavid Lanzendörfer bool wait_dma = host->wait_dma; 10183cbcb160SDavid Lanzendörfer int ret; 10193cbcb160SDavid Lanzendörfer 10203cbcb160SDavid Lanzendörfer /* Check for set_ios errors (should never happen) */ 10213cbcb160SDavid Lanzendörfer if (host->ferror) { 10223cbcb160SDavid Lanzendörfer mrq->cmd->error = host->ferror; 10233cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10243cbcb160SDavid Lanzendörfer return; 10253cbcb160SDavid Lanzendörfer } 10263cbcb160SDavid Lanzendörfer 10273cbcb160SDavid Lanzendörfer if (data) { 10283cbcb160SDavid Lanzendörfer ret = sunxi_mmc_map_dma(host, data); 10293cbcb160SDavid Lanzendörfer if (ret < 0) { 10303cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "map DMA failed\n"); 10313cbcb160SDavid Lanzendörfer cmd->error = ret; 10323cbcb160SDavid Lanzendörfer data->error = ret; 10333cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10343cbcb160SDavid Lanzendörfer return; 10353cbcb160SDavid Lanzendörfer } 10363cbcb160SDavid Lanzendörfer } 10373cbcb160SDavid Lanzendörfer 10383cbcb160SDavid Lanzendörfer if (cmd->opcode == MMC_GO_IDLE_STATE) { 10393cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_INIT_SEQUENCE; 10403cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10413cbcb160SDavid Lanzendörfer } 10423cbcb160SDavid Lanzendörfer 10433cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_PRESENT) { 10443cbcb160SDavid Lanzendörfer cmd_val |= SDXC_RESP_EXPIRE; 10453cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_136) 10463cbcb160SDavid Lanzendörfer cmd_val |= SDXC_LONG_RESPONSE; 10473cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_CRC) 10483cbcb160SDavid Lanzendörfer cmd_val |= SDXC_CHECK_RESPONSE_CRC; 10493cbcb160SDavid Lanzendörfer 10503cbcb160SDavid Lanzendörfer if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 10513cbcb160SDavid Lanzendörfer cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 10523cbcb160SDavid Lanzendörfer 10533cbcb160SDavid Lanzendörfer if (cmd->data->stop) { 10543cbcb160SDavid Lanzendörfer imask |= SDXC_AUTO_COMMAND_DONE; 10553cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_AUTO_STOP; 10563cbcb160SDavid Lanzendörfer } else { 10573cbcb160SDavid Lanzendörfer imask |= SDXC_DATA_OVER; 10583cbcb160SDavid Lanzendörfer } 10593cbcb160SDavid Lanzendörfer 10603cbcb160SDavid Lanzendörfer if (cmd->data->flags & MMC_DATA_WRITE) 10613cbcb160SDavid Lanzendörfer cmd_val |= SDXC_WRITE; 10623cbcb160SDavid Lanzendörfer else 1063dd9b3803SDavid Lanzendörfer wait_dma = true; 10643cbcb160SDavid Lanzendörfer } else { 10653cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10663cbcb160SDavid Lanzendörfer } 10673cbcb160SDavid Lanzendörfer } else { 10683cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10693cbcb160SDavid Lanzendörfer } 10703cbcb160SDavid Lanzendörfer 10713cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 10723cbcb160SDavid Lanzendörfer cmd_val & 0x3f, cmd_val, cmd->arg, imask, 10733cbcb160SDavid Lanzendörfer mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 10743cbcb160SDavid Lanzendörfer 10753cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 10763cbcb160SDavid Lanzendörfer 10773cbcb160SDavid Lanzendörfer if (host->mrq || host->manual_stop_mrq) { 10783cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 10793cbcb160SDavid Lanzendörfer 10803cbcb160SDavid Lanzendörfer if (data) 10813cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1082feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 10833cbcb160SDavid Lanzendörfer 10843cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "request already pending\n"); 10853cbcb160SDavid Lanzendörfer mrq->cmd->error = -EBUSY; 10863cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10873cbcb160SDavid Lanzendörfer return; 10883cbcb160SDavid Lanzendörfer } 10893cbcb160SDavid Lanzendörfer 10903cbcb160SDavid Lanzendörfer if (data) { 10913cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BLKSZ, data->blksz); 10923cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 10933cbcb160SDavid Lanzendörfer sunxi_mmc_start_dma(host, data); 10943cbcb160SDavid Lanzendörfer } 10953cbcb160SDavid Lanzendörfer 10963cbcb160SDavid Lanzendörfer host->mrq = mrq; 1097dd9b3803SDavid Lanzendörfer host->wait_dma = wait_dma; 10983cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 10993cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, cmd->arg); 11003cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 11013cbcb160SDavid Lanzendörfer 11023cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 11033cbcb160SDavid Lanzendörfer } 11043cbcb160SDavid Lanzendörfer 1105c1590dd8SHans de Goede static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1106c1590dd8SHans de Goede { 1107c1590dd8SHans de Goede struct sunxi_mmc_host *host = mmc_priv(mmc); 1108c1590dd8SHans de Goede 1109c1590dd8SHans de Goede return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1110c1590dd8SHans de Goede } 1111c1590dd8SHans de Goede 11121f8029c3SJulia Lawall static const struct mmc_host_ops sunxi_mmc_ops = { 11133cbcb160SDavid Lanzendörfer .request = sunxi_mmc_request, 11143cbcb160SDavid Lanzendörfer .set_ios = sunxi_mmc_set_ios, 11153cbcb160SDavid Lanzendörfer .get_ro = mmc_gpio_get_ro, 11163cbcb160SDavid Lanzendörfer .get_cd = mmc_gpio_get_cd, 11173cbcb160SDavid Lanzendörfer .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1118f771f6e8SChen-Yu Tsai .start_signal_voltage_switch = sunxi_mmc_volt_switch, 111932f18e59SWolfram Sang .card_hw_reset = sunxi_mmc_hw_reset, 1120c1590dd8SHans de Goede .card_busy = sunxi_mmc_card_busy, 11213cbcb160SDavid Lanzendörfer }; 11223cbcb160SDavid Lanzendörfer 112351424b28SHans de Goede static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 112451424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 112551424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 112651424b28SHans de Goede [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 112751424b28SHans de Goede [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 11282a7aa63aSChen-Yu Tsai /* Value from A83T "new timing mode". Works but might not be right. */ 11292a7aa63aSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 113051424b28SHans de Goede }; 113151424b28SHans de Goede 113251424b28SHans de Goede static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 113351424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 113451424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 113551424b28SHans de Goede [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 11360175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 11370175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 113851424b28SHans de Goede }; 113951424b28SHans de Goede 114086a93317SHans de Goede static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 114186a93317SHans de Goede .idma_des_size_bits = 13, 1142b465646eSHans de Goede .clk_delays = NULL, 1143e1b8dfd1SIcenowy Zheng .can_calibrate = false, 114486a93317SHans de Goede }; 114586a93317SHans de Goede 114686a93317SHans de Goede static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 114786a93317SHans de Goede .idma_des_size_bits = 16, 1148b465646eSHans de Goede .clk_delays = NULL, 1149e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1150b465646eSHans de Goede }; 1151b465646eSHans de Goede 1152b465646eSHans de Goede static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1153b465646eSHans de Goede .idma_des_size_bits = 16, 115486a93317SHans de Goede .clk_delays = sunxi_mmc_clk_delays, 1155e1b8dfd1SIcenowy Zheng .can_calibrate = false, 115686a93317SHans de Goede }; 115786a93317SHans de Goede 1158ac98caefSChen-Yu Tsai static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1159ac98caefSChen-Yu Tsai .idma_des_size_bits = 16, 1160ac98caefSChen-Yu Tsai .clk_delays = sunxi_mmc_clk_delays, 1161ac98caefSChen-Yu Tsai .can_calibrate = false, 11621ff9cabdSChen-Yu Tsai .ccu_has_timings_switch = true, 1163ac98caefSChen-Yu Tsai }; 1164ac98caefSChen-Yu Tsai 116586a93317SHans de Goede static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 116686a93317SHans de Goede .idma_des_size_bits = 16, 116786a93317SHans de Goede .clk_delays = sun9i_mmc_clk_delays, 1168e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1169e1b8dfd1SIcenowy Zheng }; 1170e1b8dfd1SIcenowy Zheng 117175a2f412SSamuel Holland static const struct sunxi_mmc_cfg sun20i_d1_cfg = { 117275a2f412SSamuel Holland .idma_des_size_bits = 13, 117375a2f412SSamuel Holland .idma_des_shift = 2, 117475a2f412SSamuel Holland .can_calibrate = true, 117575a2f412SSamuel Holland .mask_data0 = true, 117675a2f412SSamuel Holland .needs_new_timings = true, 117775a2f412SSamuel Holland }; 117875a2f412SSamuel Holland 1179e1b8dfd1SIcenowy Zheng static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1180e1b8dfd1SIcenowy Zheng .idma_des_size_bits = 16, 1181e1b8dfd1SIcenowy Zheng .clk_delays = NULL, 1182e1b8dfd1SIcenowy Zheng .can_calibrate = true, 118316e821e3SMaxime Ripard .mask_data0 = true, 11849a37e53eSMaxime Ripard .needs_new_timings = true, 118586a93317SHans de Goede }; 118686a93317SHans de Goede 11874fb3ce07SMaxime Ripard static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 11884fb3ce07SMaxime Ripard .idma_des_size_bits = 13, 11894fb3ce07SMaxime Ripard .clk_delays = NULL, 11904fb3ce07SMaxime Ripard .can_calibrate = true, 119107bafc1eSChen-Yu Tsai .needs_new_timings = true, 11924fb3ce07SMaxime Ripard }; 11934fb3ce07SMaxime Ripard 11943536b82eSYangtao Li static const struct sunxi_mmc_cfg sun50i_a100_cfg = { 11953536b82eSYangtao Li .idma_des_size_bits = 16, 11963536b82eSYangtao Li .idma_des_shift = 2, 11973536b82eSYangtao Li .clk_delays = NULL, 11983536b82eSYangtao Li .can_calibrate = true, 11993536b82eSYangtao Li .mask_data0 = true, 12003536b82eSYangtao Li .needs_new_timings = true, 12013536b82eSYangtao Li }; 12023536b82eSYangtao Li 12033536b82eSYangtao Li static const struct sunxi_mmc_cfg sun50i_a100_emmc_cfg = { 12043536b82eSYangtao Li .idma_des_size_bits = 13, 12053536b82eSYangtao Li .idma_des_shift = 2, 12063536b82eSYangtao Li .clk_delays = NULL, 12073536b82eSYangtao Li .can_calibrate = true, 12083536b82eSYangtao Li .needs_new_timings = true, 12093536b82eSYangtao Li }; 12103536b82eSYangtao Li 121186a93317SHans de Goede static const struct of_device_id sunxi_mmc_of_match[] = { 121286a93317SHans de Goede { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 121386a93317SHans de Goede { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1214b465646eSHans de Goede { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1215ac98caefSChen-Yu Tsai { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 121686a93317SHans de Goede { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 121775a2f412SSamuel Holland { .compatible = "allwinner,sun20i-d1-mmc", .data = &sun20i_d1_cfg }, 1218e1b8dfd1SIcenowy Zheng { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 12194fb3ce07SMaxime Ripard { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 12203536b82eSYangtao Li { .compatible = "allwinner,sun50i-a100-mmc", .data = &sun50i_a100_cfg }, 12213536b82eSYangtao Li { .compatible = "allwinner,sun50i-a100-emmc", .data = &sun50i_a100_emmc_cfg }, 122286a93317SHans de Goede { /* sentinel */ } 122386a93317SHans de Goede }; 122486a93317SHans de Goede MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 122586a93317SHans de Goede 1226774c0103SMaxime Ripard static int sunxi_mmc_enable(struct sunxi_mmc_host *host) 1227774c0103SMaxime Ripard { 1228774c0103SMaxime Ripard int ret; 1229774c0103SMaxime Ripard 1230d8181941SMaxime Ripard if (!IS_ERR(host->reset)) { 1231d8181941SMaxime Ripard ret = reset_control_reset(host->reset); 1232d8181941SMaxime Ripard if (ret) { 1233d8181941SMaxime Ripard dev_err(host->dev, "Couldn't reset the MMC controller (%d)\n", 1234d8181941SMaxime Ripard ret); 1235d8181941SMaxime Ripard return ret; 1236d8181941SMaxime Ripard } 1237d8181941SMaxime Ripard } 1238d8181941SMaxime Ripard 1239774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_ahb); 1240774c0103SMaxime Ripard if (ret) { 1241d8181941SMaxime Ripard dev_err(host->dev, "Couldn't enable the bus clocks (%d)\n", ret); 1242d8181941SMaxime Ripard goto error_assert_reset; 1243774c0103SMaxime Ripard } 1244774c0103SMaxime Ripard 1245774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_mmc); 1246774c0103SMaxime Ripard if (ret) { 1247774c0103SMaxime Ripard dev_err(host->dev, "Enable mmc clk err %d\n", ret); 1248774c0103SMaxime Ripard goto error_disable_clk_ahb; 1249774c0103SMaxime Ripard } 1250774c0103SMaxime Ripard 1251774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_output); 1252774c0103SMaxime Ripard if (ret) { 1253774c0103SMaxime Ripard dev_err(host->dev, "Enable output clk err %d\n", ret); 1254774c0103SMaxime Ripard goto error_disable_clk_mmc; 1255774c0103SMaxime Ripard } 1256774c0103SMaxime Ripard 1257774c0103SMaxime Ripard ret = clk_prepare_enable(host->clk_sample); 1258774c0103SMaxime Ripard if (ret) { 1259774c0103SMaxime Ripard dev_err(host->dev, "Enable sample clk err %d\n", ret); 1260774c0103SMaxime Ripard goto error_disable_clk_output; 1261774c0103SMaxime Ripard } 1262774c0103SMaxime Ripard 1263774c0103SMaxime Ripard /* 1264774c0103SMaxime Ripard * Sometimes the controller asserts the irq on boot for some reason, 1265774c0103SMaxime Ripard * make sure the controller is in a sane state before enabling irqs. 1266774c0103SMaxime Ripard */ 1267774c0103SMaxime Ripard ret = sunxi_mmc_reset_host(host); 1268774c0103SMaxime Ripard if (ret) 1269d8181941SMaxime Ripard goto error_disable_clk_sample; 1270774c0103SMaxime Ripard 1271774c0103SMaxime Ripard return 0; 1272774c0103SMaxime Ripard 1273774c0103SMaxime Ripard error_disable_clk_sample: 1274774c0103SMaxime Ripard clk_disable_unprepare(host->clk_sample); 1275774c0103SMaxime Ripard error_disable_clk_output: 1276774c0103SMaxime Ripard clk_disable_unprepare(host->clk_output); 1277774c0103SMaxime Ripard error_disable_clk_mmc: 1278774c0103SMaxime Ripard clk_disable_unprepare(host->clk_mmc); 1279774c0103SMaxime Ripard error_disable_clk_ahb: 1280774c0103SMaxime Ripard clk_disable_unprepare(host->clk_ahb); 1281d8181941SMaxime Ripard error_assert_reset: 1282d8181941SMaxime Ripard if (!IS_ERR(host->reset)) 1283d8181941SMaxime Ripard reset_control_assert(host->reset); 1284774c0103SMaxime Ripard return ret; 1285774c0103SMaxime Ripard } 1286774c0103SMaxime Ripard 1287774c0103SMaxime Ripard static void sunxi_mmc_disable(struct sunxi_mmc_host *host) 1288774c0103SMaxime Ripard { 1289774c0103SMaxime Ripard sunxi_mmc_reset_host(host); 1290774c0103SMaxime Ripard 1291774c0103SMaxime Ripard clk_disable_unprepare(host->clk_sample); 1292774c0103SMaxime Ripard clk_disable_unprepare(host->clk_output); 1293774c0103SMaxime Ripard clk_disable_unprepare(host->clk_mmc); 1294774c0103SMaxime Ripard clk_disable_unprepare(host->clk_ahb); 1295d8181941SMaxime Ripard 1296d8181941SMaxime Ripard if (!IS_ERR(host->reset)) 1297d8181941SMaxime Ripard reset_control_assert(host->reset); 1298774c0103SMaxime Ripard } 1299774c0103SMaxime Ripard 13003cbcb160SDavid Lanzendörfer static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 13013cbcb160SDavid Lanzendörfer struct platform_device *pdev) 13023cbcb160SDavid Lanzendörfer { 13033cbcb160SDavid Lanzendörfer int ret; 13043cbcb160SDavid Lanzendörfer 130586a93317SHans de Goede host->cfg = of_device_get_match_data(&pdev->dev); 130686a93317SHans de Goede if (!host->cfg) 130786a93317SHans de Goede return -EINVAL; 130851424b28SHans de Goede 13093cbcb160SDavid Lanzendörfer ret = mmc_regulator_get_supply(host->mmc); 1310aaab3c46SWolfram Sang if (ret) 13113cbcb160SDavid Lanzendörfer return ret; 13123cbcb160SDavid Lanzendörfer 1313c5c52c37SYangtao Li host->reg_base = devm_platform_ioremap_resource(pdev, 0); 13143cbcb160SDavid Lanzendörfer if (IS_ERR(host->reg_base)) 13153cbcb160SDavid Lanzendörfer return PTR_ERR(host->reg_base); 13163cbcb160SDavid Lanzendörfer 13173cbcb160SDavid Lanzendörfer host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 13183cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_ahb)) { 13193cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get ahb clock\n"); 13203cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_ahb); 13213cbcb160SDavid Lanzendörfer } 13223cbcb160SDavid Lanzendörfer 13233cbcb160SDavid Lanzendörfer host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 13243cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_mmc)) { 13253cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get mmc clock\n"); 13263cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_mmc); 13273cbcb160SDavid Lanzendörfer } 13283cbcb160SDavid Lanzendörfer 1329b465646eSHans de Goede if (host->cfg->clk_delays) { 13306c09bb85SMaxime Ripard host->clk_output = devm_clk_get(&pdev->dev, "output"); 13316c09bb85SMaxime Ripard if (IS_ERR(host->clk_output)) { 13326c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get output clock\n"); 13336c09bb85SMaxime Ripard return PTR_ERR(host->clk_output); 13346c09bb85SMaxime Ripard } 13356c09bb85SMaxime Ripard 13366c09bb85SMaxime Ripard host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 13376c09bb85SMaxime Ripard if (IS_ERR(host->clk_sample)) { 13386c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get sample clock\n"); 13396c09bb85SMaxime Ripard return PTR_ERR(host->clk_sample); 13406c09bb85SMaxime Ripard } 1341b465646eSHans de Goede } 13426c09bb85SMaxime Ripard 13435e40ddacSPhilipp Zabel host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 13445e40ddacSPhilipp Zabel "ahb"); 13459e71c589SChen-Yu Tsai if (PTR_ERR(host->reset) == -EPROBE_DEFER) 13469e71c589SChen-Yu Tsai return PTR_ERR(host->reset); 13473cbcb160SDavid Lanzendörfer 1348774c0103SMaxime Ripard ret = sunxi_mmc_enable(host); 13493cbcb160SDavid Lanzendörfer if (ret) 1350774c0103SMaxime Ripard return ret; 13513cbcb160SDavid Lanzendörfer 13523cbcb160SDavid Lanzendörfer host->irq = platform_get_irq(pdev, 0); 13532408a085SArvind Yadav if (host->irq <= 0) { 13542408a085SArvind Yadav ret = -EINVAL; 1355774c0103SMaxime Ripard goto error_disable_mmc; 13562408a085SArvind Yadav } 13572408a085SArvind Yadav 13583cbcb160SDavid Lanzendörfer return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 13593cbcb160SDavid Lanzendörfer sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 13603cbcb160SDavid Lanzendörfer 1361774c0103SMaxime Ripard error_disable_mmc: 1362774c0103SMaxime Ripard sunxi_mmc_disable(host); 13633cbcb160SDavid Lanzendörfer return ret; 13643cbcb160SDavid Lanzendörfer } 13653cbcb160SDavid Lanzendörfer 13663cbcb160SDavid Lanzendörfer static int sunxi_mmc_probe(struct platform_device *pdev) 13673cbcb160SDavid Lanzendörfer { 13683cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host; 13693cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 13703cbcb160SDavid Lanzendörfer int ret; 13713cbcb160SDavid Lanzendörfer 13723cbcb160SDavid Lanzendörfer mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 13733cbcb160SDavid Lanzendörfer if (!mmc) { 13743cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "mmc alloc host failed\n"); 13753cbcb160SDavid Lanzendörfer return -ENOMEM; 13763cbcb160SDavid Lanzendörfer } 1377cb1214d2SMaxime Ripard platform_set_drvdata(pdev, mmc); 13783cbcb160SDavid Lanzendörfer 13793cbcb160SDavid Lanzendörfer host = mmc_priv(mmc); 1380774c0103SMaxime Ripard host->dev = &pdev->dev; 13813cbcb160SDavid Lanzendörfer host->mmc = mmc; 13823cbcb160SDavid Lanzendörfer spin_lock_init(&host->lock); 13833cbcb160SDavid Lanzendörfer 13843cbcb160SDavid Lanzendörfer ret = sunxi_mmc_resource_request(host, pdev); 13853cbcb160SDavid Lanzendörfer if (ret) 13863cbcb160SDavid Lanzendörfer goto error_free_host; 13873cbcb160SDavid Lanzendörfer 13883cbcb160SDavid Lanzendörfer host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 13893cbcb160SDavid Lanzendörfer &host->sg_dma, GFP_KERNEL); 13903cbcb160SDavid Lanzendörfer if (!host->sg_cpu) { 13913cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 13923cbcb160SDavid Lanzendörfer ret = -ENOMEM; 13933cbcb160SDavid Lanzendörfer goto error_free_host; 13943cbcb160SDavid Lanzendörfer } 13953cbcb160SDavid Lanzendörfer 13961ff9cabdSChen-Yu Tsai if (host->cfg->ccu_has_timings_switch) { 1397ff39e7f7SChen-Yu Tsai /* 1398ff39e7f7SChen-Yu Tsai * Supports both old and new timing modes. 1399ff39e7f7SChen-Yu Tsai * Try setting the clk to new timing mode. 1400ff39e7f7SChen-Yu Tsai */ 1401ff39e7f7SChen-Yu Tsai sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1402ff39e7f7SChen-Yu Tsai 1403ff39e7f7SChen-Yu Tsai /* And check the result */ 1404ff39e7f7SChen-Yu Tsai ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1405ff39e7f7SChen-Yu Tsai if (ret < 0) { 1406ff39e7f7SChen-Yu Tsai /* 1407ff39e7f7SChen-Yu Tsai * For whatever reason we were not able to get 1408ff39e7f7SChen-Yu Tsai * the current active mode. Default to old mode. 1409ff39e7f7SChen-Yu Tsai */ 1410ff39e7f7SChen-Yu Tsai dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1411ff39e7f7SChen-Yu Tsai host->use_new_timings = false; 1412ff39e7f7SChen-Yu Tsai } else { 1413ff39e7f7SChen-Yu Tsai host->use_new_timings = !!ret; 1414ff39e7f7SChen-Yu Tsai } 1415ff39e7f7SChen-Yu Tsai } else if (host->cfg->needs_new_timings) { 1416ff39e7f7SChen-Yu Tsai /* Supports new timing mode only */ 1417ff39e7f7SChen-Yu Tsai host->use_new_timings = true; 1418ff39e7f7SChen-Yu Tsai } 1419ff39e7f7SChen-Yu Tsai 14203cbcb160SDavid Lanzendörfer mmc->ops = &sunxi_mmc_ops; 14213cbcb160SDavid Lanzendörfer mmc->max_blk_count = 8192; 14223cbcb160SDavid Lanzendörfer mmc->max_blk_size = 4096; 14233cbcb160SDavid Lanzendörfer mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 142486a93317SHans de Goede mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 14253cbcb160SDavid Lanzendörfer mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 14262dcb305aSChen-Yu Tsai /* 400kHz ~ 52MHz */ 14273cbcb160SDavid Lanzendörfer mmc->f_min = 400000; 14282dcb305aSChen-Yu Tsai mmc->f_max = 52000000; 14293df01a93SChen-Yu Tsai mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 14301be64c79SUlf Hansson MMC_CAP_SDIO_IRQ; 14313cbcb160SDavid Lanzendörfer 1432d49d92acSChen-Yu Tsai /* 1433d49d92acSChen-Yu Tsai * Some H5 devices do not have signal traces precise enough to 1434d49d92acSChen-Yu Tsai * use HS DDR mode for their eMMC chips. 1435d49d92acSChen-Yu Tsai * 1436d49d92acSChen-Yu Tsai * We still enable HS DDR modes for all the other controller 1437d49d92acSChen-Yu Tsai * variants that support them. 1438d49d92acSChen-Yu Tsai */ 1439d49d92acSChen-Yu Tsai if ((host->cfg->clk_delays || host->use_new_timings) && 1440d49d92acSChen-Yu Tsai !of_device_is_compatible(pdev->dev.of_node, 1441d49d92acSChen-Yu Tsai "allwinner,sun50i-h5-emmc")) 144288023d43SIcenowy Zheng mmc->caps |= MMC_CAP_1_8V_DDR | MMC_CAP_3_3V_DDR; 1443b465646eSHans de Goede 14443cbcb160SDavid Lanzendörfer ret = mmc_of_parse(mmc); 14453cbcb160SDavid Lanzendörfer if (ret) 14463cbcb160SDavid Lanzendörfer goto error_free_dma; 14473cbcb160SDavid Lanzendörfer 1448d6f11e7dSChen-Yu Tsai /* 1449d6f11e7dSChen-Yu Tsai * If we don't support delay chains in the SoC, we can't use any 1450d6f11e7dSChen-Yu Tsai * of the higher speed modes. Mask them out in case the device 1451d6f11e7dSChen-Yu Tsai * tree specifies the properties for them, which gets added to 1452d6f11e7dSChen-Yu Tsai * the caps by mmc_of_parse() above. 1453d6f11e7dSChen-Yu Tsai */ 1454d6f11e7dSChen-Yu Tsai if (!(host->cfg->clk_delays || host->use_new_timings)) { 1455d6f11e7dSChen-Yu Tsai mmc->caps &= ~(MMC_CAP_3_3V_DDR | MMC_CAP_1_8V_DDR | 1456d6f11e7dSChen-Yu Tsai MMC_CAP_1_2V_DDR | MMC_CAP_UHS); 1457d6f11e7dSChen-Yu Tsai mmc->caps2 &= ~MMC_CAP2_HS200; 1458d6f11e7dSChen-Yu Tsai } 1459d6f11e7dSChen-Yu Tsai 1460d6f11e7dSChen-Yu Tsai /* TODO: This driver doesn't support HS400 mode yet */ 1461d6f11e7dSChen-Yu Tsai mmc->caps2 &= ~MMC_CAP2_HS400; 1462d6f11e7dSChen-Yu Tsai 1463eef797acSMaxime Ripard ret = sunxi_mmc_init_host(host); 1464eef797acSMaxime Ripard if (ret) 1465eef797acSMaxime Ripard goto error_free_dma; 1466eef797acSMaxime Ripard 14679a8e1e8cSMaxime Ripard pm_runtime_set_active(&pdev->dev); 14689a8e1e8cSMaxime Ripard pm_runtime_set_autosuspend_delay(&pdev->dev, 50); 14699a8e1e8cSMaxime Ripard pm_runtime_use_autosuspend(&pdev->dev); 14709a8e1e8cSMaxime Ripard pm_runtime_enable(&pdev->dev); 14719a8e1e8cSMaxime Ripard 14723cbcb160SDavid Lanzendörfer ret = mmc_add_host(mmc); 14733cbcb160SDavid Lanzendörfer if (ret) 14743cbcb160SDavid Lanzendörfer goto error_free_dma; 14753cbcb160SDavid Lanzendörfer 14761389690bSAndre Przywara dev_info(&pdev->dev, "initialized, max. request size: %u KB%s\n", 14771389690bSAndre Przywara mmc->max_req_size >> 10, 14781389690bSAndre Przywara host->use_new_timings ? ", uses new timings mode" : ""); 14791389690bSAndre Przywara 14803cbcb160SDavid Lanzendörfer return 0; 14813cbcb160SDavid Lanzendörfer 14823cbcb160SDavid Lanzendörfer error_free_dma: 14833cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 14843cbcb160SDavid Lanzendörfer error_free_host: 14853cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 14863cbcb160SDavid Lanzendörfer return ret; 14873cbcb160SDavid Lanzendörfer } 14883cbcb160SDavid Lanzendörfer 14893cbcb160SDavid Lanzendörfer static int sunxi_mmc_remove(struct platform_device *pdev) 14903cbcb160SDavid Lanzendörfer { 14913cbcb160SDavid Lanzendörfer struct mmc_host *mmc = platform_get_drvdata(pdev); 14923cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 14933cbcb160SDavid Lanzendörfer 14943cbcb160SDavid Lanzendörfer mmc_remove_host(mmc); 1495*85094197SSamuel Holland pm_runtime_disable(&pdev->dev); 1496*85094197SSamuel Holland if (!pm_runtime_status_suspended(&pdev->dev)) { 14973cbcb160SDavid Lanzendörfer disable_irq(host->irq); 1498774c0103SMaxime Ripard sunxi_mmc_disable(host); 1499*85094197SSamuel Holland } 15003cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 15013cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 15023cbcb160SDavid Lanzendörfer 15033cbcb160SDavid Lanzendörfer return 0; 15043cbcb160SDavid Lanzendörfer } 15053cbcb160SDavid Lanzendörfer 1506af6b8ff4SUlf Hansson #ifdef CONFIG_PM 1507af6b8ff4SUlf Hansson static int sunxi_mmc_runtime_resume(struct device *dev) 15089a8e1e8cSMaxime Ripard { 15099a8e1e8cSMaxime Ripard struct mmc_host *mmc = dev_get_drvdata(dev); 15109a8e1e8cSMaxime Ripard struct sunxi_mmc_host *host = mmc_priv(mmc); 15119a8e1e8cSMaxime Ripard int ret; 15129a8e1e8cSMaxime Ripard 15139a8e1e8cSMaxime Ripard ret = sunxi_mmc_enable(host); 15149a8e1e8cSMaxime Ripard if (ret) 15159a8e1e8cSMaxime Ripard return ret; 15169a8e1e8cSMaxime Ripard 15179a8e1e8cSMaxime Ripard sunxi_mmc_init_host(host); 15189a8e1e8cSMaxime Ripard sunxi_mmc_set_bus_width(host, mmc->ios.bus_width); 15199a8e1e8cSMaxime Ripard sunxi_mmc_set_clk(host, &mmc->ios); 1520b8ba3578SStefan Mavrodiev enable_irq(host->irq); 15219a8e1e8cSMaxime Ripard 15229a8e1e8cSMaxime Ripard return 0; 15239a8e1e8cSMaxime Ripard } 15249a8e1e8cSMaxime Ripard 1525af6b8ff4SUlf Hansson static int sunxi_mmc_runtime_suspend(struct device *dev) 15269a8e1e8cSMaxime Ripard { 15279a8e1e8cSMaxime Ripard struct mmc_host *mmc = dev_get_drvdata(dev); 15289a8e1e8cSMaxime Ripard struct sunxi_mmc_host *host = mmc_priv(mmc); 15299a8e1e8cSMaxime Ripard 1530b8ba3578SStefan Mavrodiev /* 1531b8ba3578SStefan Mavrodiev * When clocks are off, it's possible receiving 1532b8ba3578SStefan Mavrodiev * fake interrupts, which will stall the system. 1533b8ba3578SStefan Mavrodiev * Disabling the irq will prevent this. 1534b8ba3578SStefan Mavrodiev */ 1535b8ba3578SStefan Mavrodiev disable_irq(host->irq); 15369a8e1e8cSMaxime Ripard sunxi_mmc_reset_host(host); 15379a8e1e8cSMaxime Ripard sunxi_mmc_disable(host); 15389a8e1e8cSMaxime Ripard 15399a8e1e8cSMaxime Ripard return 0; 15409a8e1e8cSMaxime Ripard } 1541af6b8ff4SUlf Hansson #endif 15429a8e1e8cSMaxime Ripard 15439a8e1e8cSMaxime Ripard static const struct dev_pm_ops sunxi_mmc_pm_ops = { 15443882917dSSamuel Holland SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 15453882917dSSamuel Holland pm_runtime_force_resume) 15469a8e1e8cSMaxime Ripard SET_RUNTIME_PM_OPS(sunxi_mmc_runtime_suspend, 15479a8e1e8cSMaxime Ripard sunxi_mmc_runtime_resume, 15489a8e1e8cSMaxime Ripard NULL) 15499a8e1e8cSMaxime Ripard }; 15509a8e1e8cSMaxime Ripard 15513cbcb160SDavid Lanzendörfer static struct platform_driver sunxi_mmc_driver = { 15523cbcb160SDavid Lanzendörfer .driver = { 15533cbcb160SDavid Lanzendörfer .name = "sunxi-mmc", 155421b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1555b733775fSKrzysztof Kozlowski .of_match_table = sunxi_mmc_of_match, 15569a8e1e8cSMaxime Ripard .pm = &sunxi_mmc_pm_ops, 15573cbcb160SDavid Lanzendörfer }, 15583cbcb160SDavid Lanzendörfer .probe = sunxi_mmc_probe, 15593cbcb160SDavid Lanzendörfer .remove = sunxi_mmc_remove, 15603cbcb160SDavid Lanzendörfer }; 15613cbcb160SDavid Lanzendörfer module_platform_driver(sunxi_mmc_driver); 15623cbcb160SDavid Lanzendörfer 15633cbcb160SDavid Lanzendörfer MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 15643cbcb160SDavid Lanzendörfer MODULE_LICENSE("GPL v2"); 15651907e386SAdam Borowski MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 15663cbcb160SDavid Lanzendörfer MODULE_ALIAS("platform:sunxi-mmc"); 1567