13cbcb160SDavid Lanzendörfer /* 23cbcb160SDavid Lanzendörfer * Driver for sunxi SD/MMC host controllers 33cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Reuuimlla Technology Co., Ltd. 43cbcb160SDavid Lanzendörfer * (C) Copyright 2007-2011 Aaron Maoye <leafy.myeh@reuuimllatech.com> 53cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 O2S GmbH <www.o2s.ch> 61907e386SAdam Borowski * (C) Copyright 2013-2014 David Lanzendörfer <david.lanzendoerfer@o2s.ch> 73cbcb160SDavid Lanzendörfer * (C) Copyright 2013-2014 Hans de Goede <hdegoede@redhat.com> 84fb3ce07SMaxime Ripard * (C) Copyright 2017 Sootech SA 93cbcb160SDavid Lanzendörfer * 103cbcb160SDavid Lanzendörfer * This program is free software; you can redistribute it and/or 113cbcb160SDavid Lanzendörfer * modify it under the terms of the GNU General Public License as 123cbcb160SDavid Lanzendörfer * published by the Free Software Foundation; either version 2 of 133cbcb160SDavid Lanzendörfer * the License, or (at your option) any later version. 143cbcb160SDavid Lanzendörfer */ 153cbcb160SDavid Lanzendörfer 163cbcb160SDavid Lanzendörfer #include <linux/kernel.h> 173cbcb160SDavid Lanzendörfer #include <linux/module.h> 183cbcb160SDavid Lanzendörfer #include <linux/io.h> 193cbcb160SDavid Lanzendörfer #include <linux/device.h> 203cbcb160SDavid Lanzendörfer #include <linux/interrupt.h> 213cbcb160SDavid Lanzendörfer #include <linux/delay.h> 223cbcb160SDavid Lanzendörfer #include <linux/err.h> 233cbcb160SDavid Lanzendörfer 243cbcb160SDavid Lanzendörfer #include <linux/clk.h> 25ff39e7f7SChen-Yu Tsai #include <linux/clk/sunxi-ng.h> 263cbcb160SDavid Lanzendörfer #include <linux/gpio.h> 273cbcb160SDavid Lanzendörfer #include <linux/platform_device.h> 283cbcb160SDavid Lanzendörfer #include <linux/spinlock.h> 293cbcb160SDavid Lanzendörfer #include <linux/scatterlist.h> 303cbcb160SDavid Lanzendörfer #include <linux/dma-mapping.h> 313cbcb160SDavid Lanzendörfer #include <linux/slab.h> 323cbcb160SDavid Lanzendörfer #include <linux/reset.h> 33f771f6e8SChen-Yu Tsai #include <linux/regulator/consumer.h> 343cbcb160SDavid Lanzendörfer 353cbcb160SDavid Lanzendörfer #include <linux/of_address.h> 363cbcb160SDavid Lanzendörfer #include <linux/of_gpio.h> 373cbcb160SDavid Lanzendörfer #include <linux/of_platform.h> 383cbcb160SDavid Lanzendörfer 393cbcb160SDavid Lanzendörfer #include <linux/mmc/host.h> 403cbcb160SDavid Lanzendörfer #include <linux/mmc/sd.h> 413cbcb160SDavid Lanzendörfer #include <linux/mmc/sdio.h> 423cbcb160SDavid Lanzendörfer #include <linux/mmc/mmc.h> 433cbcb160SDavid Lanzendörfer #include <linux/mmc/core.h> 443cbcb160SDavid Lanzendörfer #include <linux/mmc/card.h> 453cbcb160SDavid Lanzendörfer #include <linux/mmc/slot-gpio.h> 463cbcb160SDavid Lanzendörfer 473cbcb160SDavid Lanzendörfer /* register offset definitions */ 483cbcb160SDavid Lanzendörfer #define SDXC_REG_GCTRL (0x00) /* SMC Global Control Register */ 493cbcb160SDavid Lanzendörfer #define SDXC_REG_CLKCR (0x04) /* SMC Clock Control Register */ 503cbcb160SDavid Lanzendörfer #define SDXC_REG_TMOUT (0x08) /* SMC Time Out Register */ 513cbcb160SDavid Lanzendörfer #define SDXC_REG_WIDTH (0x0C) /* SMC Bus Width Register */ 523cbcb160SDavid Lanzendörfer #define SDXC_REG_BLKSZ (0x10) /* SMC Block Size Register */ 533cbcb160SDavid Lanzendörfer #define SDXC_REG_BCNTR (0x14) /* SMC Byte Count Register */ 543cbcb160SDavid Lanzendörfer #define SDXC_REG_CMDR (0x18) /* SMC Command Register */ 553cbcb160SDavid Lanzendörfer #define SDXC_REG_CARG (0x1C) /* SMC Argument Register */ 563cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP0 (0x20) /* SMC Response Register 0 */ 573cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP1 (0x24) /* SMC Response Register 1 */ 583cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP2 (0x28) /* SMC Response Register 2 */ 593cbcb160SDavid Lanzendörfer #define SDXC_REG_RESP3 (0x2C) /* SMC Response Register 3 */ 603cbcb160SDavid Lanzendörfer #define SDXC_REG_IMASK (0x30) /* SMC Interrupt Mask Register */ 613cbcb160SDavid Lanzendörfer #define SDXC_REG_MISTA (0x34) /* SMC Masked Interrupt Status Register */ 623cbcb160SDavid Lanzendörfer #define SDXC_REG_RINTR (0x38) /* SMC Raw Interrupt Status Register */ 633cbcb160SDavid Lanzendörfer #define SDXC_REG_STAS (0x3C) /* SMC Status Register */ 643cbcb160SDavid Lanzendörfer #define SDXC_REG_FTRGL (0x40) /* SMC FIFO Threshold Watermark Registe */ 653cbcb160SDavid Lanzendörfer #define SDXC_REG_FUNS (0x44) /* SMC Function Select Register */ 663cbcb160SDavid Lanzendörfer #define SDXC_REG_CBCR (0x48) /* SMC CIU Byte Count Register */ 673cbcb160SDavid Lanzendörfer #define SDXC_REG_BBCR (0x4C) /* SMC BIU Byte Count Register */ 683cbcb160SDavid Lanzendörfer #define SDXC_REG_DBGC (0x50) /* SMC Debug Enable Register */ 693cbcb160SDavid Lanzendörfer #define SDXC_REG_HWRST (0x78) /* SMC Card Hardware Reset for Register */ 703cbcb160SDavid Lanzendörfer #define SDXC_REG_DMAC (0x80) /* SMC IDMAC Control Register */ 713cbcb160SDavid Lanzendörfer #define SDXC_REG_DLBA (0x84) /* SMC IDMAC Descriptor List Base Addre */ 723cbcb160SDavid Lanzendörfer #define SDXC_REG_IDST (0x88) /* SMC IDMAC Status Register */ 733cbcb160SDavid Lanzendörfer #define SDXC_REG_IDIE (0x8C) /* SMC IDMAC Interrupt Enable Register */ 743cbcb160SDavid Lanzendörfer #define SDXC_REG_CHDA (0x90) 753cbcb160SDavid Lanzendörfer #define SDXC_REG_CBDA (0x94) 763cbcb160SDavid Lanzendörfer 77e1b8dfd1SIcenowy Zheng /* New registers introduced in A64 */ 78e1b8dfd1SIcenowy Zheng #define SDXC_REG_A12A 0x058 /* SMC Auto Command 12 Register */ 79e1b8dfd1SIcenowy Zheng #define SDXC_REG_SD_NTSR 0x05C /* SMC New Timing Set Register */ 80e1b8dfd1SIcenowy Zheng #define SDXC_REG_DRV_DL 0x140 /* Drive Delay Control Register */ 81e1b8dfd1SIcenowy Zheng #define SDXC_REG_SAMP_DL_REG 0x144 /* SMC sample delay control */ 82e1b8dfd1SIcenowy Zheng #define SDXC_REG_DS_DL_REG 0x148 /* SMC data strobe delay control */ 83e1b8dfd1SIcenowy Zheng 843cbcb160SDavid Lanzendörfer #define mmc_readl(host, reg) \ 853cbcb160SDavid Lanzendörfer readl((host)->reg_base + SDXC_##reg) 863cbcb160SDavid Lanzendörfer #define mmc_writel(host, reg, value) \ 873cbcb160SDavid Lanzendörfer writel((value), (host)->reg_base + SDXC_##reg) 883cbcb160SDavid Lanzendörfer 893cbcb160SDavid Lanzendörfer /* global control register bits */ 903cbcb160SDavid Lanzendörfer #define SDXC_SOFT_RESET BIT(0) 913cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RESET BIT(1) 923cbcb160SDavid Lanzendörfer #define SDXC_DMA_RESET BIT(2) 933cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ENABLE_BIT BIT(4) 943cbcb160SDavid Lanzendörfer #define SDXC_DMA_ENABLE_BIT BIT(5) 953cbcb160SDavid Lanzendörfer #define SDXC_DEBOUNCE_ENABLE_BIT BIT(8) 963cbcb160SDavid Lanzendörfer #define SDXC_POSEDGE_LATCH_DATA BIT(9) 973cbcb160SDavid Lanzendörfer #define SDXC_DDR_MODE BIT(10) 983cbcb160SDavid Lanzendörfer #define SDXC_MEMORY_ACCESS_DONE BIT(29) 993cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_DONE_DIRECT BIT(30) 1003cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_AHB BIT(31) 1013cbcb160SDavid Lanzendörfer #define SDXC_ACCESS_BY_DMA (0 << 31) 1023cbcb160SDavid Lanzendörfer #define SDXC_HARDWARE_RESET \ 1033cbcb160SDavid Lanzendörfer (SDXC_SOFT_RESET | SDXC_FIFO_RESET | SDXC_DMA_RESET) 1043cbcb160SDavid Lanzendörfer 1053cbcb160SDavid Lanzendörfer /* clock control bits */ 10616e821e3SMaxime Ripard #define SDXC_MASK_DATA0 BIT(31) 1073cbcb160SDavid Lanzendörfer #define SDXC_CARD_CLOCK_ON BIT(16) 1083cbcb160SDavid Lanzendörfer #define SDXC_LOW_POWER_ON BIT(17) 1093cbcb160SDavid Lanzendörfer 1103cbcb160SDavid Lanzendörfer /* bus width */ 1113cbcb160SDavid Lanzendörfer #define SDXC_WIDTH1 0 1123cbcb160SDavid Lanzendörfer #define SDXC_WIDTH4 1 1133cbcb160SDavid Lanzendörfer #define SDXC_WIDTH8 2 1143cbcb160SDavid Lanzendörfer 1153cbcb160SDavid Lanzendörfer /* smc command bits */ 1163cbcb160SDavid Lanzendörfer #define SDXC_RESP_EXPIRE BIT(6) 1173cbcb160SDavid Lanzendörfer #define SDXC_LONG_RESPONSE BIT(7) 1183cbcb160SDavid Lanzendörfer #define SDXC_CHECK_RESPONSE_CRC BIT(8) 1193cbcb160SDavid Lanzendörfer #define SDXC_DATA_EXPIRE BIT(9) 1203cbcb160SDavid Lanzendörfer #define SDXC_WRITE BIT(10) 1213cbcb160SDavid Lanzendörfer #define SDXC_SEQUENCE_MODE BIT(11) 1223cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOP BIT(12) 1233cbcb160SDavid Lanzendörfer #define SDXC_WAIT_PRE_OVER BIT(13) 1243cbcb160SDavid Lanzendörfer #define SDXC_STOP_ABORT_CMD BIT(14) 1253cbcb160SDavid Lanzendörfer #define SDXC_SEND_INIT_SEQUENCE BIT(15) 1263cbcb160SDavid Lanzendörfer #define SDXC_UPCLK_ONLY BIT(21) 1273cbcb160SDavid Lanzendörfer #define SDXC_READ_CEATA_DEV BIT(22) 1283cbcb160SDavid Lanzendörfer #define SDXC_CCS_EXPIRE BIT(23) 1293cbcb160SDavid Lanzendörfer #define SDXC_ENABLE_BIT_BOOT BIT(24) 1303cbcb160SDavid Lanzendörfer #define SDXC_ALT_BOOT_OPTIONS BIT(25) 1313cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ACK_EXPIRE BIT(26) 1323cbcb160SDavid Lanzendörfer #define SDXC_BOOT_ABORT BIT(27) 1333cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_SWITCH BIT(28) 1343cbcb160SDavid Lanzendörfer #define SDXC_USE_HOLD_REGISTER BIT(29) 1353cbcb160SDavid Lanzendörfer #define SDXC_START BIT(31) 1363cbcb160SDavid Lanzendörfer 1373cbcb160SDavid Lanzendörfer /* interrupt bits */ 1383cbcb160SDavid Lanzendörfer #define SDXC_RESP_ERROR BIT(1) 1393cbcb160SDavid Lanzendörfer #define SDXC_COMMAND_DONE BIT(2) 1403cbcb160SDavid Lanzendörfer #define SDXC_DATA_OVER BIT(3) 1413cbcb160SDavid Lanzendörfer #define SDXC_TX_DATA_REQUEST BIT(4) 1423cbcb160SDavid Lanzendörfer #define SDXC_RX_DATA_REQUEST BIT(5) 1433cbcb160SDavid Lanzendörfer #define SDXC_RESP_CRC_ERROR BIT(6) 1443cbcb160SDavid Lanzendörfer #define SDXC_DATA_CRC_ERROR BIT(7) 1453cbcb160SDavid Lanzendörfer #define SDXC_RESP_TIMEOUT BIT(8) 1463cbcb160SDavid Lanzendörfer #define SDXC_DATA_TIMEOUT BIT(9) 1473cbcb160SDavid Lanzendörfer #define SDXC_VOLTAGE_CHANGE_DONE BIT(10) 1483cbcb160SDavid Lanzendörfer #define SDXC_FIFO_RUN_ERROR BIT(11) 1493cbcb160SDavid Lanzendörfer #define SDXC_HARD_WARE_LOCKED BIT(12) 1503cbcb160SDavid Lanzendörfer #define SDXC_START_BIT_ERROR BIT(13) 1513cbcb160SDavid Lanzendörfer #define SDXC_AUTO_COMMAND_DONE BIT(14) 1523cbcb160SDavid Lanzendörfer #define SDXC_END_BIT_ERROR BIT(15) 1533cbcb160SDavid Lanzendörfer #define SDXC_SDIO_INTERRUPT BIT(16) 1543cbcb160SDavid Lanzendörfer #define SDXC_CARD_INSERT BIT(30) 1553cbcb160SDavid Lanzendörfer #define SDXC_CARD_REMOVE BIT(31) 1563cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_ERROR_BIT \ 1573cbcb160SDavid Lanzendörfer (SDXC_RESP_ERROR | SDXC_RESP_CRC_ERROR | SDXC_DATA_CRC_ERROR | \ 1583cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT | SDXC_DATA_TIMEOUT | SDXC_FIFO_RUN_ERROR | \ 1593cbcb160SDavid Lanzendörfer SDXC_HARD_WARE_LOCKED | SDXC_START_BIT_ERROR | SDXC_END_BIT_ERROR) 1603cbcb160SDavid Lanzendörfer #define SDXC_INTERRUPT_DONE_BIT \ 1613cbcb160SDavid Lanzendörfer (SDXC_AUTO_COMMAND_DONE | SDXC_DATA_OVER | \ 1623cbcb160SDavid Lanzendörfer SDXC_COMMAND_DONE | SDXC_VOLTAGE_CHANGE_DONE) 1633cbcb160SDavid Lanzendörfer 1643cbcb160SDavid Lanzendörfer /* status */ 1653cbcb160SDavid Lanzendörfer #define SDXC_RXWL_FLAG BIT(0) 1663cbcb160SDavid Lanzendörfer #define SDXC_TXWL_FLAG BIT(1) 1673cbcb160SDavid Lanzendörfer #define SDXC_FIFO_EMPTY BIT(2) 1683cbcb160SDavid Lanzendörfer #define SDXC_FIFO_FULL BIT(3) 1693cbcb160SDavid Lanzendörfer #define SDXC_CARD_PRESENT BIT(8) 1703cbcb160SDavid Lanzendörfer #define SDXC_CARD_DATA_BUSY BIT(9) 1713cbcb160SDavid Lanzendörfer #define SDXC_DATA_FSM_BUSY BIT(10) 1723cbcb160SDavid Lanzendörfer #define SDXC_DMA_REQUEST BIT(31) 1733cbcb160SDavid Lanzendörfer #define SDXC_FIFO_SIZE 16 1743cbcb160SDavid Lanzendörfer 1753cbcb160SDavid Lanzendörfer /* Function select */ 1763cbcb160SDavid Lanzendörfer #define SDXC_CEATA_ON (0xceaa << 16) 1773cbcb160SDavid Lanzendörfer #define SDXC_SEND_IRQ_RESPONSE BIT(0) 1783cbcb160SDavid Lanzendörfer #define SDXC_SDIO_READ_WAIT BIT(1) 1793cbcb160SDavid Lanzendörfer #define SDXC_ABORT_READ_DATA BIT(2) 1803cbcb160SDavid Lanzendörfer #define SDXC_SEND_CCSD BIT(8) 1813cbcb160SDavid Lanzendörfer #define SDXC_SEND_AUTO_STOPCCSD BIT(9) 1823cbcb160SDavid Lanzendörfer #define SDXC_CEATA_DEV_IRQ_ENABLE BIT(10) 1833cbcb160SDavid Lanzendörfer 1843cbcb160SDavid Lanzendörfer /* IDMA controller bus mod bit field */ 1853cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SOFT_RESET BIT(0) 1863cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FIX_BURST BIT(1) 1873cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDMA_ON BIT(7) 1883cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_REFETCH_DES BIT(31) 1893cbcb160SDavid Lanzendörfer 1903cbcb160SDavid Lanzendörfer /* IDMA status bit field */ 1913cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_TRANSMIT_INTERRUPT BIT(0) 1923cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_RECEIVE_INTERRUPT BIT(1) 1933cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_FATAL_BUS_ERROR BIT(2) 1943cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESTINATION_INVALID BIT(4) 1953cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_CARD_ERROR_SUM BIT(5) 1963cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_NORMAL_INTERRUPT_SUM BIT(8) 1973cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_ABNORMAL_INTERRUPT_SUM BIT(9) 1983cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_HOST_ABORT_INTERRUPT BIT(10) 1993cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_IDLE (0 << 13) 2003cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_SUSPEND (1 << 13) 2013cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_READ (2 << 13) 2023cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CHECK (3 << 13) 2033cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ_REQUEST_WAIT (4 << 13) 2043cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE_REQUEST_WAIT (5 << 13) 2053cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_READ (6 << 13) 2063cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_WRITE (7 << 13) 2073cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DESC_CLOSE (8 << 13) 2083cbcb160SDavid Lanzendörfer 2093cbcb160SDavid Lanzendörfer /* 2103cbcb160SDavid Lanzendörfer * If the idma-des-size-bits of property is ie 13, bufsize bits are: 2113cbcb160SDavid Lanzendörfer * Bits 0-12: buf1 size 2123cbcb160SDavid Lanzendörfer * Bits 13-25: buf2 size 2133cbcb160SDavid Lanzendörfer * Bits 26-31: not used 2143cbcb160SDavid Lanzendörfer * Since we only ever set buf1 size, we can simply store it directly. 2153cbcb160SDavid Lanzendörfer */ 2163cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_DIC BIT(1) /* disable interrupt on completion */ 2173cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_LD BIT(2) /* last descriptor */ 2183cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_FD BIT(3) /* first descriptor */ 2193cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CH BIT(4) /* chain mode */ 2203cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_ER BIT(5) /* end of ring */ 2213cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_CES BIT(30) /* card error summary */ 2223cbcb160SDavid Lanzendörfer #define SDXC_IDMAC_DES0_OWN BIT(31) /* 1-idma owns it, 0-host owns it */ 2233cbcb160SDavid Lanzendörfer 22451424b28SHans de Goede #define SDXC_CLK_400K 0 22551424b28SHans de Goede #define SDXC_CLK_25M 1 22651424b28SHans de Goede #define SDXC_CLK_50M 2 22751424b28SHans de Goede #define SDXC_CLK_50M_DDR 3 2282a7aa63aSChen-Yu Tsai #define SDXC_CLK_50M_DDR_8BIT 4 22951424b28SHans de Goede 230e1b8dfd1SIcenowy Zheng #define SDXC_2X_TIMING_MODE BIT(31) 231e1b8dfd1SIcenowy Zheng 232e1b8dfd1SIcenowy Zheng #define SDXC_CAL_START BIT(15) 233e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DONE BIT(14) 234e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SHIFT 8 235e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_EN BIT(7) 236e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_SW_SHIFT 0 237e1b8dfd1SIcenowy Zheng #define SDXC_CAL_DL_MASK 0x3f 238e1b8dfd1SIcenowy Zheng 239e1b8dfd1SIcenowy Zheng #define SDXC_CAL_TIMEOUT 3 /* in seconds, 3s is enough*/ 240e1b8dfd1SIcenowy Zheng 24151424b28SHans de Goede struct sunxi_mmc_clk_delay { 24251424b28SHans de Goede u32 output; 24351424b28SHans de Goede u32 sample; 24451424b28SHans de Goede }; 24551424b28SHans de Goede 2463cbcb160SDavid Lanzendörfer struct sunxi_idma_des { 2472dd110b2SMichael Weiser __le32 config; 2482dd110b2SMichael Weiser __le32 buf_size; 2492dd110b2SMichael Weiser __le32 buf_addr_ptr1; 2502dd110b2SMichael Weiser __le32 buf_addr_ptr2; 2513cbcb160SDavid Lanzendörfer }; 2523cbcb160SDavid Lanzendörfer 25386a93317SHans de Goede struct sunxi_mmc_cfg { 25486a93317SHans de Goede u32 idma_des_size_bits; 25586a93317SHans de Goede const struct sunxi_mmc_clk_delay *clk_delays; 256e1b8dfd1SIcenowy Zheng 257e1b8dfd1SIcenowy Zheng /* does the IP block support autocalibration? */ 258e1b8dfd1SIcenowy Zheng bool can_calibrate; 2599a37e53eSMaxime Ripard 26016e821e3SMaxime Ripard /* Does DATA0 needs to be masked while the clock is updated */ 26116e821e3SMaxime Ripard bool mask_data0; 26216e821e3SMaxime Ripard 263ff39e7f7SChen-Yu Tsai /* hardware only supports new timing mode */ 2649a37e53eSMaxime Ripard bool needs_new_timings; 265ff39e7f7SChen-Yu Tsai 266ff39e7f7SChen-Yu Tsai /* hardware can switch between old and new timing modes */ 267ff39e7f7SChen-Yu Tsai bool has_timings_switch; 26886a93317SHans de Goede }; 26986a93317SHans de Goede 2703cbcb160SDavid Lanzendörfer struct sunxi_mmc_host { 2713cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 2723cbcb160SDavid Lanzendörfer struct reset_control *reset; 27386a93317SHans de Goede const struct sunxi_mmc_cfg *cfg; 2743cbcb160SDavid Lanzendörfer 2753cbcb160SDavid Lanzendörfer /* IO mapping base */ 2763cbcb160SDavid Lanzendörfer void __iomem *reg_base; 2773cbcb160SDavid Lanzendörfer 2783cbcb160SDavid Lanzendörfer /* clock management */ 2793cbcb160SDavid Lanzendörfer struct clk *clk_ahb; 2803cbcb160SDavid Lanzendörfer struct clk *clk_mmc; 2816c09bb85SMaxime Ripard struct clk *clk_sample; 2826c09bb85SMaxime Ripard struct clk *clk_output; 2833cbcb160SDavid Lanzendörfer 2843cbcb160SDavid Lanzendörfer /* irq */ 2853cbcb160SDavid Lanzendörfer spinlock_t lock; 2863cbcb160SDavid Lanzendörfer int irq; 2873cbcb160SDavid Lanzendörfer u32 int_sum; 2883cbcb160SDavid Lanzendörfer u32 sdio_imask; 2893cbcb160SDavid Lanzendörfer 2903cbcb160SDavid Lanzendörfer /* dma */ 2913cbcb160SDavid Lanzendörfer dma_addr_t sg_dma; 2923cbcb160SDavid Lanzendörfer void *sg_cpu; 2933cbcb160SDavid Lanzendörfer bool wait_dma; 2943cbcb160SDavid Lanzendörfer 2953cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 2963cbcb160SDavid Lanzendörfer struct mmc_request *manual_stop_mrq; 2973cbcb160SDavid Lanzendörfer int ferror; 298f771f6e8SChen-Yu Tsai 299f771f6e8SChen-Yu Tsai /* vqmmc */ 300f771f6e8SChen-Yu Tsai bool vqmmc_enabled; 301ff39e7f7SChen-Yu Tsai 302ff39e7f7SChen-Yu Tsai /* timings */ 303ff39e7f7SChen-Yu Tsai bool use_new_timings; 3043cbcb160SDavid Lanzendörfer }; 3053cbcb160SDavid Lanzendörfer 3063cbcb160SDavid Lanzendörfer static int sunxi_mmc_reset_host(struct sunxi_mmc_host *host) 3073cbcb160SDavid Lanzendörfer { 3083cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(250); 3093cbcb160SDavid Lanzendörfer u32 rval; 3103cbcb160SDavid Lanzendörfer 3110f0fcd37SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, SDXC_HARDWARE_RESET); 3123cbcb160SDavid Lanzendörfer do { 3133cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3143cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_HARDWARE_RESET)); 3153cbcb160SDavid Lanzendörfer 3163cbcb160SDavid Lanzendörfer if (rval & SDXC_HARDWARE_RESET) { 3173cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err reset timeout\n"); 3183cbcb160SDavid Lanzendörfer return -EIO; 3193cbcb160SDavid Lanzendörfer } 3203cbcb160SDavid Lanzendörfer 3213cbcb160SDavid Lanzendörfer return 0; 3223cbcb160SDavid Lanzendörfer } 3233cbcb160SDavid Lanzendörfer 3243cbcb160SDavid Lanzendörfer static int sunxi_mmc_init_host(struct mmc_host *mmc) 3253cbcb160SDavid Lanzendörfer { 3263cbcb160SDavid Lanzendörfer u32 rval; 3273cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 3283cbcb160SDavid Lanzendörfer 3293cbcb160SDavid Lanzendörfer if (sunxi_mmc_reset_host(host)) 3303cbcb160SDavid Lanzendörfer return -EIO; 3313cbcb160SDavid Lanzendörfer 3320314cbd4SChen-Yu Tsai /* 3330314cbd4SChen-Yu Tsai * Burst 8 transfers, RX trigger level: 7, TX trigger level: 8 3340314cbd4SChen-Yu Tsai * 3350314cbd4SChen-Yu Tsai * TODO: sun9i has a larger FIFO and supports higher trigger values 3360314cbd4SChen-Yu Tsai */ 3373cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FTRGL, 0x20070008); 3380314cbd4SChen-Yu Tsai /* Maximum timeout value */ 3393cbcb160SDavid Lanzendörfer mmc_writel(host, REG_TMOUT, 0xffffffff); 3400314cbd4SChen-Yu Tsai /* Unmask SDIO interrupt if needed */ 3413cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 3420314cbd4SChen-Yu Tsai /* Clear all pending interrupts */ 3433cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffffffff); 3440314cbd4SChen-Yu Tsai /* Debug register? undocumented */ 3453cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DBGC, 0xdeb); 3460314cbd4SChen-Yu Tsai /* Enable CEATA support */ 3473cbcb160SDavid Lanzendörfer mmc_writel(host, REG_FUNS, SDXC_CEATA_ON); 3480314cbd4SChen-Yu Tsai /* Set DMA descriptor list base address */ 3493cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DLBA, host->sg_dma); 3503cbcb160SDavid Lanzendörfer 3513cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 3523cbcb160SDavid Lanzendörfer rval |= SDXC_INTERRUPT_ENABLE_BIT; 3530314cbd4SChen-Yu Tsai /* Undocumented, but found in Allwinner code */ 3543cbcb160SDavid Lanzendörfer rval &= ~SDXC_ACCESS_DONE_DIRECT; 3553cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 3563cbcb160SDavid Lanzendörfer 3573cbcb160SDavid Lanzendörfer return 0; 3583cbcb160SDavid Lanzendörfer } 3593cbcb160SDavid Lanzendörfer 3603cbcb160SDavid Lanzendörfer static void sunxi_mmc_init_idma_des(struct sunxi_mmc_host *host, 3613cbcb160SDavid Lanzendörfer struct mmc_data *data) 3623cbcb160SDavid Lanzendörfer { 3633cbcb160SDavid Lanzendörfer struct sunxi_idma_des *pdes = (struct sunxi_idma_des *)host->sg_cpu; 364d34712d2SArnd Bergmann dma_addr_t next_desc = host->sg_dma; 36586a93317SHans de Goede int i, max_len = (1 << host->cfg->idma_des_size_bits); 3663cbcb160SDavid Lanzendörfer 3673cbcb160SDavid Lanzendörfer for (i = 0; i < data->sg_len; i++) { 3682dd110b2SMichael Weiser pdes[i].config = cpu_to_le32(SDXC_IDMAC_DES0_CH | 3692dd110b2SMichael Weiser SDXC_IDMAC_DES0_OWN | 3702dd110b2SMichael Weiser SDXC_IDMAC_DES0_DIC); 3713cbcb160SDavid Lanzendörfer 3723cbcb160SDavid Lanzendörfer if (data->sg[i].length == max_len) 3733cbcb160SDavid Lanzendörfer pdes[i].buf_size = 0; /* 0 == max_len */ 3743cbcb160SDavid Lanzendörfer else 3752dd110b2SMichael Weiser pdes[i].buf_size = cpu_to_le32(data->sg[i].length); 3763cbcb160SDavid Lanzendörfer 377d34712d2SArnd Bergmann next_desc += sizeof(struct sunxi_idma_des); 3782dd110b2SMichael Weiser pdes[i].buf_addr_ptr1 = 3792dd110b2SMichael Weiser cpu_to_le32(sg_dma_address(&data->sg[i])); 3802dd110b2SMichael Weiser pdes[i].buf_addr_ptr2 = cpu_to_le32((u32)next_desc); 3813cbcb160SDavid Lanzendörfer } 3823cbcb160SDavid Lanzendörfer 3832dd110b2SMichael Weiser pdes[0].config |= cpu_to_le32(SDXC_IDMAC_DES0_FD); 3842dd110b2SMichael Weiser pdes[i - 1].config |= cpu_to_le32(SDXC_IDMAC_DES0_LD | 3852dd110b2SMichael Weiser SDXC_IDMAC_DES0_ER); 3862dd110b2SMichael Weiser pdes[i - 1].config &= cpu_to_le32(~SDXC_IDMAC_DES0_DIC); 387e8a59049SHans de Goede pdes[i - 1].buf_addr_ptr2 = 0; 3883cbcb160SDavid Lanzendörfer 3893cbcb160SDavid Lanzendörfer /* 3903cbcb160SDavid Lanzendörfer * Avoid the io-store starting the idmac hitting io-mem before the 3913cbcb160SDavid Lanzendörfer * descriptors hit the main-mem. 3923cbcb160SDavid Lanzendörfer */ 3933cbcb160SDavid Lanzendörfer wmb(); 3943cbcb160SDavid Lanzendörfer } 3953cbcb160SDavid Lanzendörfer 3963cbcb160SDavid Lanzendörfer static int sunxi_mmc_map_dma(struct sunxi_mmc_host *host, 3973cbcb160SDavid Lanzendörfer struct mmc_data *data) 3983cbcb160SDavid Lanzendörfer { 3993cbcb160SDavid Lanzendörfer u32 i, dma_len; 4003cbcb160SDavid Lanzendörfer struct scatterlist *sg; 4013cbcb160SDavid Lanzendörfer 4023cbcb160SDavid Lanzendörfer dma_len = dma_map_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 403feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 4043cbcb160SDavid Lanzendörfer if (dma_len == 0) { 4053cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "dma_map_sg failed\n"); 4063cbcb160SDavid Lanzendörfer return -ENOMEM; 4073cbcb160SDavid Lanzendörfer } 4083cbcb160SDavid Lanzendörfer 4093cbcb160SDavid Lanzendörfer for_each_sg(data->sg, sg, data->sg_len, i) { 4103cbcb160SDavid Lanzendörfer if (sg->offset & 3 || sg->length & 3) { 4113cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), 4123cbcb160SDavid Lanzendörfer "unaligned scatterlist: os %x length %d\n", 4133cbcb160SDavid Lanzendörfer sg->offset, sg->length); 4143cbcb160SDavid Lanzendörfer return -EINVAL; 4153cbcb160SDavid Lanzendörfer } 4163cbcb160SDavid Lanzendörfer } 4173cbcb160SDavid Lanzendörfer 4183cbcb160SDavid Lanzendörfer return 0; 4193cbcb160SDavid Lanzendörfer } 4203cbcb160SDavid Lanzendörfer 4213cbcb160SDavid Lanzendörfer static void sunxi_mmc_start_dma(struct sunxi_mmc_host *host, 4223cbcb160SDavid Lanzendörfer struct mmc_data *data) 4233cbcb160SDavid Lanzendörfer { 4243cbcb160SDavid Lanzendörfer u32 rval; 4253cbcb160SDavid Lanzendörfer 4263cbcb160SDavid Lanzendörfer sunxi_mmc_init_idma_des(host, data); 4273cbcb160SDavid Lanzendörfer 4283cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 4293cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_ENABLE_BIT; 4303cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4313cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 4323cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 4333cbcb160SDavid Lanzendörfer 4343cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, SDXC_IDMAC_SOFT_RESET); 4353cbcb160SDavid Lanzendörfer 4363cbcb160SDavid Lanzendörfer if (!(data->flags & MMC_DATA_WRITE)) 4373cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, SDXC_IDMAC_RECEIVE_INTERRUPT); 4383cbcb160SDavid Lanzendörfer 4393cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 4403cbcb160SDavid Lanzendörfer SDXC_IDMAC_FIX_BURST | SDXC_IDMAC_IDMA_ON); 4413cbcb160SDavid Lanzendörfer } 4423cbcb160SDavid Lanzendörfer 4433cbcb160SDavid Lanzendörfer static void sunxi_mmc_send_manual_stop(struct sunxi_mmc_host *host, 4443cbcb160SDavid Lanzendörfer struct mmc_request *req) 4453cbcb160SDavid Lanzendörfer { 4463cbcb160SDavid Lanzendörfer u32 arg, cmd_val, ri; 4473cbcb160SDavid Lanzendörfer unsigned long expire = jiffies + msecs_to_jiffies(1000); 4483cbcb160SDavid Lanzendörfer 4493cbcb160SDavid Lanzendörfer cmd_val = SDXC_START | SDXC_RESP_EXPIRE | 4503cbcb160SDavid Lanzendörfer SDXC_STOP_ABORT_CMD | SDXC_CHECK_RESPONSE_CRC; 4513cbcb160SDavid Lanzendörfer 4523cbcb160SDavid Lanzendörfer if (req->cmd->opcode == SD_IO_RW_EXTENDED) { 4533cbcb160SDavid Lanzendörfer cmd_val |= SD_IO_RW_DIRECT; 4543cbcb160SDavid Lanzendörfer arg = (1 << 31) | (0 << 28) | (SDIO_CCCR_ABORT << 9) | 4553cbcb160SDavid Lanzendörfer ((req->cmd->arg >> 28) & 0x7); 4563cbcb160SDavid Lanzendörfer } else { 4573cbcb160SDavid Lanzendörfer cmd_val |= MMC_STOP_TRANSMISSION; 4583cbcb160SDavid Lanzendörfer arg = 0; 4593cbcb160SDavid Lanzendörfer } 4603cbcb160SDavid Lanzendörfer 4613cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, arg); 4623cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 4633cbcb160SDavid Lanzendörfer 4643cbcb160SDavid Lanzendörfer do { 4653cbcb160SDavid Lanzendörfer ri = mmc_readl(host, REG_RINTR); 4663cbcb160SDavid Lanzendörfer } while (!(ri & (SDXC_COMMAND_DONE | SDXC_INTERRUPT_ERROR_BIT)) && 4673cbcb160SDavid Lanzendörfer time_before(jiffies, expire)); 4683cbcb160SDavid Lanzendörfer 4693cbcb160SDavid Lanzendörfer if (!(ri & SDXC_COMMAND_DONE) || (ri & SDXC_INTERRUPT_ERROR_BIT)) { 4703cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "send stop command failed\n"); 4713cbcb160SDavid Lanzendörfer if (req->stop) 4723cbcb160SDavid Lanzendörfer req->stop->resp[0] = -ETIMEDOUT; 4733cbcb160SDavid Lanzendörfer } else { 4743cbcb160SDavid Lanzendörfer if (req->stop) 4753cbcb160SDavid Lanzendörfer req->stop->resp[0] = mmc_readl(host, REG_RESP0); 4763cbcb160SDavid Lanzendörfer } 4773cbcb160SDavid Lanzendörfer 4783cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 4793cbcb160SDavid Lanzendörfer } 4803cbcb160SDavid Lanzendörfer 4813cbcb160SDavid Lanzendörfer static void sunxi_mmc_dump_errinfo(struct sunxi_mmc_host *host) 4823cbcb160SDavid Lanzendörfer { 4833cbcb160SDavid Lanzendörfer struct mmc_command *cmd = host->mrq->cmd; 4843cbcb160SDavid Lanzendörfer struct mmc_data *data = host->mrq->data; 4853cbcb160SDavid Lanzendörfer 4863cbcb160SDavid Lanzendörfer /* For some cmds timeout is normal with sd/mmc cards */ 4873cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_INTERRUPT_ERROR_BIT) == 4883cbcb160SDavid Lanzendörfer SDXC_RESP_TIMEOUT && (cmd->opcode == SD_IO_SEND_OP_COND || 4893cbcb160SDavid Lanzendörfer cmd->opcode == SD_IO_RW_DIRECT)) 4903cbcb160SDavid Lanzendörfer return; 4913cbcb160SDavid Lanzendörfer 492bd675698SIcenowy Zheng dev_dbg(mmc_dev(host->mmc), 4933cbcb160SDavid Lanzendörfer "smc %d err, cmd %d,%s%s%s%s%s%s%s%s%s%s !!\n", 4943cbcb160SDavid Lanzendörfer host->mmc->index, cmd->opcode, 4953cbcb160SDavid Lanzendörfer data ? (data->flags & MMC_DATA_WRITE ? " WR" : " RD") : "", 4963cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_ERROR ? " RE" : "", 4973cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_CRC_ERROR ? " RCE" : "", 4983cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_CRC_ERROR ? " DCE" : "", 4993cbcb160SDavid Lanzendörfer host->int_sum & SDXC_RESP_TIMEOUT ? " RTO" : "", 5003cbcb160SDavid Lanzendörfer host->int_sum & SDXC_DATA_TIMEOUT ? " DTO" : "", 5013cbcb160SDavid Lanzendörfer host->int_sum & SDXC_FIFO_RUN_ERROR ? " FE" : "", 5023cbcb160SDavid Lanzendörfer host->int_sum & SDXC_HARD_WARE_LOCKED ? " HL" : "", 5033cbcb160SDavid Lanzendörfer host->int_sum & SDXC_START_BIT_ERROR ? " SBE" : "", 5043cbcb160SDavid Lanzendörfer host->int_sum & SDXC_END_BIT_ERROR ? " EBE" : "" 5053cbcb160SDavid Lanzendörfer ); 5063cbcb160SDavid Lanzendörfer } 5073cbcb160SDavid Lanzendörfer 5083cbcb160SDavid Lanzendörfer /* Called in interrupt context! */ 5093cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_finalize_request(struct sunxi_mmc_host *host) 5103cbcb160SDavid Lanzendörfer { 5113cbcb160SDavid Lanzendörfer struct mmc_request *mrq = host->mrq; 5123cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 5133cbcb160SDavid Lanzendörfer u32 rval; 5143cbcb160SDavid Lanzendörfer 5153cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask); 5163cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDIE, 0); 5173cbcb160SDavid Lanzendörfer 5183cbcb160SDavid Lanzendörfer if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) { 5193cbcb160SDavid Lanzendörfer sunxi_mmc_dump_errinfo(host); 5203cbcb160SDavid Lanzendörfer mrq->cmd->error = -ETIMEDOUT; 5213cbcb160SDavid Lanzendörfer 5223cbcb160SDavid Lanzendörfer if (data) { 5233cbcb160SDavid Lanzendörfer data->error = -ETIMEDOUT; 5243cbcb160SDavid Lanzendörfer host->manual_stop_mrq = mrq; 5253cbcb160SDavid Lanzendörfer } 5263cbcb160SDavid Lanzendörfer 5273cbcb160SDavid Lanzendörfer if (mrq->stop) 5283cbcb160SDavid Lanzendörfer mrq->stop->error = -ETIMEDOUT; 5293cbcb160SDavid Lanzendörfer } else { 5303cbcb160SDavid Lanzendörfer if (mrq->cmd->flags & MMC_RSP_136) { 5313cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP3); 5323cbcb160SDavid Lanzendörfer mrq->cmd->resp[1] = mmc_readl(host, REG_RESP2); 5333cbcb160SDavid Lanzendörfer mrq->cmd->resp[2] = mmc_readl(host, REG_RESP1); 5343cbcb160SDavid Lanzendörfer mrq->cmd->resp[3] = mmc_readl(host, REG_RESP0); 5353cbcb160SDavid Lanzendörfer } else { 5363cbcb160SDavid Lanzendörfer mrq->cmd->resp[0] = mmc_readl(host, REG_RESP0); 5373cbcb160SDavid Lanzendörfer } 5383cbcb160SDavid Lanzendörfer 5393cbcb160SDavid Lanzendörfer if (data) 5403cbcb160SDavid Lanzendörfer data->bytes_xfered = data->blocks * data->blksz; 5413cbcb160SDavid Lanzendörfer } 5423cbcb160SDavid Lanzendörfer 5433cbcb160SDavid Lanzendörfer if (data) { 5443cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, 0x337); 5453cbcb160SDavid Lanzendörfer mmc_writel(host, REG_DMAC, 0); 5463cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 5473cbcb160SDavid Lanzendörfer rval |= SDXC_DMA_RESET; 5483cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5493cbcb160SDavid Lanzendörfer rval &= ~SDXC_DMA_ENABLE_BIT; 5503cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5513cbcb160SDavid Lanzendörfer rval |= SDXC_FIFO_RESET; 5523cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 5533cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(host->mmc), data->sg, data->sg_len, 554feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 5553cbcb160SDavid Lanzendörfer } 5563cbcb160SDavid Lanzendörfer 5573cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 0xffff); 5583cbcb160SDavid Lanzendörfer 5593cbcb160SDavid Lanzendörfer host->mrq = NULL; 5603cbcb160SDavid Lanzendörfer host->int_sum = 0; 5613cbcb160SDavid Lanzendörfer host->wait_dma = false; 5623cbcb160SDavid Lanzendörfer 5633cbcb160SDavid Lanzendörfer return host->manual_stop_mrq ? IRQ_WAKE_THREAD : IRQ_HANDLED; 5643cbcb160SDavid Lanzendörfer } 5653cbcb160SDavid Lanzendörfer 5663cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_irq(int irq, void *dev_id) 5673cbcb160SDavid Lanzendörfer { 5683cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 5693cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 5703cbcb160SDavid Lanzendörfer u32 msk_int, idma_int; 5713cbcb160SDavid Lanzendörfer bool finalize = false; 5723cbcb160SDavid Lanzendörfer bool sdio_int = false; 5733cbcb160SDavid Lanzendörfer irqreturn_t ret = IRQ_HANDLED; 5743cbcb160SDavid Lanzendörfer 5753cbcb160SDavid Lanzendörfer spin_lock(&host->lock); 5763cbcb160SDavid Lanzendörfer 5773cbcb160SDavid Lanzendörfer idma_int = mmc_readl(host, REG_IDST); 5783cbcb160SDavid Lanzendörfer msk_int = mmc_readl(host, REG_MISTA); 5793cbcb160SDavid Lanzendörfer 5803cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(host->mmc), "irq: rq %p mi %08x idi %08x\n", 5813cbcb160SDavid Lanzendörfer host->mrq, msk_int, idma_int); 5823cbcb160SDavid Lanzendörfer 5833cbcb160SDavid Lanzendörfer mrq = host->mrq; 5843cbcb160SDavid Lanzendörfer if (mrq) { 5853cbcb160SDavid Lanzendörfer if (idma_int & SDXC_IDMAC_RECEIVE_INTERRUPT) 5863cbcb160SDavid Lanzendörfer host->wait_dma = false; 5873cbcb160SDavid Lanzendörfer 5883cbcb160SDavid Lanzendörfer host->int_sum |= msk_int; 5893cbcb160SDavid Lanzendörfer 5903cbcb160SDavid Lanzendörfer /* Wait for COMMAND_DONE on RESPONSE_TIMEOUT before finalize */ 5913cbcb160SDavid Lanzendörfer if ((host->int_sum & SDXC_RESP_TIMEOUT) && 5923cbcb160SDavid Lanzendörfer !(host->int_sum & SDXC_COMMAND_DONE)) 5933cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, 5943cbcb160SDavid Lanzendörfer host->sdio_imask | SDXC_COMMAND_DONE); 5953cbcb160SDavid Lanzendörfer /* Don't wait for dma on error */ 5963cbcb160SDavid Lanzendörfer else if (host->int_sum & SDXC_INTERRUPT_ERROR_BIT) 5973cbcb160SDavid Lanzendörfer finalize = true; 5983cbcb160SDavid Lanzendörfer else if ((host->int_sum & SDXC_INTERRUPT_DONE_BIT) && 5993cbcb160SDavid Lanzendörfer !host->wait_dma) 6003cbcb160SDavid Lanzendörfer finalize = true; 6013cbcb160SDavid Lanzendörfer } 6023cbcb160SDavid Lanzendörfer 6033cbcb160SDavid Lanzendörfer if (msk_int & SDXC_SDIO_INTERRUPT) 6043cbcb160SDavid Lanzendörfer sdio_int = true; 6053cbcb160SDavid Lanzendörfer 6063cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, msk_int); 6073cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IDST, idma_int); 6083cbcb160SDavid Lanzendörfer 6093cbcb160SDavid Lanzendörfer if (finalize) 6103cbcb160SDavid Lanzendörfer ret = sunxi_mmc_finalize_request(host); 6113cbcb160SDavid Lanzendörfer 6123cbcb160SDavid Lanzendörfer spin_unlock(&host->lock); 6133cbcb160SDavid Lanzendörfer 6143cbcb160SDavid Lanzendörfer if (finalize && ret == IRQ_HANDLED) 6153cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6163cbcb160SDavid Lanzendörfer 6173cbcb160SDavid Lanzendörfer if (sdio_int) 6183cbcb160SDavid Lanzendörfer mmc_signal_sdio_irq(host->mmc); 6193cbcb160SDavid Lanzendörfer 6203cbcb160SDavid Lanzendörfer return ret; 6213cbcb160SDavid Lanzendörfer } 6223cbcb160SDavid Lanzendörfer 6233cbcb160SDavid Lanzendörfer static irqreturn_t sunxi_mmc_handle_manual_stop(int irq, void *dev_id) 6243cbcb160SDavid Lanzendörfer { 6253cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = dev_id; 6263cbcb160SDavid Lanzendörfer struct mmc_request *mrq; 6273cbcb160SDavid Lanzendörfer unsigned long iflags; 6283cbcb160SDavid Lanzendörfer 6293cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6303cbcb160SDavid Lanzendörfer mrq = host->manual_stop_mrq; 6313cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6323cbcb160SDavid Lanzendörfer 6333cbcb160SDavid Lanzendörfer if (!mrq) { 6343cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "no request for manual stop\n"); 6353cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6363cbcb160SDavid Lanzendörfer } 6373cbcb160SDavid Lanzendörfer 6383cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "data error, sending stop command\n"); 639dd9b3803SDavid Lanzendörfer 640dd9b3803SDavid Lanzendörfer /* 641dd9b3803SDavid Lanzendörfer * We will never have more than one outstanding request, 642dd9b3803SDavid Lanzendörfer * and we do not complete the request until after 643dd9b3803SDavid Lanzendörfer * we've cleared host->manual_stop_mrq so we do not need to 644dd9b3803SDavid Lanzendörfer * spin lock this function. 645dd9b3803SDavid Lanzendörfer * Additionally we have wait states within this function 646dd9b3803SDavid Lanzendörfer * so having it in a lock is a very bad idea. 647dd9b3803SDavid Lanzendörfer */ 6483cbcb160SDavid Lanzendörfer sunxi_mmc_send_manual_stop(host, mrq); 6493cbcb160SDavid Lanzendörfer 6503cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 6513cbcb160SDavid Lanzendörfer host->manual_stop_mrq = NULL; 6523cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 6533cbcb160SDavid Lanzendörfer 6543cbcb160SDavid Lanzendörfer mmc_request_done(host->mmc, mrq); 6553cbcb160SDavid Lanzendörfer 6563cbcb160SDavid Lanzendörfer return IRQ_HANDLED; 6573cbcb160SDavid Lanzendörfer } 6583cbcb160SDavid Lanzendörfer 6593cbcb160SDavid Lanzendörfer static int sunxi_mmc_oclk_onoff(struct sunxi_mmc_host *host, u32 oclk_en) 6603cbcb160SDavid Lanzendörfer { 6617bb9c244SMichal Suchanek unsigned long expire = jiffies + msecs_to_jiffies(750); 6623cbcb160SDavid Lanzendörfer u32 rval; 6633cbcb160SDavid Lanzendörfer 66443c15e96SMaxime Ripard dev_dbg(mmc_dev(host->mmc), "%sabling the clock\n", 66543c15e96SMaxime Ripard oclk_en ? "en" : "dis"); 66643c15e96SMaxime Ripard 6673cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 66816e821e3SMaxime Ripard rval &= ~(SDXC_CARD_CLOCK_ON | SDXC_LOW_POWER_ON | SDXC_MASK_DATA0); 6693cbcb160SDavid Lanzendörfer 6703cbcb160SDavid Lanzendörfer if (oclk_en) 6713cbcb160SDavid Lanzendörfer rval |= SDXC_CARD_CLOCK_ON; 67216e821e3SMaxime Ripard if (host->cfg->mask_data0) 67316e821e3SMaxime Ripard rval |= SDXC_MASK_DATA0; 6743cbcb160SDavid Lanzendörfer 6753cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 6763cbcb160SDavid Lanzendörfer 6773cbcb160SDavid Lanzendörfer rval = SDXC_START | SDXC_UPCLK_ONLY | SDXC_WAIT_PRE_OVER; 6783cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, rval); 6793cbcb160SDavid Lanzendörfer 6803cbcb160SDavid Lanzendörfer do { 6813cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CMDR); 6823cbcb160SDavid Lanzendörfer } while (time_before(jiffies, expire) && (rval & SDXC_START)); 6833cbcb160SDavid Lanzendörfer 6843cbcb160SDavid Lanzendörfer /* clear irq status bits set by the command */ 6853cbcb160SDavid Lanzendörfer mmc_writel(host, REG_RINTR, 6863cbcb160SDavid Lanzendörfer mmc_readl(host, REG_RINTR) & ~SDXC_SDIO_INTERRUPT); 6873cbcb160SDavid Lanzendörfer 6883cbcb160SDavid Lanzendörfer if (rval & SDXC_START) { 6893cbcb160SDavid Lanzendörfer dev_err(mmc_dev(host->mmc), "fatal err update clk timeout\n"); 6903cbcb160SDavid Lanzendörfer return -EIO; 6913cbcb160SDavid Lanzendörfer } 6923cbcb160SDavid Lanzendörfer 69316e821e3SMaxime Ripard if (host->cfg->mask_data0) { 69416e821e3SMaxime Ripard rval = mmc_readl(host, REG_CLKCR); 69516e821e3SMaxime Ripard mmc_writel(host, REG_CLKCR, rval & ~SDXC_MASK_DATA0); 69616e821e3SMaxime Ripard } 69716e821e3SMaxime Ripard 6983cbcb160SDavid Lanzendörfer return 0; 6993cbcb160SDavid Lanzendörfer } 7003cbcb160SDavid Lanzendörfer 701e1b8dfd1SIcenowy Zheng static int sunxi_mmc_calibrate(struct sunxi_mmc_host *host, int reg_off) 702e1b8dfd1SIcenowy Zheng { 703e1b8dfd1SIcenowy Zheng if (!host->cfg->can_calibrate) 704e1b8dfd1SIcenowy Zheng return 0; 705e1b8dfd1SIcenowy Zheng 706860fdf89SMaxime Ripard /* 707860fdf89SMaxime Ripard * FIXME: 708860fdf89SMaxime Ripard * This is not clear how the calibration is supposed to work 709860fdf89SMaxime Ripard * yet. The best rate have been obtained by simply setting the 710860fdf89SMaxime Ripard * delay to 0, as Allwinner does in its BSP. 711860fdf89SMaxime Ripard * 712860fdf89SMaxime Ripard * The only mode that doesn't have such a delay is HS400, that 713860fdf89SMaxime Ripard * is in itself a TODO. 714860fdf89SMaxime Ripard */ 715860fdf89SMaxime Ripard writel(SDXC_CAL_DL_SW_EN, host->reg_base + reg_off); 716e1b8dfd1SIcenowy Zheng 717e1b8dfd1SIcenowy Zheng return 0; 718e1b8dfd1SIcenowy Zheng } 719e1b8dfd1SIcenowy Zheng 720f2cecb70SHans de Goede static int sunxi_mmc_clk_set_phase(struct sunxi_mmc_host *host, 721f2cecb70SHans de Goede struct mmc_ios *ios, u32 rate) 722f2cecb70SHans de Goede { 723f2cecb70SHans de Goede int index; 724f2cecb70SHans de Goede 725a6461134SChen-Yu Tsai /* clk controller delays not used under new timings mode */ 726ff39e7f7SChen-Yu Tsai if (host->use_new_timings) 727b465646eSHans de Goede return 0; 728b465646eSHans de Goede 729a6461134SChen-Yu Tsai /* some old controllers don't support delays */ 730a6461134SChen-Yu Tsai if (!host->cfg->clk_delays) 731a6461134SChen-Yu Tsai return 0; 732a6461134SChen-Yu Tsai 733f2cecb70SHans de Goede /* determine delays */ 734f2cecb70SHans de Goede if (rate <= 400000) { 735f2cecb70SHans de Goede index = SDXC_CLK_400K; 736f2cecb70SHans de Goede } else if (rate <= 25000000) { 737f2cecb70SHans de Goede index = SDXC_CLK_25M; 738f2cecb70SHans de Goede } else if (rate <= 52000000) { 739f2cecb70SHans de Goede if (ios->timing != MMC_TIMING_UHS_DDR50 && 740f2cecb70SHans de Goede ios->timing != MMC_TIMING_MMC_DDR52) { 741f2cecb70SHans de Goede index = SDXC_CLK_50M; 742f2cecb70SHans de Goede } else if (ios->bus_width == MMC_BUS_WIDTH_8) { 743f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR_8BIT; 744f2cecb70SHans de Goede } else { 745f2cecb70SHans de Goede index = SDXC_CLK_50M_DDR; 746f2cecb70SHans de Goede } 747f2cecb70SHans de Goede } else { 74843c15e96SMaxime Ripard dev_dbg(mmc_dev(host->mmc), "Invalid clock... returning\n"); 749f2cecb70SHans de Goede return -EINVAL; 750f2cecb70SHans de Goede } 751f2cecb70SHans de Goede 752f2cecb70SHans de Goede clk_set_phase(host->clk_sample, host->cfg->clk_delays[index].sample); 753f2cecb70SHans de Goede clk_set_phase(host->clk_output, host->cfg->clk_delays[index].output); 754f2cecb70SHans de Goede 755f2cecb70SHans de Goede return 0; 756f2cecb70SHans de Goede } 757f2cecb70SHans de Goede 7583cbcb160SDavid Lanzendörfer static int sunxi_mmc_clk_set_rate(struct sunxi_mmc_host *host, 7593cbcb160SDavid Lanzendörfer struct mmc_ios *ios) 7603cbcb160SDavid Lanzendörfer { 76143c15e96SMaxime Ripard struct mmc_host *mmc = host->mmc; 76263311becSJean-Francois Moine long rate; 763c903a2aeSChen-Yu Tsai u32 rval, clock = ios->clock, div = 1; 7643cbcb160SDavid Lanzendörfer int ret; 7653cbcb160SDavid Lanzendörfer 76639cc281fSMaxime Ripard ret = sunxi_mmc_oclk_onoff(host, 0); 76739cc281fSMaxime Ripard if (ret) 76839cc281fSMaxime Ripard return ret; 76939cc281fSMaxime Ripard 77043c15e96SMaxime Ripard /* Our clock is gated now */ 77143c15e96SMaxime Ripard mmc->actual_clock = 0; 77243c15e96SMaxime Ripard 7739479074eSMaxime Ripard if (!ios->clock) 7749479074eSMaxime Ripard return 0; 7759479074eSMaxime Ripard 776c903a2aeSChen-Yu Tsai /* 777c903a2aeSChen-Yu Tsai * Under the old timing mode, 8 bit DDR requires the module 778c903a2aeSChen-Yu Tsai * clock to be double the card clock. Under the new timing 779c903a2aeSChen-Yu Tsai * mode, all DDR modes require a doubled module clock. 780c903a2aeSChen-Yu Tsai * 781c903a2aeSChen-Yu Tsai * We currently only support the standard MMC DDR52 mode. 782c903a2aeSChen-Yu Tsai * This block should be updated once support for other DDR 783c903a2aeSChen-Yu Tsai * modes is added. 784c903a2aeSChen-Yu Tsai */ 7852a7aa63aSChen-Yu Tsai if (ios->timing == MMC_TIMING_MMC_DDR52 && 786c903a2aeSChen-Yu Tsai (host->use_new_timings || 787c903a2aeSChen-Yu Tsai ios->bus_width == MMC_BUS_WIDTH_8)) { 788c903a2aeSChen-Yu Tsai div = 2; 7892a7aa63aSChen-Yu Tsai clock <<= 1; 790c903a2aeSChen-Yu Tsai } 7912a7aa63aSChen-Yu Tsai 792b939e0b7SIcenowy Zheng if (host->use_new_timings && host->cfg->has_timings_switch) { 793ff39e7f7SChen-Yu Tsai ret = sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 794ff39e7f7SChen-Yu Tsai if (ret) { 795ff39e7f7SChen-Yu Tsai dev_err(mmc_dev(mmc), 796ff39e7f7SChen-Yu Tsai "error setting new timing mode\n"); 797ff39e7f7SChen-Yu Tsai return ret; 798ff39e7f7SChen-Yu Tsai } 799ff39e7f7SChen-Yu Tsai } 800ff39e7f7SChen-Yu Tsai 8012a7aa63aSChen-Yu Tsai rate = clk_round_rate(host->clk_mmc, clock); 80263311becSJean-Francois Moine if (rate < 0) { 80343c15e96SMaxime Ripard dev_err(mmc_dev(mmc), "error rounding clk to %d: %ld\n", 80463311becSJean-Francois Moine clock, rate); 80563311becSJean-Francois Moine return rate; 80663311becSJean-Francois Moine } 80743c15e96SMaxime Ripard dev_dbg(mmc_dev(mmc), "setting clk to %d, rounded %ld\n", 8082a7aa63aSChen-Yu Tsai clock, rate); 8093cbcb160SDavid Lanzendörfer 8103cbcb160SDavid Lanzendörfer /* setting clock rate */ 8113cbcb160SDavid Lanzendörfer ret = clk_set_rate(host->clk_mmc, rate); 8123cbcb160SDavid Lanzendörfer if (ret) { 81343c15e96SMaxime Ripard dev_err(mmc_dev(mmc), "error setting clk to %ld: %d\n", 8143cbcb160SDavid Lanzendörfer rate, ret); 8153cbcb160SDavid Lanzendörfer return ret; 8163cbcb160SDavid Lanzendörfer } 8173cbcb160SDavid Lanzendörfer 818c903a2aeSChen-Yu Tsai /* set internal divider */ 8193cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_CLKCR); 8203cbcb160SDavid Lanzendörfer rval &= ~0xff; 821c903a2aeSChen-Yu Tsai rval |= div - 1; 8223cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CLKCR, rval); 8233cbcb160SDavid Lanzendörfer 824082bb85fSChen-Yu Tsai /* update card clock rate to account for internal divider */ 825082bb85fSChen-Yu Tsai rate /= div; 826082bb85fSChen-Yu Tsai 827ff39e7f7SChen-Yu Tsai if (host->use_new_timings) { 82826cb2be4SChen-Yu Tsai /* Don't touch the delay bits */ 82926cb2be4SChen-Yu Tsai rval = mmc_readl(host, REG_SD_NTSR); 83026cb2be4SChen-Yu Tsai rval |= SDXC_2X_TIMING_MODE; 83126cb2be4SChen-Yu Tsai mmc_writel(host, REG_SD_NTSR, rval); 83226cb2be4SChen-Yu Tsai } 8339a37e53eSMaxime Ripard 834082bb85fSChen-Yu Tsai /* sunxi_mmc_clk_set_phase expects the actual card clock rate */ 835f2cecb70SHans de Goede ret = sunxi_mmc_clk_set_phase(host, ios, rate); 836f2cecb70SHans de Goede if (ret) 837f2cecb70SHans de Goede return ret; 8383cbcb160SDavid Lanzendörfer 839e1b8dfd1SIcenowy Zheng ret = sunxi_mmc_calibrate(host, SDXC_REG_SAMP_DL_REG); 840e1b8dfd1SIcenowy Zheng if (ret) 841e1b8dfd1SIcenowy Zheng return ret; 842e1b8dfd1SIcenowy Zheng 843860fdf89SMaxime Ripard /* 844860fdf89SMaxime Ripard * FIXME: 845860fdf89SMaxime Ripard * 846860fdf89SMaxime Ripard * In HS400 we'll also need to calibrate the data strobe 847860fdf89SMaxime Ripard * signal. This should only happen on the MMC2 controller (at 848860fdf89SMaxime Ripard * least on the A64). 849860fdf89SMaxime Ripard */ 850e1b8dfd1SIcenowy Zheng 85143c15e96SMaxime Ripard ret = sunxi_mmc_oclk_onoff(host, 1); 85243c15e96SMaxime Ripard if (ret) 85343c15e96SMaxime Ripard return ret; 85443c15e96SMaxime Ripard 85543c15e96SMaxime Ripard /* And we just enabled our clock back */ 856082bb85fSChen-Yu Tsai mmc->actual_clock = rate; 85743c15e96SMaxime Ripard 85843c15e96SMaxime Ripard return 0; 8593cbcb160SDavid Lanzendörfer } 8603cbcb160SDavid Lanzendörfer 8613cbcb160SDavid Lanzendörfer static void sunxi_mmc_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 8623cbcb160SDavid Lanzendörfer { 8633cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 8643cbcb160SDavid Lanzendörfer u32 rval; 8653cbcb160SDavid Lanzendörfer 8663cbcb160SDavid Lanzendörfer /* Set the power state */ 8673cbcb160SDavid Lanzendörfer switch (ios->power_mode) { 8683cbcb160SDavid Lanzendörfer case MMC_POWER_ON: 8693cbcb160SDavid Lanzendörfer break; 8703cbcb160SDavid Lanzendörfer 8713cbcb160SDavid Lanzendörfer case MMC_POWER_UP: 872424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) { 873424feb59SMaxime Ripard host->ferror = mmc_regulator_set_ocr(mmc, 874424feb59SMaxime Ripard mmc->supply.vmmc, 8754159215aSChen-Yu Tsai ios->vdd); 8764159215aSChen-Yu Tsai if (host->ferror) 8774159215aSChen-Yu Tsai return; 878424feb59SMaxime Ripard } 8793cbcb160SDavid Lanzendörfer 880f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc)) { 881f771f6e8SChen-Yu Tsai host->ferror = regulator_enable(mmc->supply.vqmmc); 882f771f6e8SChen-Yu Tsai if (host->ferror) { 883f771f6e8SChen-Yu Tsai dev_err(mmc_dev(mmc), 884f771f6e8SChen-Yu Tsai "failed to enable vqmmc\n"); 885f771f6e8SChen-Yu Tsai return; 886f771f6e8SChen-Yu Tsai } 887f771f6e8SChen-Yu Tsai host->vqmmc_enabled = true; 888f771f6e8SChen-Yu Tsai } 889f771f6e8SChen-Yu Tsai 8903cbcb160SDavid Lanzendörfer host->ferror = sunxi_mmc_init_host(mmc); 8913cbcb160SDavid Lanzendörfer if (host->ferror) 8923cbcb160SDavid Lanzendörfer return; 8933cbcb160SDavid Lanzendörfer 8943cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "power on!\n"); 8953cbcb160SDavid Lanzendörfer break; 8963cbcb160SDavid Lanzendörfer 8973cbcb160SDavid Lanzendörfer case MMC_POWER_OFF: 8983cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "power off!\n"); 8993cbcb160SDavid Lanzendörfer sunxi_mmc_reset_host(host); 900424feb59SMaxime Ripard if (!IS_ERR(mmc->supply.vmmc)) 9013cbcb160SDavid Lanzendörfer mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 902424feb59SMaxime Ripard 903f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc) && host->vqmmc_enabled) 904f771f6e8SChen-Yu Tsai regulator_disable(mmc->supply.vqmmc); 905f771f6e8SChen-Yu Tsai host->vqmmc_enabled = false; 9063cbcb160SDavid Lanzendörfer break; 9073cbcb160SDavid Lanzendörfer } 9083cbcb160SDavid Lanzendörfer 9093cbcb160SDavid Lanzendörfer /* set bus width */ 9103cbcb160SDavid Lanzendörfer switch (ios->bus_width) { 9113cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_1: 9123cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH1); 9133cbcb160SDavid Lanzendörfer break; 9143cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_4: 9153cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH4); 9163cbcb160SDavid Lanzendörfer break; 9173cbcb160SDavid Lanzendörfer case MMC_BUS_WIDTH_8: 9183cbcb160SDavid Lanzendörfer mmc_writel(host, REG_WIDTH, SDXC_WIDTH8); 9193cbcb160SDavid Lanzendörfer break; 9203cbcb160SDavid Lanzendörfer } 9213cbcb160SDavid Lanzendörfer 9223cbcb160SDavid Lanzendörfer /* set ddr mode */ 9233cbcb160SDavid Lanzendörfer rval = mmc_readl(host, REG_GCTRL); 9242dcb305aSChen-Yu Tsai if (ios->timing == MMC_TIMING_UHS_DDR50 || 9252dcb305aSChen-Yu Tsai ios->timing == MMC_TIMING_MMC_DDR52) 9263cbcb160SDavid Lanzendörfer rval |= SDXC_DDR_MODE; 9273cbcb160SDavid Lanzendörfer else 9283cbcb160SDavid Lanzendörfer rval &= ~SDXC_DDR_MODE; 9293cbcb160SDavid Lanzendörfer mmc_writel(host, REG_GCTRL, rval); 9303cbcb160SDavid Lanzendörfer 9313cbcb160SDavid Lanzendörfer /* set up clock */ 9329479074eSMaxime Ripard if (ios->power_mode) { 9333cbcb160SDavid Lanzendörfer host->ferror = sunxi_mmc_clk_set_rate(host, ios); 9343cbcb160SDavid Lanzendörfer /* Android code had a usleep_range(50000, 55000); here */ 9353cbcb160SDavid Lanzendörfer } 9363cbcb160SDavid Lanzendörfer } 9373cbcb160SDavid Lanzendörfer 938f771f6e8SChen-Yu Tsai static int sunxi_mmc_volt_switch(struct mmc_host *mmc, struct mmc_ios *ios) 939f771f6e8SChen-Yu Tsai { 940f771f6e8SChen-Yu Tsai /* vqmmc regulator is available */ 941f771f6e8SChen-Yu Tsai if (!IS_ERR(mmc->supply.vqmmc)) 942f771f6e8SChen-Yu Tsai return mmc_regulator_set_vqmmc(mmc, ios); 943f771f6e8SChen-Yu Tsai 944f771f6e8SChen-Yu Tsai /* no vqmmc regulator, assume fixed regulator at 3/3.3V */ 945f771f6e8SChen-Yu Tsai if (mmc->ios.signal_voltage == MMC_SIGNAL_VOLTAGE_330) 946f771f6e8SChen-Yu Tsai return 0; 947f771f6e8SChen-Yu Tsai 948f771f6e8SChen-Yu Tsai return -EINVAL; 949f771f6e8SChen-Yu Tsai } 950f771f6e8SChen-Yu Tsai 9513cbcb160SDavid Lanzendörfer static void sunxi_mmc_enable_sdio_irq(struct mmc_host *mmc, int enable) 9523cbcb160SDavid Lanzendörfer { 9533cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 9543cbcb160SDavid Lanzendörfer unsigned long flags; 9553cbcb160SDavid Lanzendörfer u32 imask; 9563cbcb160SDavid Lanzendörfer 9573cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, flags); 9583cbcb160SDavid Lanzendörfer 9593cbcb160SDavid Lanzendörfer imask = mmc_readl(host, REG_IMASK); 9603cbcb160SDavid Lanzendörfer if (enable) { 9613cbcb160SDavid Lanzendörfer host->sdio_imask = SDXC_SDIO_INTERRUPT; 9623cbcb160SDavid Lanzendörfer imask |= SDXC_SDIO_INTERRUPT; 9633cbcb160SDavid Lanzendörfer } else { 9643cbcb160SDavid Lanzendörfer host->sdio_imask = 0; 9653cbcb160SDavid Lanzendörfer imask &= ~SDXC_SDIO_INTERRUPT; 9663cbcb160SDavid Lanzendörfer } 9673cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, imask); 9683cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, flags); 9693cbcb160SDavid Lanzendörfer } 9703cbcb160SDavid Lanzendörfer 9713cbcb160SDavid Lanzendörfer static void sunxi_mmc_hw_reset(struct mmc_host *mmc) 9723cbcb160SDavid Lanzendörfer { 9733cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 9743cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 0); 9753cbcb160SDavid Lanzendörfer udelay(10); 9763cbcb160SDavid Lanzendörfer mmc_writel(host, REG_HWRST, 1); 9773cbcb160SDavid Lanzendörfer udelay(300); 9783cbcb160SDavid Lanzendörfer } 9793cbcb160SDavid Lanzendörfer 9803cbcb160SDavid Lanzendörfer static void sunxi_mmc_request(struct mmc_host *mmc, struct mmc_request *mrq) 9813cbcb160SDavid Lanzendörfer { 9823cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 9833cbcb160SDavid Lanzendörfer struct mmc_command *cmd = mrq->cmd; 9843cbcb160SDavid Lanzendörfer struct mmc_data *data = mrq->data; 9853cbcb160SDavid Lanzendörfer unsigned long iflags; 9863cbcb160SDavid Lanzendörfer u32 imask = SDXC_INTERRUPT_ERROR_BIT; 9873cbcb160SDavid Lanzendörfer u32 cmd_val = SDXC_START | (cmd->opcode & 0x3f); 988dd9b3803SDavid Lanzendörfer bool wait_dma = host->wait_dma; 9893cbcb160SDavid Lanzendörfer int ret; 9903cbcb160SDavid Lanzendörfer 9913cbcb160SDavid Lanzendörfer /* Check for set_ios errors (should never happen) */ 9923cbcb160SDavid Lanzendörfer if (host->ferror) { 9933cbcb160SDavid Lanzendörfer mrq->cmd->error = host->ferror; 9943cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 9953cbcb160SDavid Lanzendörfer return; 9963cbcb160SDavid Lanzendörfer } 9973cbcb160SDavid Lanzendörfer 9983cbcb160SDavid Lanzendörfer if (data) { 9993cbcb160SDavid Lanzendörfer ret = sunxi_mmc_map_dma(host, data); 10003cbcb160SDavid Lanzendörfer if (ret < 0) { 10013cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "map DMA failed\n"); 10023cbcb160SDavid Lanzendörfer cmd->error = ret; 10033cbcb160SDavid Lanzendörfer data->error = ret; 10043cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10053cbcb160SDavid Lanzendörfer return; 10063cbcb160SDavid Lanzendörfer } 10073cbcb160SDavid Lanzendörfer } 10083cbcb160SDavid Lanzendörfer 10093cbcb160SDavid Lanzendörfer if (cmd->opcode == MMC_GO_IDLE_STATE) { 10103cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_INIT_SEQUENCE; 10113cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10123cbcb160SDavid Lanzendörfer } 10133cbcb160SDavid Lanzendörfer 10143cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_PRESENT) { 10153cbcb160SDavid Lanzendörfer cmd_val |= SDXC_RESP_EXPIRE; 10163cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_136) 10173cbcb160SDavid Lanzendörfer cmd_val |= SDXC_LONG_RESPONSE; 10183cbcb160SDavid Lanzendörfer if (cmd->flags & MMC_RSP_CRC) 10193cbcb160SDavid Lanzendörfer cmd_val |= SDXC_CHECK_RESPONSE_CRC; 10203cbcb160SDavid Lanzendörfer 10213cbcb160SDavid Lanzendörfer if ((cmd->flags & MMC_CMD_MASK) == MMC_CMD_ADTC) { 10223cbcb160SDavid Lanzendörfer cmd_val |= SDXC_DATA_EXPIRE | SDXC_WAIT_PRE_OVER; 10233cbcb160SDavid Lanzendörfer 10243cbcb160SDavid Lanzendörfer if (cmd->data->stop) { 10253cbcb160SDavid Lanzendörfer imask |= SDXC_AUTO_COMMAND_DONE; 10263cbcb160SDavid Lanzendörfer cmd_val |= SDXC_SEND_AUTO_STOP; 10273cbcb160SDavid Lanzendörfer } else { 10283cbcb160SDavid Lanzendörfer imask |= SDXC_DATA_OVER; 10293cbcb160SDavid Lanzendörfer } 10303cbcb160SDavid Lanzendörfer 10313cbcb160SDavid Lanzendörfer if (cmd->data->flags & MMC_DATA_WRITE) 10323cbcb160SDavid Lanzendörfer cmd_val |= SDXC_WRITE; 10333cbcb160SDavid Lanzendörfer else 1034dd9b3803SDavid Lanzendörfer wait_dma = true; 10353cbcb160SDavid Lanzendörfer } else { 10363cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10373cbcb160SDavid Lanzendörfer } 10383cbcb160SDavid Lanzendörfer } else { 10393cbcb160SDavid Lanzendörfer imask |= SDXC_COMMAND_DONE; 10403cbcb160SDavid Lanzendörfer } 10413cbcb160SDavid Lanzendörfer 10423cbcb160SDavid Lanzendörfer dev_dbg(mmc_dev(mmc), "cmd %d(%08x) arg %x ie 0x%08x len %d\n", 10433cbcb160SDavid Lanzendörfer cmd_val & 0x3f, cmd_val, cmd->arg, imask, 10443cbcb160SDavid Lanzendörfer mrq->data ? mrq->data->blksz * mrq->data->blocks : 0); 10453cbcb160SDavid Lanzendörfer 10463cbcb160SDavid Lanzendörfer spin_lock_irqsave(&host->lock, iflags); 10473cbcb160SDavid Lanzendörfer 10483cbcb160SDavid Lanzendörfer if (host->mrq || host->manual_stop_mrq) { 10493cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 10503cbcb160SDavid Lanzendörfer 10513cbcb160SDavid Lanzendörfer if (data) 10523cbcb160SDavid Lanzendörfer dma_unmap_sg(mmc_dev(mmc), data->sg, data->sg_len, 1053feeef096SHeiner Kallweit mmc_get_dma_dir(data)); 10543cbcb160SDavid Lanzendörfer 10553cbcb160SDavid Lanzendörfer dev_err(mmc_dev(mmc), "request already pending\n"); 10563cbcb160SDavid Lanzendörfer mrq->cmd->error = -EBUSY; 10573cbcb160SDavid Lanzendörfer mmc_request_done(mmc, mrq); 10583cbcb160SDavid Lanzendörfer return; 10593cbcb160SDavid Lanzendörfer } 10603cbcb160SDavid Lanzendörfer 10613cbcb160SDavid Lanzendörfer if (data) { 10623cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BLKSZ, data->blksz); 10633cbcb160SDavid Lanzendörfer mmc_writel(host, REG_BCNTR, data->blksz * data->blocks); 10643cbcb160SDavid Lanzendörfer sunxi_mmc_start_dma(host, data); 10653cbcb160SDavid Lanzendörfer } 10663cbcb160SDavid Lanzendörfer 10673cbcb160SDavid Lanzendörfer host->mrq = mrq; 1068dd9b3803SDavid Lanzendörfer host->wait_dma = wait_dma; 10693cbcb160SDavid Lanzendörfer mmc_writel(host, REG_IMASK, host->sdio_imask | imask); 10703cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CARG, cmd->arg); 10713cbcb160SDavid Lanzendörfer mmc_writel(host, REG_CMDR, cmd_val); 10723cbcb160SDavid Lanzendörfer 10733cbcb160SDavid Lanzendörfer spin_unlock_irqrestore(&host->lock, iflags); 10743cbcb160SDavid Lanzendörfer } 10753cbcb160SDavid Lanzendörfer 1076c1590dd8SHans de Goede static int sunxi_mmc_card_busy(struct mmc_host *mmc) 1077c1590dd8SHans de Goede { 1078c1590dd8SHans de Goede struct sunxi_mmc_host *host = mmc_priv(mmc); 1079c1590dd8SHans de Goede 1080c1590dd8SHans de Goede return !!(mmc_readl(host, REG_STAS) & SDXC_CARD_DATA_BUSY); 1081c1590dd8SHans de Goede } 1082c1590dd8SHans de Goede 10831f8029c3SJulia Lawall static const struct mmc_host_ops sunxi_mmc_ops = { 10843cbcb160SDavid Lanzendörfer .request = sunxi_mmc_request, 10853cbcb160SDavid Lanzendörfer .set_ios = sunxi_mmc_set_ios, 10863cbcb160SDavid Lanzendörfer .get_ro = mmc_gpio_get_ro, 10873cbcb160SDavid Lanzendörfer .get_cd = mmc_gpio_get_cd, 10883cbcb160SDavid Lanzendörfer .enable_sdio_irq = sunxi_mmc_enable_sdio_irq, 1089f771f6e8SChen-Yu Tsai .start_signal_voltage_switch = sunxi_mmc_volt_switch, 10903cbcb160SDavid Lanzendörfer .hw_reset = sunxi_mmc_hw_reset, 1091c1590dd8SHans de Goede .card_busy = sunxi_mmc_card_busy, 10923cbcb160SDavid Lanzendörfer }; 10933cbcb160SDavid Lanzendörfer 109451424b28SHans de Goede static const struct sunxi_mmc_clk_delay sunxi_mmc_clk_delays[] = { 109551424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 109651424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 109751424b28SHans de Goede [SDXC_CLK_50M] = { .output = 90, .sample = 120 }, 109851424b28SHans de Goede [SDXC_CLK_50M_DDR] = { .output = 60, .sample = 120 }, 10992a7aa63aSChen-Yu Tsai /* Value from A83T "new timing mode". Works but might not be right. */ 11002a7aa63aSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 90, .sample = 180 }, 110151424b28SHans de Goede }; 110251424b28SHans de Goede 110351424b28SHans de Goede static const struct sunxi_mmc_clk_delay sun9i_mmc_clk_delays[] = { 110451424b28SHans de Goede [SDXC_CLK_400K] = { .output = 180, .sample = 180 }, 110551424b28SHans de Goede [SDXC_CLK_25M] = { .output = 180, .sample = 75 }, 110651424b28SHans de Goede [SDXC_CLK_50M] = { .output = 150, .sample = 120 }, 11070175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR] = { .output = 54, .sample = 36 }, 11080175249eSChen-Yu Tsai [SDXC_CLK_50M_DDR_8BIT] = { .output = 72, .sample = 72 }, 110951424b28SHans de Goede }; 111051424b28SHans de Goede 111186a93317SHans de Goede static const struct sunxi_mmc_cfg sun4i_a10_cfg = { 111286a93317SHans de Goede .idma_des_size_bits = 13, 1113b465646eSHans de Goede .clk_delays = NULL, 1114e1b8dfd1SIcenowy Zheng .can_calibrate = false, 111586a93317SHans de Goede }; 111686a93317SHans de Goede 111786a93317SHans de Goede static const struct sunxi_mmc_cfg sun5i_a13_cfg = { 111886a93317SHans de Goede .idma_des_size_bits = 16, 1119b465646eSHans de Goede .clk_delays = NULL, 1120e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1121b465646eSHans de Goede }; 1122b465646eSHans de Goede 1123b465646eSHans de Goede static const struct sunxi_mmc_cfg sun7i_a20_cfg = { 1124b465646eSHans de Goede .idma_des_size_bits = 16, 112586a93317SHans de Goede .clk_delays = sunxi_mmc_clk_delays, 1126e1b8dfd1SIcenowy Zheng .can_calibrate = false, 112786a93317SHans de Goede }; 112886a93317SHans de Goede 1129ac98caefSChen-Yu Tsai static const struct sunxi_mmc_cfg sun8i_a83t_emmc_cfg = { 1130ac98caefSChen-Yu Tsai .idma_des_size_bits = 16, 1131ac98caefSChen-Yu Tsai .clk_delays = sunxi_mmc_clk_delays, 1132ac98caefSChen-Yu Tsai .can_calibrate = false, 1133ac98caefSChen-Yu Tsai .has_timings_switch = true, 1134ac98caefSChen-Yu Tsai }; 1135ac98caefSChen-Yu Tsai 113686a93317SHans de Goede static const struct sunxi_mmc_cfg sun9i_a80_cfg = { 113786a93317SHans de Goede .idma_des_size_bits = 16, 113886a93317SHans de Goede .clk_delays = sun9i_mmc_clk_delays, 1139e1b8dfd1SIcenowy Zheng .can_calibrate = false, 1140e1b8dfd1SIcenowy Zheng }; 1141e1b8dfd1SIcenowy Zheng 1142e1b8dfd1SIcenowy Zheng static const struct sunxi_mmc_cfg sun50i_a64_cfg = { 1143e1b8dfd1SIcenowy Zheng .idma_des_size_bits = 16, 1144e1b8dfd1SIcenowy Zheng .clk_delays = NULL, 1145e1b8dfd1SIcenowy Zheng .can_calibrate = true, 114616e821e3SMaxime Ripard .mask_data0 = true, 11479a37e53eSMaxime Ripard .needs_new_timings = true, 114886a93317SHans de Goede }; 114986a93317SHans de Goede 11504fb3ce07SMaxime Ripard static const struct sunxi_mmc_cfg sun50i_a64_emmc_cfg = { 11514fb3ce07SMaxime Ripard .idma_des_size_bits = 13, 11524fb3ce07SMaxime Ripard .clk_delays = NULL, 11534fb3ce07SMaxime Ripard .can_calibrate = true, 11544fb3ce07SMaxime Ripard }; 11554fb3ce07SMaxime Ripard 115686a93317SHans de Goede static const struct of_device_id sunxi_mmc_of_match[] = { 115786a93317SHans de Goede { .compatible = "allwinner,sun4i-a10-mmc", .data = &sun4i_a10_cfg }, 115886a93317SHans de Goede { .compatible = "allwinner,sun5i-a13-mmc", .data = &sun5i_a13_cfg }, 1159b465646eSHans de Goede { .compatible = "allwinner,sun7i-a20-mmc", .data = &sun7i_a20_cfg }, 1160ac98caefSChen-Yu Tsai { .compatible = "allwinner,sun8i-a83t-emmc", .data = &sun8i_a83t_emmc_cfg }, 116186a93317SHans de Goede { .compatible = "allwinner,sun9i-a80-mmc", .data = &sun9i_a80_cfg }, 1162e1b8dfd1SIcenowy Zheng { .compatible = "allwinner,sun50i-a64-mmc", .data = &sun50i_a64_cfg }, 11634fb3ce07SMaxime Ripard { .compatible = "allwinner,sun50i-a64-emmc", .data = &sun50i_a64_emmc_cfg }, 116486a93317SHans de Goede { /* sentinel */ } 116586a93317SHans de Goede }; 116686a93317SHans de Goede MODULE_DEVICE_TABLE(of, sunxi_mmc_of_match); 116786a93317SHans de Goede 11683cbcb160SDavid Lanzendörfer static int sunxi_mmc_resource_request(struct sunxi_mmc_host *host, 11693cbcb160SDavid Lanzendörfer struct platform_device *pdev) 11703cbcb160SDavid Lanzendörfer { 11713cbcb160SDavid Lanzendörfer int ret; 11723cbcb160SDavid Lanzendörfer 117386a93317SHans de Goede host->cfg = of_device_get_match_data(&pdev->dev); 117486a93317SHans de Goede if (!host->cfg) 117586a93317SHans de Goede return -EINVAL; 117651424b28SHans de Goede 11773cbcb160SDavid Lanzendörfer ret = mmc_regulator_get_supply(host->mmc); 1178aaab3c46SWolfram Sang if (ret) 11793cbcb160SDavid Lanzendörfer return ret; 11803cbcb160SDavid Lanzendörfer 11813cbcb160SDavid Lanzendörfer host->reg_base = devm_ioremap_resource(&pdev->dev, 11823cbcb160SDavid Lanzendörfer platform_get_resource(pdev, IORESOURCE_MEM, 0)); 11833cbcb160SDavid Lanzendörfer if (IS_ERR(host->reg_base)) 11843cbcb160SDavid Lanzendörfer return PTR_ERR(host->reg_base); 11853cbcb160SDavid Lanzendörfer 11863cbcb160SDavid Lanzendörfer host->clk_ahb = devm_clk_get(&pdev->dev, "ahb"); 11873cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_ahb)) { 11883cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get ahb clock\n"); 11893cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_ahb); 11903cbcb160SDavid Lanzendörfer } 11913cbcb160SDavid Lanzendörfer 11923cbcb160SDavid Lanzendörfer host->clk_mmc = devm_clk_get(&pdev->dev, "mmc"); 11933cbcb160SDavid Lanzendörfer if (IS_ERR(host->clk_mmc)) { 11943cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Could not get mmc clock\n"); 11953cbcb160SDavid Lanzendörfer return PTR_ERR(host->clk_mmc); 11963cbcb160SDavid Lanzendörfer } 11973cbcb160SDavid Lanzendörfer 1198b465646eSHans de Goede if (host->cfg->clk_delays) { 11996c09bb85SMaxime Ripard host->clk_output = devm_clk_get(&pdev->dev, "output"); 12006c09bb85SMaxime Ripard if (IS_ERR(host->clk_output)) { 12016c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get output clock\n"); 12026c09bb85SMaxime Ripard return PTR_ERR(host->clk_output); 12036c09bb85SMaxime Ripard } 12046c09bb85SMaxime Ripard 12056c09bb85SMaxime Ripard host->clk_sample = devm_clk_get(&pdev->dev, "sample"); 12066c09bb85SMaxime Ripard if (IS_ERR(host->clk_sample)) { 12076c09bb85SMaxime Ripard dev_err(&pdev->dev, "Could not get sample clock\n"); 12086c09bb85SMaxime Ripard return PTR_ERR(host->clk_sample); 12096c09bb85SMaxime Ripard } 1210b465646eSHans de Goede } 12116c09bb85SMaxime Ripard 12125e40ddacSPhilipp Zabel host->reset = devm_reset_control_get_optional_exclusive(&pdev->dev, 12135e40ddacSPhilipp Zabel "ahb"); 12149e71c589SChen-Yu Tsai if (PTR_ERR(host->reset) == -EPROBE_DEFER) 12159e71c589SChen-Yu Tsai return PTR_ERR(host->reset); 12163cbcb160SDavid Lanzendörfer 12173cbcb160SDavid Lanzendörfer ret = clk_prepare_enable(host->clk_ahb); 12183cbcb160SDavid Lanzendörfer if (ret) { 12193cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Enable ahb clk err %d\n", ret); 12203cbcb160SDavid Lanzendörfer return ret; 12213cbcb160SDavid Lanzendörfer } 12223cbcb160SDavid Lanzendörfer 12233cbcb160SDavid Lanzendörfer ret = clk_prepare_enable(host->clk_mmc); 12243cbcb160SDavid Lanzendörfer if (ret) { 12253cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Enable mmc clk err %d\n", ret); 12263cbcb160SDavid Lanzendörfer goto error_disable_clk_ahb; 12273cbcb160SDavid Lanzendörfer } 12283cbcb160SDavid Lanzendörfer 12296c09bb85SMaxime Ripard ret = clk_prepare_enable(host->clk_output); 12306c09bb85SMaxime Ripard if (ret) { 12316c09bb85SMaxime Ripard dev_err(&pdev->dev, "Enable output clk err %d\n", ret); 12326c09bb85SMaxime Ripard goto error_disable_clk_mmc; 12336c09bb85SMaxime Ripard } 12346c09bb85SMaxime Ripard 12356c09bb85SMaxime Ripard ret = clk_prepare_enable(host->clk_sample); 12366c09bb85SMaxime Ripard if (ret) { 12376c09bb85SMaxime Ripard dev_err(&pdev->dev, "Enable sample clk err %d\n", ret); 12386c09bb85SMaxime Ripard goto error_disable_clk_output; 12396c09bb85SMaxime Ripard } 12406c09bb85SMaxime Ripard 12413cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) { 1242c34eda69SMaxime Ripard ret = reset_control_reset(host->reset); 12433cbcb160SDavid Lanzendörfer if (ret) { 12443cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "reset err %d\n", ret); 12456c09bb85SMaxime Ripard goto error_disable_clk_sample; 12463cbcb160SDavid Lanzendörfer } 12473cbcb160SDavid Lanzendörfer } 12483cbcb160SDavid Lanzendörfer 12493cbcb160SDavid Lanzendörfer /* 12503cbcb160SDavid Lanzendörfer * Sometimes the controller asserts the irq on boot for some reason, 12513cbcb160SDavid Lanzendörfer * make sure the controller is in a sane state before enabling irqs. 12523cbcb160SDavid Lanzendörfer */ 12533cbcb160SDavid Lanzendörfer ret = sunxi_mmc_reset_host(host); 12543cbcb160SDavid Lanzendörfer if (ret) 12553cbcb160SDavid Lanzendörfer goto error_assert_reset; 12563cbcb160SDavid Lanzendörfer 12573cbcb160SDavid Lanzendörfer host->irq = platform_get_irq(pdev, 0); 12582408a085SArvind Yadav if (host->irq <= 0) { 12592408a085SArvind Yadav ret = -EINVAL; 12602408a085SArvind Yadav goto error_assert_reset; 12612408a085SArvind Yadav } 12622408a085SArvind Yadav 12633cbcb160SDavid Lanzendörfer return devm_request_threaded_irq(&pdev->dev, host->irq, sunxi_mmc_irq, 12643cbcb160SDavid Lanzendörfer sunxi_mmc_handle_manual_stop, 0, "sunxi-mmc", host); 12653cbcb160SDavid Lanzendörfer 12663cbcb160SDavid Lanzendörfer error_assert_reset: 12673cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) 12683cbcb160SDavid Lanzendörfer reset_control_assert(host->reset); 12696c09bb85SMaxime Ripard error_disable_clk_sample: 12706c09bb85SMaxime Ripard clk_disable_unprepare(host->clk_sample); 12716c09bb85SMaxime Ripard error_disable_clk_output: 12726c09bb85SMaxime Ripard clk_disable_unprepare(host->clk_output); 12733cbcb160SDavid Lanzendörfer error_disable_clk_mmc: 12743cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_mmc); 12753cbcb160SDavid Lanzendörfer error_disable_clk_ahb: 12763cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_ahb); 12773cbcb160SDavid Lanzendörfer return ret; 12783cbcb160SDavid Lanzendörfer } 12793cbcb160SDavid Lanzendörfer 12803cbcb160SDavid Lanzendörfer static int sunxi_mmc_probe(struct platform_device *pdev) 12813cbcb160SDavid Lanzendörfer { 12823cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host; 12833cbcb160SDavid Lanzendörfer struct mmc_host *mmc; 12843cbcb160SDavid Lanzendörfer int ret; 12853cbcb160SDavid Lanzendörfer 12863cbcb160SDavid Lanzendörfer mmc = mmc_alloc_host(sizeof(struct sunxi_mmc_host), &pdev->dev); 12873cbcb160SDavid Lanzendörfer if (!mmc) { 12883cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "mmc alloc host failed\n"); 12893cbcb160SDavid Lanzendörfer return -ENOMEM; 12903cbcb160SDavid Lanzendörfer } 12913cbcb160SDavid Lanzendörfer 12923cbcb160SDavid Lanzendörfer host = mmc_priv(mmc); 12933cbcb160SDavid Lanzendörfer host->mmc = mmc; 12943cbcb160SDavid Lanzendörfer spin_lock_init(&host->lock); 12953cbcb160SDavid Lanzendörfer 12963cbcb160SDavid Lanzendörfer ret = sunxi_mmc_resource_request(host, pdev); 12973cbcb160SDavid Lanzendörfer if (ret) 12983cbcb160SDavid Lanzendörfer goto error_free_host; 12993cbcb160SDavid Lanzendörfer 13003cbcb160SDavid Lanzendörfer host->sg_cpu = dma_alloc_coherent(&pdev->dev, PAGE_SIZE, 13013cbcb160SDavid Lanzendörfer &host->sg_dma, GFP_KERNEL); 13023cbcb160SDavid Lanzendörfer if (!host->sg_cpu) { 13033cbcb160SDavid Lanzendörfer dev_err(&pdev->dev, "Failed to allocate DMA descriptor mem\n"); 13043cbcb160SDavid Lanzendörfer ret = -ENOMEM; 13053cbcb160SDavid Lanzendörfer goto error_free_host; 13063cbcb160SDavid Lanzendörfer } 13073cbcb160SDavid Lanzendörfer 1308ff39e7f7SChen-Yu Tsai if (host->cfg->has_timings_switch) { 1309ff39e7f7SChen-Yu Tsai /* 1310ff39e7f7SChen-Yu Tsai * Supports both old and new timing modes. 1311ff39e7f7SChen-Yu Tsai * Try setting the clk to new timing mode. 1312ff39e7f7SChen-Yu Tsai */ 1313ff39e7f7SChen-Yu Tsai sunxi_ccu_set_mmc_timing_mode(host->clk_mmc, true); 1314ff39e7f7SChen-Yu Tsai 1315ff39e7f7SChen-Yu Tsai /* And check the result */ 1316ff39e7f7SChen-Yu Tsai ret = sunxi_ccu_get_mmc_timing_mode(host->clk_mmc); 1317ff39e7f7SChen-Yu Tsai if (ret < 0) { 1318ff39e7f7SChen-Yu Tsai /* 1319ff39e7f7SChen-Yu Tsai * For whatever reason we were not able to get 1320ff39e7f7SChen-Yu Tsai * the current active mode. Default to old mode. 1321ff39e7f7SChen-Yu Tsai */ 1322ff39e7f7SChen-Yu Tsai dev_warn(&pdev->dev, "MMC clk timing mode unknown\n"); 1323ff39e7f7SChen-Yu Tsai host->use_new_timings = false; 1324ff39e7f7SChen-Yu Tsai } else { 1325ff39e7f7SChen-Yu Tsai host->use_new_timings = !!ret; 1326ff39e7f7SChen-Yu Tsai } 1327ff39e7f7SChen-Yu Tsai } else if (host->cfg->needs_new_timings) { 1328ff39e7f7SChen-Yu Tsai /* Supports new timing mode only */ 1329ff39e7f7SChen-Yu Tsai host->use_new_timings = true; 1330ff39e7f7SChen-Yu Tsai } 1331ff39e7f7SChen-Yu Tsai 13323cbcb160SDavid Lanzendörfer mmc->ops = &sunxi_mmc_ops; 13333cbcb160SDavid Lanzendörfer mmc->max_blk_count = 8192; 13343cbcb160SDavid Lanzendörfer mmc->max_blk_size = 4096; 13353cbcb160SDavid Lanzendörfer mmc->max_segs = PAGE_SIZE / sizeof(struct sunxi_idma_des); 133686a93317SHans de Goede mmc->max_seg_size = (1 << host->cfg->idma_des_size_bits); 13373cbcb160SDavid Lanzendörfer mmc->max_req_size = mmc->max_seg_size * mmc->max_segs; 13382dcb305aSChen-Yu Tsai /* 400kHz ~ 52MHz */ 13393cbcb160SDavid Lanzendörfer mmc->f_min = 400000; 13402dcb305aSChen-Yu Tsai mmc->f_max = 52000000; 13413df01a93SChen-Yu Tsai mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_SD_HIGHSPEED | 1342a4101dcbSHans de Goede MMC_CAP_ERASE | MMC_CAP_SDIO_IRQ; 13433cbcb160SDavid Lanzendörfer 1344c903a2aeSChen-Yu Tsai if (host->cfg->clk_delays || host->use_new_timings) 1345b465646eSHans de Goede mmc->caps |= MMC_CAP_1_8V_DDR; 1346b465646eSHans de Goede 13473cbcb160SDavid Lanzendörfer ret = mmc_of_parse(mmc); 13483cbcb160SDavid Lanzendörfer if (ret) 13493cbcb160SDavid Lanzendörfer goto error_free_dma; 13503cbcb160SDavid Lanzendörfer 13513cbcb160SDavid Lanzendörfer ret = mmc_add_host(mmc); 13523cbcb160SDavid Lanzendörfer if (ret) 13533cbcb160SDavid Lanzendörfer goto error_free_dma; 13543cbcb160SDavid Lanzendörfer 13553cbcb160SDavid Lanzendörfer dev_info(&pdev->dev, "base:0x%p irq:%u\n", host->reg_base, host->irq); 13563cbcb160SDavid Lanzendörfer platform_set_drvdata(pdev, mmc); 13573cbcb160SDavid Lanzendörfer return 0; 13583cbcb160SDavid Lanzendörfer 13593cbcb160SDavid Lanzendörfer error_free_dma: 13603cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 13613cbcb160SDavid Lanzendörfer error_free_host: 13623cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 13633cbcb160SDavid Lanzendörfer return ret; 13643cbcb160SDavid Lanzendörfer } 13653cbcb160SDavid Lanzendörfer 13663cbcb160SDavid Lanzendörfer static int sunxi_mmc_remove(struct platform_device *pdev) 13673cbcb160SDavid Lanzendörfer { 13683cbcb160SDavid Lanzendörfer struct mmc_host *mmc = platform_get_drvdata(pdev); 13693cbcb160SDavid Lanzendörfer struct sunxi_mmc_host *host = mmc_priv(mmc); 13703cbcb160SDavid Lanzendörfer 13713cbcb160SDavid Lanzendörfer mmc_remove_host(mmc); 13723cbcb160SDavid Lanzendörfer disable_irq(host->irq); 13733cbcb160SDavid Lanzendörfer sunxi_mmc_reset_host(host); 13743cbcb160SDavid Lanzendörfer 13753cbcb160SDavid Lanzendörfer if (!IS_ERR(host->reset)) 13763cbcb160SDavid Lanzendörfer reset_control_assert(host->reset); 13773cbcb160SDavid Lanzendörfer 13784c5f4bf4SHans de Goede clk_disable_unprepare(host->clk_sample); 13794c5f4bf4SHans de Goede clk_disable_unprepare(host->clk_output); 13803cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_mmc); 13813cbcb160SDavid Lanzendörfer clk_disable_unprepare(host->clk_ahb); 13823cbcb160SDavid Lanzendörfer 13833cbcb160SDavid Lanzendörfer dma_free_coherent(&pdev->dev, PAGE_SIZE, host->sg_cpu, host->sg_dma); 13843cbcb160SDavid Lanzendörfer mmc_free_host(mmc); 13853cbcb160SDavid Lanzendörfer 13863cbcb160SDavid Lanzendörfer return 0; 13873cbcb160SDavid Lanzendörfer } 13883cbcb160SDavid Lanzendörfer 13893cbcb160SDavid Lanzendörfer static struct platform_driver sunxi_mmc_driver = { 13903cbcb160SDavid Lanzendörfer .driver = { 13913cbcb160SDavid Lanzendörfer .name = "sunxi-mmc", 13923cbcb160SDavid Lanzendörfer .of_match_table = of_match_ptr(sunxi_mmc_of_match), 13933cbcb160SDavid Lanzendörfer }, 13943cbcb160SDavid Lanzendörfer .probe = sunxi_mmc_probe, 13953cbcb160SDavid Lanzendörfer .remove = sunxi_mmc_remove, 13963cbcb160SDavid Lanzendörfer }; 13973cbcb160SDavid Lanzendörfer module_platform_driver(sunxi_mmc_driver); 13983cbcb160SDavid Lanzendörfer 13993cbcb160SDavid Lanzendörfer MODULE_DESCRIPTION("Allwinner's SD/MMC Card Controller Driver"); 14003cbcb160SDavid Lanzendörfer MODULE_LICENSE("GPL v2"); 14011907e386SAdam Borowski MODULE_AUTHOR("David Lanzendörfer <david.lanzendoerfer@o2s.ch>"); 14023cbcb160SDavid Lanzendörfer MODULE_ALIAS("platform:sunxi-mmc"); 1403