1 /* 2 * MMCIF eMMC driver. 3 * 4 * Copyright (C) 2010 Renesas Solutions Corp. 5 * Yusuke Goda <yusuke.goda.sx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License. 10 * 11 * 12 * TODO 13 * 1. DMA 14 * 2. Power management 15 * 3. Handle MMC errors better 16 * 17 */ 18 19 /* 20 * The MMCIF driver is now processing MMC requests asynchronously, according 21 * to the Linux MMC API requirement. 22 * 23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24 * data, and optional stop. To achieve asynchronous processing each of these 25 * stages is split into two halves: a top and a bottom half. The top half 26 * initialises the hardware, installs a timeout handler to handle completion 27 * timeouts, and returns. In case of the command stage this immediately returns 28 * control to the caller, leaving all further processing to run asynchronously. 29 * All further request processing is performed by the bottom halves. 30 * 31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32 * thread, a DMA completion callback, if DMA is used, a timeout work, and 33 * request- and stage-specific handler methods. 34 * 35 * Each bottom half run begins with either a hardware interrupt, a DMA callback 36 * invocation, or a timeout work run. In case of an error or a successful 37 * processing completion, the MMC core is informed and the request processing is 38 * finished. In case processing has to continue, i.e., if data has to be read 39 * from or written to the card, or if a stop command has to be sent, the next 40 * top half is called, which performs the necessary hardware handling and 41 * reschedules the timeout work. This returns the driver state machine into the 42 * bottom half waiting state. 43 */ 44 45 #include <linux/bitops.h> 46 #include <linux/clk.h> 47 #include <linux/completion.h> 48 #include <linux/delay.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/dmaengine.h> 51 #include <linux/mmc/card.h> 52 #include <linux/mmc/core.h> 53 #include <linux/mmc/host.h> 54 #include <linux/mmc/mmc.h> 55 #include <linux/mmc/sdio.h> 56 #include <linux/mmc/sh_mmcif.h> 57 #include <linux/pagemap.h> 58 #include <linux/platform_device.h> 59 #include <linux/pm_qos.h> 60 #include <linux/pm_runtime.h> 61 #include <linux/spinlock.h> 62 #include <linux/module.h> 63 64 #define DRIVER_NAME "sh_mmcif" 65 #define DRIVER_VERSION "2010-04-28" 66 67 /* CE_CMD_SET */ 68 #define CMD_MASK 0x3f000000 69 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 70 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 71 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 72 #define CMD_SET_RBSY (1 << 21) /* R1b */ 73 #define CMD_SET_CCSEN (1 << 20) 74 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 75 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 76 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 77 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 78 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 79 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 80 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 81 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 82 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 83 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 84 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 85 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 86 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 87 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 88 #define CMD_SET_CCSH (1 << 5) 89 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 90 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 91 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 92 93 /* CE_CMD_CTRL */ 94 #define CMD_CTRL_BREAK (1 << 0) 95 96 /* CE_BLOCK_SET */ 97 #define BLOCK_SIZE_MASK 0x0000ffff 98 99 /* CE_INT */ 100 #define INT_CCSDE (1 << 29) 101 #define INT_CMD12DRE (1 << 26) 102 #define INT_CMD12RBE (1 << 25) 103 #define INT_CMD12CRE (1 << 24) 104 #define INT_DTRANE (1 << 23) 105 #define INT_BUFRE (1 << 22) 106 #define INT_BUFWEN (1 << 21) 107 #define INT_BUFREN (1 << 20) 108 #define INT_CCSRCV (1 << 19) 109 #define INT_RBSYE (1 << 17) 110 #define INT_CRSPE (1 << 16) 111 #define INT_CMDVIO (1 << 15) 112 #define INT_BUFVIO (1 << 14) 113 #define INT_WDATERR (1 << 11) 114 #define INT_RDATERR (1 << 10) 115 #define INT_RIDXERR (1 << 9) 116 #define INT_RSPERR (1 << 8) 117 #define INT_CCSTO (1 << 5) 118 #define INT_CRCSTO (1 << 4) 119 #define INT_WDATTO (1 << 3) 120 #define INT_RDATTO (1 << 2) 121 #define INT_RBSYTO (1 << 1) 122 #define INT_RSPTO (1 << 0) 123 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 124 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 125 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 126 INT_RDATTO | INT_RBSYTO | INT_RSPTO) 127 128 /* CE_INT_MASK */ 129 #define MASK_ALL 0x00000000 130 #define MASK_MCCSDE (1 << 29) 131 #define MASK_MCMD12DRE (1 << 26) 132 #define MASK_MCMD12RBE (1 << 25) 133 #define MASK_MCMD12CRE (1 << 24) 134 #define MASK_MDTRANE (1 << 23) 135 #define MASK_MBUFRE (1 << 22) 136 #define MASK_MBUFWEN (1 << 21) 137 #define MASK_MBUFREN (1 << 20) 138 #define MASK_MCCSRCV (1 << 19) 139 #define MASK_MRBSYE (1 << 17) 140 #define MASK_MCRSPE (1 << 16) 141 #define MASK_MCMDVIO (1 << 15) 142 #define MASK_MBUFVIO (1 << 14) 143 #define MASK_MWDATERR (1 << 11) 144 #define MASK_MRDATERR (1 << 10) 145 #define MASK_MRIDXERR (1 << 9) 146 #define MASK_MRSPERR (1 << 8) 147 #define MASK_MCCSTO (1 << 5) 148 #define MASK_MCRCSTO (1 << 4) 149 #define MASK_MWDATTO (1 << 3) 150 #define MASK_MRDATTO (1 << 2) 151 #define MASK_MRBSYTO (1 << 1) 152 #define MASK_MRSPTO (1 << 0) 153 154 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 155 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 156 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ 157 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 158 159 /* CE_HOST_STS1 */ 160 #define STS1_CMDSEQ (1 << 31) 161 162 /* CE_HOST_STS2 */ 163 #define STS2_CRCSTE (1 << 31) 164 #define STS2_CRC16E (1 << 30) 165 #define STS2_AC12CRCE (1 << 29) 166 #define STS2_RSPCRC7E (1 << 28) 167 #define STS2_CRCSTEBE (1 << 27) 168 #define STS2_RDATEBE (1 << 26) 169 #define STS2_AC12REBE (1 << 25) 170 #define STS2_RSPEBE (1 << 24) 171 #define STS2_AC12IDXE (1 << 23) 172 #define STS2_RSPIDXE (1 << 22) 173 #define STS2_CCSTO (1 << 15) 174 #define STS2_RDATTO (1 << 14) 175 #define STS2_DATBSYTO (1 << 13) 176 #define STS2_CRCSTTO (1 << 12) 177 #define STS2_AC12BSYTO (1 << 11) 178 #define STS2_RSPBSYTO (1 << 10) 179 #define STS2_AC12RSPTO (1 << 9) 180 #define STS2_RSPTO (1 << 8) 181 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 182 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 183 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 184 STS2_DATBSYTO | STS2_CRCSTTO | \ 185 STS2_AC12BSYTO | STS2_RSPBSYTO | \ 186 STS2_AC12RSPTO | STS2_RSPTO) 187 188 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 189 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 190 #define CLKDEV_INIT 400000 /* 400 KHz */ 191 192 enum mmcif_state { 193 STATE_IDLE, 194 STATE_REQUEST, 195 STATE_IOS, 196 }; 197 198 enum mmcif_wait_for { 199 MMCIF_WAIT_FOR_REQUEST, 200 MMCIF_WAIT_FOR_CMD, 201 MMCIF_WAIT_FOR_MREAD, 202 MMCIF_WAIT_FOR_MWRITE, 203 MMCIF_WAIT_FOR_READ, 204 MMCIF_WAIT_FOR_WRITE, 205 MMCIF_WAIT_FOR_READ_END, 206 MMCIF_WAIT_FOR_WRITE_END, 207 MMCIF_WAIT_FOR_STOP, 208 }; 209 210 struct sh_mmcif_host { 211 struct mmc_host *mmc; 212 struct mmc_request *mrq; 213 struct platform_device *pd; 214 struct sh_dmae_slave dma_slave_tx; 215 struct sh_dmae_slave dma_slave_rx; 216 struct clk *hclk; 217 unsigned int clk; 218 int bus_width; 219 bool sd_error; 220 bool dying; 221 long timeout; 222 void __iomem *addr; 223 u32 *pio_ptr; 224 spinlock_t lock; /* protect sh_mmcif_host::state */ 225 enum mmcif_state state; 226 enum mmcif_wait_for wait_for; 227 struct delayed_work timeout_work; 228 size_t blocksize; 229 int sg_idx; 230 int sg_blkidx; 231 bool power; 232 bool card_present; 233 234 /* DMA support */ 235 struct dma_chan *chan_rx; 236 struct dma_chan *chan_tx; 237 struct completion dma_complete; 238 bool dma_active; 239 }; 240 241 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 242 unsigned int reg, u32 val) 243 { 244 writel(val | readl(host->addr + reg), host->addr + reg); 245 } 246 247 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 248 unsigned int reg, u32 val) 249 { 250 writel(~val & readl(host->addr + reg), host->addr + reg); 251 } 252 253 static void mmcif_dma_complete(void *arg) 254 { 255 struct sh_mmcif_host *host = arg; 256 struct mmc_data *data = host->mrq->data; 257 258 dev_dbg(&host->pd->dev, "Command completed\n"); 259 260 if (WARN(!data, "%s: NULL data in DMA completion!\n", 261 dev_name(&host->pd->dev))) 262 return; 263 264 if (data->flags & MMC_DATA_READ) 265 dma_unmap_sg(host->chan_rx->device->dev, 266 data->sg, data->sg_len, 267 DMA_FROM_DEVICE); 268 else 269 dma_unmap_sg(host->chan_tx->device->dev, 270 data->sg, data->sg_len, 271 DMA_TO_DEVICE); 272 273 complete(&host->dma_complete); 274 } 275 276 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 277 { 278 struct mmc_data *data = host->mrq->data; 279 struct scatterlist *sg = data->sg; 280 struct dma_async_tx_descriptor *desc = NULL; 281 struct dma_chan *chan = host->chan_rx; 282 dma_cookie_t cookie = -EINVAL; 283 int ret; 284 285 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 286 DMA_FROM_DEVICE); 287 if (ret > 0) { 288 host->dma_active = true; 289 desc = dmaengine_prep_slave_sg(chan, sg, ret, 290 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 291 } 292 293 if (desc) { 294 desc->callback = mmcif_dma_complete; 295 desc->callback_param = host; 296 cookie = dmaengine_submit(desc); 297 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 298 dma_async_issue_pending(chan); 299 } 300 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 301 __func__, data->sg_len, ret, cookie); 302 303 if (!desc) { 304 /* DMA failed, fall back to PIO */ 305 if (ret >= 0) 306 ret = -EIO; 307 host->chan_rx = NULL; 308 host->dma_active = false; 309 dma_release_channel(chan); 310 /* Free the Tx channel too */ 311 chan = host->chan_tx; 312 if (chan) { 313 host->chan_tx = NULL; 314 dma_release_channel(chan); 315 } 316 dev_warn(&host->pd->dev, 317 "DMA failed: %d, falling back to PIO\n", ret); 318 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 319 } 320 321 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 322 desc, cookie, data->sg_len); 323 } 324 325 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 326 { 327 struct mmc_data *data = host->mrq->data; 328 struct scatterlist *sg = data->sg; 329 struct dma_async_tx_descriptor *desc = NULL; 330 struct dma_chan *chan = host->chan_tx; 331 dma_cookie_t cookie = -EINVAL; 332 int ret; 333 334 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 335 DMA_TO_DEVICE); 336 if (ret > 0) { 337 host->dma_active = true; 338 desc = dmaengine_prep_slave_sg(chan, sg, ret, 339 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 340 } 341 342 if (desc) { 343 desc->callback = mmcif_dma_complete; 344 desc->callback_param = host; 345 cookie = dmaengine_submit(desc); 346 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 347 dma_async_issue_pending(chan); 348 } 349 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 350 __func__, data->sg_len, ret, cookie); 351 352 if (!desc) { 353 /* DMA failed, fall back to PIO */ 354 if (ret >= 0) 355 ret = -EIO; 356 host->chan_tx = NULL; 357 host->dma_active = false; 358 dma_release_channel(chan); 359 /* Free the Rx channel too */ 360 chan = host->chan_rx; 361 if (chan) { 362 host->chan_rx = NULL; 363 dma_release_channel(chan); 364 } 365 dev_warn(&host->pd->dev, 366 "DMA failed: %d, falling back to PIO\n", ret); 367 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 368 } 369 370 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 371 desc, cookie); 372 } 373 374 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg) 375 { 376 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); 377 chan->private = arg; 378 return true; 379 } 380 381 static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 382 struct sh_mmcif_plat_data *pdata) 383 { 384 struct sh_dmae_slave *tx, *rx; 385 host->dma_active = false; 386 387 /* We can only either use DMA for both Tx and Rx or not use it at all */ 388 if (pdata->dma) { 389 dev_warn(&host->pd->dev, 390 "Update your platform to use embedded DMA slave IDs\n"); 391 tx = &pdata->dma->chan_priv_tx; 392 rx = &pdata->dma->chan_priv_rx; 393 } else { 394 tx = &host->dma_slave_tx; 395 tx->slave_id = pdata->slave_id_tx; 396 rx = &host->dma_slave_rx; 397 rx->slave_id = pdata->slave_id_rx; 398 } 399 if (tx->slave_id > 0 && rx->slave_id > 0) { 400 dma_cap_mask_t mask; 401 402 dma_cap_zero(mask); 403 dma_cap_set(DMA_SLAVE, mask); 404 405 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx); 406 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 407 host->chan_tx); 408 409 if (!host->chan_tx) 410 return; 411 412 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx); 413 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 414 host->chan_rx); 415 416 if (!host->chan_rx) { 417 dma_release_channel(host->chan_tx); 418 host->chan_tx = NULL; 419 return; 420 } 421 422 init_completion(&host->dma_complete); 423 } 424 } 425 426 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 427 { 428 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 429 /* Descriptors are freed automatically */ 430 if (host->chan_tx) { 431 struct dma_chan *chan = host->chan_tx; 432 host->chan_tx = NULL; 433 dma_release_channel(chan); 434 } 435 if (host->chan_rx) { 436 struct dma_chan *chan = host->chan_rx; 437 host->chan_rx = NULL; 438 dma_release_channel(chan); 439 } 440 441 host->dma_active = false; 442 } 443 444 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 445 { 446 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 447 448 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 449 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 450 451 if (!clk) 452 return; 453 if (p->sup_pclk && clk == host->clk) 454 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 455 else 456 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 457 ((fls(DIV_ROUND_UP(host->clk, 458 clk) - 1) - 1) << 16)); 459 460 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 461 } 462 463 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 464 { 465 u32 tmp; 466 467 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 468 469 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 470 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 471 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 472 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 473 /* byte swap on */ 474 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 475 } 476 477 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 478 { 479 u32 state1, state2; 480 int ret, timeout; 481 482 host->sd_error = false; 483 484 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 485 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 486 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 487 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 488 489 if (state1 & STS1_CMDSEQ) { 490 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 491 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 492 for (timeout = 10000000; timeout; timeout--) { 493 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 494 & STS1_CMDSEQ)) 495 break; 496 mdelay(1); 497 } 498 if (!timeout) { 499 dev_err(&host->pd->dev, 500 "Forced end of command sequence timeout err\n"); 501 return -EIO; 502 } 503 sh_mmcif_sync_reset(host); 504 dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 505 return -EIO; 506 } 507 508 if (state2 & STS2_CRC_ERR) { 509 dev_dbg(&host->pd->dev, ": CRC error\n"); 510 ret = -EIO; 511 } else if (state2 & STS2_TIMEOUT_ERR) { 512 dev_dbg(&host->pd->dev, ": Timeout\n"); 513 ret = -ETIMEDOUT; 514 } else { 515 dev_dbg(&host->pd->dev, ": End/Index error\n"); 516 ret = -EIO; 517 } 518 return ret; 519 } 520 521 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 522 { 523 struct mmc_data *data = host->mrq->data; 524 525 host->sg_blkidx += host->blocksize; 526 527 /* data->sg->length must be a multiple of host->blocksize? */ 528 BUG_ON(host->sg_blkidx > data->sg->length); 529 530 if (host->sg_blkidx == data->sg->length) { 531 host->sg_blkidx = 0; 532 if (++host->sg_idx < data->sg_len) 533 host->pio_ptr = sg_virt(++data->sg); 534 } else { 535 host->pio_ptr = p; 536 } 537 538 if (host->sg_idx == data->sg_len) 539 return false; 540 541 return true; 542 } 543 544 static void sh_mmcif_single_read(struct sh_mmcif_host *host, 545 struct mmc_request *mrq) 546 { 547 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 548 BLOCK_SIZE_MASK) + 3; 549 550 host->wait_for = MMCIF_WAIT_FOR_READ; 551 schedule_delayed_work(&host->timeout_work, host->timeout); 552 553 /* buf read enable */ 554 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 555 } 556 557 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 558 { 559 struct mmc_data *data = host->mrq->data; 560 u32 *p = sg_virt(data->sg); 561 int i; 562 563 if (host->sd_error) { 564 data->error = sh_mmcif_error_manage(host); 565 return false; 566 } 567 568 for (i = 0; i < host->blocksize / 4; i++) 569 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 570 571 /* buffer read end */ 572 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 573 host->wait_for = MMCIF_WAIT_FOR_READ_END; 574 575 return true; 576 } 577 578 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 579 struct mmc_request *mrq) 580 { 581 struct mmc_data *data = mrq->data; 582 583 if (!data->sg_len || !data->sg->length) 584 return; 585 586 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 587 BLOCK_SIZE_MASK; 588 589 host->wait_for = MMCIF_WAIT_FOR_MREAD; 590 host->sg_idx = 0; 591 host->sg_blkidx = 0; 592 host->pio_ptr = sg_virt(data->sg); 593 schedule_delayed_work(&host->timeout_work, host->timeout); 594 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 595 } 596 597 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 598 { 599 struct mmc_data *data = host->mrq->data; 600 u32 *p = host->pio_ptr; 601 int i; 602 603 if (host->sd_error) { 604 data->error = sh_mmcif_error_manage(host); 605 return false; 606 } 607 608 BUG_ON(!data->sg->length); 609 610 for (i = 0; i < host->blocksize / 4; i++) 611 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 612 613 if (!sh_mmcif_next_block(host, p)) 614 return false; 615 616 schedule_delayed_work(&host->timeout_work, host->timeout); 617 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 618 619 return true; 620 } 621 622 static void sh_mmcif_single_write(struct sh_mmcif_host *host, 623 struct mmc_request *mrq) 624 { 625 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 626 BLOCK_SIZE_MASK) + 3; 627 628 host->wait_for = MMCIF_WAIT_FOR_WRITE; 629 schedule_delayed_work(&host->timeout_work, host->timeout); 630 631 /* buf write enable */ 632 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 633 } 634 635 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 636 { 637 struct mmc_data *data = host->mrq->data; 638 u32 *p = sg_virt(data->sg); 639 int i; 640 641 if (host->sd_error) { 642 data->error = sh_mmcif_error_manage(host); 643 return false; 644 } 645 646 for (i = 0; i < host->blocksize / 4; i++) 647 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 648 649 /* buffer write end */ 650 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 651 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 652 653 return true; 654 } 655 656 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 657 struct mmc_request *mrq) 658 { 659 struct mmc_data *data = mrq->data; 660 661 if (!data->sg_len || !data->sg->length) 662 return; 663 664 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 665 BLOCK_SIZE_MASK; 666 667 host->wait_for = MMCIF_WAIT_FOR_MWRITE; 668 host->sg_idx = 0; 669 host->sg_blkidx = 0; 670 host->pio_ptr = sg_virt(data->sg); 671 schedule_delayed_work(&host->timeout_work, host->timeout); 672 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 673 } 674 675 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 676 { 677 struct mmc_data *data = host->mrq->data; 678 u32 *p = host->pio_ptr; 679 int i; 680 681 if (host->sd_error) { 682 data->error = sh_mmcif_error_manage(host); 683 return false; 684 } 685 686 BUG_ON(!data->sg->length); 687 688 for (i = 0; i < host->blocksize / 4; i++) 689 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 690 691 if (!sh_mmcif_next_block(host, p)) 692 return false; 693 694 schedule_delayed_work(&host->timeout_work, host->timeout); 695 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 696 697 return true; 698 } 699 700 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 701 struct mmc_command *cmd) 702 { 703 if (cmd->flags & MMC_RSP_136) { 704 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 705 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 706 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 707 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 708 } else 709 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 710 } 711 712 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 713 struct mmc_command *cmd) 714 { 715 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 716 } 717 718 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 719 struct mmc_request *mrq) 720 { 721 struct mmc_data *data = mrq->data; 722 struct mmc_command *cmd = mrq->cmd; 723 u32 opc = cmd->opcode; 724 u32 tmp = 0; 725 726 /* Response Type check */ 727 switch (mmc_resp_type(cmd)) { 728 case MMC_RSP_NONE: 729 tmp |= CMD_SET_RTYP_NO; 730 break; 731 case MMC_RSP_R1: 732 case MMC_RSP_R1B: 733 case MMC_RSP_R3: 734 tmp |= CMD_SET_RTYP_6B; 735 break; 736 case MMC_RSP_R2: 737 tmp |= CMD_SET_RTYP_17B; 738 break; 739 default: 740 dev_err(&host->pd->dev, "Unsupported response type.\n"); 741 break; 742 } 743 switch (opc) { 744 /* RBSY */ 745 case MMC_SWITCH: 746 case MMC_STOP_TRANSMISSION: 747 case MMC_SET_WRITE_PROT: 748 case MMC_CLR_WRITE_PROT: 749 case MMC_ERASE: 750 tmp |= CMD_SET_RBSY; 751 break; 752 } 753 /* WDAT / DATW */ 754 if (data) { 755 tmp |= CMD_SET_WDAT; 756 switch (host->bus_width) { 757 case MMC_BUS_WIDTH_1: 758 tmp |= CMD_SET_DATW_1; 759 break; 760 case MMC_BUS_WIDTH_4: 761 tmp |= CMD_SET_DATW_4; 762 break; 763 case MMC_BUS_WIDTH_8: 764 tmp |= CMD_SET_DATW_8; 765 break; 766 default: 767 dev_err(&host->pd->dev, "Unsupported bus width.\n"); 768 break; 769 } 770 } 771 /* DWEN */ 772 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 773 tmp |= CMD_SET_DWEN; 774 /* CMLTE/CMD12EN */ 775 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 776 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 777 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 778 data->blocks << 16); 779 } 780 /* RIDXC[1:0] check bits */ 781 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 782 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 783 tmp |= CMD_SET_RIDXC_BITS; 784 /* RCRC7C[1:0] check bits */ 785 if (opc == MMC_SEND_OP_COND) 786 tmp |= CMD_SET_CRC7C_BITS; 787 /* RCRC7C[1:0] internal CRC7 */ 788 if (opc == MMC_ALL_SEND_CID || 789 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 790 tmp |= CMD_SET_CRC7C_INTERNAL; 791 792 return (opc << 24) | tmp; 793 } 794 795 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 796 struct mmc_request *mrq, u32 opc) 797 { 798 switch (opc) { 799 case MMC_READ_MULTIPLE_BLOCK: 800 sh_mmcif_multi_read(host, mrq); 801 return 0; 802 case MMC_WRITE_MULTIPLE_BLOCK: 803 sh_mmcif_multi_write(host, mrq); 804 return 0; 805 case MMC_WRITE_BLOCK: 806 sh_mmcif_single_write(host, mrq); 807 return 0; 808 case MMC_READ_SINGLE_BLOCK: 809 case MMC_SEND_EXT_CSD: 810 sh_mmcif_single_read(host, mrq); 811 return 0; 812 default: 813 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 814 return -EINVAL; 815 } 816 } 817 818 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 819 struct mmc_request *mrq) 820 { 821 struct mmc_command *cmd = mrq->cmd; 822 u32 opc = cmd->opcode; 823 u32 mask; 824 825 switch (opc) { 826 /* response busy check */ 827 case MMC_SWITCH: 828 case MMC_STOP_TRANSMISSION: 829 case MMC_SET_WRITE_PROT: 830 case MMC_CLR_WRITE_PROT: 831 case MMC_ERASE: 832 mask = MASK_START_CMD | MASK_MRBSYE; 833 break; 834 default: 835 mask = MASK_START_CMD | MASK_MCRSPE; 836 break; 837 } 838 839 if (mrq->data) { 840 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 841 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 842 mrq->data->blksz); 843 } 844 opc = sh_mmcif_set_cmd(host, mrq); 845 846 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 847 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 848 /* set arg */ 849 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 850 /* set cmd */ 851 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 852 853 host->wait_for = MMCIF_WAIT_FOR_CMD; 854 schedule_delayed_work(&host->timeout_work, host->timeout); 855 } 856 857 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 858 struct mmc_request *mrq) 859 { 860 switch (mrq->cmd->opcode) { 861 case MMC_READ_MULTIPLE_BLOCK: 862 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 863 break; 864 case MMC_WRITE_MULTIPLE_BLOCK: 865 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 866 break; 867 default: 868 dev_err(&host->pd->dev, "unsupported stop cmd\n"); 869 mrq->stop->error = sh_mmcif_error_manage(host); 870 return; 871 } 872 873 host->wait_for = MMCIF_WAIT_FOR_STOP; 874 schedule_delayed_work(&host->timeout_work, host->timeout); 875 } 876 877 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 878 { 879 struct sh_mmcif_host *host = mmc_priv(mmc); 880 unsigned long flags; 881 882 spin_lock_irqsave(&host->lock, flags); 883 if (host->state != STATE_IDLE) { 884 spin_unlock_irqrestore(&host->lock, flags); 885 mrq->cmd->error = -EAGAIN; 886 mmc_request_done(mmc, mrq); 887 return; 888 } 889 890 host->state = STATE_REQUEST; 891 spin_unlock_irqrestore(&host->lock, flags); 892 893 switch (mrq->cmd->opcode) { 894 /* MMCIF does not support SD/SDIO command */ 895 case SD_IO_SEND_OP_COND: 896 case MMC_APP_CMD: 897 host->state = STATE_IDLE; 898 mrq->cmd->error = -ETIMEDOUT; 899 mmc_request_done(mmc, mrq); 900 return; 901 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 902 if (!mrq->data) { 903 /* send_if_cond cmd (not support) */ 904 host->state = STATE_IDLE; 905 mrq->cmd->error = -ETIMEDOUT; 906 mmc_request_done(mmc, mrq); 907 return; 908 } 909 break; 910 default: 911 break; 912 } 913 914 host->mrq = mrq; 915 916 sh_mmcif_start_cmd(host, mrq); 917 } 918 919 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 920 { 921 struct sh_mmcif_host *host = mmc_priv(mmc); 922 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 923 unsigned long flags; 924 925 spin_lock_irqsave(&host->lock, flags); 926 if (host->state != STATE_IDLE) { 927 spin_unlock_irqrestore(&host->lock, flags); 928 return; 929 } 930 931 host->state = STATE_IOS; 932 spin_unlock_irqrestore(&host->lock, flags); 933 934 if (ios->power_mode == MMC_POWER_UP) { 935 if (!host->card_present) { 936 /* See if we also get DMA */ 937 sh_mmcif_request_dma(host, host->pd->dev.platform_data); 938 host->card_present = true; 939 } 940 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 941 /* clock stop */ 942 sh_mmcif_clock_control(host, 0); 943 if (ios->power_mode == MMC_POWER_OFF) { 944 if (host->card_present) { 945 sh_mmcif_release_dma(host); 946 host->card_present = false; 947 } 948 } 949 if (host->power) { 950 pm_runtime_put(&host->pd->dev); 951 host->power = false; 952 if (p->down_pwr && ios->power_mode == MMC_POWER_OFF) 953 p->down_pwr(host->pd); 954 } 955 host->state = STATE_IDLE; 956 return; 957 } 958 959 if (ios->clock) { 960 if (!host->power) { 961 if (p->set_pwr) 962 p->set_pwr(host->pd, ios->power_mode); 963 pm_runtime_get_sync(&host->pd->dev); 964 host->power = true; 965 sh_mmcif_sync_reset(host); 966 } 967 sh_mmcif_clock_control(host, ios->clock); 968 } 969 970 host->bus_width = ios->bus_width; 971 host->state = STATE_IDLE; 972 } 973 974 static int sh_mmcif_get_cd(struct mmc_host *mmc) 975 { 976 struct sh_mmcif_host *host = mmc_priv(mmc); 977 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 978 979 if (!p->get_cd) 980 return -ENOSYS; 981 else 982 return p->get_cd(host->pd); 983 } 984 985 static struct mmc_host_ops sh_mmcif_ops = { 986 .request = sh_mmcif_request, 987 .set_ios = sh_mmcif_set_ios, 988 .get_cd = sh_mmcif_get_cd, 989 }; 990 991 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 992 { 993 struct mmc_command *cmd = host->mrq->cmd; 994 struct mmc_data *data = host->mrq->data; 995 long time; 996 997 if (host->sd_error) { 998 switch (cmd->opcode) { 999 case MMC_ALL_SEND_CID: 1000 case MMC_SELECT_CARD: 1001 case MMC_APP_CMD: 1002 cmd->error = -ETIMEDOUT; 1003 host->sd_error = false; 1004 break; 1005 default: 1006 cmd->error = sh_mmcif_error_manage(host); 1007 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n", 1008 cmd->opcode, cmd->error); 1009 break; 1010 } 1011 return false; 1012 } 1013 if (!(cmd->flags & MMC_RSP_PRESENT)) { 1014 cmd->error = 0; 1015 return false; 1016 } 1017 1018 sh_mmcif_get_response(host, cmd); 1019 1020 if (!data) 1021 return false; 1022 1023 if (data->flags & MMC_DATA_READ) { 1024 if (host->chan_rx) 1025 sh_mmcif_start_dma_rx(host); 1026 } else { 1027 if (host->chan_tx) 1028 sh_mmcif_start_dma_tx(host); 1029 } 1030 1031 if (!host->dma_active) { 1032 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 1033 if (!data->error) 1034 return true; 1035 return false; 1036 } 1037 1038 /* Running in the IRQ thread, can sleep */ 1039 time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1040 host->timeout); 1041 if (host->sd_error) { 1042 dev_err(host->mmc->parent, 1043 "Error IRQ while waiting for DMA completion!\n"); 1044 /* Woken up by an error IRQ: abort DMA */ 1045 if (data->flags & MMC_DATA_READ) 1046 dmaengine_terminate_all(host->chan_rx); 1047 else 1048 dmaengine_terminate_all(host->chan_tx); 1049 data->error = sh_mmcif_error_manage(host); 1050 } else if (!time) { 1051 data->error = -ETIMEDOUT; 1052 } else if (time < 0) { 1053 data->error = time; 1054 } 1055 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1056 BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1057 host->dma_active = false; 1058 1059 if (data->error) 1060 data->bytes_xfered = 0; 1061 1062 return false; 1063 } 1064 1065 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1066 { 1067 struct sh_mmcif_host *host = dev_id; 1068 struct mmc_request *mrq = host->mrq; 1069 struct mmc_data *data = mrq->data; 1070 1071 cancel_delayed_work_sync(&host->timeout_work); 1072 1073 /* 1074 * All handlers return true, if processing continues, and false, if the 1075 * request has to be completed - successfully or not 1076 */ 1077 switch (host->wait_for) { 1078 case MMCIF_WAIT_FOR_REQUEST: 1079 /* We're too late, the timeout has already kicked in */ 1080 return IRQ_HANDLED; 1081 case MMCIF_WAIT_FOR_CMD: 1082 if (sh_mmcif_end_cmd(host)) 1083 /* Wait for data */ 1084 return IRQ_HANDLED; 1085 break; 1086 case MMCIF_WAIT_FOR_MREAD: 1087 if (sh_mmcif_mread_block(host)) 1088 /* Wait for more data */ 1089 return IRQ_HANDLED; 1090 break; 1091 case MMCIF_WAIT_FOR_READ: 1092 if (sh_mmcif_read_block(host)) 1093 /* Wait for data end */ 1094 return IRQ_HANDLED; 1095 break; 1096 case MMCIF_WAIT_FOR_MWRITE: 1097 if (sh_mmcif_mwrite_block(host)) 1098 /* Wait data to write */ 1099 return IRQ_HANDLED; 1100 break; 1101 case MMCIF_WAIT_FOR_WRITE: 1102 if (sh_mmcif_write_block(host)) 1103 /* Wait for data end */ 1104 return IRQ_HANDLED; 1105 break; 1106 case MMCIF_WAIT_FOR_STOP: 1107 if (host->sd_error) { 1108 mrq->stop->error = sh_mmcif_error_manage(host); 1109 break; 1110 } 1111 sh_mmcif_get_cmd12response(host, mrq->stop); 1112 mrq->stop->error = 0; 1113 break; 1114 case MMCIF_WAIT_FOR_READ_END: 1115 case MMCIF_WAIT_FOR_WRITE_END: 1116 if (host->sd_error) 1117 data->error = sh_mmcif_error_manage(host); 1118 break; 1119 default: 1120 BUG(); 1121 } 1122 1123 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 1124 if (!mrq->cmd->error && data && !data->error) 1125 data->bytes_xfered = 1126 data->blocks * data->blksz; 1127 1128 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1129 sh_mmcif_stop_cmd(host, mrq); 1130 if (!mrq->stop->error) 1131 return IRQ_HANDLED; 1132 } 1133 } 1134 1135 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1136 host->state = STATE_IDLE; 1137 host->mrq = NULL; 1138 mmc_request_done(host->mmc, mrq); 1139 1140 return IRQ_HANDLED; 1141 } 1142 1143 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1144 { 1145 struct sh_mmcif_host *host = dev_id; 1146 u32 state; 1147 int err = 0; 1148 1149 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1150 1151 if (state & INT_ERR_STS) { 1152 /* error interrupts - process first */ 1153 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1154 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1155 err = 1; 1156 } else if (state & INT_RBSYE) { 1157 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1158 ~(INT_RBSYE | INT_CRSPE)); 1159 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 1160 } else if (state & INT_CRSPE) { 1161 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 1162 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 1163 } else if (state & INT_BUFREN) { 1164 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 1165 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 1166 } else if (state & INT_BUFWEN) { 1167 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 1168 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 1169 } else if (state & INT_CMD12DRE) { 1170 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1171 ~(INT_CMD12DRE | INT_CMD12RBE | 1172 INT_CMD12CRE | INT_BUFRE)); 1173 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 1174 } else if (state & INT_BUFRE) { 1175 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 1176 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 1177 } else if (state & INT_DTRANE) { 1178 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); 1179 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 1180 } else if (state & INT_CMD12RBE) { 1181 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1182 ~(INT_CMD12RBE | INT_CMD12CRE)); 1183 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 1184 } else { 1185 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 1186 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1187 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1188 err = 1; 1189 } 1190 if (err) { 1191 host->sd_error = true; 1192 dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 1193 } 1194 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1195 if (!host->dma_active) 1196 return IRQ_WAKE_THREAD; 1197 else if (host->sd_error) 1198 mmcif_dma_complete(host); 1199 } else { 1200 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1201 } 1202 1203 return IRQ_HANDLED; 1204 } 1205 1206 static void mmcif_timeout_work(struct work_struct *work) 1207 { 1208 struct delayed_work *d = container_of(work, struct delayed_work, work); 1209 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1210 struct mmc_request *mrq = host->mrq; 1211 1212 if (host->dying) 1213 /* Don't run after mmc_remove_host() */ 1214 return; 1215 1216 /* 1217 * Handle races with cancel_delayed_work(), unless 1218 * cancel_delayed_work_sync() is used 1219 */ 1220 switch (host->wait_for) { 1221 case MMCIF_WAIT_FOR_CMD: 1222 mrq->cmd->error = sh_mmcif_error_manage(host); 1223 break; 1224 case MMCIF_WAIT_FOR_STOP: 1225 mrq->stop->error = sh_mmcif_error_manage(host); 1226 break; 1227 case MMCIF_WAIT_FOR_MREAD: 1228 case MMCIF_WAIT_FOR_MWRITE: 1229 case MMCIF_WAIT_FOR_READ: 1230 case MMCIF_WAIT_FOR_WRITE: 1231 case MMCIF_WAIT_FOR_READ_END: 1232 case MMCIF_WAIT_FOR_WRITE_END: 1233 mrq->data->error = sh_mmcif_error_manage(host); 1234 break; 1235 default: 1236 BUG(); 1237 } 1238 1239 host->state = STATE_IDLE; 1240 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1241 host->mrq = NULL; 1242 mmc_request_done(host->mmc, mrq); 1243 } 1244 1245 static int __devinit sh_mmcif_probe(struct platform_device *pdev) 1246 { 1247 int ret = 0, irq[2]; 1248 struct mmc_host *mmc; 1249 struct sh_mmcif_host *host; 1250 struct sh_mmcif_plat_data *pd; 1251 struct resource *res; 1252 void __iomem *reg; 1253 char clk_name[8]; 1254 1255 irq[0] = platform_get_irq(pdev, 0); 1256 irq[1] = platform_get_irq(pdev, 1); 1257 if (irq[0] < 0 || irq[1] < 0) { 1258 dev_err(&pdev->dev, "Get irq error\n"); 1259 return -ENXIO; 1260 } 1261 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1262 if (!res) { 1263 dev_err(&pdev->dev, "platform_get_resource error.\n"); 1264 return -ENXIO; 1265 } 1266 reg = ioremap(res->start, resource_size(res)); 1267 if (!reg) { 1268 dev_err(&pdev->dev, "ioremap error.\n"); 1269 return -ENOMEM; 1270 } 1271 pd = pdev->dev.platform_data; 1272 if (!pd) { 1273 dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); 1274 ret = -ENXIO; 1275 goto clean_up; 1276 } 1277 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1278 if (!mmc) { 1279 ret = -ENOMEM; 1280 goto clean_up; 1281 } 1282 host = mmc_priv(mmc); 1283 host->mmc = mmc; 1284 host->addr = reg; 1285 host->timeout = 1000; 1286 1287 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 1288 host->hclk = clk_get(&pdev->dev, clk_name); 1289 if (IS_ERR(host->hclk)) { 1290 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 1291 ret = PTR_ERR(host->hclk); 1292 goto clean_up1; 1293 } 1294 clk_enable(host->hclk); 1295 host->clk = clk_get_rate(host->hclk); 1296 host->pd = pdev; 1297 1298 spin_lock_init(&host->lock); 1299 1300 mmc->ops = &sh_mmcif_ops; 1301 mmc->f_max = host->clk; 1302 /* close to 400KHz */ 1303 if (mmc->f_max < 51200000) 1304 mmc->f_min = mmc->f_max / 128; 1305 else if (mmc->f_max < 102400000) 1306 mmc->f_min = mmc->f_max / 256; 1307 else 1308 mmc->f_min = mmc->f_max / 512; 1309 if (pd->ocr) 1310 mmc->ocr_avail = pd->ocr; 1311 mmc->caps = MMC_CAP_MMC_HIGHSPEED; 1312 if (pd->caps) 1313 mmc->caps |= pd->caps; 1314 mmc->max_segs = 32; 1315 mmc->max_blk_size = 512; 1316 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1317 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1318 mmc->max_seg_size = mmc->max_req_size; 1319 1320 sh_mmcif_sync_reset(host); 1321 platform_set_drvdata(pdev, host); 1322 1323 pm_runtime_enable(&pdev->dev); 1324 host->power = false; 1325 1326 ret = pm_runtime_resume(&pdev->dev); 1327 if (ret < 0) 1328 goto clean_up2; 1329 1330 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1331 1332 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1333 1334 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host); 1335 if (ret) { 1336 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); 1337 goto clean_up3; 1338 } 1339 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host); 1340 if (ret) { 1341 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1342 goto clean_up4; 1343 } 1344 1345 ret = mmc_add_host(mmc); 1346 if (ret < 0) 1347 goto clean_up5; 1348 1349 dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1350 1351 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1352 dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1353 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1354 return ret; 1355 1356 clean_up5: 1357 free_irq(irq[1], host); 1358 clean_up4: 1359 free_irq(irq[0], host); 1360 clean_up3: 1361 pm_runtime_suspend(&pdev->dev); 1362 clean_up2: 1363 pm_runtime_disable(&pdev->dev); 1364 clk_disable(host->hclk); 1365 clean_up1: 1366 mmc_free_host(mmc); 1367 clean_up: 1368 if (reg) 1369 iounmap(reg); 1370 return ret; 1371 } 1372 1373 static int __devexit sh_mmcif_remove(struct platform_device *pdev) 1374 { 1375 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1376 int irq[2]; 1377 1378 host->dying = true; 1379 pm_runtime_get_sync(&pdev->dev); 1380 1381 dev_pm_qos_hide_latency_limit(&pdev->dev); 1382 1383 mmc_remove_host(host->mmc); 1384 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1385 1386 /* 1387 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1388 * mmc_remove_host() call above. But swapping order doesn't help either 1389 * (a query on the linux-mmc mailing list didn't bring any replies). 1390 */ 1391 cancel_delayed_work_sync(&host->timeout_work); 1392 1393 if (host->addr) 1394 iounmap(host->addr); 1395 1396 irq[0] = platform_get_irq(pdev, 0); 1397 irq[1] = platform_get_irq(pdev, 1); 1398 1399 free_irq(irq[0], host); 1400 free_irq(irq[1], host); 1401 1402 platform_set_drvdata(pdev, NULL); 1403 1404 clk_disable(host->hclk); 1405 mmc_free_host(host->mmc); 1406 pm_runtime_put_sync(&pdev->dev); 1407 pm_runtime_disable(&pdev->dev); 1408 1409 return 0; 1410 } 1411 1412 #ifdef CONFIG_PM 1413 static int sh_mmcif_suspend(struct device *dev) 1414 { 1415 struct platform_device *pdev = to_platform_device(dev); 1416 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1417 int ret = mmc_suspend_host(host->mmc); 1418 1419 if (!ret) { 1420 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1421 clk_disable(host->hclk); 1422 } 1423 1424 return ret; 1425 } 1426 1427 static int sh_mmcif_resume(struct device *dev) 1428 { 1429 struct platform_device *pdev = to_platform_device(dev); 1430 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1431 1432 clk_enable(host->hclk); 1433 1434 return mmc_resume_host(host->mmc); 1435 } 1436 #else 1437 #define sh_mmcif_suspend NULL 1438 #define sh_mmcif_resume NULL 1439 #endif /* CONFIG_PM */ 1440 1441 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1442 .suspend = sh_mmcif_suspend, 1443 .resume = sh_mmcif_resume, 1444 }; 1445 1446 static struct platform_driver sh_mmcif_driver = { 1447 .probe = sh_mmcif_probe, 1448 .remove = sh_mmcif_remove, 1449 .driver = { 1450 .name = DRIVER_NAME, 1451 .pm = &sh_mmcif_dev_pm_ops, 1452 }, 1453 }; 1454 1455 module_platform_driver(sh_mmcif_driver); 1456 1457 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1458 MODULE_LICENSE("GPL"); 1459 MODULE_ALIAS("platform:" DRIVER_NAME); 1460 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1461