1 /* 2 * MMCIF eMMC driver. 3 * 4 * Copyright (C) 2010 Renesas Solutions Corp. 5 * Yusuke Goda <yusuke.goda.sx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License. 10 * 11 * 12 * TODO 13 * 1. DMA 14 * 2. Power management 15 * 3. Handle MMC errors better 16 * 17 */ 18 19 /* 20 * The MMCIF driver is now processing MMC requests asynchronously, according 21 * to the Linux MMC API requirement. 22 * 23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24 * data, and optional stop. To achieve asynchronous processing each of these 25 * stages is split into two halves: a top and a bottom half. The top half 26 * initialises the hardware, installs a timeout handler to handle completion 27 * timeouts, and returns. In case of the command stage this immediately returns 28 * control to the caller, leaving all further processing to run asynchronously. 29 * All further request processing is performed by the bottom halves. 30 * 31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32 * thread, a DMA completion callback, if DMA is used, a timeout work, and 33 * request- and stage-specific handler methods. 34 * 35 * Each bottom half run begins with either a hardware interrupt, a DMA callback 36 * invocation, or a timeout work run. In case of an error or a successful 37 * processing completion, the MMC core is informed and the request processing is 38 * finished. In case processing has to continue, i.e., if data has to be read 39 * from or written to the card, or if a stop command has to be sent, the next 40 * top half is called, which performs the necessary hardware handling and 41 * reschedules the timeout work. This returns the driver state machine into the 42 * bottom half waiting state. 43 */ 44 45 #include <linux/bitops.h> 46 #include <linux/clk.h> 47 #include <linux/completion.h> 48 #include <linux/delay.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/dmaengine.h> 51 #include <linux/mmc/card.h> 52 #include <linux/mmc/core.h> 53 #include <linux/mmc/host.h> 54 #include <linux/mmc/mmc.h> 55 #include <linux/mmc/sdio.h> 56 #include <linux/mmc/sh_mmcif.h> 57 #include <linux/pagemap.h> 58 #include <linux/platform_device.h> 59 #include <linux/pm_qos.h> 60 #include <linux/pm_runtime.h> 61 #include <linux/spinlock.h> 62 #include <linux/module.h> 63 64 #define DRIVER_NAME "sh_mmcif" 65 #define DRIVER_VERSION "2010-04-28" 66 67 /* CE_CMD_SET */ 68 #define CMD_MASK 0x3f000000 69 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 70 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 71 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 72 #define CMD_SET_RBSY (1 << 21) /* R1b */ 73 #define CMD_SET_CCSEN (1 << 20) 74 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 75 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 76 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 77 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 78 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 79 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 80 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 81 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 82 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 83 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 84 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 85 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 86 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 87 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 88 #define CMD_SET_CCSH (1 << 5) 89 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 90 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 91 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 92 93 /* CE_CMD_CTRL */ 94 #define CMD_CTRL_BREAK (1 << 0) 95 96 /* CE_BLOCK_SET */ 97 #define BLOCK_SIZE_MASK 0x0000ffff 98 99 /* CE_INT */ 100 #define INT_CCSDE (1 << 29) 101 #define INT_CMD12DRE (1 << 26) 102 #define INT_CMD12RBE (1 << 25) 103 #define INT_CMD12CRE (1 << 24) 104 #define INT_DTRANE (1 << 23) 105 #define INT_BUFRE (1 << 22) 106 #define INT_BUFWEN (1 << 21) 107 #define INT_BUFREN (1 << 20) 108 #define INT_CCSRCV (1 << 19) 109 #define INT_RBSYE (1 << 17) 110 #define INT_CRSPE (1 << 16) 111 #define INT_CMDVIO (1 << 15) 112 #define INT_BUFVIO (1 << 14) 113 #define INT_WDATERR (1 << 11) 114 #define INT_RDATERR (1 << 10) 115 #define INT_RIDXERR (1 << 9) 116 #define INT_RSPERR (1 << 8) 117 #define INT_CCSTO (1 << 5) 118 #define INT_CRCSTO (1 << 4) 119 #define INT_WDATTO (1 << 3) 120 #define INT_RDATTO (1 << 2) 121 #define INT_RBSYTO (1 << 1) 122 #define INT_RSPTO (1 << 0) 123 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 124 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 125 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 126 INT_RDATTO | INT_RBSYTO | INT_RSPTO) 127 128 /* CE_INT_MASK */ 129 #define MASK_ALL 0x00000000 130 #define MASK_MCCSDE (1 << 29) 131 #define MASK_MCMD12DRE (1 << 26) 132 #define MASK_MCMD12RBE (1 << 25) 133 #define MASK_MCMD12CRE (1 << 24) 134 #define MASK_MDTRANE (1 << 23) 135 #define MASK_MBUFRE (1 << 22) 136 #define MASK_MBUFWEN (1 << 21) 137 #define MASK_MBUFREN (1 << 20) 138 #define MASK_MCCSRCV (1 << 19) 139 #define MASK_MRBSYE (1 << 17) 140 #define MASK_MCRSPE (1 << 16) 141 #define MASK_MCMDVIO (1 << 15) 142 #define MASK_MBUFVIO (1 << 14) 143 #define MASK_MWDATERR (1 << 11) 144 #define MASK_MRDATERR (1 << 10) 145 #define MASK_MRIDXERR (1 << 9) 146 #define MASK_MRSPERR (1 << 8) 147 #define MASK_MCCSTO (1 << 5) 148 #define MASK_MCRCSTO (1 << 4) 149 #define MASK_MWDATTO (1 << 3) 150 #define MASK_MRDATTO (1 << 2) 151 #define MASK_MRBSYTO (1 << 1) 152 #define MASK_MRSPTO (1 << 0) 153 154 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 155 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 156 MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ 157 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 158 159 /* CE_HOST_STS1 */ 160 #define STS1_CMDSEQ (1 << 31) 161 162 /* CE_HOST_STS2 */ 163 #define STS2_CRCSTE (1 << 31) 164 #define STS2_CRC16E (1 << 30) 165 #define STS2_AC12CRCE (1 << 29) 166 #define STS2_RSPCRC7E (1 << 28) 167 #define STS2_CRCSTEBE (1 << 27) 168 #define STS2_RDATEBE (1 << 26) 169 #define STS2_AC12REBE (1 << 25) 170 #define STS2_RSPEBE (1 << 24) 171 #define STS2_AC12IDXE (1 << 23) 172 #define STS2_RSPIDXE (1 << 22) 173 #define STS2_CCSTO (1 << 15) 174 #define STS2_RDATTO (1 << 14) 175 #define STS2_DATBSYTO (1 << 13) 176 #define STS2_CRCSTTO (1 << 12) 177 #define STS2_AC12BSYTO (1 << 11) 178 #define STS2_RSPBSYTO (1 << 10) 179 #define STS2_AC12RSPTO (1 << 9) 180 #define STS2_RSPTO (1 << 8) 181 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 182 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 183 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 184 STS2_DATBSYTO | STS2_CRCSTTO | \ 185 STS2_AC12BSYTO | STS2_RSPBSYTO | \ 186 STS2_AC12RSPTO | STS2_RSPTO) 187 188 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 189 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 190 #define CLKDEV_INIT 400000 /* 400 KHz */ 191 192 enum mmcif_state { 193 STATE_IDLE, 194 STATE_REQUEST, 195 STATE_IOS, 196 }; 197 198 enum mmcif_wait_for { 199 MMCIF_WAIT_FOR_REQUEST, 200 MMCIF_WAIT_FOR_CMD, 201 MMCIF_WAIT_FOR_MREAD, 202 MMCIF_WAIT_FOR_MWRITE, 203 MMCIF_WAIT_FOR_READ, 204 MMCIF_WAIT_FOR_WRITE, 205 MMCIF_WAIT_FOR_READ_END, 206 MMCIF_WAIT_FOR_WRITE_END, 207 MMCIF_WAIT_FOR_STOP, 208 }; 209 210 struct sh_mmcif_host { 211 struct mmc_host *mmc; 212 struct mmc_request *mrq; 213 struct platform_device *pd; 214 struct sh_dmae_slave dma_slave_tx; 215 struct sh_dmae_slave dma_slave_rx; 216 struct clk *hclk; 217 unsigned int clk; 218 int bus_width; 219 bool sd_error; 220 bool dying; 221 long timeout; 222 void __iomem *addr; 223 u32 *pio_ptr; 224 spinlock_t lock; /* protect sh_mmcif_host::state */ 225 enum mmcif_state state; 226 enum mmcif_wait_for wait_for; 227 struct delayed_work timeout_work; 228 size_t blocksize; 229 int sg_idx; 230 int sg_blkidx; 231 bool power; 232 bool card_present; 233 234 /* DMA support */ 235 struct dma_chan *chan_rx; 236 struct dma_chan *chan_tx; 237 struct completion dma_complete; 238 bool dma_active; 239 }; 240 241 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 242 unsigned int reg, u32 val) 243 { 244 writel(val | readl(host->addr + reg), host->addr + reg); 245 } 246 247 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 248 unsigned int reg, u32 val) 249 { 250 writel(~val & readl(host->addr + reg), host->addr + reg); 251 } 252 253 static void mmcif_dma_complete(void *arg) 254 { 255 struct sh_mmcif_host *host = arg; 256 struct mmc_data *data = host->mrq->data; 257 258 dev_dbg(&host->pd->dev, "Command completed\n"); 259 260 if (WARN(!data, "%s: NULL data in DMA completion!\n", 261 dev_name(&host->pd->dev))) 262 return; 263 264 if (data->flags & MMC_DATA_READ) 265 dma_unmap_sg(host->chan_rx->device->dev, 266 data->sg, data->sg_len, 267 DMA_FROM_DEVICE); 268 else 269 dma_unmap_sg(host->chan_tx->device->dev, 270 data->sg, data->sg_len, 271 DMA_TO_DEVICE); 272 273 complete(&host->dma_complete); 274 } 275 276 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 277 { 278 struct mmc_data *data = host->mrq->data; 279 struct scatterlist *sg = data->sg; 280 struct dma_async_tx_descriptor *desc = NULL; 281 struct dma_chan *chan = host->chan_rx; 282 dma_cookie_t cookie = -EINVAL; 283 int ret; 284 285 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 286 DMA_FROM_DEVICE); 287 if (ret > 0) { 288 host->dma_active = true; 289 desc = chan->device->device_prep_slave_sg(chan, sg, ret, 290 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 291 } 292 293 if (desc) { 294 desc->callback = mmcif_dma_complete; 295 desc->callback_param = host; 296 cookie = dmaengine_submit(desc); 297 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 298 dma_async_issue_pending(chan); 299 } 300 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 301 __func__, data->sg_len, ret, cookie); 302 303 if (!desc) { 304 /* DMA failed, fall back to PIO */ 305 if (ret >= 0) 306 ret = -EIO; 307 host->chan_rx = NULL; 308 host->dma_active = false; 309 dma_release_channel(chan); 310 /* Free the Tx channel too */ 311 chan = host->chan_tx; 312 if (chan) { 313 host->chan_tx = NULL; 314 dma_release_channel(chan); 315 } 316 dev_warn(&host->pd->dev, 317 "DMA failed: %d, falling back to PIO\n", ret); 318 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 319 } 320 321 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 322 desc, cookie, data->sg_len); 323 } 324 325 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 326 { 327 struct mmc_data *data = host->mrq->data; 328 struct scatterlist *sg = data->sg; 329 struct dma_async_tx_descriptor *desc = NULL; 330 struct dma_chan *chan = host->chan_tx; 331 dma_cookie_t cookie = -EINVAL; 332 int ret; 333 334 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 335 DMA_TO_DEVICE); 336 if (ret > 0) { 337 host->dma_active = true; 338 desc = chan->device->device_prep_slave_sg(chan, sg, ret, 339 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 340 } 341 342 if (desc) { 343 desc->callback = mmcif_dma_complete; 344 desc->callback_param = host; 345 cookie = dmaengine_submit(desc); 346 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 347 dma_async_issue_pending(chan); 348 } 349 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 350 __func__, data->sg_len, ret, cookie); 351 352 if (!desc) { 353 /* DMA failed, fall back to PIO */ 354 if (ret >= 0) 355 ret = -EIO; 356 host->chan_tx = NULL; 357 host->dma_active = false; 358 dma_release_channel(chan); 359 /* Free the Rx channel too */ 360 chan = host->chan_rx; 361 if (chan) { 362 host->chan_rx = NULL; 363 dma_release_channel(chan); 364 } 365 dev_warn(&host->pd->dev, 366 "DMA failed: %d, falling back to PIO\n", ret); 367 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 368 } 369 370 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 371 desc, cookie); 372 } 373 374 static bool sh_mmcif_filter(struct dma_chan *chan, void *arg) 375 { 376 dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); 377 chan->private = arg; 378 return true; 379 } 380 381 static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 382 struct sh_mmcif_plat_data *pdata) 383 { 384 struct sh_dmae_slave *tx, *rx; 385 host->dma_active = false; 386 387 /* We can only either use DMA for both Tx and Rx or not use it at all */ 388 if (pdata->dma) { 389 dev_warn(&host->pd->dev, 390 "Update your platform to use embedded DMA slave IDs\n"); 391 tx = &pdata->dma->chan_priv_tx; 392 rx = &pdata->dma->chan_priv_rx; 393 } else { 394 tx = &host->dma_slave_tx; 395 tx->slave_id = pdata->slave_id_tx; 396 rx = &host->dma_slave_rx; 397 rx->slave_id = pdata->slave_id_rx; 398 } 399 if (tx->slave_id > 0 && rx->slave_id > 0) { 400 dma_cap_mask_t mask; 401 402 dma_cap_zero(mask); 403 dma_cap_set(DMA_SLAVE, mask); 404 405 host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx); 406 dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 407 host->chan_tx); 408 409 if (!host->chan_tx) 410 return; 411 412 host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx); 413 dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 414 host->chan_rx); 415 416 if (!host->chan_rx) { 417 dma_release_channel(host->chan_tx); 418 host->chan_tx = NULL; 419 return; 420 } 421 422 init_completion(&host->dma_complete); 423 } 424 } 425 426 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 427 { 428 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 429 /* Descriptors are freed automatically */ 430 if (host->chan_tx) { 431 struct dma_chan *chan = host->chan_tx; 432 host->chan_tx = NULL; 433 dma_release_channel(chan); 434 } 435 if (host->chan_rx) { 436 struct dma_chan *chan = host->chan_rx; 437 host->chan_rx = NULL; 438 dma_release_channel(chan); 439 } 440 441 host->dma_active = false; 442 } 443 444 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 445 { 446 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 447 448 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 449 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 450 451 if (!clk) 452 return; 453 if (p->sup_pclk && clk == host->clk) 454 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 455 else 456 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 457 ((fls(host->clk / clk) - 1) << 16)); 458 459 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 460 } 461 462 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 463 { 464 u32 tmp; 465 466 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 467 468 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 469 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 470 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 471 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 472 /* byte swap on */ 473 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 474 } 475 476 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 477 { 478 u32 state1, state2; 479 int ret, timeout; 480 481 host->sd_error = false; 482 483 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 484 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 485 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 486 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 487 488 if (state1 & STS1_CMDSEQ) { 489 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 490 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 491 for (timeout = 10000000; timeout; timeout--) { 492 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 493 & STS1_CMDSEQ)) 494 break; 495 mdelay(1); 496 } 497 if (!timeout) { 498 dev_err(&host->pd->dev, 499 "Forced end of command sequence timeout err\n"); 500 return -EIO; 501 } 502 sh_mmcif_sync_reset(host); 503 dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 504 return -EIO; 505 } 506 507 if (state2 & STS2_CRC_ERR) { 508 dev_dbg(&host->pd->dev, ": CRC error\n"); 509 ret = -EIO; 510 } else if (state2 & STS2_TIMEOUT_ERR) { 511 dev_dbg(&host->pd->dev, ": Timeout\n"); 512 ret = -ETIMEDOUT; 513 } else { 514 dev_dbg(&host->pd->dev, ": End/Index error\n"); 515 ret = -EIO; 516 } 517 return ret; 518 } 519 520 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 521 { 522 struct mmc_data *data = host->mrq->data; 523 524 host->sg_blkidx += host->blocksize; 525 526 /* data->sg->length must be a multiple of host->blocksize? */ 527 BUG_ON(host->sg_blkidx > data->sg->length); 528 529 if (host->sg_blkidx == data->sg->length) { 530 host->sg_blkidx = 0; 531 if (++host->sg_idx < data->sg_len) 532 host->pio_ptr = sg_virt(++data->sg); 533 } else { 534 host->pio_ptr = p; 535 } 536 537 if (host->sg_idx == data->sg_len) 538 return false; 539 540 return true; 541 } 542 543 static void sh_mmcif_single_read(struct sh_mmcif_host *host, 544 struct mmc_request *mrq) 545 { 546 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 547 BLOCK_SIZE_MASK) + 3; 548 549 host->wait_for = MMCIF_WAIT_FOR_READ; 550 schedule_delayed_work(&host->timeout_work, host->timeout); 551 552 /* buf read enable */ 553 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 554 } 555 556 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 557 { 558 struct mmc_data *data = host->mrq->data; 559 u32 *p = sg_virt(data->sg); 560 int i; 561 562 if (host->sd_error) { 563 data->error = sh_mmcif_error_manage(host); 564 return false; 565 } 566 567 for (i = 0; i < host->blocksize / 4; i++) 568 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 569 570 /* buffer read end */ 571 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 572 host->wait_for = MMCIF_WAIT_FOR_READ_END; 573 574 return true; 575 } 576 577 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 578 struct mmc_request *mrq) 579 { 580 struct mmc_data *data = mrq->data; 581 582 if (!data->sg_len || !data->sg->length) 583 return; 584 585 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 586 BLOCK_SIZE_MASK; 587 588 host->wait_for = MMCIF_WAIT_FOR_MREAD; 589 host->sg_idx = 0; 590 host->sg_blkidx = 0; 591 host->pio_ptr = sg_virt(data->sg); 592 schedule_delayed_work(&host->timeout_work, host->timeout); 593 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 594 } 595 596 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 597 { 598 struct mmc_data *data = host->mrq->data; 599 u32 *p = host->pio_ptr; 600 int i; 601 602 if (host->sd_error) { 603 data->error = sh_mmcif_error_manage(host); 604 return false; 605 } 606 607 BUG_ON(!data->sg->length); 608 609 for (i = 0; i < host->blocksize / 4; i++) 610 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 611 612 if (!sh_mmcif_next_block(host, p)) 613 return false; 614 615 schedule_delayed_work(&host->timeout_work, host->timeout); 616 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 617 618 return true; 619 } 620 621 static void sh_mmcif_single_write(struct sh_mmcif_host *host, 622 struct mmc_request *mrq) 623 { 624 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 625 BLOCK_SIZE_MASK) + 3; 626 627 host->wait_for = MMCIF_WAIT_FOR_WRITE; 628 schedule_delayed_work(&host->timeout_work, host->timeout); 629 630 /* buf write enable */ 631 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 632 } 633 634 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 635 { 636 struct mmc_data *data = host->mrq->data; 637 u32 *p = sg_virt(data->sg); 638 int i; 639 640 if (host->sd_error) { 641 data->error = sh_mmcif_error_manage(host); 642 return false; 643 } 644 645 for (i = 0; i < host->blocksize / 4; i++) 646 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 647 648 /* buffer write end */ 649 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 650 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 651 652 return true; 653 } 654 655 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 656 struct mmc_request *mrq) 657 { 658 struct mmc_data *data = mrq->data; 659 660 if (!data->sg_len || !data->sg->length) 661 return; 662 663 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 664 BLOCK_SIZE_MASK; 665 666 host->wait_for = MMCIF_WAIT_FOR_MWRITE; 667 host->sg_idx = 0; 668 host->sg_blkidx = 0; 669 host->pio_ptr = sg_virt(data->sg); 670 schedule_delayed_work(&host->timeout_work, host->timeout); 671 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 672 } 673 674 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 675 { 676 struct mmc_data *data = host->mrq->data; 677 u32 *p = host->pio_ptr; 678 int i; 679 680 if (host->sd_error) { 681 data->error = sh_mmcif_error_manage(host); 682 return false; 683 } 684 685 BUG_ON(!data->sg->length); 686 687 for (i = 0; i < host->blocksize / 4; i++) 688 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 689 690 if (!sh_mmcif_next_block(host, p)) 691 return false; 692 693 schedule_delayed_work(&host->timeout_work, host->timeout); 694 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 695 696 return true; 697 } 698 699 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 700 struct mmc_command *cmd) 701 { 702 if (cmd->flags & MMC_RSP_136) { 703 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 704 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 705 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 706 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 707 } else 708 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 709 } 710 711 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 712 struct mmc_command *cmd) 713 { 714 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 715 } 716 717 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 718 struct mmc_request *mrq) 719 { 720 struct mmc_data *data = mrq->data; 721 struct mmc_command *cmd = mrq->cmd; 722 u32 opc = cmd->opcode; 723 u32 tmp = 0; 724 725 /* Response Type check */ 726 switch (mmc_resp_type(cmd)) { 727 case MMC_RSP_NONE: 728 tmp |= CMD_SET_RTYP_NO; 729 break; 730 case MMC_RSP_R1: 731 case MMC_RSP_R1B: 732 case MMC_RSP_R3: 733 tmp |= CMD_SET_RTYP_6B; 734 break; 735 case MMC_RSP_R2: 736 tmp |= CMD_SET_RTYP_17B; 737 break; 738 default: 739 dev_err(&host->pd->dev, "Unsupported response type.\n"); 740 break; 741 } 742 switch (opc) { 743 /* RBSY */ 744 case MMC_SWITCH: 745 case MMC_STOP_TRANSMISSION: 746 case MMC_SET_WRITE_PROT: 747 case MMC_CLR_WRITE_PROT: 748 case MMC_ERASE: 749 case MMC_GEN_CMD: 750 tmp |= CMD_SET_RBSY; 751 break; 752 } 753 /* WDAT / DATW */ 754 if (data) { 755 tmp |= CMD_SET_WDAT; 756 switch (host->bus_width) { 757 case MMC_BUS_WIDTH_1: 758 tmp |= CMD_SET_DATW_1; 759 break; 760 case MMC_BUS_WIDTH_4: 761 tmp |= CMD_SET_DATW_4; 762 break; 763 case MMC_BUS_WIDTH_8: 764 tmp |= CMD_SET_DATW_8; 765 break; 766 default: 767 dev_err(&host->pd->dev, "Unsupported bus width.\n"); 768 break; 769 } 770 } 771 /* DWEN */ 772 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 773 tmp |= CMD_SET_DWEN; 774 /* CMLTE/CMD12EN */ 775 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 776 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 777 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 778 data->blocks << 16); 779 } 780 /* RIDXC[1:0] check bits */ 781 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 782 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 783 tmp |= CMD_SET_RIDXC_BITS; 784 /* RCRC7C[1:0] check bits */ 785 if (opc == MMC_SEND_OP_COND) 786 tmp |= CMD_SET_CRC7C_BITS; 787 /* RCRC7C[1:0] internal CRC7 */ 788 if (opc == MMC_ALL_SEND_CID || 789 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 790 tmp |= CMD_SET_CRC7C_INTERNAL; 791 792 return (opc << 24) | tmp; 793 } 794 795 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 796 struct mmc_request *mrq, u32 opc) 797 { 798 switch (opc) { 799 case MMC_READ_MULTIPLE_BLOCK: 800 sh_mmcif_multi_read(host, mrq); 801 return 0; 802 case MMC_WRITE_MULTIPLE_BLOCK: 803 sh_mmcif_multi_write(host, mrq); 804 return 0; 805 case MMC_WRITE_BLOCK: 806 sh_mmcif_single_write(host, mrq); 807 return 0; 808 case MMC_READ_SINGLE_BLOCK: 809 case MMC_SEND_EXT_CSD: 810 sh_mmcif_single_read(host, mrq); 811 return 0; 812 default: 813 dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 814 return -EINVAL; 815 } 816 } 817 818 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 819 struct mmc_request *mrq) 820 { 821 struct mmc_command *cmd = mrq->cmd; 822 u32 opc = cmd->opcode; 823 u32 mask; 824 825 switch (opc) { 826 /* response busy check */ 827 case MMC_SWITCH: 828 case MMC_STOP_TRANSMISSION: 829 case MMC_SET_WRITE_PROT: 830 case MMC_CLR_WRITE_PROT: 831 case MMC_ERASE: 832 case MMC_GEN_CMD: 833 mask = MASK_START_CMD | MASK_MRBSYE; 834 break; 835 default: 836 mask = MASK_START_CMD | MASK_MCRSPE; 837 break; 838 } 839 840 if (mrq->data) { 841 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 842 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 843 mrq->data->blksz); 844 } 845 opc = sh_mmcif_set_cmd(host, mrq); 846 847 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 848 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 849 /* set arg */ 850 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 851 /* set cmd */ 852 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 853 854 host->wait_for = MMCIF_WAIT_FOR_CMD; 855 schedule_delayed_work(&host->timeout_work, host->timeout); 856 } 857 858 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 859 struct mmc_request *mrq) 860 { 861 switch (mrq->cmd->opcode) { 862 case MMC_READ_MULTIPLE_BLOCK: 863 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 864 break; 865 case MMC_WRITE_MULTIPLE_BLOCK: 866 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 867 break; 868 default: 869 dev_err(&host->pd->dev, "unsupported stop cmd\n"); 870 mrq->stop->error = sh_mmcif_error_manage(host); 871 return; 872 } 873 874 host->wait_for = MMCIF_WAIT_FOR_STOP; 875 schedule_delayed_work(&host->timeout_work, host->timeout); 876 } 877 878 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 879 { 880 struct sh_mmcif_host *host = mmc_priv(mmc); 881 unsigned long flags; 882 883 spin_lock_irqsave(&host->lock, flags); 884 if (host->state != STATE_IDLE) { 885 spin_unlock_irqrestore(&host->lock, flags); 886 mrq->cmd->error = -EAGAIN; 887 mmc_request_done(mmc, mrq); 888 return; 889 } 890 891 host->state = STATE_REQUEST; 892 spin_unlock_irqrestore(&host->lock, flags); 893 894 switch (mrq->cmd->opcode) { 895 /* MMCIF does not support SD/SDIO command */ 896 case SD_IO_SEND_OP_COND: 897 case MMC_APP_CMD: 898 host->state = STATE_IDLE; 899 mrq->cmd->error = -ETIMEDOUT; 900 mmc_request_done(mmc, mrq); 901 return; 902 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 903 if (!mrq->data) { 904 /* send_if_cond cmd (not support) */ 905 host->state = STATE_IDLE; 906 mrq->cmd->error = -ETIMEDOUT; 907 mmc_request_done(mmc, mrq); 908 return; 909 } 910 break; 911 default: 912 break; 913 } 914 915 host->mrq = mrq; 916 917 sh_mmcif_start_cmd(host, mrq); 918 } 919 920 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 921 { 922 struct sh_mmcif_host *host = mmc_priv(mmc); 923 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 924 unsigned long flags; 925 926 spin_lock_irqsave(&host->lock, flags); 927 if (host->state != STATE_IDLE) { 928 spin_unlock_irqrestore(&host->lock, flags); 929 return; 930 } 931 932 host->state = STATE_IOS; 933 spin_unlock_irqrestore(&host->lock, flags); 934 935 if (ios->power_mode == MMC_POWER_UP) { 936 if (!host->card_present) { 937 /* See if we also get DMA */ 938 sh_mmcif_request_dma(host, host->pd->dev.platform_data); 939 host->card_present = true; 940 } 941 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 942 /* clock stop */ 943 sh_mmcif_clock_control(host, 0); 944 if (ios->power_mode == MMC_POWER_OFF) { 945 if (host->card_present) { 946 sh_mmcif_release_dma(host); 947 host->card_present = false; 948 } 949 } 950 if (host->power) { 951 pm_runtime_put(&host->pd->dev); 952 host->power = false; 953 if (p->down_pwr && ios->power_mode == MMC_POWER_OFF) 954 p->down_pwr(host->pd); 955 } 956 host->state = STATE_IDLE; 957 return; 958 } 959 960 if (ios->clock) { 961 if (!host->power) { 962 if (p->set_pwr) 963 p->set_pwr(host->pd, ios->power_mode); 964 pm_runtime_get_sync(&host->pd->dev); 965 host->power = true; 966 sh_mmcif_sync_reset(host); 967 } 968 sh_mmcif_clock_control(host, ios->clock); 969 } 970 971 host->bus_width = ios->bus_width; 972 host->state = STATE_IDLE; 973 } 974 975 static int sh_mmcif_get_cd(struct mmc_host *mmc) 976 { 977 struct sh_mmcif_host *host = mmc_priv(mmc); 978 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 979 980 if (!p->get_cd) 981 return -ENOSYS; 982 else 983 return p->get_cd(host->pd); 984 } 985 986 static struct mmc_host_ops sh_mmcif_ops = { 987 .request = sh_mmcif_request, 988 .set_ios = sh_mmcif_set_ios, 989 .get_cd = sh_mmcif_get_cd, 990 }; 991 992 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 993 { 994 struct mmc_command *cmd = host->mrq->cmd; 995 struct mmc_data *data = host->mrq->data; 996 long time; 997 998 if (host->sd_error) { 999 switch (cmd->opcode) { 1000 case MMC_ALL_SEND_CID: 1001 case MMC_SELECT_CARD: 1002 case MMC_APP_CMD: 1003 cmd->error = -ETIMEDOUT; 1004 host->sd_error = false; 1005 break; 1006 default: 1007 cmd->error = sh_mmcif_error_manage(host); 1008 dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n", 1009 cmd->opcode, cmd->error); 1010 break; 1011 } 1012 return false; 1013 } 1014 if (!(cmd->flags & MMC_RSP_PRESENT)) { 1015 cmd->error = 0; 1016 return false; 1017 } 1018 1019 sh_mmcif_get_response(host, cmd); 1020 1021 if (!data) 1022 return false; 1023 1024 if (data->flags & MMC_DATA_READ) { 1025 if (host->chan_rx) 1026 sh_mmcif_start_dma_rx(host); 1027 } else { 1028 if (host->chan_tx) 1029 sh_mmcif_start_dma_tx(host); 1030 } 1031 1032 if (!host->dma_active) { 1033 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 1034 if (!data->error) 1035 return true; 1036 return false; 1037 } 1038 1039 /* Running in the IRQ thread, can sleep */ 1040 time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1041 host->timeout); 1042 if (host->sd_error) { 1043 dev_err(host->mmc->parent, 1044 "Error IRQ while waiting for DMA completion!\n"); 1045 /* Woken up by an error IRQ: abort DMA */ 1046 if (data->flags & MMC_DATA_READ) 1047 dmaengine_terminate_all(host->chan_rx); 1048 else 1049 dmaengine_terminate_all(host->chan_tx); 1050 data->error = sh_mmcif_error_manage(host); 1051 } else if (!time) { 1052 data->error = -ETIMEDOUT; 1053 } else if (time < 0) { 1054 data->error = time; 1055 } 1056 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1057 BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1058 host->dma_active = false; 1059 1060 if (data->error) 1061 data->bytes_xfered = 0; 1062 1063 return false; 1064 } 1065 1066 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1067 { 1068 struct sh_mmcif_host *host = dev_id; 1069 struct mmc_request *mrq = host->mrq; 1070 struct mmc_data *data = mrq->data; 1071 1072 cancel_delayed_work_sync(&host->timeout_work); 1073 1074 /* 1075 * All handlers return true, if processing continues, and false, if the 1076 * request has to be completed - successfully or not 1077 */ 1078 switch (host->wait_for) { 1079 case MMCIF_WAIT_FOR_REQUEST: 1080 /* We're too late, the timeout has already kicked in */ 1081 return IRQ_HANDLED; 1082 case MMCIF_WAIT_FOR_CMD: 1083 if (sh_mmcif_end_cmd(host)) 1084 /* Wait for data */ 1085 return IRQ_HANDLED; 1086 break; 1087 case MMCIF_WAIT_FOR_MREAD: 1088 if (sh_mmcif_mread_block(host)) 1089 /* Wait for more data */ 1090 return IRQ_HANDLED; 1091 break; 1092 case MMCIF_WAIT_FOR_READ: 1093 if (sh_mmcif_read_block(host)) 1094 /* Wait for data end */ 1095 return IRQ_HANDLED; 1096 break; 1097 case MMCIF_WAIT_FOR_MWRITE: 1098 if (sh_mmcif_mwrite_block(host)) 1099 /* Wait data to write */ 1100 return IRQ_HANDLED; 1101 break; 1102 case MMCIF_WAIT_FOR_WRITE: 1103 if (sh_mmcif_write_block(host)) 1104 /* Wait for data end */ 1105 return IRQ_HANDLED; 1106 break; 1107 case MMCIF_WAIT_FOR_STOP: 1108 if (host->sd_error) { 1109 mrq->stop->error = sh_mmcif_error_manage(host); 1110 break; 1111 } 1112 sh_mmcif_get_cmd12response(host, mrq->stop); 1113 mrq->stop->error = 0; 1114 break; 1115 case MMCIF_WAIT_FOR_READ_END: 1116 case MMCIF_WAIT_FOR_WRITE_END: 1117 if (host->sd_error) 1118 data->error = sh_mmcif_error_manage(host); 1119 break; 1120 default: 1121 BUG(); 1122 } 1123 1124 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 1125 if (!mrq->cmd->error && data && !data->error) 1126 data->bytes_xfered = 1127 data->blocks * data->blksz; 1128 1129 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1130 sh_mmcif_stop_cmd(host, mrq); 1131 if (!mrq->stop->error) 1132 return IRQ_HANDLED; 1133 } 1134 } 1135 1136 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1137 host->state = STATE_IDLE; 1138 host->mrq = NULL; 1139 mmc_request_done(host->mmc, mrq); 1140 1141 return IRQ_HANDLED; 1142 } 1143 1144 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1145 { 1146 struct sh_mmcif_host *host = dev_id; 1147 u32 state; 1148 int err = 0; 1149 1150 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1151 1152 if (state & INT_ERR_STS) { 1153 /* error interrupts - process first */ 1154 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1155 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1156 err = 1; 1157 } else if (state & INT_RBSYE) { 1158 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1159 ~(INT_RBSYE | INT_CRSPE)); 1160 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 1161 } else if (state & INT_CRSPE) { 1162 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 1163 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 1164 } else if (state & INT_BUFREN) { 1165 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 1166 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 1167 } else if (state & INT_BUFWEN) { 1168 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 1169 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 1170 } else if (state & INT_CMD12DRE) { 1171 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1172 ~(INT_CMD12DRE | INT_CMD12RBE | 1173 INT_CMD12CRE | INT_BUFRE)); 1174 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 1175 } else if (state & INT_BUFRE) { 1176 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 1177 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 1178 } else if (state & INT_DTRANE) { 1179 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); 1180 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 1181 } else if (state & INT_CMD12RBE) { 1182 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1183 ~(INT_CMD12RBE | INT_CMD12CRE)); 1184 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 1185 } else { 1186 dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 1187 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1188 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1189 err = 1; 1190 } 1191 if (err) { 1192 host->sd_error = true; 1193 dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 1194 } 1195 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1196 if (!host->dma_active) 1197 return IRQ_WAKE_THREAD; 1198 else if (host->sd_error) 1199 mmcif_dma_complete(host); 1200 } else { 1201 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1202 } 1203 1204 return IRQ_HANDLED; 1205 } 1206 1207 static void mmcif_timeout_work(struct work_struct *work) 1208 { 1209 struct delayed_work *d = container_of(work, struct delayed_work, work); 1210 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1211 struct mmc_request *mrq = host->mrq; 1212 1213 if (host->dying) 1214 /* Don't run after mmc_remove_host() */ 1215 return; 1216 1217 /* 1218 * Handle races with cancel_delayed_work(), unless 1219 * cancel_delayed_work_sync() is used 1220 */ 1221 switch (host->wait_for) { 1222 case MMCIF_WAIT_FOR_CMD: 1223 mrq->cmd->error = sh_mmcif_error_manage(host); 1224 break; 1225 case MMCIF_WAIT_FOR_STOP: 1226 mrq->stop->error = sh_mmcif_error_manage(host); 1227 break; 1228 case MMCIF_WAIT_FOR_MREAD: 1229 case MMCIF_WAIT_FOR_MWRITE: 1230 case MMCIF_WAIT_FOR_READ: 1231 case MMCIF_WAIT_FOR_WRITE: 1232 case MMCIF_WAIT_FOR_READ_END: 1233 case MMCIF_WAIT_FOR_WRITE_END: 1234 mrq->data->error = sh_mmcif_error_manage(host); 1235 break; 1236 default: 1237 BUG(); 1238 } 1239 1240 host->state = STATE_IDLE; 1241 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1242 host->mrq = NULL; 1243 mmc_request_done(host->mmc, mrq); 1244 } 1245 1246 static int __devinit sh_mmcif_probe(struct platform_device *pdev) 1247 { 1248 int ret = 0, irq[2]; 1249 struct mmc_host *mmc; 1250 struct sh_mmcif_host *host; 1251 struct sh_mmcif_plat_data *pd; 1252 struct resource *res; 1253 void __iomem *reg; 1254 char clk_name[8]; 1255 1256 irq[0] = platform_get_irq(pdev, 0); 1257 irq[1] = platform_get_irq(pdev, 1); 1258 if (irq[0] < 0 || irq[1] < 0) { 1259 dev_err(&pdev->dev, "Get irq error\n"); 1260 return -ENXIO; 1261 } 1262 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1263 if (!res) { 1264 dev_err(&pdev->dev, "platform_get_resource error.\n"); 1265 return -ENXIO; 1266 } 1267 reg = ioremap(res->start, resource_size(res)); 1268 if (!reg) { 1269 dev_err(&pdev->dev, "ioremap error.\n"); 1270 return -ENOMEM; 1271 } 1272 pd = pdev->dev.platform_data; 1273 if (!pd) { 1274 dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); 1275 ret = -ENXIO; 1276 goto clean_up; 1277 } 1278 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1279 if (!mmc) { 1280 ret = -ENOMEM; 1281 goto clean_up; 1282 } 1283 host = mmc_priv(mmc); 1284 host->mmc = mmc; 1285 host->addr = reg; 1286 host->timeout = 1000; 1287 1288 snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 1289 host->hclk = clk_get(&pdev->dev, clk_name); 1290 if (IS_ERR(host->hclk)) { 1291 dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 1292 ret = PTR_ERR(host->hclk); 1293 goto clean_up1; 1294 } 1295 clk_enable(host->hclk); 1296 host->clk = clk_get_rate(host->hclk); 1297 host->pd = pdev; 1298 1299 spin_lock_init(&host->lock); 1300 1301 mmc->ops = &sh_mmcif_ops; 1302 mmc->f_max = host->clk; 1303 /* close to 400KHz */ 1304 if (mmc->f_max < 51200000) 1305 mmc->f_min = mmc->f_max / 128; 1306 else if (mmc->f_max < 102400000) 1307 mmc->f_min = mmc->f_max / 256; 1308 else 1309 mmc->f_min = mmc->f_max / 512; 1310 if (pd->ocr) 1311 mmc->ocr_avail = pd->ocr; 1312 mmc->caps = MMC_CAP_MMC_HIGHSPEED; 1313 if (pd->caps) 1314 mmc->caps |= pd->caps; 1315 mmc->max_segs = 32; 1316 mmc->max_blk_size = 512; 1317 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1318 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1319 mmc->max_seg_size = mmc->max_req_size; 1320 1321 sh_mmcif_sync_reset(host); 1322 platform_set_drvdata(pdev, host); 1323 1324 pm_runtime_enable(&pdev->dev); 1325 host->power = false; 1326 1327 ret = pm_runtime_resume(&pdev->dev); 1328 if (ret < 0) 1329 goto clean_up2; 1330 1331 mmc_add_host(mmc); 1332 1333 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1334 1335 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host); 1336 if (ret) { 1337 dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); 1338 goto clean_up3; 1339 } 1340 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host); 1341 if (ret) { 1342 free_irq(irq[0], host); 1343 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1344 goto clean_up3; 1345 } 1346 1347 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1348 1349 mmc_detect_change(host->mmc, 0); 1350 1351 dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1352 1353 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1354 dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1355 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1356 return ret; 1357 1358 clean_up3: 1359 mmc_remove_host(mmc); 1360 pm_runtime_suspend(&pdev->dev); 1361 clean_up2: 1362 pm_runtime_disable(&pdev->dev); 1363 clk_disable(host->hclk); 1364 clean_up1: 1365 mmc_free_host(mmc); 1366 clean_up: 1367 if (reg) 1368 iounmap(reg); 1369 return ret; 1370 } 1371 1372 static int __devexit sh_mmcif_remove(struct platform_device *pdev) 1373 { 1374 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1375 int irq[2]; 1376 1377 host->dying = true; 1378 pm_runtime_get_sync(&pdev->dev); 1379 1380 dev_pm_qos_hide_latency_limit(&pdev->dev); 1381 1382 mmc_remove_host(host->mmc); 1383 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1384 1385 /* 1386 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1387 * mmc_remove_host() call above. But swapping order doesn't help either 1388 * (a query on the linux-mmc mailing list didn't bring any replies). 1389 */ 1390 cancel_delayed_work_sync(&host->timeout_work); 1391 1392 if (host->addr) 1393 iounmap(host->addr); 1394 1395 irq[0] = platform_get_irq(pdev, 0); 1396 irq[1] = platform_get_irq(pdev, 1); 1397 1398 free_irq(irq[0], host); 1399 free_irq(irq[1], host); 1400 1401 platform_set_drvdata(pdev, NULL); 1402 1403 clk_disable(host->hclk); 1404 mmc_free_host(host->mmc); 1405 pm_runtime_put_sync(&pdev->dev); 1406 pm_runtime_disable(&pdev->dev); 1407 1408 return 0; 1409 } 1410 1411 #ifdef CONFIG_PM 1412 static int sh_mmcif_suspend(struct device *dev) 1413 { 1414 struct platform_device *pdev = to_platform_device(dev); 1415 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1416 int ret = mmc_suspend_host(host->mmc); 1417 1418 if (!ret) { 1419 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1420 clk_disable(host->hclk); 1421 } 1422 1423 return ret; 1424 } 1425 1426 static int sh_mmcif_resume(struct device *dev) 1427 { 1428 struct platform_device *pdev = to_platform_device(dev); 1429 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1430 1431 clk_enable(host->hclk); 1432 1433 return mmc_resume_host(host->mmc); 1434 } 1435 #else 1436 #define sh_mmcif_suspend NULL 1437 #define sh_mmcif_resume NULL 1438 #endif /* CONFIG_PM */ 1439 1440 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1441 .suspend = sh_mmcif_suspend, 1442 .resume = sh_mmcif_resume, 1443 }; 1444 1445 static struct platform_driver sh_mmcif_driver = { 1446 .probe = sh_mmcif_probe, 1447 .remove = sh_mmcif_remove, 1448 .driver = { 1449 .name = DRIVER_NAME, 1450 .pm = &sh_mmcif_dev_pm_ops, 1451 }, 1452 }; 1453 1454 module_platform_driver(sh_mmcif_driver); 1455 1456 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1457 MODULE_LICENSE("GPL"); 1458 MODULE_ALIAS("platform:" DRIVER_NAME); 1459 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1460