1 /* 2 * MMCIF eMMC driver. 3 * 4 * Copyright (C) 2010 Renesas Solutions Corp. 5 * Yusuke Goda <yusuke.goda.sx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License. 10 * 11 * 12 * TODO 13 * 1. DMA 14 * 2. Power management 15 * 3. Handle MMC errors better 16 * 17 */ 18 19 /* 20 * The MMCIF driver is now processing MMC requests asynchronously, according 21 * to the Linux MMC API requirement. 22 * 23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24 * data, and optional stop. To achieve asynchronous processing each of these 25 * stages is split into two halves: a top and a bottom half. The top half 26 * initialises the hardware, installs a timeout handler to handle completion 27 * timeouts, and returns. In case of the command stage this immediately returns 28 * control to the caller, leaving all further processing to run asynchronously. 29 * All further request processing is performed by the bottom halves. 30 * 31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32 * thread, a DMA completion callback, if DMA is used, a timeout work, and 33 * request- and stage-specific handler methods. 34 * 35 * Each bottom half run begins with either a hardware interrupt, a DMA callback 36 * invocation, or a timeout work run. In case of an error or a successful 37 * processing completion, the MMC core is informed and the request processing is 38 * finished. In case processing has to continue, i.e., if data has to be read 39 * from or written to the card, or if a stop command has to be sent, the next 40 * top half is called, which performs the necessary hardware handling and 41 * reschedules the timeout work. This returns the driver state machine into the 42 * bottom half waiting state. 43 */ 44 45 #include <linux/bitops.h> 46 #include <linux/clk.h> 47 #include <linux/completion.h> 48 #include <linux/delay.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/dmaengine.h> 51 #include <linux/mmc/card.h> 52 #include <linux/mmc/core.h> 53 #include <linux/mmc/host.h> 54 #include <linux/mmc/mmc.h> 55 #include <linux/mmc/sdio.h> 56 #include <linux/mmc/sh_mmcif.h> 57 #include <linux/mmc/slot-gpio.h> 58 #include <linux/mod_devicetable.h> 59 #include <linux/mutex.h> 60 #include <linux/pagemap.h> 61 #include <linux/platform_device.h> 62 #include <linux/pm_qos.h> 63 #include <linux/pm_runtime.h> 64 #include <linux/sh_dma.h> 65 #include <linux/spinlock.h> 66 #include <linux/module.h> 67 68 #define DRIVER_NAME "sh_mmcif" 69 #define DRIVER_VERSION "2010-04-28" 70 71 /* CE_CMD_SET */ 72 #define CMD_MASK 0x3f000000 73 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 74 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 75 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 76 #define CMD_SET_RBSY (1 << 21) /* R1b */ 77 #define CMD_SET_CCSEN (1 << 20) 78 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 79 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 80 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 81 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 82 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 83 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 84 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 85 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 86 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 87 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 88 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 89 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 90 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 91 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 92 #define CMD_SET_CCSH (1 << 5) 93 #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 94 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 95 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 96 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 97 98 /* CE_CMD_CTRL */ 99 #define CMD_CTRL_BREAK (1 << 0) 100 101 /* CE_BLOCK_SET */ 102 #define BLOCK_SIZE_MASK 0x0000ffff 103 104 /* CE_INT */ 105 #define INT_CCSDE (1 << 29) 106 #define INT_CMD12DRE (1 << 26) 107 #define INT_CMD12RBE (1 << 25) 108 #define INT_CMD12CRE (1 << 24) 109 #define INT_DTRANE (1 << 23) 110 #define INT_BUFRE (1 << 22) 111 #define INT_BUFWEN (1 << 21) 112 #define INT_BUFREN (1 << 20) 113 #define INT_CCSRCV (1 << 19) 114 #define INT_RBSYE (1 << 17) 115 #define INT_CRSPE (1 << 16) 116 #define INT_CMDVIO (1 << 15) 117 #define INT_BUFVIO (1 << 14) 118 #define INT_WDATERR (1 << 11) 119 #define INT_RDATERR (1 << 10) 120 #define INT_RIDXERR (1 << 9) 121 #define INT_RSPERR (1 << 8) 122 #define INT_CCSTO (1 << 5) 123 #define INT_CRCSTO (1 << 4) 124 #define INT_WDATTO (1 << 3) 125 #define INT_RDATTO (1 << 2) 126 #define INT_RBSYTO (1 << 1) 127 #define INT_RSPTO (1 << 0) 128 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 129 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 130 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 131 INT_RDATTO | INT_RBSYTO | INT_RSPTO) 132 133 #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 134 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 135 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 136 137 #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 138 139 /* CE_INT_MASK */ 140 #define MASK_ALL 0x00000000 141 #define MASK_MCCSDE (1 << 29) 142 #define MASK_MCMD12DRE (1 << 26) 143 #define MASK_MCMD12RBE (1 << 25) 144 #define MASK_MCMD12CRE (1 << 24) 145 #define MASK_MDTRANE (1 << 23) 146 #define MASK_MBUFRE (1 << 22) 147 #define MASK_MBUFWEN (1 << 21) 148 #define MASK_MBUFREN (1 << 20) 149 #define MASK_MCCSRCV (1 << 19) 150 #define MASK_MRBSYE (1 << 17) 151 #define MASK_MCRSPE (1 << 16) 152 #define MASK_MCMDVIO (1 << 15) 153 #define MASK_MBUFVIO (1 << 14) 154 #define MASK_MWDATERR (1 << 11) 155 #define MASK_MRDATERR (1 << 10) 156 #define MASK_MRIDXERR (1 << 9) 157 #define MASK_MRSPERR (1 << 8) 158 #define MASK_MCCSTO (1 << 5) 159 #define MASK_MCRCSTO (1 << 4) 160 #define MASK_MWDATTO (1 << 3) 161 #define MASK_MRDATTO (1 << 2) 162 #define MASK_MRBSYTO (1 << 1) 163 #define MASK_MRSPTO (1 << 0) 164 165 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 166 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 167 MASK_MCRCSTO | MASK_MWDATTO | \ 168 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 169 170 #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 171 MASK_MBUFREN | MASK_MBUFWEN | \ 172 MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 173 MASK_MCMD12RBE | MASK_MCMD12CRE) 174 175 /* CE_HOST_STS1 */ 176 #define STS1_CMDSEQ (1 << 31) 177 178 /* CE_HOST_STS2 */ 179 #define STS2_CRCSTE (1 << 31) 180 #define STS2_CRC16E (1 << 30) 181 #define STS2_AC12CRCE (1 << 29) 182 #define STS2_RSPCRC7E (1 << 28) 183 #define STS2_CRCSTEBE (1 << 27) 184 #define STS2_RDATEBE (1 << 26) 185 #define STS2_AC12REBE (1 << 25) 186 #define STS2_RSPEBE (1 << 24) 187 #define STS2_AC12IDXE (1 << 23) 188 #define STS2_RSPIDXE (1 << 22) 189 #define STS2_CCSTO (1 << 15) 190 #define STS2_RDATTO (1 << 14) 191 #define STS2_DATBSYTO (1 << 13) 192 #define STS2_CRCSTTO (1 << 12) 193 #define STS2_AC12BSYTO (1 << 11) 194 #define STS2_RSPBSYTO (1 << 10) 195 #define STS2_AC12RSPTO (1 << 9) 196 #define STS2_RSPTO (1 << 8) 197 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 198 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 199 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 200 STS2_DATBSYTO | STS2_CRCSTTO | \ 201 STS2_AC12BSYTO | STS2_RSPBSYTO | \ 202 STS2_AC12RSPTO | STS2_RSPTO) 203 204 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 205 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 206 #define CLKDEV_INIT 400000 /* 400 KHz */ 207 208 enum mmcif_state { 209 STATE_IDLE, 210 STATE_REQUEST, 211 STATE_IOS, 212 STATE_TIMEOUT, 213 }; 214 215 enum mmcif_wait_for { 216 MMCIF_WAIT_FOR_REQUEST, 217 MMCIF_WAIT_FOR_CMD, 218 MMCIF_WAIT_FOR_MREAD, 219 MMCIF_WAIT_FOR_MWRITE, 220 MMCIF_WAIT_FOR_READ, 221 MMCIF_WAIT_FOR_WRITE, 222 MMCIF_WAIT_FOR_READ_END, 223 MMCIF_WAIT_FOR_WRITE_END, 224 MMCIF_WAIT_FOR_STOP, 225 }; 226 227 struct sh_mmcif_host { 228 struct mmc_host *mmc; 229 struct mmc_request *mrq; 230 struct platform_device *pd; 231 struct clk *hclk; 232 unsigned int clk; 233 int bus_width; 234 unsigned char timing; 235 bool sd_error; 236 bool dying; 237 long timeout; 238 void __iomem *addr; 239 u32 *pio_ptr; 240 spinlock_t lock; /* protect sh_mmcif_host::state */ 241 enum mmcif_state state; 242 enum mmcif_wait_for wait_for; 243 struct delayed_work timeout_work; 244 size_t blocksize; 245 int sg_idx; 246 int sg_blkidx; 247 bool power; 248 bool card_present; 249 bool ccs_enable; /* Command Completion Signal support */ 250 bool clk_ctrl2_enable; 251 struct mutex thread_lock; 252 253 /* DMA support */ 254 struct dma_chan *chan_rx; 255 struct dma_chan *chan_tx; 256 struct completion dma_complete; 257 bool dma_active; 258 }; 259 260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 261 unsigned int reg, u32 val) 262 { 263 writel(val | readl(host->addr + reg), host->addr + reg); 264 } 265 266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 267 unsigned int reg, u32 val) 268 { 269 writel(~val & readl(host->addr + reg), host->addr + reg); 270 } 271 272 static void mmcif_dma_complete(void *arg) 273 { 274 struct sh_mmcif_host *host = arg; 275 struct mmc_request *mrq = host->mrq; 276 277 dev_dbg(&host->pd->dev, "Command completed\n"); 278 279 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 280 dev_name(&host->pd->dev))) 281 return; 282 283 complete(&host->dma_complete); 284 } 285 286 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 287 { 288 struct mmc_data *data = host->mrq->data; 289 struct scatterlist *sg = data->sg; 290 struct dma_async_tx_descriptor *desc = NULL; 291 struct dma_chan *chan = host->chan_rx; 292 dma_cookie_t cookie = -EINVAL; 293 int ret; 294 295 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 296 DMA_FROM_DEVICE); 297 if (ret > 0) { 298 host->dma_active = true; 299 desc = dmaengine_prep_slave_sg(chan, sg, ret, 300 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 301 } 302 303 if (desc) { 304 desc->callback = mmcif_dma_complete; 305 desc->callback_param = host; 306 cookie = dmaengine_submit(desc); 307 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 308 dma_async_issue_pending(chan); 309 } 310 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 311 __func__, data->sg_len, ret, cookie); 312 313 if (!desc) { 314 /* DMA failed, fall back to PIO */ 315 if (ret >= 0) 316 ret = -EIO; 317 host->chan_rx = NULL; 318 host->dma_active = false; 319 dma_release_channel(chan); 320 /* Free the Tx channel too */ 321 chan = host->chan_tx; 322 if (chan) { 323 host->chan_tx = NULL; 324 dma_release_channel(chan); 325 } 326 dev_warn(&host->pd->dev, 327 "DMA failed: %d, falling back to PIO\n", ret); 328 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 329 } 330 331 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 332 desc, cookie, data->sg_len); 333 } 334 335 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 336 { 337 struct mmc_data *data = host->mrq->data; 338 struct scatterlist *sg = data->sg; 339 struct dma_async_tx_descriptor *desc = NULL; 340 struct dma_chan *chan = host->chan_tx; 341 dma_cookie_t cookie = -EINVAL; 342 int ret; 343 344 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 345 DMA_TO_DEVICE); 346 if (ret > 0) { 347 host->dma_active = true; 348 desc = dmaengine_prep_slave_sg(chan, sg, ret, 349 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 350 } 351 352 if (desc) { 353 desc->callback = mmcif_dma_complete; 354 desc->callback_param = host; 355 cookie = dmaengine_submit(desc); 356 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 357 dma_async_issue_pending(chan); 358 } 359 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 360 __func__, data->sg_len, ret, cookie); 361 362 if (!desc) { 363 /* DMA failed, fall back to PIO */ 364 if (ret >= 0) 365 ret = -EIO; 366 host->chan_tx = NULL; 367 host->dma_active = false; 368 dma_release_channel(chan); 369 /* Free the Rx channel too */ 370 chan = host->chan_rx; 371 if (chan) { 372 host->chan_rx = NULL; 373 dma_release_channel(chan); 374 } 375 dev_warn(&host->pd->dev, 376 "DMA failed: %d, falling back to PIO\n", ret); 377 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 378 } 379 380 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 381 desc, cookie); 382 } 383 384 static struct dma_chan * 385 sh_mmcif_request_dma_one(struct sh_mmcif_host *host, 386 struct sh_mmcif_plat_data *pdata, 387 enum dma_transfer_direction direction) 388 { 389 struct dma_slave_config cfg = { 0, }; 390 struct dma_chan *chan; 391 unsigned int slave_id; 392 struct resource *res; 393 dma_cap_mask_t mask; 394 int ret; 395 396 dma_cap_zero(mask); 397 dma_cap_set(DMA_SLAVE, mask); 398 399 if (pdata) 400 slave_id = direction == DMA_MEM_TO_DEV 401 ? pdata->slave_id_tx : pdata->slave_id_rx; 402 else 403 slave_id = 0; 404 405 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 406 (void *)(unsigned long)slave_id, &host->pd->dev, 407 direction == DMA_MEM_TO_DEV ? "tx" : "rx"); 408 409 dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__, 410 direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); 411 412 if (!chan) 413 return NULL; 414 415 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 416 417 /* In the OF case the driver will get the slave ID from the DT */ 418 cfg.slave_id = slave_id; 419 cfg.direction = direction; 420 421 if (direction == DMA_DEV_TO_MEM) { 422 cfg.src_addr = res->start + MMCIF_CE_DATA; 423 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 424 } else { 425 cfg.dst_addr = res->start + MMCIF_CE_DATA; 426 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 427 } 428 429 ret = dmaengine_slave_config(chan, &cfg); 430 if (ret < 0) { 431 dma_release_channel(chan); 432 return NULL; 433 } 434 435 return chan; 436 } 437 438 static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 439 struct sh_mmcif_plat_data *pdata) 440 { 441 host->dma_active = false; 442 443 if (pdata) { 444 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 445 return; 446 } else if (!host->pd->dev.of_node) { 447 return; 448 } 449 450 /* We can only either use DMA for both Tx and Rx or not use it at all */ 451 host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); 452 if (!host->chan_tx) 453 return; 454 455 host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); 456 if (!host->chan_rx) { 457 dma_release_channel(host->chan_tx); 458 host->chan_tx = NULL; 459 } 460 } 461 462 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 463 { 464 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 465 /* Descriptors are freed automatically */ 466 if (host->chan_tx) { 467 struct dma_chan *chan = host->chan_tx; 468 host->chan_tx = NULL; 469 dma_release_channel(chan); 470 } 471 if (host->chan_rx) { 472 struct dma_chan *chan = host->chan_rx; 473 host->chan_rx = NULL; 474 dma_release_channel(chan); 475 } 476 477 host->dma_active = false; 478 } 479 480 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 481 { 482 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 483 bool sup_pclk = p ? p->sup_pclk : false; 484 485 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 486 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 487 488 if (!clk) 489 return; 490 if (sup_pclk && clk == host->clk) 491 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 492 else 493 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 494 ((fls(DIV_ROUND_UP(host->clk, 495 clk) - 1) - 1) << 16)); 496 497 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 498 } 499 500 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 501 { 502 u32 tmp; 503 504 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 505 506 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 507 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 508 if (host->ccs_enable) 509 tmp |= SCCSTO_29; 510 if (host->clk_ctrl2_enable) 511 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 512 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 513 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 514 /* byte swap on */ 515 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 516 } 517 518 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 519 { 520 u32 state1, state2; 521 int ret, timeout; 522 523 host->sd_error = false; 524 525 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 526 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 527 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 528 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 529 530 if (state1 & STS1_CMDSEQ) { 531 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 532 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 533 for (timeout = 10000000; timeout; timeout--) { 534 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 535 & STS1_CMDSEQ)) 536 break; 537 mdelay(1); 538 } 539 if (!timeout) { 540 dev_err(&host->pd->dev, 541 "Forced end of command sequence timeout err\n"); 542 return -EIO; 543 } 544 sh_mmcif_sync_reset(host); 545 dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 546 return -EIO; 547 } 548 549 if (state2 & STS2_CRC_ERR) { 550 dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", 551 host->state, host->wait_for); 552 ret = -EIO; 553 } else if (state2 & STS2_TIMEOUT_ERR) { 554 dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", 555 host->state, host->wait_for); 556 ret = -ETIMEDOUT; 557 } else { 558 dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", 559 host->state, host->wait_for); 560 ret = -EIO; 561 } 562 return ret; 563 } 564 565 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 566 { 567 struct mmc_data *data = host->mrq->data; 568 569 host->sg_blkidx += host->blocksize; 570 571 /* data->sg->length must be a multiple of host->blocksize? */ 572 BUG_ON(host->sg_blkidx > data->sg->length); 573 574 if (host->sg_blkidx == data->sg->length) { 575 host->sg_blkidx = 0; 576 if (++host->sg_idx < data->sg_len) 577 host->pio_ptr = sg_virt(++data->sg); 578 } else { 579 host->pio_ptr = p; 580 } 581 582 return host->sg_idx != data->sg_len; 583 } 584 585 static void sh_mmcif_single_read(struct sh_mmcif_host *host, 586 struct mmc_request *mrq) 587 { 588 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 589 BLOCK_SIZE_MASK) + 3; 590 591 host->wait_for = MMCIF_WAIT_FOR_READ; 592 593 /* buf read enable */ 594 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 595 } 596 597 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 598 { 599 struct mmc_data *data = host->mrq->data; 600 u32 *p = sg_virt(data->sg); 601 int i; 602 603 if (host->sd_error) { 604 data->error = sh_mmcif_error_manage(host); 605 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 606 return false; 607 } 608 609 for (i = 0; i < host->blocksize / 4; i++) 610 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 611 612 /* buffer read end */ 613 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 614 host->wait_for = MMCIF_WAIT_FOR_READ_END; 615 616 return true; 617 } 618 619 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 620 struct mmc_request *mrq) 621 { 622 struct mmc_data *data = mrq->data; 623 624 if (!data->sg_len || !data->sg->length) 625 return; 626 627 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 628 BLOCK_SIZE_MASK; 629 630 host->wait_for = MMCIF_WAIT_FOR_MREAD; 631 host->sg_idx = 0; 632 host->sg_blkidx = 0; 633 host->pio_ptr = sg_virt(data->sg); 634 635 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 636 } 637 638 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 639 { 640 struct mmc_data *data = host->mrq->data; 641 u32 *p = host->pio_ptr; 642 int i; 643 644 if (host->sd_error) { 645 data->error = sh_mmcif_error_manage(host); 646 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 647 return false; 648 } 649 650 BUG_ON(!data->sg->length); 651 652 for (i = 0; i < host->blocksize / 4; i++) 653 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 654 655 if (!sh_mmcif_next_block(host, p)) 656 return false; 657 658 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 659 660 return true; 661 } 662 663 static void sh_mmcif_single_write(struct sh_mmcif_host *host, 664 struct mmc_request *mrq) 665 { 666 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 667 BLOCK_SIZE_MASK) + 3; 668 669 host->wait_for = MMCIF_WAIT_FOR_WRITE; 670 671 /* buf write enable */ 672 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 673 } 674 675 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 676 { 677 struct mmc_data *data = host->mrq->data; 678 u32 *p = sg_virt(data->sg); 679 int i; 680 681 if (host->sd_error) { 682 data->error = sh_mmcif_error_manage(host); 683 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 684 return false; 685 } 686 687 for (i = 0; i < host->blocksize / 4; i++) 688 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 689 690 /* buffer write end */ 691 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 692 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 693 694 return true; 695 } 696 697 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 698 struct mmc_request *mrq) 699 { 700 struct mmc_data *data = mrq->data; 701 702 if (!data->sg_len || !data->sg->length) 703 return; 704 705 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 706 BLOCK_SIZE_MASK; 707 708 host->wait_for = MMCIF_WAIT_FOR_MWRITE; 709 host->sg_idx = 0; 710 host->sg_blkidx = 0; 711 host->pio_ptr = sg_virt(data->sg); 712 713 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 714 } 715 716 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 717 { 718 struct mmc_data *data = host->mrq->data; 719 u32 *p = host->pio_ptr; 720 int i; 721 722 if (host->sd_error) { 723 data->error = sh_mmcif_error_manage(host); 724 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 725 return false; 726 } 727 728 BUG_ON(!data->sg->length); 729 730 for (i = 0; i < host->blocksize / 4; i++) 731 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 732 733 if (!sh_mmcif_next_block(host, p)) 734 return false; 735 736 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 737 738 return true; 739 } 740 741 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 742 struct mmc_command *cmd) 743 { 744 if (cmd->flags & MMC_RSP_136) { 745 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 746 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 747 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 748 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 749 } else 750 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 751 } 752 753 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 754 struct mmc_command *cmd) 755 { 756 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 757 } 758 759 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 760 struct mmc_request *mrq) 761 { 762 struct mmc_data *data = mrq->data; 763 struct mmc_command *cmd = mrq->cmd; 764 u32 opc = cmd->opcode; 765 u32 tmp = 0; 766 767 /* Response Type check */ 768 switch (mmc_resp_type(cmd)) { 769 case MMC_RSP_NONE: 770 tmp |= CMD_SET_RTYP_NO; 771 break; 772 case MMC_RSP_R1: 773 case MMC_RSP_R1B: 774 case MMC_RSP_R3: 775 tmp |= CMD_SET_RTYP_6B; 776 break; 777 case MMC_RSP_R2: 778 tmp |= CMD_SET_RTYP_17B; 779 break; 780 default: 781 dev_err(&host->pd->dev, "Unsupported response type.\n"); 782 break; 783 } 784 switch (opc) { 785 /* RBSY */ 786 case MMC_SLEEP_AWAKE: 787 case MMC_SWITCH: 788 case MMC_STOP_TRANSMISSION: 789 case MMC_SET_WRITE_PROT: 790 case MMC_CLR_WRITE_PROT: 791 case MMC_ERASE: 792 tmp |= CMD_SET_RBSY; 793 break; 794 } 795 /* WDAT / DATW */ 796 if (data) { 797 tmp |= CMD_SET_WDAT; 798 switch (host->bus_width) { 799 case MMC_BUS_WIDTH_1: 800 tmp |= CMD_SET_DATW_1; 801 break; 802 case MMC_BUS_WIDTH_4: 803 tmp |= CMD_SET_DATW_4; 804 break; 805 case MMC_BUS_WIDTH_8: 806 tmp |= CMD_SET_DATW_8; 807 break; 808 default: 809 dev_err(&host->pd->dev, "Unsupported bus width.\n"); 810 break; 811 } 812 switch (host->timing) { 813 case MMC_TIMING_MMC_DDR52: 814 /* 815 * MMC core will only set this timing, if the host 816 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 817 * capability. MMCIF implementations with this 818 * capability, e.g. sh73a0, will have to set it 819 * in their platform data. 820 */ 821 tmp |= CMD_SET_DARS; 822 break; 823 } 824 } 825 /* DWEN */ 826 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 827 tmp |= CMD_SET_DWEN; 828 /* CMLTE/CMD12EN */ 829 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 830 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 831 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 832 data->blocks << 16); 833 } 834 /* RIDXC[1:0] check bits */ 835 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 836 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 837 tmp |= CMD_SET_RIDXC_BITS; 838 /* RCRC7C[1:0] check bits */ 839 if (opc == MMC_SEND_OP_COND) 840 tmp |= CMD_SET_CRC7C_BITS; 841 /* RCRC7C[1:0] internal CRC7 */ 842 if (opc == MMC_ALL_SEND_CID || 843 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 844 tmp |= CMD_SET_CRC7C_INTERNAL; 845 846 return (opc << 24) | tmp; 847 } 848 849 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 850 struct mmc_request *mrq, u32 opc) 851 { 852 switch (opc) { 853 case MMC_READ_MULTIPLE_BLOCK: 854 sh_mmcif_multi_read(host, mrq); 855 return 0; 856 case MMC_WRITE_MULTIPLE_BLOCK: 857 sh_mmcif_multi_write(host, mrq); 858 return 0; 859 case MMC_WRITE_BLOCK: 860 sh_mmcif_single_write(host, mrq); 861 return 0; 862 case MMC_READ_SINGLE_BLOCK: 863 case MMC_SEND_EXT_CSD: 864 sh_mmcif_single_read(host, mrq); 865 return 0; 866 default: 867 dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); 868 return -EINVAL; 869 } 870 } 871 872 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 873 struct mmc_request *mrq) 874 { 875 struct mmc_command *cmd = mrq->cmd; 876 u32 opc = cmd->opcode; 877 u32 mask; 878 unsigned long flags; 879 880 switch (opc) { 881 /* response busy check */ 882 case MMC_SLEEP_AWAKE: 883 case MMC_SWITCH: 884 case MMC_STOP_TRANSMISSION: 885 case MMC_SET_WRITE_PROT: 886 case MMC_CLR_WRITE_PROT: 887 case MMC_ERASE: 888 mask = MASK_START_CMD | MASK_MRBSYE; 889 break; 890 default: 891 mask = MASK_START_CMD | MASK_MCRSPE; 892 break; 893 } 894 895 if (host->ccs_enable) 896 mask |= MASK_MCCSTO; 897 898 if (mrq->data) { 899 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 900 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 901 mrq->data->blksz); 902 } 903 opc = sh_mmcif_set_cmd(host, mrq); 904 905 if (host->ccs_enable) 906 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 907 else 908 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 909 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 910 /* set arg */ 911 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 912 /* set cmd */ 913 spin_lock_irqsave(&host->lock, flags); 914 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 915 916 host->wait_for = MMCIF_WAIT_FOR_CMD; 917 schedule_delayed_work(&host->timeout_work, host->timeout); 918 spin_unlock_irqrestore(&host->lock, flags); 919 } 920 921 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 922 struct mmc_request *mrq) 923 { 924 switch (mrq->cmd->opcode) { 925 case MMC_READ_MULTIPLE_BLOCK: 926 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 927 break; 928 case MMC_WRITE_MULTIPLE_BLOCK: 929 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 930 break; 931 default: 932 dev_err(&host->pd->dev, "unsupported stop cmd\n"); 933 mrq->stop->error = sh_mmcif_error_manage(host); 934 return; 935 } 936 937 host->wait_for = MMCIF_WAIT_FOR_STOP; 938 } 939 940 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 941 { 942 struct sh_mmcif_host *host = mmc_priv(mmc); 943 unsigned long flags; 944 945 spin_lock_irqsave(&host->lock, flags); 946 if (host->state != STATE_IDLE) { 947 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 948 spin_unlock_irqrestore(&host->lock, flags); 949 mrq->cmd->error = -EAGAIN; 950 mmc_request_done(mmc, mrq); 951 return; 952 } 953 954 host->state = STATE_REQUEST; 955 spin_unlock_irqrestore(&host->lock, flags); 956 957 switch (mrq->cmd->opcode) { 958 /* MMCIF does not support SD/SDIO command */ 959 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 960 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 961 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 962 break; 963 case MMC_APP_CMD: 964 case SD_IO_RW_DIRECT: 965 host->state = STATE_IDLE; 966 mrq->cmd->error = -ETIMEDOUT; 967 mmc_request_done(mmc, mrq); 968 return; 969 default: 970 break; 971 } 972 973 host->mrq = mrq; 974 975 sh_mmcif_start_cmd(host, mrq); 976 } 977 978 static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 979 { 980 int ret = clk_prepare_enable(host->hclk); 981 982 if (!ret) { 983 host->clk = clk_get_rate(host->hclk); 984 host->mmc->f_max = host->clk / 2; 985 host->mmc->f_min = host->clk / 512; 986 } 987 988 return ret; 989 } 990 991 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 992 { 993 struct mmc_host *mmc = host->mmc; 994 995 if (!IS_ERR(mmc->supply.vmmc)) 996 /* Errors ignored... */ 997 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 998 ios->power_mode ? ios->vdd : 0); 999 } 1000 1001 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1002 { 1003 struct sh_mmcif_host *host = mmc_priv(mmc); 1004 unsigned long flags; 1005 1006 spin_lock_irqsave(&host->lock, flags); 1007 if (host->state != STATE_IDLE) { 1008 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 1009 spin_unlock_irqrestore(&host->lock, flags); 1010 return; 1011 } 1012 1013 host->state = STATE_IOS; 1014 spin_unlock_irqrestore(&host->lock, flags); 1015 1016 if (ios->power_mode == MMC_POWER_UP) { 1017 if (!host->card_present) { 1018 /* See if we also get DMA */ 1019 sh_mmcif_request_dma(host, host->pd->dev.platform_data); 1020 host->card_present = true; 1021 } 1022 sh_mmcif_set_power(host, ios); 1023 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 1024 /* clock stop */ 1025 sh_mmcif_clock_control(host, 0); 1026 if (ios->power_mode == MMC_POWER_OFF) { 1027 if (host->card_present) { 1028 sh_mmcif_release_dma(host); 1029 host->card_present = false; 1030 } 1031 } 1032 if (host->power) { 1033 pm_runtime_put_sync(&host->pd->dev); 1034 clk_disable_unprepare(host->hclk); 1035 host->power = false; 1036 if (ios->power_mode == MMC_POWER_OFF) 1037 sh_mmcif_set_power(host, ios); 1038 } 1039 host->state = STATE_IDLE; 1040 return; 1041 } 1042 1043 if (ios->clock) { 1044 if (!host->power) { 1045 sh_mmcif_clk_update(host); 1046 pm_runtime_get_sync(&host->pd->dev); 1047 host->power = true; 1048 sh_mmcif_sync_reset(host); 1049 } 1050 sh_mmcif_clock_control(host, ios->clock); 1051 } 1052 1053 host->timing = ios->timing; 1054 host->bus_width = ios->bus_width; 1055 host->state = STATE_IDLE; 1056 } 1057 1058 static int sh_mmcif_get_cd(struct mmc_host *mmc) 1059 { 1060 struct sh_mmcif_host *host = mmc_priv(mmc); 1061 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1062 int ret = mmc_gpio_get_cd(mmc); 1063 1064 if (ret >= 0) 1065 return ret; 1066 1067 if (!p || !p->get_cd) 1068 return -ENOSYS; 1069 else 1070 return p->get_cd(host->pd); 1071 } 1072 1073 static struct mmc_host_ops sh_mmcif_ops = { 1074 .request = sh_mmcif_request, 1075 .set_ios = sh_mmcif_set_ios, 1076 .get_cd = sh_mmcif_get_cd, 1077 }; 1078 1079 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1080 { 1081 struct mmc_command *cmd = host->mrq->cmd; 1082 struct mmc_data *data = host->mrq->data; 1083 long time; 1084 1085 if (host->sd_error) { 1086 switch (cmd->opcode) { 1087 case MMC_ALL_SEND_CID: 1088 case MMC_SELECT_CARD: 1089 case MMC_APP_CMD: 1090 cmd->error = -ETIMEDOUT; 1091 break; 1092 default: 1093 cmd->error = sh_mmcif_error_manage(host); 1094 break; 1095 } 1096 dev_dbg(&host->pd->dev, "CMD%d error %d\n", 1097 cmd->opcode, cmd->error); 1098 host->sd_error = false; 1099 return false; 1100 } 1101 if (!(cmd->flags & MMC_RSP_PRESENT)) { 1102 cmd->error = 0; 1103 return false; 1104 } 1105 1106 sh_mmcif_get_response(host, cmd); 1107 1108 if (!data) 1109 return false; 1110 1111 /* 1112 * Completion can be signalled from DMA callback and error, so, have to 1113 * reset here, before setting .dma_active 1114 */ 1115 init_completion(&host->dma_complete); 1116 1117 if (data->flags & MMC_DATA_READ) { 1118 if (host->chan_rx) 1119 sh_mmcif_start_dma_rx(host); 1120 } else { 1121 if (host->chan_tx) 1122 sh_mmcif_start_dma_tx(host); 1123 } 1124 1125 if (!host->dma_active) { 1126 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 1127 return !data->error; 1128 } 1129 1130 /* Running in the IRQ thread, can sleep */ 1131 time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1132 host->timeout); 1133 1134 if (data->flags & MMC_DATA_READ) 1135 dma_unmap_sg(host->chan_rx->device->dev, 1136 data->sg, data->sg_len, 1137 DMA_FROM_DEVICE); 1138 else 1139 dma_unmap_sg(host->chan_tx->device->dev, 1140 data->sg, data->sg_len, 1141 DMA_TO_DEVICE); 1142 1143 if (host->sd_error) { 1144 dev_err(host->mmc->parent, 1145 "Error IRQ while waiting for DMA completion!\n"); 1146 /* Woken up by an error IRQ: abort DMA */ 1147 data->error = sh_mmcif_error_manage(host); 1148 } else if (!time) { 1149 dev_err(host->mmc->parent, "DMA timeout!\n"); 1150 data->error = -ETIMEDOUT; 1151 } else if (time < 0) { 1152 dev_err(host->mmc->parent, 1153 "wait_for_completion_...() error %ld!\n", time); 1154 data->error = time; 1155 } 1156 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1157 BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1158 host->dma_active = false; 1159 1160 if (data->error) { 1161 data->bytes_xfered = 0; 1162 /* Abort DMA */ 1163 if (data->flags & MMC_DATA_READ) 1164 dmaengine_terminate_all(host->chan_rx); 1165 else 1166 dmaengine_terminate_all(host->chan_tx); 1167 } 1168 1169 return false; 1170 } 1171 1172 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1173 { 1174 struct sh_mmcif_host *host = dev_id; 1175 struct mmc_request *mrq; 1176 bool wait = false; 1177 unsigned long flags; 1178 int wait_work; 1179 1180 spin_lock_irqsave(&host->lock, flags); 1181 wait_work = host->wait_for; 1182 spin_unlock_irqrestore(&host->lock, flags); 1183 1184 cancel_delayed_work_sync(&host->timeout_work); 1185 1186 mutex_lock(&host->thread_lock); 1187 1188 mrq = host->mrq; 1189 if (!mrq) { 1190 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 1191 host->state, host->wait_for); 1192 mutex_unlock(&host->thread_lock); 1193 return IRQ_HANDLED; 1194 } 1195 1196 /* 1197 * All handlers return true, if processing continues, and false, if the 1198 * request has to be completed - successfully or not 1199 */ 1200 switch (wait_work) { 1201 case MMCIF_WAIT_FOR_REQUEST: 1202 /* We're too late, the timeout has already kicked in */ 1203 mutex_unlock(&host->thread_lock); 1204 return IRQ_HANDLED; 1205 case MMCIF_WAIT_FOR_CMD: 1206 /* Wait for data? */ 1207 wait = sh_mmcif_end_cmd(host); 1208 break; 1209 case MMCIF_WAIT_FOR_MREAD: 1210 /* Wait for more data? */ 1211 wait = sh_mmcif_mread_block(host); 1212 break; 1213 case MMCIF_WAIT_FOR_READ: 1214 /* Wait for data end? */ 1215 wait = sh_mmcif_read_block(host); 1216 break; 1217 case MMCIF_WAIT_FOR_MWRITE: 1218 /* Wait data to write? */ 1219 wait = sh_mmcif_mwrite_block(host); 1220 break; 1221 case MMCIF_WAIT_FOR_WRITE: 1222 /* Wait for data end? */ 1223 wait = sh_mmcif_write_block(host); 1224 break; 1225 case MMCIF_WAIT_FOR_STOP: 1226 if (host->sd_error) { 1227 mrq->stop->error = sh_mmcif_error_manage(host); 1228 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); 1229 break; 1230 } 1231 sh_mmcif_get_cmd12response(host, mrq->stop); 1232 mrq->stop->error = 0; 1233 break; 1234 case MMCIF_WAIT_FOR_READ_END: 1235 case MMCIF_WAIT_FOR_WRITE_END: 1236 if (host->sd_error) { 1237 mrq->data->error = sh_mmcif_error_manage(host); 1238 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); 1239 } 1240 break; 1241 default: 1242 BUG(); 1243 } 1244 1245 if (wait) { 1246 schedule_delayed_work(&host->timeout_work, host->timeout); 1247 /* Wait for more data */ 1248 mutex_unlock(&host->thread_lock); 1249 return IRQ_HANDLED; 1250 } 1251 1252 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 1253 struct mmc_data *data = mrq->data; 1254 if (!mrq->cmd->error && data && !data->error) 1255 data->bytes_xfered = 1256 data->blocks * data->blksz; 1257 1258 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1259 sh_mmcif_stop_cmd(host, mrq); 1260 if (!mrq->stop->error) { 1261 schedule_delayed_work(&host->timeout_work, host->timeout); 1262 mutex_unlock(&host->thread_lock); 1263 return IRQ_HANDLED; 1264 } 1265 } 1266 } 1267 1268 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1269 host->state = STATE_IDLE; 1270 host->mrq = NULL; 1271 mmc_request_done(host->mmc, mrq); 1272 1273 mutex_unlock(&host->thread_lock); 1274 1275 return IRQ_HANDLED; 1276 } 1277 1278 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1279 { 1280 struct sh_mmcif_host *host = dev_id; 1281 u32 state, mask; 1282 1283 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1284 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1285 if (host->ccs_enable) 1286 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1287 else 1288 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 1289 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1290 1291 if (state & ~MASK_CLEAN) 1292 dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", 1293 state); 1294 1295 if (state & INT_ERR_STS || state & ~INT_ALL) { 1296 host->sd_error = true; 1297 dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); 1298 } 1299 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1300 if (!host->mrq) 1301 dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); 1302 if (!host->dma_active) 1303 return IRQ_WAKE_THREAD; 1304 else if (host->sd_error) 1305 mmcif_dma_complete(host); 1306 } else { 1307 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1308 } 1309 1310 return IRQ_HANDLED; 1311 } 1312 1313 static void mmcif_timeout_work(struct work_struct *work) 1314 { 1315 struct delayed_work *d = container_of(work, struct delayed_work, work); 1316 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1317 struct mmc_request *mrq = host->mrq; 1318 unsigned long flags; 1319 1320 if (host->dying) 1321 /* Don't run after mmc_remove_host() */ 1322 return; 1323 1324 spin_lock_irqsave(&host->lock, flags); 1325 if (host->state == STATE_IDLE) { 1326 spin_unlock_irqrestore(&host->lock, flags); 1327 return; 1328 } 1329 1330 dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", 1331 host->wait_for, mrq->cmd->opcode); 1332 1333 host->state = STATE_TIMEOUT; 1334 spin_unlock_irqrestore(&host->lock, flags); 1335 1336 /* 1337 * Handle races with cancel_delayed_work(), unless 1338 * cancel_delayed_work_sync() is used 1339 */ 1340 switch (host->wait_for) { 1341 case MMCIF_WAIT_FOR_CMD: 1342 mrq->cmd->error = sh_mmcif_error_manage(host); 1343 break; 1344 case MMCIF_WAIT_FOR_STOP: 1345 mrq->stop->error = sh_mmcif_error_manage(host); 1346 break; 1347 case MMCIF_WAIT_FOR_MREAD: 1348 case MMCIF_WAIT_FOR_MWRITE: 1349 case MMCIF_WAIT_FOR_READ: 1350 case MMCIF_WAIT_FOR_WRITE: 1351 case MMCIF_WAIT_FOR_READ_END: 1352 case MMCIF_WAIT_FOR_WRITE_END: 1353 mrq->data->error = sh_mmcif_error_manage(host); 1354 break; 1355 default: 1356 BUG(); 1357 } 1358 1359 host->state = STATE_IDLE; 1360 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1361 host->mrq = NULL; 1362 mmc_request_done(host->mmc, mrq); 1363 } 1364 1365 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 1366 { 1367 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 1368 struct mmc_host *mmc = host->mmc; 1369 1370 mmc_regulator_get_supply(mmc); 1371 1372 if (!pd) 1373 return; 1374 1375 if (!mmc->ocr_avail) 1376 mmc->ocr_avail = pd->ocr; 1377 else if (pd->ocr) 1378 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1379 } 1380 1381 static int sh_mmcif_probe(struct platform_device *pdev) 1382 { 1383 int ret = 0, irq[2]; 1384 struct mmc_host *mmc; 1385 struct sh_mmcif_host *host; 1386 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1387 struct resource *res; 1388 void __iomem *reg; 1389 const char *name; 1390 1391 irq[0] = platform_get_irq(pdev, 0); 1392 irq[1] = platform_get_irq(pdev, 1); 1393 if (irq[0] < 0) { 1394 dev_err(&pdev->dev, "Get irq error\n"); 1395 return -ENXIO; 1396 } 1397 1398 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1399 reg = devm_ioremap_resource(&pdev->dev, res); 1400 if (IS_ERR(reg)) 1401 return PTR_ERR(reg); 1402 1403 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1404 if (!mmc) 1405 return -ENOMEM; 1406 1407 ret = mmc_of_parse(mmc); 1408 if (ret < 0) 1409 goto err_host; 1410 1411 host = mmc_priv(mmc); 1412 host->mmc = mmc; 1413 host->addr = reg; 1414 host->timeout = msecs_to_jiffies(1000); 1415 host->ccs_enable = !pd || !pd->ccs_unsupported; 1416 host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; 1417 1418 host->pd = pdev; 1419 1420 spin_lock_init(&host->lock); 1421 1422 mmc->ops = &sh_mmcif_ops; 1423 sh_mmcif_init_ocr(host); 1424 1425 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1426 if (pd && pd->caps) 1427 mmc->caps |= pd->caps; 1428 mmc->max_segs = 32; 1429 mmc->max_blk_size = 512; 1430 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1431 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1432 mmc->max_seg_size = mmc->max_req_size; 1433 1434 platform_set_drvdata(pdev, host); 1435 1436 pm_runtime_enable(&pdev->dev); 1437 host->power = false; 1438 1439 host->hclk = devm_clk_get(&pdev->dev, NULL); 1440 if (IS_ERR(host->hclk)) { 1441 ret = PTR_ERR(host->hclk); 1442 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 1443 goto err_pm; 1444 } 1445 ret = sh_mmcif_clk_update(host); 1446 if (ret < 0) 1447 goto err_pm; 1448 1449 ret = pm_runtime_resume(&pdev->dev); 1450 if (ret < 0) 1451 goto err_clk; 1452 1453 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1454 1455 sh_mmcif_sync_reset(host); 1456 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1457 1458 name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; 1459 ret = devm_request_threaded_irq(&pdev->dev, irq[0], sh_mmcif_intr, 1460 sh_mmcif_irqt, 0, name, host); 1461 if (ret) { 1462 dev_err(&pdev->dev, "request_irq error (%s)\n", name); 1463 goto err_clk; 1464 } 1465 if (irq[1] >= 0) { 1466 ret = devm_request_threaded_irq(&pdev->dev, irq[1], 1467 sh_mmcif_intr, sh_mmcif_irqt, 1468 0, "sh_mmc:int", host); 1469 if (ret) { 1470 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1471 goto err_clk; 1472 } 1473 } 1474 1475 if (pd && pd->use_cd_gpio) { 1476 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); 1477 if (ret < 0) 1478 goto err_clk; 1479 } 1480 1481 mutex_init(&host->thread_lock); 1482 1483 ret = mmc_add_host(mmc); 1484 if (ret < 0) 1485 goto err_clk; 1486 1487 dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1488 1489 dev_info(&pdev->dev, "Chip version 0x%04x, clock rate %luMHz\n", 1490 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 1491 clk_get_rate(host->hclk) / 1000000UL); 1492 1493 clk_disable_unprepare(host->hclk); 1494 return ret; 1495 1496 err_clk: 1497 clk_disable_unprepare(host->hclk); 1498 err_pm: 1499 pm_runtime_disable(&pdev->dev); 1500 err_host: 1501 mmc_free_host(mmc); 1502 return ret; 1503 } 1504 1505 static int sh_mmcif_remove(struct platform_device *pdev) 1506 { 1507 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1508 1509 host->dying = true; 1510 clk_prepare_enable(host->hclk); 1511 pm_runtime_get_sync(&pdev->dev); 1512 1513 dev_pm_qos_hide_latency_limit(&pdev->dev); 1514 1515 mmc_remove_host(host->mmc); 1516 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1517 1518 /* 1519 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1520 * mmc_remove_host() call above. But swapping order doesn't help either 1521 * (a query on the linux-mmc mailing list didn't bring any replies). 1522 */ 1523 cancel_delayed_work_sync(&host->timeout_work); 1524 1525 clk_disable_unprepare(host->hclk); 1526 mmc_free_host(host->mmc); 1527 pm_runtime_put_sync(&pdev->dev); 1528 pm_runtime_disable(&pdev->dev); 1529 1530 return 0; 1531 } 1532 1533 #ifdef CONFIG_PM_SLEEP 1534 static int sh_mmcif_suspend(struct device *dev) 1535 { 1536 struct sh_mmcif_host *host = dev_get_drvdata(dev); 1537 1538 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1539 1540 return 0; 1541 } 1542 1543 static int sh_mmcif_resume(struct device *dev) 1544 { 1545 return 0; 1546 } 1547 #endif 1548 1549 static const struct of_device_id mmcif_of_match[] = { 1550 { .compatible = "renesas,sh-mmcif" }, 1551 { } 1552 }; 1553 MODULE_DEVICE_TABLE(of, mmcif_of_match); 1554 1555 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1556 SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1557 }; 1558 1559 static struct platform_driver sh_mmcif_driver = { 1560 .probe = sh_mmcif_probe, 1561 .remove = sh_mmcif_remove, 1562 .driver = { 1563 .name = DRIVER_NAME, 1564 .pm = &sh_mmcif_dev_pm_ops, 1565 .of_match_table = mmcif_of_match, 1566 }, 1567 }; 1568 1569 module_platform_driver(sh_mmcif_driver); 1570 1571 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1572 MODULE_LICENSE("GPL"); 1573 MODULE_ALIAS("platform:" DRIVER_NAME); 1574 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1575