1 /* 2 * MMCIF eMMC driver. 3 * 4 * Copyright (C) 2010 Renesas Solutions Corp. 5 * Yusuke Goda <yusuke.goda.sx@renesas.com> 6 * 7 * This program is free software; you can redistribute it and/or modify 8 * it under the terms of the GNU General Public License as published by 9 * the Free Software Foundation; either version 2 of the License. 10 * 11 * 12 * TODO 13 * 1. DMA 14 * 2. Power management 15 * 3. Handle MMC errors better 16 * 17 */ 18 19 /* 20 * The MMCIF driver is now processing MMC requests asynchronously, according 21 * to the Linux MMC API requirement. 22 * 23 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24 * data, and optional stop. To achieve asynchronous processing each of these 25 * stages is split into two halves: a top and a bottom half. The top half 26 * initialises the hardware, installs a timeout handler to handle completion 27 * timeouts, and returns. In case of the command stage this immediately returns 28 * control to the caller, leaving all further processing to run asynchronously. 29 * All further request processing is performed by the bottom halves. 30 * 31 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32 * thread, a DMA completion callback, if DMA is used, a timeout work, and 33 * request- and stage-specific handler methods. 34 * 35 * Each bottom half run begins with either a hardware interrupt, a DMA callback 36 * invocation, or a timeout work run. In case of an error or a successful 37 * processing completion, the MMC core is informed and the request processing is 38 * finished. In case processing has to continue, i.e., if data has to be read 39 * from or written to the card, or if a stop command has to be sent, the next 40 * top half is called, which performs the necessary hardware handling and 41 * reschedules the timeout work. This returns the driver state machine into the 42 * bottom half waiting state. 43 */ 44 45 #include <linux/bitops.h> 46 #include <linux/clk.h> 47 #include <linux/completion.h> 48 #include <linux/delay.h> 49 #include <linux/dma-mapping.h> 50 #include <linux/dmaengine.h> 51 #include <linux/mmc/card.h> 52 #include <linux/mmc/core.h> 53 #include <linux/mmc/host.h> 54 #include <linux/mmc/mmc.h> 55 #include <linux/mmc/sdio.h> 56 #include <linux/mmc/sh_mmcif.h> 57 #include <linux/mmc/slot-gpio.h> 58 #include <linux/mod_devicetable.h> 59 #include <linux/mutex.h> 60 #include <linux/pagemap.h> 61 #include <linux/platform_device.h> 62 #include <linux/pm_qos.h> 63 #include <linux/pm_runtime.h> 64 #include <linux/sh_dma.h> 65 #include <linux/spinlock.h> 66 #include <linux/module.h> 67 68 #define DRIVER_NAME "sh_mmcif" 69 #define DRIVER_VERSION "2010-04-28" 70 71 /* CE_CMD_SET */ 72 #define CMD_MASK 0x3f000000 73 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 74 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 75 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 76 #define CMD_SET_RBSY (1 << 21) /* R1b */ 77 #define CMD_SET_CCSEN (1 << 20) 78 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 79 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 80 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 81 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 82 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 83 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 84 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 85 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 86 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 87 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 88 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 89 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 90 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 91 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 92 #define CMD_SET_CCSH (1 << 5) 93 #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 94 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 95 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 96 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 97 98 /* CE_CMD_CTRL */ 99 #define CMD_CTRL_BREAK (1 << 0) 100 101 /* CE_BLOCK_SET */ 102 #define BLOCK_SIZE_MASK 0x0000ffff 103 104 /* CE_INT */ 105 #define INT_CCSDE (1 << 29) 106 #define INT_CMD12DRE (1 << 26) 107 #define INT_CMD12RBE (1 << 25) 108 #define INT_CMD12CRE (1 << 24) 109 #define INT_DTRANE (1 << 23) 110 #define INT_BUFRE (1 << 22) 111 #define INT_BUFWEN (1 << 21) 112 #define INT_BUFREN (1 << 20) 113 #define INT_CCSRCV (1 << 19) 114 #define INT_RBSYE (1 << 17) 115 #define INT_CRSPE (1 << 16) 116 #define INT_CMDVIO (1 << 15) 117 #define INT_BUFVIO (1 << 14) 118 #define INT_WDATERR (1 << 11) 119 #define INT_RDATERR (1 << 10) 120 #define INT_RIDXERR (1 << 9) 121 #define INT_RSPERR (1 << 8) 122 #define INT_CCSTO (1 << 5) 123 #define INT_CRCSTO (1 << 4) 124 #define INT_WDATTO (1 << 3) 125 #define INT_RDATTO (1 << 2) 126 #define INT_RBSYTO (1 << 1) 127 #define INT_RSPTO (1 << 0) 128 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 129 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 130 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 131 INT_RDATTO | INT_RBSYTO | INT_RSPTO) 132 133 #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 134 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 135 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 136 137 #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 138 139 /* CE_INT_MASK */ 140 #define MASK_ALL 0x00000000 141 #define MASK_MCCSDE (1 << 29) 142 #define MASK_MCMD12DRE (1 << 26) 143 #define MASK_MCMD12RBE (1 << 25) 144 #define MASK_MCMD12CRE (1 << 24) 145 #define MASK_MDTRANE (1 << 23) 146 #define MASK_MBUFRE (1 << 22) 147 #define MASK_MBUFWEN (1 << 21) 148 #define MASK_MBUFREN (1 << 20) 149 #define MASK_MCCSRCV (1 << 19) 150 #define MASK_MRBSYE (1 << 17) 151 #define MASK_MCRSPE (1 << 16) 152 #define MASK_MCMDVIO (1 << 15) 153 #define MASK_MBUFVIO (1 << 14) 154 #define MASK_MWDATERR (1 << 11) 155 #define MASK_MRDATERR (1 << 10) 156 #define MASK_MRIDXERR (1 << 9) 157 #define MASK_MRSPERR (1 << 8) 158 #define MASK_MCCSTO (1 << 5) 159 #define MASK_MCRCSTO (1 << 4) 160 #define MASK_MWDATTO (1 << 3) 161 #define MASK_MRDATTO (1 << 2) 162 #define MASK_MRBSYTO (1 << 1) 163 #define MASK_MRSPTO (1 << 0) 164 165 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 166 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 167 MASK_MCRCSTO | MASK_MWDATTO | \ 168 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 169 170 #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 171 MASK_MBUFREN | MASK_MBUFWEN | \ 172 MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 173 MASK_MCMD12RBE | MASK_MCMD12CRE) 174 175 /* CE_HOST_STS1 */ 176 #define STS1_CMDSEQ (1 << 31) 177 178 /* CE_HOST_STS2 */ 179 #define STS2_CRCSTE (1 << 31) 180 #define STS2_CRC16E (1 << 30) 181 #define STS2_AC12CRCE (1 << 29) 182 #define STS2_RSPCRC7E (1 << 28) 183 #define STS2_CRCSTEBE (1 << 27) 184 #define STS2_RDATEBE (1 << 26) 185 #define STS2_AC12REBE (1 << 25) 186 #define STS2_RSPEBE (1 << 24) 187 #define STS2_AC12IDXE (1 << 23) 188 #define STS2_RSPIDXE (1 << 22) 189 #define STS2_CCSTO (1 << 15) 190 #define STS2_RDATTO (1 << 14) 191 #define STS2_DATBSYTO (1 << 13) 192 #define STS2_CRCSTTO (1 << 12) 193 #define STS2_AC12BSYTO (1 << 11) 194 #define STS2_RSPBSYTO (1 << 10) 195 #define STS2_AC12RSPTO (1 << 9) 196 #define STS2_RSPTO (1 << 8) 197 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 198 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 199 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 200 STS2_DATBSYTO | STS2_CRCSTTO | \ 201 STS2_AC12BSYTO | STS2_RSPBSYTO | \ 202 STS2_AC12RSPTO | STS2_RSPTO) 203 204 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 205 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 206 #define CLKDEV_INIT 400000 /* 400 KHz */ 207 208 enum mmcif_state { 209 STATE_IDLE, 210 STATE_REQUEST, 211 STATE_IOS, 212 STATE_TIMEOUT, 213 }; 214 215 enum mmcif_wait_for { 216 MMCIF_WAIT_FOR_REQUEST, 217 MMCIF_WAIT_FOR_CMD, 218 MMCIF_WAIT_FOR_MREAD, 219 MMCIF_WAIT_FOR_MWRITE, 220 MMCIF_WAIT_FOR_READ, 221 MMCIF_WAIT_FOR_WRITE, 222 MMCIF_WAIT_FOR_READ_END, 223 MMCIF_WAIT_FOR_WRITE_END, 224 MMCIF_WAIT_FOR_STOP, 225 }; 226 227 struct sh_mmcif_host { 228 struct mmc_host *mmc; 229 struct mmc_request *mrq; 230 struct platform_device *pd; 231 struct clk *hclk; 232 unsigned int clk; 233 int bus_width; 234 unsigned char timing; 235 bool sd_error; 236 bool dying; 237 long timeout; 238 void __iomem *addr; 239 u32 *pio_ptr; 240 spinlock_t lock; /* protect sh_mmcif_host::state */ 241 enum mmcif_state state; 242 enum mmcif_wait_for wait_for; 243 struct delayed_work timeout_work; 244 size_t blocksize; 245 int sg_idx; 246 int sg_blkidx; 247 bool power; 248 bool card_present; 249 bool ccs_enable; /* Command Completion Signal support */ 250 bool clk_ctrl2_enable; 251 struct mutex thread_lock; 252 253 /* DMA support */ 254 struct dma_chan *chan_rx; 255 struct dma_chan *chan_tx; 256 struct completion dma_complete; 257 bool dma_active; 258 }; 259 260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 261 unsigned int reg, u32 val) 262 { 263 writel(val | readl(host->addr + reg), host->addr + reg); 264 } 265 266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 267 unsigned int reg, u32 val) 268 { 269 writel(~val & readl(host->addr + reg), host->addr + reg); 270 } 271 272 static void mmcif_dma_complete(void *arg) 273 { 274 struct sh_mmcif_host *host = arg; 275 struct mmc_request *mrq = host->mrq; 276 277 dev_dbg(&host->pd->dev, "Command completed\n"); 278 279 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 280 dev_name(&host->pd->dev))) 281 return; 282 283 complete(&host->dma_complete); 284 } 285 286 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 287 { 288 struct mmc_data *data = host->mrq->data; 289 struct scatterlist *sg = data->sg; 290 struct dma_async_tx_descriptor *desc = NULL; 291 struct dma_chan *chan = host->chan_rx; 292 dma_cookie_t cookie = -EINVAL; 293 int ret; 294 295 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 296 DMA_FROM_DEVICE); 297 if (ret > 0) { 298 host->dma_active = true; 299 desc = dmaengine_prep_slave_sg(chan, sg, ret, 300 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 301 } 302 303 if (desc) { 304 desc->callback = mmcif_dma_complete; 305 desc->callback_param = host; 306 cookie = dmaengine_submit(desc); 307 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 308 dma_async_issue_pending(chan); 309 } 310 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 311 __func__, data->sg_len, ret, cookie); 312 313 if (!desc) { 314 /* DMA failed, fall back to PIO */ 315 if (ret >= 0) 316 ret = -EIO; 317 host->chan_rx = NULL; 318 host->dma_active = false; 319 dma_release_channel(chan); 320 /* Free the Tx channel too */ 321 chan = host->chan_tx; 322 if (chan) { 323 host->chan_tx = NULL; 324 dma_release_channel(chan); 325 } 326 dev_warn(&host->pd->dev, 327 "DMA failed: %d, falling back to PIO\n", ret); 328 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 329 } 330 331 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 332 desc, cookie, data->sg_len); 333 } 334 335 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 336 { 337 struct mmc_data *data = host->mrq->data; 338 struct scatterlist *sg = data->sg; 339 struct dma_async_tx_descriptor *desc = NULL; 340 struct dma_chan *chan = host->chan_tx; 341 dma_cookie_t cookie = -EINVAL; 342 int ret; 343 344 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 345 DMA_TO_DEVICE); 346 if (ret > 0) { 347 host->dma_active = true; 348 desc = dmaengine_prep_slave_sg(chan, sg, ret, 349 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 350 } 351 352 if (desc) { 353 desc->callback = mmcif_dma_complete; 354 desc->callback_param = host; 355 cookie = dmaengine_submit(desc); 356 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 357 dma_async_issue_pending(chan); 358 } 359 dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 360 __func__, data->sg_len, ret, cookie); 361 362 if (!desc) { 363 /* DMA failed, fall back to PIO */ 364 if (ret >= 0) 365 ret = -EIO; 366 host->chan_tx = NULL; 367 host->dma_active = false; 368 dma_release_channel(chan); 369 /* Free the Rx channel too */ 370 chan = host->chan_rx; 371 if (chan) { 372 host->chan_rx = NULL; 373 dma_release_channel(chan); 374 } 375 dev_warn(&host->pd->dev, 376 "DMA failed: %d, falling back to PIO\n", ret); 377 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 378 } 379 380 dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 381 desc, cookie); 382 } 383 384 static struct dma_chan * 385 sh_mmcif_request_dma_one(struct sh_mmcif_host *host, 386 struct sh_mmcif_plat_data *pdata, 387 enum dma_transfer_direction direction) 388 { 389 struct dma_slave_config cfg; 390 struct dma_chan *chan; 391 unsigned int slave_id; 392 struct resource *res; 393 dma_cap_mask_t mask; 394 int ret; 395 396 dma_cap_zero(mask); 397 dma_cap_set(DMA_SLAVE, mask); 398 399 if (pdata) 400 slave_id = direction == DMA_MEM_TO_DEV 401 ? pdata->slave_id_tx : pdata->slave_id_rx; 402 else 403 slave_id = 0; 404 405 chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 406 (void *)(unsigned long)slave_id, &host->pd->dev, 407 direction == DMA_MEM_TO_DEV ? "tx" : "rx"); 408 409 dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__, 410 direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); 411 412 if (!chan) 413 return NULL; 414 415 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 416 417 /* In the OF case the driver will get the slave ID from the DT */ 418 cfg.slave_id = slave_id; 419 cfg.direction = direction; 420 cfg.dst_addr = res->start + MMCIF_CE_DATA; 421 cfg.src_addr = 0; 422 ret = dmaengine_slave_config(chan, &cfg); 423 if (ret < 0) { 424 dma_release_channel(chan); 425 return NULL; 426 } 427 428 return chan; 429 } 430 431 static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 432 struct sh_mmcif_plat_data *pdata) 433 { 434 host->dma_active = false; 435 436 if (pdata) { 437 if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 438 return; 439 } else if (!host->pd->dev.of_node) { 440 return; 441 } 442 443 /* We can only either use DMA for both Tx and Rx or not use it at all */ 444 host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); 445 if (!host->chan_tx) 446 return; 447 448 host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); 449 if (!host->chan_rx) { 450 dma_release_channel(host->chan_tx); 451 host->chan_tx = NULL; 452 } 453 } 454 455 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 456 { 457 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 458 /* Descriptors are freed automatically */ 459 if (host->chan_tx) { 460 struct dma_chan *chan = host->chan_tx; 461 host->chan_tx = NULL; 462 dma_release_channel(chan); 463 } 464 if (host->chan_rx) { 465 struct dma_chan *chan = host->chan_rx; 466 host->chan_rx = NULL; 467 dma_release_channel(chan); 468 } 469 470 host->dma_active = false; 471 } 472 473 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 474 { 475 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 476 bool sup_pclk = p ? p->sup_pclk : false; 477 478 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 479 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 480 481 if (!clk) 482 return; 483 if (sup_pclk && clk == host->clk) 484 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 485 else 486 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 487 ((fls(DIV_ROUND_UP(host->clk, 488 clk) - 1) - 1) << 16)); 489 490 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 491 } 492 493 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 494 { 495 u32 tmp; 496 497 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 498 499 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 500 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 501 if (host->ccs_enable) 502 tmp |= SCCSTO_29; 503 if (host->clk_ctrl2_enable) 504 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 505 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 506 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 507 /* byte swap on */ 508 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 509 } 510 511 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 512 { 513 u32 state1, state2; 514 int ret, timeout; 515 516 host->sd_error = false; 517 518 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 519 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 520 dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 521 dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 522 523 if (state1 & STS1_CMDSEQ) { 524 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 525 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 526 for (timeout = 10000000; timeout; timeout--) { 527 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 528 & STS1_CMDSEQ)) 529 break; 530 mdelay(1); 531 } 532 if (!timeout) { 533 dev_err(&host->pd->dev, 534 "Forced end of command sequence timeout err\n"); 535 return -EIO; 536 } 537 sh_mmcif_sync_reset(host); 538 dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 539 return -EIO; 540 } 541 542 if (state2 & STS2_CRC_ERR) { 543 dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", 544 host->state, host->wait_for); 545 ret = -EIO; 546 } else if (state2 & STS2_TIMEOUT_ERR) { 547 dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", 548 host->state, host->wait_for); 549 ret = -ETIMEDOUT; 550 } else { 551 dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", 552 host->state, host->wait_for); 553 ret = -EIO; 554 } 555 return ret; 556 } 557 558 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 559 { 560 struct mmc_data *data = host->mrq->data; 561 562 host->sg_blkidx += host->blocksize; 563 564 /* data->sg->length must be a multiple of host->blocksize? */ 565 BUG_ON(host->sg_blkidx > data->sg->length); 566 567 if (host->sg_blkidx == data->sg->length) { 568 host->sg_blkidx = 0; 569 if (++host->sg_idx < data->sg_len) 570 host->pio_ptr = sg_virt(++data->sg); 571 } else { 572 host->pio_ptr = p; 573 } 574 575 return host->sg_idx != data->sg_len; 576 } 577 578 static void sh_mmcif_single_read(struct sh_mmcif_host *host, 579 struct mmc_request *mrq) 580 { 581 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 582 BLOCK_SIZE_MASK) + 3; 583 584 host->wait_for = MMCIF_WAIT_FOR_READ; 585 586 /* buf read enable */ 587 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 588 } 589 590 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 591 { 592 struct mmc_data *data = host->mrq->data; 593 u32 *p = sg_virt(data->sg); 594 int i; 595 596 if (host->sd_error) { 597 data->error = sh_mmcif_error_manage(host); 598 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 599 return false; 600 } 601 602 for (i = 0; i < host->blocksize / 4; i++) 603 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 604 605 /* buffer read end */ 606 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 607 host->wait_for = MMCIF_WAIT_FOR_READ_END; 608 609 return true; 610 } 611 612 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 613 struct mmc_request *mrq) 614 { 615 struct mmc_data *data = mrq->data; 616 617 if (!data->sg_len || !data->sg->length) 618 return; 619 620 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 621 BLOCK_SIZE_MASK; 622 623 host->wait_for = MMCIF_WAIT_FOR_MREAD; 624 host->sg_idx = 0; 625 host->sg_blkidx = 0; 626 host->pio_ptr = sg_virt(data->sg); 627 628 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 629 } 630 631 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 632 { 633 struct mmc_data *data = host->mrq->data; 634 u32 *p = host->pio_ptr; 635 int i; 636 637 if (host->sd_error) { 638 data->error = sh_mmcif_error_manage(host); 639 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 640 return false; 641 } 642 643 BUG_ON(!data->sg->length); 644 645 for (i = 0; i < host->blocksize / 4; i++) 646 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 647 648 if (!sh_mmcif_next_block(host, p)) 649 return false; 650 651 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 652 653 return true; 654 } 655 656 static void sh_mmcif_single_write(struct sh_mmcif_host *host, 657 struct mmc_request *mrq) 658 { 659 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 660 BLOCK_SIZE_MASK) + 3; 661 662 host->wait_for = MMCIF_WAIT_FOR_WRITE; 663 664 /* buf write enable */ 665 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 666 } 667 668 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 669 { 670 struct mmc_data *data = host->mrq->data; 671 u32 *p = sg_virt(data->sg); 672 int i; 673 674 if (host->sd_error) { 675 data->error = sh_mmcif_error_manage(host); 676 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 677 return false; 678 } 679 680 for (i = 0; i < host->blocksize / 4; i++) 681 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 682 683 /* buffer write end */ 684 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 685 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 686 687 return true; 688 } 689 690 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 691 struct mmc_request *mrq) 692 { 693 struct mmc_data *data = mrq->data; 694 695 if (!data->sg_len || !data->sg->length) 696 return; 697 698 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 699 BLOCK_SIZE_MASK; 700 701 host->wait_for = MMCIF_WAIT_FOR_MWRITE; 702 host->sg_idx = 0; 703 host->sg_blkidx = 0; 704 host->pio_ptr = sg_virt(data->sg); 705 706 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 707 } 708 709 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 710 { 711 struct mmc_data *data = host->mrq->data; 712 u32 *p = host->pio_ptr; 713 int i; 714 715 if (host->sd_error) { 716 data->error = sh_mmcif_error_manage(host); 717 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 718 return false; 719 } 720 721 BUG_ON(!data->sg->length); 722 723 for (i = 0; i < host->blocksize / 4; i++) 724 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 725 726 if (!sh_mmcif_next_block(host, p)) 727 return false; 728 729 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 730 731 return true; 732 } 733 734 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 735 struct mmc_command *cmd) 736 { 737 if (cmd->flags & MMC_RSP_136) { 738 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 739 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 740 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 741 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 742 } else 743 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 744 } 745 746 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 747 struct mmc_command *cmd) 748 { 749 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 750 } 751 752 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 753 struct mmc_request *mrq) 754 { 755 struct mmc_data *data = mrq->data; 756 struct mmc_command *cmd = mrq->cmd; 757 u32 opc = cmd->opcode; 758 u32 tmp = 0; 759 760 /* Response Type check */ 761 switch (mmc_resp_type(cmd)) { 762 case MMC_RSP_NONE: 763 tmp |= CMD_SET_RTYP_NO; 764 break; 765 case MMC_RSP_R1: 766 case MMC_RSP_R1B: 767 case MMC_RSP_R3: 768 tmp |= CMD_SET_RTYP_6B; 769 break; 770 case MMC_RSP_R2: 771 tmp |= CMD_SET_RTYP_17B; 772 break; 773 default: 774 dev_err(&host->pd->dev, "Unsupported response type.\n"); 775 break; 776 } 777 switch (opc) { 778 /* RBSY */ 779 case MMC_SLEEP_AWAKE: 780 case MMC_SWITCH: 781 case MMC_STOP_TRANSMISSION: 782 case MMC_SET_WRITE_PROT: 783 case MMC_CLR_WRITE_PROT: 784 case MMC_ERASE: 785 tmp |= CMD_SET_RBSY; 786 break; 787 } 788 /* WDAT / DATW */ 789 if (data) { 790 tmp |= CMD_SET_WDAT; 791 switch (host->bus_width) { 792 case MMC_BUS_WIDTH_1: 793 tmp |= CMD_SET_DATW_1; 794 break; 795 case MMC_BUS_WIDTH_4: 796 tmp |= CMD_SET_DATW_4; 797 break; 798 case MMC_BUS_WIDTH_8: 799 tmp |= CMD_SET_DATW_8; 800 break; 801 default: 802 dev_err(&host->pd->dev, "Unsupported bus width.\n"); 803 break; 804 } 805 switch (host->timing) { 806 case MMC_TIMING_MMC_DDR52: 807 /* 808 * MMC core will only set this timing, if the host 809 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 810 * capability. MMCIF implementations with this 811 * capability, e.g. sh73a0, will have to set it 812 * in their platform data. 813 */ 814 tmp |= CMD_SET_DARS; 815 break; 816 } 817 } 818 /* DWEN */ 819 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 820 tmp |= CMD_SET_DWEN; 821 /* CMLTE/CMD12EN */ 822 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 823 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 824 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 825 data->blocks << 16); 826 } 827 /* RIDXC[1:0] check bits */ 828 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 829 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 830 tmp |= CMD_SET_RIDXC_BITS; 831 /* RCRC7C[1:0] check bits */ 832 if (opc == MMC_SEND_OP_COND) 833 tmp |= CMD_SET_CRC7C_BITS; 834 /* RCRC7C[1:0] internal CRC7 */ 835 if (opc == MMC_ALL_SEND_CID || 836 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 837 tmp |= CMD_SET_CRC7C_INTERNAL; 838 839 return (opc << 24) | tmp; 840 } 841 842 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 843 struct mmc_request *mrq, u32 opc) 844 { 845 switch (opc) { 846 case MMC_READ_MULTIPLE_BLOCK: 847 sh_mmcif_multi_read(host, mrq); 848 return 0; 849 case MMC_WRITE_MULTIPLE_BLOCK: 850 sh_mmcif_multi_write(host, mrq); 851 return 0; 852 case MMC_WRITE_BLOCK: 853 sh_mmcif_single_write(host, mrq); 854 return 0; 855 case MMC_READ_SINGLE_BLOCK: 856 case MMC_SEND_EXT_CSD: 857 sh_mmcif_single_read(host, mrq); 858 return 0; 859 default: 860 dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); 861 return -EINVAL; 862 } 863 } 864 865 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 866 struct mmc_request *mrq) 867 { 868 struct mmc_command *cmd = mrq->cmd; 869 u32 opc = cmd->opcode; 870 u32 mask; 871 872 switch (opc) { 873 /* response busy check */ 874 case MMC_SLEEP_AWAKE: 875 case MMC_SWITCH: 876 case MMC_STOP_TRANSMISSION: 877 case MMC_SET_WRITE_PROT: 878 case MMC_CLR_WRITE_PROT: 879 case MMC_ERASE: 880 mask = MASK_START_CMD | MASK_MRBSYE; 881 break; 882 default: 883 mask = MASK_START_CMD | MASK_MCRSPE; 884 break; 885 } 886 887 if (host->ccs_enable) 888 mask |= MASK_MCCSTO; 889 890 if (mrq->data) { 891 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 892 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 893 mrq->data->blksz); 894 } 895 opc = sh_mmcif_set_cmd(host, mrq); 896 897 if (host->ccs_enable) 898 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 899 else 900 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 901 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 902 /* set arg */ 903 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 904 /* set cmd */ 905 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 906 907 host->wait_for = MMCIF_WAIT_FOR_CMD; 908 schedule_delayed_work(&host->timeout_work, host->timeout); 909 } 910 911 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 912 struct mmc_request *mrq) 913 { 914 switch (mrq->cmd->opcode) { 915 case MMC_READ_MULTIPLE_BLOCK: 916 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 917 break; 918 case MMC_WRITE_MULTIPLE_BLOCK: 919 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 920 break; 921 default: 922 dev_err(&host->pd->dev, "unsupported stop cmd\n"); 923 mrq->stop->error = sh_mmcif_error_manage(host); 924 return; 925 } 926 927 host->wait_for = MMCIF_WAIT_FOR_STOP; 928 } 929 930 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 931 { 932 struct sh_mmcif_host *host = mmc_priv(mmc); 933 unsigned long flags; 934 935 spin_lock_irqsave(&host->lock, flags); 936 if (host->state != STATE_IDLE) { 937 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 938 spin_unlock_irqrestore(&host->lock, flags); 939 mrq->cmd->error = -EAGAIN; 940 mmc_request_done(mmc, mrq); 941 return; 942 } 943 944 host->state = STATE_REQUEST; 945 spin_unlock_irqrestore(&host->lock, flags); 946 947 switch (mrq->cmd->opcode) { 948 /* MMCIF does not support SD/SDIO command */ 949 case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 950 case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 951 if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 952 break; 953 case MMC_APP_CMD: 954 case SD_IO_RW_DIRECT: 955 host->state = STATE_IDLE; 956 mrq->cmd->error = -ETIMEDOUT; 957 mmc_request_done(mmc, mrq); 958 return; 959 default: 960 break; 961 } 962 963 host->mrq = mrq; 964 965 sh_mmcif_start_cmd(host, mrq); 966 } 967 968 static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 969 { 970 int ret = clk_prepare_enable(host->hclk); 971 972 if (!ret) { 973 host->clk = clk_get_rate(host->hclk); 974 host->mmc->f_max = host->clk / 2; 975 host->mmc->f_min = host->clk / 512; 976 } 977 978 return ret; 979 } 980 981 static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 982 { 983 struct mmc_host *mmc = host->mmc; 984 985 if (!IS_ERR(mmc->supply.vmmc)) 986 /* Errors ignored... */ 987 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 988 ios->power_mode ? ios->vdd : 0); 989 } 990 991 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 992 { 993 struct sh_mmcif_host *host = mmc_priv(mmc); 994 unsigned long flags; 995 996 spin_lock_irqsave(&host->lock, flags); 997 if (host->state != STATE_IDLE) { 998 dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 999 spin_unlock_irqrestore(&host->lock, flags); 1000 return; 1001 } 1002 1003 host->state = STATE_IOS; 1004 spin_unlock_irqrestore(&host->lock, flags); 1005 1006 if (ios->power_mode == MMC_POWER_UP) { 1007 if (!host->card_present) { 1008 /* See if we also get DMA */ 1009 sh_mmcif_request_dma(host, host->pd->dev.platform_data); 1010 host->card_present = true; 1011 } 1012 sh_mmcif_set_power(host, ios); 1013 } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 1014 /* clock stop */ 1015 sh_mmcif_clock_control(host, 0); 1016 if (ios->power_mode == MMC_POWER_OFF) { 1017 if (host->card_present) { 1018 sh_mmcif_release_dma(host); 1019 host->card_present = false; 1020 } 1021 } 1022 if (host->power) { 1023 pm_runtime_put_sync(&host->pd->dev); 1024 clk_disable_unprepare(host->hclk); 1025 host->power = false; 1026 if (ios->power_mode == MMC_POWER_OFF) 1027 sh_mmcif_set_power(host, ios); 1028 } 1029 host->state = STATE_IDLE; 1030 return; 1031 } 1032 1033 if (ios->clock) { 1034 if (!host->power) { 1035 sh_mmcif_clk_update(host); 1036 pm_runtime_get_sync(&host->pd->dev); 1037 host->power = true; 1038 sh_mmcif_sync_reset(host); 1039 } 1040 sh_mmcif_clock_control(host, ios->clock); 1041 } 1042 1043 host->timing = ios->timing; 1044 host->bus_width = ios->bus_width; 1045 host->state = STATE_IDLE; 1046 } 1047 1048 static int sh_mmcif_get_cd(struct mmc_host *mmc) 1049 { 1050 struct sh_mmcif_host *host = mmc_priv(mmc); 1051 struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1052 int ret = mmc_gpio_get_cd(mmc); 1053 1054 if (ret >= 0) 1055 return ret; 1056 1057 if (!p || !p->get_cd) 1058 return -ENOSYS; 1059 else 1060 return p->get_cd(host->pd); 1061 } 1062 1063 static struct mmc_host_ops sh_mmcif_ops = { 1064 .request = sh_mmcif_request, 1065 .set_ios = sh_mmcif_set_ios, 1066 .get_cd = sh_mmcif_get_cd, 1067 }; 1068 1069 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1070 { 1071 struct mmc_command *cmd = host->mrq->cmd; 1072 struct mmc_data *data = host->mrq->data; 1073 long time; 1074 1075 if (host->sd_error) { 1076 switch (cmd->opcode) { 1077 case MMC_ALL_SEND_CID: 1078 case MMC_SELECT_CARD: 1079 case MMC_APP_CMD: 1080 cmd->error = -ETIMEDOUT; 1081 break; 1082 default: 1083 cmd->error = sh_mmcif_error_manage(host); 1084 break; 1085 } 1086 dev_dbg(&host->pd->dev, "CMD%d error %d\n", 1087 cmd->opcode, cmd->error); 1088 host->sd_error = false; 1089 return false; 1090 } 1091 if (!(cmd->flags & MMC_RSP_PRESENT)) { 1092 cmd->error = 0; 1093 return false; 1094 } 1095 1096 sh_mmcif_get_response(host, cmd); 1097 1098 if (!data) 1099 return false; 1100 1101 /* 1102 * Completion can be signalled from DMA callback and error, so, have to 1103 * reset here, before setting .dma_active 1104 */ 1105 init_completion(&host->dma_complete); 1106 1107 if (data->flags & MMC_DATA_READ) { 1108 if (host->chan_rx) 1109 sh_mmcif_start_dma_rx(host); 1110 } else { 1111 if (host->chan_tx) 1112 sh_mmcif_start_dma_tx(host); 1113 } 1114 1115 if (!host->dma_active) { 1116 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 1117 return !data->error; 1118 } 1119 1120 /* Running in the IRQ thread, can sleep */ 1121 time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1122 host->timeout); 1123 1124 if (data->flags & MMC_DATA_READ) 1125 dma_unmap_sg(host->chan_rx->device->dev, 1126 data->sg, data->sg_len, 1127 DMA_FROM_DEVICE); 1128 else 1129 dma_unmap_sg(host->chan_tx->device->dev, 1130 data->sg, data->sg_len, 1131 DMA_TO_DEVICE); 1132 1133 if (host->sd_error) { 1134 dev_err(host->mmc->parent, 1135 "Error IRQ while waiting for DMA completion!\n"); 1136 /* Woken up by an error IRQ: abort DMA */ 1137 data->error = sh_mmcif_error_manage(host); 1138 } else if (!time) { 1139 dev_err(host->mmc->parent, "DMA timeout!\n"); 1140 data->error = -ETIMEDOUT; 1141 } else if (time < 0) { 1142 dev_err(host->mmc->parent, 1143 "wait_for_completion_...() error %ld!\n", time); 1144 data->error = time; 1145 } 1146 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1147 BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1148 host->dma_active = false; 1149 1150 if (data->error) { 1151 data->bytes_xfered = 0; 1152 /* Abort DMA */ 1153 if (data->flags & MMC_DATA_READ) 1154 dmaengine_terminate_all(host->chan_rx); 1155 else 1156 dmaengine_terminate_all(host->chan_tx); 1157 } 1158 1159 return false; 1160 } 1161 1162 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1163 { 1164 struct sh_mmcif_host *host = dev_id; 1165 struct mmc_request *mrq; 1166 bool wait = false; 1167 1168 cancel_delayed_work_sync(&host->timeout_work); 1169 1170 mutex_lock(&host->thread_lock); 1171 1172 mrq = host->mrq; 1173 if (!mrq) { 1174 dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 1175 host->state, host->wait_for); 1176 mutex_unlock(&host->thread_lock); 1177 return IRQ_HANDLED; 1178 } 1179 1180 /* 1181 * All handlers return true, if processing continues, and false, if the 1182 * request has to be completed - successfully or not 1183 */ 1184 switch (host->wait_for) { 1185 case MMCIF_WAIT_FOR_REQUEST: 1186 /* We're too late, the timeout has already kicked in */ 1187 mutex_unlock(&host->thread_lock); 1188 return IRQ_HANDLED; 1189 case MMCIF_WAIT_FOR_CMD: 1190 /* Wait for data? */ 1191 wait = sh_mmcif_end_cmd(host); 1192 break; 1193 case MMCIF_WAIT_FOR_MREAD: 1194 /* Wait for more data? */ 1195 wait = sh_mmcif_mread_block(host); 1196 break; 1197 case MMCIF_WAIT_FOR_READ: 1198 /* Wait for data end? */ 1199 wait = sh_mmcif_read_block(host); 1200 break; 1201 case MMCIF_WAIT_FOR_MWRITE: 1202 /* Wait data to write? */ 1203 wait = sh_mmcif_mwrite_block(host); 1204 break; 1205 case MMCIF_WAIT_FOR_WRITE: 1206 /* Wait for data end? */ 1207 wait = sh_mmcif_write_block(host); 1208 break; 1209 case MMCIF_WAIT_FOR_STOP: 1210 if (host->sd_error) { 1211 mrq->stop->error = sh_mmcif_error_manage(host); 1212 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); 1213 break; 1214 } 1215 sh_mmcif_get_cmd12response(host, mrq->stop); 1216 mrq->stop->error = 0; 1217 break; 1218 case MMCIF_WAIT_FOR_READ_END: 1219 case MMCIF_WAIT_FOR_WRITE_END: 1220 if (host->sd_error) { 1221 mrq->data->error = sh_mmcif_error_manage(host); 1222 dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); 1223 } 1224 break; 1225 default: 1226 BUG(); 1227 } 1228 1229 if (wait) { 1230 schedule_delayed_work(&host->timeout_work, host->timeout); 1231 /* Wait for more data */ 1232 mutex_unlock(&host->thread_lock); 1233 return IRQ_HANDLED; 1234 } 1235 1236 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 1237 struct mmc_data *data = mrq->data; 1238 if (!mrq->cmd->error && data && !data->error) 1239 data->bytes_xfered = 1240 data->blocks * data->blksz; 1241 1242 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1243 sh_mmcif_stop_cmd(host, mrq); 1244 if (!mrq->stop->error) { 1245 schedule_delayed_work(&host->timeout_work, host->timeout); 1246 mutex_unlock(&host->thread_lock); 1247 return IRQ_HANDLED; 1248 } 1249 } 1250 } 1251 1252 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1253 host->state = STATE_IDLE; 1254 host->mrq = NULL; 1255 mmc_request_done(host->mmc, mrq); 1256 1257 mutex_unlock(&host->thread_lock); 1258 1259 return IRQ_HANDLED; 1260 } 1261 1262 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1263 { 1264 struct sh_mmcif_host *host = dev_id; 1265 u32 state, mask; 1266 1267 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1268 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1269 if (host->ccs_enable) 1270 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1271 else 1272 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 1273 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1274 1275 if (state & ~MASK_CLEAN) 1276 dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", 1277 state); 1278 1279 if (state & INT_ERR_STS || state & ~INT_ALL) { 1280 host->sd_error = true; 1281 dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); 1282 } 1283 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1284 if (!host->mrq) 1285 dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); 1286 if (!host->dma_active) 1287 return IRQ_WAKE_THREAD; 1288 else if (host->sd_error) 1289 mmcif_dma_complete(host); 1290 } else { 1291 dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1292 } 1293 1294 return IRQ_HANDLED; 1295 } 1296 1297 static void mmcif_timeout_work(struct work_struct *work) 1298 { 1299 struct delayed_work *d = container_of(work, struct delayed_work, work); 1300 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1301 struct mmc_request *mrq = host->mrq; 1302 unsigned long flags; 1303 1304 if (host->dying) 1305 /* Don't run after mmc_remove_host() */ 1306 return; 1307 1308 dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", 1309 host->wait_for, mrq->cmd->opcode); 1310 1311 spin_lock_irqsave(&host->lock, flags); 1312 if (host->state == STATE_IDLE) { 1313 spin_unlock_irqrestore(&host->lock, flags); 1314 return; 1315 } 1316 1317 host->state = STATE_TIMEOUT; 1318 spin_unlock_irqrestore(&host->lock, flags); 1319 1320 /* 1321 * Handle races with cancel_delayed_work(), unless 1322 * cancel_delayed_work_sync() is used 1323 */ 1324 switch (host->wait_for) { 1325 case MMCIF_WAIT_FOR_CMD: 1326 mrq->cmd->error = sh_mmcif_error_manage(host); 1327 break; 1328 case MMCIF_WAIT_FOR_STOP: 1329 mrq->stop->error = sh_mmcif_error_manage(host); 1330 break; 1331 case MMCIF_WAIT_FOR_MREAD: 1332 case MMCIF_WAIT_FOR_MWRITE: 1333 case MMCIF_WAIT_FOR_READ: 1334 case MMCIF_WAIT_FOR_WRITE: 1335 case MMCIF_WAIT_FOR_READ_END: 1336 case MMCIF_WAIT_FOR_WRITE_END: 1337 mrq->data->error = sh_mmcif_error_manage(host); 1338 break; 1339 default: 1340 BUG(); 1341 } 1342 1343 host->state = STATE_IDLE; 1344 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1345 host->mrq = NULL; 1346 mmc_request_done(host->mmc, mrq); 1347 } 1348 1349 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 1350 { 1351 struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 1352 struct mmc_host *mmc = host->mmc; 1353 1354 mmc_regulator_get_supply(mmc); 1355 1356 if (!pd) 1357 return; 1358 1359 if (!mmc->ocr_avail) 1360 mmc->ocr_avail = pd->ocr; 1361 else if (pd->ocr) 1362 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1363 } 1364 1365 static int sh_mmcif_probe(struct platform_device *pdev) 1366 { 1367 int ret = 0, irq[2]; 1368 struct mmc_host *mmc; 1369 struct sh_mmcif_host *host; 1370 struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1371 struct resource *res; 1372 void __iomem *reg; 1373 const char *name; 1374 1375 irq[0] = platform_get_irq(pdev, 0); 1376 irq[1] = platform_get_irq(pdev, 1); 1377 if (irq[0] < 0) { 1378 dev_err(&pdev->dev, "Get irq error\n"); 1379 return -ENXIO; 1380 } 1381 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1382 if (!res) { 1383 dev_err(&pdev->dev, "platform_get_resource error.\n"); 1384 return -ENXIO; 1385 } 1386 reg = ioremap(res->start, resource_size(res)); 1387 if (!reg) { 1388 dev_err(&pdev->dev, "ioremap error.\n"); 1389 return -ENOMEM; 1390 } 1391 1392 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1393 if (!mmc) { 1394 ret = -ENOMEM; 1395 goto ealloch; 1396 } 1397 1398 ret = mmc_of_parse(mmc); 1399 if (ret < 0) 1400 goto eofparse; 1401 1402 host = mmc_priv(mmc); 1403 host->mmc = mmc; 1404 host->addr = reg; 1405 host->timeout = msecs_to_jiffies(1000); 1406 host->ccs_enable = !pd || !pd->ccs_unsupported; 1407 host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; 1408 1409 host->pd = pdev; 1410 1411 spin_lock_init(&host->lock); 1412 1413 mmc->ops = &sh_mmcif_ops; 1414 sh_mmcif_init_ocr(host); 1415 1416 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1417 if (pd && pd->caps) 1418 mmc->caps |= pd->caps; 1419 mmc->max_segs = 32; 1420 mmc->max_blk_size = 512; 1421 mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1422 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1423 mmc->max_seg_size = mmc->max_req_size; 1424 1425 platform_set_drvdata(pdev, host); 1426 1427 pm_runtime_enable(&pdev->dev); 1428 host->power = false; 1429 1430 host->hclk = clk_get(&pdev->dev, NULL); 1431 if (IS_ERR(host->hclk)) { 1432 ret = PTR_ERR(host->hclk); 1433 dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 1434 goto eclkget; 1435 } 1436 ret = sh_mmcif_clk_update(host); 1437 if (ret < 0) 1438 goto eclkupdate; 1439 1440 ret = pm_runtime_resume(&pdev->dev); 1441 if (ret < 0) 1442 goto eresume; 1443 1444 INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1445 1446 sh_mmcif_sync_reset(host); 1447 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1448 1449 name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; 1450 ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host); 1451 if (ret) { 1452 dev_err(&pdev->dev, "request_irq error (%s)\n", name); 1453 goto ereqirq0; 1454 } 1455 if (irq[1] >= 0) { 1456 ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 1457 0, "sh_mmc:int", host); 1458 if (ret) { 1459 dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1460 goto ereqirq1; 1461 } 1462 } 1463 1464 if (pd && pd->use_cd_gpio) { 1465 ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); 1466 if (ret < 0) 1467 goto erqcd; 1468 } 1469 1470 mutex_init(&host->thread_lock); 1471 1472 clk_disable_unprepare(host->hclk); 1473 ret = mmc_add_host(mmc); 1474 if (ret < 0) 1475 goto emmcaddh; 1476 1477 dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1478 1479 dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1480 dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1481 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1482 return ret; 1483 1484 emmcaddh: 1485 erqcd: 1486 if (irq[1] >= 0) 1487 free_irq(irq[1], host); 1488 ereqirq1: 1489 free_irq(irq[0], host); 1490 ereqirq0: 1491 pm_runtime_suspend(&pdev->dev); 1492 eresume: 1493 clk_disable_unprepare(host->hclk); 1494 eclkupdate: 1495 clk_put(host->hclk); 1496 eclkget: 1497 pm_runtime_disable(&pdev->dev); 1498 eofparse: 1499 mmc_free_host(mmc); 1500 ealloch: 1501 iounmap(reg); 1502 return ret; 1503 } 1504 1505 static int sh_mmcif_remove(struct platform_device *pdev) 1506 { 1507 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1508 int irq[2]; 1509 1510 host->dying = true; 1511 clk_prepare_enable(host->hclk); 1512 pm_runtime_get_sync(&pdev->dev); 1513 1514 dev_pm_qos_hide_latency_limit(&pdev->dev); 1515 1516 mmc_remove_host(host->mmc); 1517 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1518 1519 /* 1520 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1521 * mmc_remove_host() call above. But swapping order doesn't help either 1522 * (a query on the linux-mmc mailing list didn't bring any replies). 1523 */ 1524 cancel_delayed_work_sync(&host->timeout_work); 1525 1526 if (host->addr) 1527 iounmap(host->addr); 1528 1529 irq[0] = platform_get_irq(pdev, 0); 1530 irq[1] = platform_get_irq(pdev, 1); 1531 1532 free_irq(irq[0], host); 1533 if (irq[1] >= 0) 1534 free_irq(irq[1], host); 1535 1536 clk_disable_unprepare(host->hclk); 1537 mmc_free_host(host->mmc); 1538 pm_runtime_put_sync(&pdev->dev); 1539 pm_runtime_disable(&pdev->dev); 1540 1541 return 0; 1542 } 1543 1544 #ifdef CONFIG_PM_SLEEP 1545 static int sh_mmcif_suspend(struct device *dev) 1546 { 1547 struct sh_mmcif_host *host = dev_get_drvdata(dev); 1548 1549 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1550 1551 return 0; 1552 } 1553 1554 static int sh_mmcif_resume(struct device *dev) 1555 { 1556 return 0; 1557 } 1558 #endif 1559 1560 static const struct of_device_id mmcif_of_match[] = { 1561 { .compatible = "renesas,sh-mmcif" }, 1562 { } 1563 }; 1564 MODULE_DEVICE_TABLE(of, mmcif_of_match); 1565 1566 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1567 SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1568 }; 1569 1570 static struct platform_driver sh_mmcif_driver = { 1571 .probe = sh_mmcif_probe, 1572 .remove = sh_mmcif_remove, 1573 .driver = { 1574 .name = DRIVER_NAME, 1575 .pm = &sh_mmcif_dev_pm_ops, 1576 .owner = THIS_MODULE, 1577 .of_match_table = mmcif_of_match, 1578 }, 1579 }; 1580 1581 module_platform_driver(sh_mmcif_driver); 1582 1583 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1584 MODULE_LICENSE("GPL"); 1585 MODULE_ALIAS("platform:" DRIVER_NAME); 1586 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1587