1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * MMCIF eMMC driver. 4 * 5 * Copyright (C) 2010 Renesas Solutions Corp. 6 * Yusuke Goda <yusuke.goda.sx@renesas.com> 7 */ 8 9 /* 10 * The MMCIF driver is now processing MMC requests asynchronously, according 11 * to the Linux MMC API requirement. 12 * 13 * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 14 * data, and optional stop. To achieve asynchronous processing each of these 15 * stages is split into two halves: a top and a bottom half. The top half 16 * initialises the hardware, installs a timeout handler to handle completion 17 * timeouts, and returns. In case of the command stage this immediately returns 18 * control to the caller, leaving all further processing to run asynchronously. 19 * All further request processing is performed by the bottom halves. 20 * 21 * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 22 * thread, a DMA completion callback, if DMA is used, a timeout work, and 23 * request- and stage-specific handler methods. 24 * 25 * Each bottom half run begins with either a hardware interrupt, a DMA callback 26 * invocation, or a timeout work run. In case of an error or a successful 27 * processing completion, the MMC core is informed and the request processing is 28 * finished. In case processing has to continue, i.e., if data has to be read 29 * from or written to the card, or if a stop command has to be sent, the next 30 * top half is called, which performs the necessary hardware handling and 31 * reschedules the timeout work. This returns the driver state machine into the 32 * bottom half waiting state. 33 */ 34 35 #include <linux/bitops.h> 36 #include <linux/clk.h> 37 #include <linux/completion.h> 38 #include <linux/delay.h> 39 #include <linux/dma-mapping.h> 40 #include <linux/dmaengine.h> 41 #include <linux/mmc/card.h> 42 #include <linux/mmc/core.h> 43 #include <linux/mmc/host.h> 44 #include <linux/mmc/mmc.h> 45 #include <linux/mmc/sdio.h> 46 #include <linux/mmc/sh_mmcif.h> 47 #include <linux/mmc/slot-gpio.h> 48 #include <linux/mod_devicetable.h> 49 #include <linux/mutex.h> 50 #include <linux/of_device.h> 51 #include <linux/pagemap.h> 52 #include <linux/platform_device.h> 53 #include <linux/pm_qos.h> 54 #include <linux/pm_runtime.h> 55 #include <linux/sh_dma.h> 56 #include <linux/spinlock.h> 57 #include <linux/module.h> 58 59 #define DRIVER_NAME "sh_mmcif" 60 61 /* CE_CMD_SET */ 62 #define CMD_MASK 0x3f000000 63 #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 64 #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 65 #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 66 #define CMD_SET_RBSY (1 << 21) /* R1b */ 67 #define CMD_SET_CCSEN (1 << 20) 68 #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 69 #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 70 #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 71 #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 72 #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 73 #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 74 #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 75 #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 76 #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 77 #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 78 #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 79 #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 80 #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 81 #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 82 #define CMD_SET_CCSH (1 << 5) 83 #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 84 #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 85 #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 86 #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 87 88 /* CE_CMD_CTRL */ 89 #define CMD_CTRL_BREAK (1 << 0) 90 91 /* CE_BLOCK_SET */ 92 #define BLOCK_SIZE_MASK 0x0000ffff 93 94 /* CE_INT */ 95 #define INT_CCSDE (1 << 29) 96 #define INT_CMD12DRE (1 << 26) 97 #define INT_CMD12RBE (1 << 25) 98 #define INT_CMD12CRE (1 << 24) 99 #define INT_DTRANE (1 << 23) 100 #define INT_BUFRE (1 << 22) 101 #define INT_BUFWEN (1 << 21) 102 #define INT_BUFREN (1 << 20) 103 #define INT_CCSRCV (1 << 19) 104 #define INT_RBSYE (1 << 17) 105 #define INT_CRSPE (1 << 16) 106 #define INT_CMDVIO (1 << 15) 107 #define INT_BUFVIO (1 << 14) 108 #define INT_WDATERR (1 << 11) 109 #define INT_RDATERR (1 << 10) 110 #define INT_RIDXERR (1 << 9) 111 #define INT_RSPERR (1 << 8) 112 #define INT_CCSTO (1 << 5) 113 #define INT_CRCSTO (1 << 4) 114 #define INT_WDATTO (1 << 3) 115 #define INT_RDATTO (1 << 2) 116 #define INT_RBSYTO (1 << 1) 117 #define INT_RSPTO (1 << 0) 118 #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 119 INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 120 INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 121 INT_RDATTO | INT_RBSYTO | INT_RSPTO) 122 123 #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 124 INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 125 INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 126 127 #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 128 129 /* CE_INT_MASK */ 130 #define MASK_ALL 0x00000000 131 #define MASK_MCCSDE (1 << 29) 132 #define MASK_MCMD12DRE (1 << 26) 133 #define MASK_MCMD12RBE (1 << 25) 134 #define MASK_MCMD12CRE (1 << 24) 135 #define MASK_MDTRANE (1 << 23) 136 #define MASK_MBUFRE (1 << 22) 137 #define MASK_MBUFWEN (1 << 21) 138 #define MASK_MBUFREN (1 << 20) 139 #define MASK_MCCSRCV (1 << 19) 140 #define MASK_MRBSYE (1 << 17) 141 #define MASK_MCRSPE (1 << 16) 142 #define MASK_MCMDVIO (1 << 15) 143 #define MASK_MBUFVIO (1 << 14) 144 #define MASK_MWDATERR (1 << 11) 145 #define MASK_MRDATERR (1 << 10) 146 #define MASK_MRIDXERR (1 << 9) 147 #define MASK_MRSPERR (1 << 8) 148 #define MASK_MCCSTO (1 << 5) 149 #define MASK_MCRCSTO (1 << 4) 150 #define MASK_MWDATTO (1 << 3) 151 #define MASK_MRDATTO (1 << 2) 152 #define MASK_MRBSYTO (1 << 1) 153 #define MASK_MRSPTO (1 << 0) 154 155 #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 156 MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 157 MASK_MCRCSTO | MASK_MWDATTO | \ 158 MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 159 160 #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 161 MASK_MBUFREN | MASK_MBUFWEN | \ 162 MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 163 MASK_MCMD12RBE | MASK_MCMD12CRE) 164 165 /* CE_HOST_STS1 */ 166 #define STS1_CMDSEQ (1 << 31) 167 168 /* CE_HOST_STS2 */ 169 #define STS2_CRCSTE (1 << 31) 170 #define STS2_CRC16E (1 << 30) 171 #define STS2_AC12CRCE (1 << 29) 172 #define STS2_RSPCRC7E (1 << 28) 173 #define STS2_CRCSTEBE (1 << 27) 174 #define STS2_RDATEBE (1 << 26) 175 #define STS2_AC12REBE (1 << 25) 176 #define STS2_RSPEBE (1 << 24) 177 #define STS2_AC12IDXE (1 << 23) 178 #define STS2_RSPIDXE (1 << 22) 179 #define STS2_CCSTO (1 << 15) 180 #define STS2_RDATTO (1 << 14) 181 #define STS2_DATBSYTO (1 << 13) 182 #define STS2_CRCSTTO (1 << 12) 183 #define STS2_AC12BSYTO (1 << 11) 184 #define STS2_RSPBSYTO (1 << 10) 185 #define STS2_AC12RSPTO (1 << 9) 186 #define STS2_RSPTO (1 << 8) 187 #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 188 STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 189 #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 190 STS2_DATBSYTO | STS2_CRCSTTO | \ 191 STS2_AC12BSYTO | STS2_RSPBSYTO | \ 192 STS2_AC12RSPTO | STS2_RSPTO) 193 194 #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 195 #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 196 #define CLKDEV_INIT 400000 /* 400 KHz */ 197 198 enum sh_mmcif_state { 199 STATE_IDLE, 200 STATE_REQUEST, 201 STATE_IOS, 202 STATE_TIMEOUT, 203 }; 204 205 enum sh_mmcif_wait_for { 206 MMCIF_WAIT_FOR_REQUEST, 207 MMCIF_WAIT_FOR_CMD, 208 MMCIF_WAIT_FOR_MREAD, 209 MMCIF_WAIT_FOR_MWRITE, 210 MMCIF_WAIT_FOR_READ, 211 MMCIF_WAIT_FOR_WRITE, 212 MMCIF_WAIT_FOR_READ_END, 213 MMCIF_WAIT_FOR_WRITE_END, 214 MMCIF_WAIT_FOR_STOP, 215 }; 216 217 /* 218 * difference for each SoC 219 */ 220 struct sh_mmcif_host { 221 struct mmc_host *mmc; 222 struct mmc_request *mrq; 223 struct platform_device *pd; 224 struct clk *clk; 225 int bus_width; 226 unsigned char timing; 227 bool sd_error; 228 bool dying; 229 long timeout; 230 void __iomem *addr; 231 u32 *pio_ptr; 232 spinlock_t lock; /* protect sh_mmcif_host::state */ 233 enum sh_mmcif_state state; 234 enum sh_mmcif_wait_for wait_for; 235 struct delayed_work timeout_work; 236 size_t blocksize; 237 int sg_idx; 238 int sg_blkidx; 239 bool power; 240 bool ccs_enable; /* Command Completion Signal support */ 241 bool clk_ctrl2_enable; 242 struct mutex thread_lock; 243 u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ 244 245 /* DMA support */ 246 struct dma_chan *chan_rx; 247 struct dma_chan *chan_tx; 248 struct completion dma_complete; 249 bool dma_active; 250 }; 251 252 static const struct of_device_id sh_mmcif_of_match[] = { 253 { .compatible = "renesas,sh-mmcif" }, 254 { } 255 }; 256 MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); 257 258 #define sh_mmcif_host_to_dev(host) (&host->pd->dev) 259 260 static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 261 unsigned int reg, u32 val) 262 { 263 writel(val | readl(host->addr + reg), host->addr + reg); 264 } 265 266 static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 267 unsigned int reg, u32 val) 268 { 269 writel(~val & readl(host->addr + reg), host->addr + reg); 270 } 271 272 static void sh_mmcif_dma_complete(void *arg) 273 { 274 struct sh_mmcif_host *host = arg; 275 struct mmc_request *mrq = host->mrq; 276 struct device *dev = sh_mmcif_host_to_dev(host); 277 278 dev_dbg(dev, "Command completed\n"); 279 280 if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 281 dev_name(dev))) 282 return; 283 284 complete(&host->dma_complete); 285 } 286 287 static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 288 { 289 struct mmc_data *data = host->mrq->data; 290 struct scatterlist *sg = data->sg; 291 struct dma_async_tx_descriptor *desc = NULL; 292 struct dma_chan *chan = host->chan_rx; 293 struct device *dev = sh_mmcif_host_to_dev(host); 294 dma_cookie_t cookie = -EINVAL; 295 int ret; 296 297 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 298 DMA_FROM_DEVICE); 299 if (ret > 0) { 300 host->dma_active = true; 301 desc = dmaengine_prep_slave_sg(chan, sg, ret, 302 DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 303 } 304 305 if (desc) { 306 desc->callback = sh_mmcif_dma_complete; 307 desc->callback_param = host; 308 cookie = dmaengine_submit(desc); 309 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 310 dma_async_issue_pending(chan); 311 } 312 dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 313 __func__, data->sg_len, ret, cookie); 314 315 if (!desc) { 316 /* DMA failed, fall back to PIO */ 317 if (ret >= 0) 318 ret = -EIO; 319 host->chan_rx = NULL; 320 host->dma_active = false; 321 dma_release_channel(chan); 322 /* Free the Tx channel too */ 323 chan = host->chan_tx; 324 if (chan) { 325 host->chan_tx = NULL; 326 dma_release_channel(chan); 327 } 328 dev_warn(dev, 329 "DMA failed: %d, falling back to PIO\n", ret); 330 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 331 } 332 333 dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 334 desc, cookie, data->sg_len); 335 } 336 337 static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 338 { 339 struct mmc_data *data = host->mrq->data; 340 struct scatterlist *sg = data->sg; 341 struct dma_async_tx_descriptor *desc = NULL; 342 struct dma_chan *chan = host->chan_tx; 343 struct device *dev = sh_mmcif_host_to_dev(host); 344 dma_cookie_t cookie = -EINVAL; 345 int ret; 346 347 ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 348 DMA_TO_DEVICE); 349 if (ret > 0) { 350 host->dma_active = true; 351 desc = dmaengine_prep_slave_sg(chan, sg, ret, 352 DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 353 } 354 355 if (desc) { 356 desc->callback = sh_mmcif_dma_complete; 357 desc->callback_param = host; 358 cookie = dmaengine_submit(desc); 359 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 360 dma_async_issue_pending(chan); 361 } 362 dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 363 __func__, data->sg_len, ret, cookie); 364 365 if (!desc) { 366 /* DMA failed, fall back to PIO */ 367 if (ret >= 0) 368 ret = -EIO; 369 host->chan_tx = NULL; 370 host->dma_active = false; 371 dma_release_channel(chan); 372 /* Free the Rx channel too */ 373 chan = host->chan_rx; 374 if (chan) { 375 host->chan_rx = NULL; 376 dma_release_channel(chan); 377 } 378 dev_warn(dev, 379 "DMA failed: %d, falling back to PIO\n", ret); 380 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 381 } 382 383 dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, 384 desc, cookie); 385 } 386 387 static struct dma_chan * 388 sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) 389 { 390 dma_cap_mask_t mask; 391 392 dma_cap_zero(mask); 393 dma_cap_set(DMA_SLAVE, mask); 394 if (slave_id <= 0) 395 return NULL; 396 397 return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id); 398 } 399 400 static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, 401 struct dma_chan *chan, 402 enum dma_transfer_direction direction) 403 { 404 struct resource *res; 405 struct dma_slave_config cfg = { 0, }; 406 407 res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 408 cfg.direction = direction; 409 410 if (direction == DMA_DEV_TO_MEM) { 411 cfg.src_addr = res->start + MMCIF_CE_DATA; 412 cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 413 } else { 414 cfg.dst_addr = res->start + MMCIF_CE_DATA; 415 cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 416 } 417 418 return dmaengine_slave_config(chan, &cfg); 419 } 420 421 static void sh_mmcif_request_dma(struct sh_mmcif_host *host) 422 { 423 struct device *dev = sh_mmcif_host_to_dev(host); 424 host->dma_active = false; 425 426 /* We can only either use DMA for both Tx and Rx or not use it at all */ 427 if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) { 428 struct sh_mmcif_plat_data *pdata = dev->platform_data; 429 430 host->chan_tx = sh_mmcif_request_dma_pdata(host, 431 pdata->slave_id_tx); 432 host->chan_rx = sh_mmcif_request_dma_pdata(host, 433 pdata->slave_id_rx); 434 } else { 435 host->chan_tx = dma_request_slave_channel(dev, "tx"); 436 host->chan_rx = dma_request_slave_channel(dev, "rx"); 437 } 438 dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, 439 host->chan_rx); 440 441 if (!host->chan_tx || !host->chan_rx || 442 sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || 443 sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) 444 goto error; 445 446 return; 447 448 error: 449 if (host->chan_tx) 450 dma_release_channel(host->chan_tx); 451 if (host->chan_rx) 452 dma_release_channel(host->chan_rx); 453 host->chan_tx = host->chan_rx = NULL; 454 } 455 456 static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 457 { 458 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 459 /* Descriptors are freed automatically */ 460 if (host->chan_tx) { 461 struct dma_chan *chan = host->chan_tx; 462 host->chan_tx = NULL; 463 dma_release_channel(chan); 464 } 465 if (host->chan_rx) { 466 struct dma_chan *chan = host->chan_rx; 467 host->chan_rx = NULL; 468 dma_release_channel(chan); 469 } 470 471 host->dma_active = false; 472 } 473 474 static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 475 { 476 struct device *dev = sh_mmcif_host_to_dev(host); 477 struct sh_mmcif_plat_data *p = dev->platform_data; 478 bool sup_pclk = p ? p->sup_pclk : false; 479 unsigned int current_clk = clk_get_rate(host->clk); 480 unsigned int clkdiv; 481 482 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 483 sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 484 485 if (!clk) 486 return; 487 488 if (host->clkdiv_map) { 489 unsigned int freq, best_freq, myclk, div, diff_min, diff; 490 int i; 491 492 clkdiv = 0; 493 diff_min = ~0; 494 best_freq = 0; 495 for (i = 31; i >= 0; i--) { 496 if (!((1 << i) & host->clkdiv_map)) 497 continue; 498 499 /* 500 * clk = parent_freq / div 501 * -> parent_freq = clk x div 502 */ 503 504 div = 1 << (i + 1); 505 freq = clk_round_rate(host->clk, clk * div); 506 myclk = freq / div; 507 diff = (myclk > clk) ? myclk - clk : clk - myclk; 508 509 if (diff <= diff_min) { 510 best_freq = freq; 511 clkdiv = i; 512 diff_min = diff; 513 } 514 } 515 516 dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", 517 (best_freq / (1 << (clkdiv + 1))), clk, 518 best_freq, clkdiv); 519 520 clk_set_rate(host->clk, best_freq); 521 clkdiv = clkdiv << 16; 522 } else if (sup_pclk && clk == current_clk) { 523 clkdiv = CLK_SUP_PCLK; 524 } else { 525 clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; 526 } 527 528 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); 529 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 530 } 531 532 static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 533 { 534 u32 tmp; 535 536 tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 537 538 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 539 sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 540 if (host->ccs_enable) 541 tmp |= SCCSTO_29; 542 if (host->clk_ctrl2_enable) 543 sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 544 sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 545 SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 546 /* byte swap on */ 547 sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 548 } 549 550 static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 551 { 552 struct device *dev = sh_mmcif_host_to_dev(host); 553 u32 state1, state2; 554 int ret, timeout; 555 556 host->sd_error = false; 557 558 state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 559 state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 560 dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); 561 dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); 562 563 if (state1 & STS1_CMDSEQ) { 564 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 565 sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 566 for (timeout = 10000; timeout; timeout--) { 567 if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 568 & STS1_CMDSEQ)) 569 break; 570 mdelay(1); 571 } 572 if (!timeout) { 573 dev_err(dev, 574 "Forced end of command sequence timeout err\n"); 575 return -EIO; 576 } 577 sh_mmcif_sync_reset(host); 578 dev_dbg(dev, "Forced end of command sequence\n"); 579 return -EIO; 580 } 581 582 if (state2 & STS2_CRC_ERR) { 583 dev_err(dev, " CRC error: state %u, wait %u\n", 584 host->state, host->wait_for); 585 ret = -EIO; 586 } else if (state2 & STS2_TIMEOUT_ERR) { 587 dev_err(dev, " Timeout: state %u, wait %u\n", 588 host->state, host->wait_for); 589 ret = -ETIMEDOUT; 590 } else { 591 dev_dbg(dev, " End/Index error: state %u, wait %u\n", 592 host->state, host->wait_for); 593 ret = -EIO; 594 } 595 return ret; 596 } 597 598 static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 599 { 600 struct mmc_data *data = host->mrq->data; 601 602 host->sg_blkidx += host->blocksize; 603 604 /* data->sg->length must be a multiple of host->blocksize? */ 605 BUG_ON(host->sg_blkidx > data->sg->length); 606 607 if (host->sg_blkidx == data->sg->length) { 608 host->sg_blkidx = 0; 609 if (++host->sg_idx < data->sg_len) 610 host->pio_ptr = sg_virt(++data->sg); 611 } else { 612 host->pio_ptr = p; 613 } 614 615 return host->sg_idx != data->sg_len; 616 } 617 618 static void sh_mmcif_single_read(struct sh_mmcif_host *host, 619 struct mmc_request *mrq) 620 { 621 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 622 BLOCK_SIZE_MASK) + 3; 623 624 host->wait_for = MMCIF_WAIT_FOR_READ; 625 626 /* buf read enable */ 627 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 628 } 629 630 static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 631 { 632 struct device *dev = sh_mmcif_host_to_dev(host); 633 struct mmc_data *data = host->mrq->data; 634 u32 *p = sg_virt(data->sg); 635 int i; 636 637 if (host->sd_error) { 638 data->error = sh_mmcif_error_manage(host); 639 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 640 return false; 641 } 642 643 for (i = 0; i < host->blocksize / 4; i++) 644 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 645 646 /* buffer read end */ 647 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 648 host->wait_for = MMCIF_WAIT_FOR_READ_END; 649 650 return true; 651 } 652 653 static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 654 struct mmc_request *mrq) 655 { 656 struct mmc_data *data = mrq->data; 657 658 if (!data->sg_len || !data->sg->length) 659 return; 660 661 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 662 BLOCK_SIZE_MASK; 663 664 host->wait_for = MMCIF_WAIT_FOR_MREAD; 665 host->sg_idx = 0; 666 host->sg_blkidx = 0; 667 host->pio_ptr = sg_virt(data->sg); 668 669 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 670 } 671 672 static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 673 { 674 struct device *dev = sh_mmcif_host_to_dev(host); 675 struct mmc_data *data = host->mrq->data; 676 u32 *p = host->pio_ptr; 677 int i; 678 679 if (host->sd_error) { 680 data->error = sh_mmcif_error_manage(host); 681 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 682 return false; 683 } 684 685 BUG_ON(!data->sg->length); 686 687 for (i = 0; i < host->blocksize / 4; i++) 688 *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 689 690 if (!sh_mmcif_next_block(host, p)) 691 return false; 692 693 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 694 695 return true; 696 } 697 698 static void sh_mmcif_single_write(struct sh_mmcif_host *host, 699 struct mmc_request *mrq) 700 { 701 host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 702 BLOCK_SIZE_MASK) + 3; 703 704 host->wait_for = MMCIF_WAIT_FOR_WRITE; 705 706 /* buf write enable */ 707 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 708 } 709 710 static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 711 { 712 struct device *dev = sh_mmcif_host_to_dev(host); 713 struct mmc_data *data = host->mrq->data; 714 u32 *p = sg_virt(data->sg); 715 int i; 716 717 if (host->sd_error) { 718 data->error = sh_mmcif_error_manage(host); 719 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 720 return false; 721 } 722 723 for (i = 0; i < host->blocksize / 4; i++) 724 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 725 726 /* buffer write end */ 727 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 728 host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 729 730 return true; 731 } 732 733 static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 734 struct mmc_request *mrq) 735 { 736 struct mmc_data *data = mrq->data; 737 738 if (!data->sg_len || !data->sg->length) 739 return; 740 741 host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 742 BLOCK_SIZE_MASK; 743 744 host->wait_for = MMCIF_WAIT_FOR_MWRITE; 745 host->sg_idx = 0; 746 host->sg_blkidx = 0; 747 host->pio_ptr = sg_virt(data->sg); 748 749 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 750 } 751 752 static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 753 { 754 struct device *dev = sh_mmcif_host_to_dev(host); 755 struct mmc_data *data = host->mrq->data; 756 u32 *p = host->pio_ptr; 757 int i; 758 759 if (host->sd_error) { 760 data->error = sh_mmcif_error_manage(host); 761 dev_dbg(dev, "%s(): %d\n", __func__, data->error); 762 return false; 763 } 764 765 BUG_ON(!data->sg->length); 766 767 for (i = 0; i < host->blocksize / 4; i++) 768 sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 769 770 if (!sh_mmcif_next_block(host, p)) 771 return false; 772 773 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 774 775 return true; 776 } 777 778 static void sh_mmcif_get_response(struct sh_mmcif_host *host, 779 struct mmc_command *cmd) 780 { 781 if (cmd->flags & MMC_RSP_136) { 782 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 783 cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 784 cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 785 cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 786 } else 787 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 788 } 789 790 static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 791 struct mmc_command *cmd) 792 { 793 cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 794 } 795 796 static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 797 struct mmc_request *mrq) 798 { 799 struct device *dev = sh_mmcif_host_to_dev(host); 800 struct mmc_data *data = mrq->data; 801 struct mmc_command *cmd = mrq->cmd; 802 u32 opc = cmd->opcode; 803 u32 tmp = 0; 804 805 /* Response Type check */ 806 switch (mmc_resp_type(cmd)) { 807 case MMC_RSP_NONE: 808 tmp |= CMD_SET_RTYP_NO; 809 break; 810 case MMC_RSP_R1: 811 case MMC_RSP_R3: 812 tmp |= CMD_SET_RTYP_6B; 813 break; 814 case MMC_RSP_R1B: 815 tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B; 816 break; 817 case MMC_RSP_R2: 818 tmp |= CMD_SET_RTYP_17B; 819 break; 820 default: 821 dev_err(dev, "Unsupported response type.\n"); 822 break; 823 } 824 825 /* WDAT / DATW */ 826 if (data) { 827 tmp |= CMD_SET_WDAT; 828 switch (host->bus_width) { 829 case MMC_BUS_WIDTH_1: 830 tmp |= CMD_SET_DATW_1; 831 break; 832 case MMC_BUS_WIDTH_4: 833 tmp |= CMD_SET_DATW_4; 834 break; 835 case MMC_BUS_WIDTH_8: 836 tmp |= CMD_SET_DATW_8; 837 break; 838 default: 839 dev_err(dev, "Unsupported bus width.\n"); 840 break; 841 } 842 switch (host->timing) { 843 case MMC_TIMING_MMC_DDR52: 844 /* 845 * MMC core will only set this timing, if the host 846 * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 847 * capability. MMCIF implementations with this 848 * capability, e.g. sh73a0, will have to set it 849 * in their platform data. 850 */ 851 tmp |= CMD_SET_DARS; 852 break; 853 } 854 } 855 /* DWEN */ 856 if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 857 tmp |= CMD_SET_DWEN; 858 /* CMLTE/CMD12EN */ 859 if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 860 tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 861 sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 862 data->blocks << 16); 863 } 864 /* RIDXC[1:0] check bits */ 865 if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 866 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 867 tmp |= CMD_SET_RIDXC_BITS; 868 /* RCRC7C[1:0] check bits */ 869 if (opc == MMC_SEND_OP_COND) 870 tmp |= CMD_SET_CRC7C_BITS; 871 /* RCRC7C[1:0] internal CRC7 */ 872 if (opc == MMC_ALL_SEND_CID || 873 opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 874 tmp |= CMD_SET_CRC7C_INTERNAL; 875 876 return (opc << 24) | tmp; 877 } 878 879 static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 880 struct mmc_request *mrq, u32 opc) 881 { 882 struct device *dev = sh_mmcif_host_to_dev(host); 883 884 switch (opc) { 885 case MMC_READ_MULTIPLE_BLOCK: 886 sh_mmcif_multi_read(host, mrq); 887 return 0; 888 case MMC_WRITE_MULTIPLE_BLOCK: 889 sh_mmcif_multi_write(host, mrq); 890 return 0; 891 case MMC_WRITE_BLOCK: 892 sh_mmcif_single_write(host, mrq); 893 return 0; 894 case MMC_READ_SINGLE_BLOCK: 895 case MMC_SEND_EXT_CSD: 896 sh_mmcif_single_read(host, mrq); 897 return 0; 898 default: 899 dev_err(dev, "Unsupported CMD%d\n", opc); 900 return -EINVAL; 901 } 902 } 903 904 static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 905 struct mmc_request *mrq) 906 { 907 struct mmc_command *cmd = mrq->cmd; 908 u32 opc; 909 u32 mask = 0; 910 unsigned long flags; 911 912 if (cmd->flags & MMC_RSP_BUSY) 913 mask = MASK_START_CMD | MASK_MRBSYE; 914 else 915 mask = MASK_START_CMD | MASK_MCRSPE; 916 917 if (host->ccs_enable) 918 mask |= MASK_MCCSTO; 919 920 if (mrq->data) { 921 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 922 sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 923 mrq->data->blksz); 924 } 925 opc = sh_mmcif_set_cmd(host, mrq); 926 927 if (host->ccs_enable) 928 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 929 else 930 sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 931 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 932 /* set arg */ 933 sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 934 /* set cmd */ 935 spin_lock_irqsave(&host->lock, flags); 936 sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 937 938 host->wait_for = MMCIF_WAIT_FOR_CMD; 939 schedule_delayed_work(&host->timeout_work, host->timeout); 940 spin_unlock_irqrestore(&host->lock, flags); 941 } 942 943 static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 944 struct mmc_request *mrq) 945 { 946 struct device *dev = sh_mmcif_host_to_dev(host); 947 948 switch (mrq->cmd->opcode) { 949 case MMC_READ_MULTIPLE_BLOCK: 950 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 951 break; 952 case MMC_WRITE_MULTIPLE_BLOCK: 953 sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 954 break; 955 default: 956 dev_err(dev, "unsupported stop cmd\n"); 957 mrq->stop->error = sh_mmcif_error_manage(host); 958 return; 959 } 960 961 host->wait_for = MMCIF_WAIT_FOR_STOP; 962 } 963 964 static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 965 { 966 struct sh_mmcif_host *host = mmc_priv(mmc); 967 struct device *dev = sh_mmcif_host_to_dev(host); 968 unsigned long flags; 969 970 spin_lock_irqsave(&host->lock, flags); 971 if (host->state != STATE_IDLE) { 972 dev_dbg(dev, "%s() rejected, state %u\n", 973 __func__, host->state); 974 spin_unlock_irqrestore(&host->lock, flags); 975 mrq->cmd->error = -EAGAIN; 976 mmc_request_done(mmc, mrq); 977 return; 978 } 979 980 host->state = STATE_REQUEST; 981 spin_unlock_irqrestore(&host->lock, flags); 982 983 host->mrq = mrq; 984 985 sh_mmcif_start_cmd(host, mrq); 986 } 987 988 static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) 989 { 990 struct device *dev = sh_mmcif_host_to_dev(host); 991 992 if (host->mmc->f_max) { 993 unsigned int f_max, f_min = 0, f_min_old; 994 995 f_max = host->mmc->f_max; 996 for (f_min_old = f_max; f_min_old > 2;) { 997 f_min = clk_round_rate(host->clk, f_min_old / 2); 998 if (f_min == f_min_old) 999 break; 1000 f_min_old = f_min; 1001 } 1002 1003 /* 1004 * This driver assumes this SoC is R-Car Gen2 or later 1005 */ 1006 host->clkdiv_map = 0x3ff; 1007 1008 host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); 1009 host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); 1010 } else { 1011 unsigned int clk = clk_get_rate(host->clk); 1012 1013 host->mmc->f_max = clk / 2; 1014 host->mmc->f_min = clk / 512; 1015 } 1016 1017 dev_dbg(dev, "clk max/min = %d/%d\n", 1018 host->mmc->f_max, host->mmc->f_min); 1019 } 1020 1021 static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1022 { 1023 struct sh_mmcif_host *host = mmc_priv(mmc); 1024 struct device *dev = sh_mmcif_host_to_dev(host); 1025 unsigned long flags; 1026 1027 spin_lock_irqsave(&host->lock, flags); 1028 if (host->state != STATE_IDLE) { 1029 dev_dbg(dev, "%s() rejected, state %u\n", 1030 __func__, host->state); 1031 spin_unlock_irqrestore(&host->lock, flags); 1032 return; 1033 } 1034 1035 host->state = STATE_IOS; 1036 spin_unlock_irqrestore(&host->lock, flags); 1037 1038 switch (ios->power_mode) { 1039 case MMC_POWER_UP: 1040 if (!IS_ERR(mmc->supply.vmmc)) 1041 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1042 if (!host->power) { 1043 clk_prepare_enable(host->clk); 1044 pm_runtime_get_sync(dev); 1045 sh_mmcif_sync_reset(host); 1046 sh_mmcif_request_dma(host); 1047 host->power = true; 1048 } 1049 break; 1050 case MMC_POWER_OFF: 1051 if (!IS_ERR(mmc->supply.vmmc)) 1052 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 1053 if (host->power) { 1054 sh_mmcif_clock_control(host, 0); 1055 sh_mmcif_release_dma(host); 1056 pm_runtime_put(dev); 1057 clk_disable_unprepare(host->clk); 1058 host->power = false; 1059 } 1060 break; 1061 case MMC_POWER_ON: 1062 sh_mmcif_clock_control(host, ios->clock); 1063 break; 1064 } 1065 1066 host->timing = ios->timing; 1067 host->bus_width = ios->bus_width; 1068 host->state = STATE_IDLE; 1069 } 1070 1071 static const struct mmc_host_ops sh_mmcif_ops = { 1072 .request = sh_mmcif_request, 1073 .set_ios = sh_mmcif_set_ios, 1074 .get_cd = mmc_gpio_get_cd, 1075 }; 1076 1077 static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1078 { 1079 struct mmc_command *cmd = host->mrq->cmd; 1080 struct mmc_data *data = host->mrq->data; 1081 struct device *dev = sh_mmcif_host_to_dev(host); 1082 long time; 1083 1084 if (host->sd_error) { 1085 switch (cmd->opcode) { 1086 case MMC_ALL_SEND_CID: 1087 case MMC_SELECT_CARD: 1088 case MMC_APP_CMD: 1089 cmd->error = -ETIMEDOUT; 1090 break; 1091 default: 1092 cmd->error = sh_mmcif_error_manage(host); 1093 break; 1094 } 1095 dev_dbg(dev, "CMD%d error %d\n", 1096 cmd->opcode, cmd->error); 1097 host->sd_error = false; 1098 return false; 1099 } 1100 if (!(cmd->flags & MMC_RSP_PRESENT)) { 1101 cmd->error = 0; 1102 return false; 1103 } 1104 1105 sh_mmcif_get_response(host, cmd); 1106 1107 if (!data) 1108 return false; 1109 1110 /* 1111 * Completion can be signalled from DMA callback and error, so, have to 1112 * reset here, before setting .dma_active 1113 */ 1114 init_completion(&host->dma_complete); 1115 1116 if (data->flags & MMC_DATA_READ) { 1117 if (host->chan_rx) 1118 sh_mmcif_start_dma_rx(host); 1119 } else { 1120 if (host->chan_tx) 1121 sh_mmcif_start_dma_tx(host); 1122 } 1123 1124 if (!host->dma_active) { 1125 data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 1126 return !data->error; 1127 } 1128 1129 /* Running in the IRQ thread, can sleep */ 1130 time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1131 host->timeout); 1132 1133 if (data->flags & MMC_DATA_READ) 1134 dma_unmap_sg(host->chan_rx->device->dev, 1135 data->sg, data->sg_len, 1136 DMA_FROM_DEVICE); 1137 else 1138 dma_unmap_sg(host->chan_tx->device->dev, 1139 data->sg, data->sg_len, 1140 DMA_TO_DEVICE); 1141 1142 if (host->sd_error) { 1143 dev_err(host->mmc->parent, 1144 "Error IRQ while waiting for DMA completion!\n"); 1145 /* Woken up by an error IRQ: abort DMA */ 1146 data->error = sh_mmcif_error_manage(host); 1147 } else if (!time) { 1148 dev_err(host->mmc->parent, "DMA timeout!\n"); 1149 data->error = -ETIMEDOUT; 1150 } else if (time < 0) { 1151 dev_err(host->mmc->parent, 1152 "wait_for_completion_...() error %ld!\n", time); 1153 data->error = time; 1154 } 1155 sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1156 BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1157 host->dma_active = false; 1158 1159 if (data->error) { 1160 data->bytes_xfered = 0; 1161 /* Abort DMA */ 1162 if (data->flags & MMC_DATA_READ) 1163 dmaengine_terminate_all(host->chan_rx); 1164 else 1165 dmaengine_terminate_all(host->chan_tx); 1166 } 1167 1168 return false; 1169 } 1170 1171 static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1172 { 1173 struct sh_mmcif_host *host = dev_id; 1174 struct mmc_request *mrq; 1175 struct device *dev = sh_mmcif_host_to_dev(host); 1176 bool wait = false; 1177 unsigned long flags; 1178 int wait_work; 1179 1180 spin_lock_irqsave(&host->lock, flags); 1181 wait_work = host->wait_for; 1182 spin_unlock_irqrestore(&host->lock, flags); 1183 1184 cancel_delayed_work_sync(&host->timeout_work); 1185 1186 mutex_lock(&host->thread_lock); 1187 1188 mrq = host->mrq; 1189 if (!mrq) { 1190 dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 1191 host->state, host->wait_for); 1192 mutex_unlock(&host->thread_lock); 1193 return IRQ_HANDLED; 1194 } 1195 1196 /* 1197 * All handlers return true, if processing continues, and false, if the 1198 * request has to be completed - successfully or not 1199 */ 1200 switch (wait_work) { 1201 case MMCIF_WAIT_FOR_REQUEST: 1202 /* We're too late, the timeout has already kicked in */ 1203 mutex_unlock(&host->thread_lock); 1204 return IRQ_HANDLED; 1205 case MMCIF_WAIT_FOR_CMD: 1206 /* Wait for data? */ 1207 wait = sh_mmcif_end_cmd(host); 1208 break; 1209 case MMCIF_WAIT_FOR_MREAD: 1210 /* Wait for more data? */ 1211 wait = sh_mmcif_mread_block(host); 1212 break; 1213 case MMCIF_WAIT_FOR_READ: 1214 /* Wait for data end? */ 1215 wait = sh_mmcif_read_block(host); 1216 break; 1217 case MMCIF_WAIT_FOR_MWRITE: 1218 /* Wait data to write? */ 1219 wait = sh_mmcif_mwrite_block(host); 1220 break; 1221 case MMCIF_WAIT_FOR_WRITE: 1222 /* Wait for data end? */ 1223 wait = sh_mmcif_write_block(host); 1224 break; 1225 case MMCIF_WAIT_FOR_STOP: 1226 if (host->sd_error) { 1227 mrq->stop->error = sh_mmcif_error_manage(host); 1228 dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); 1229 break; 1230 } 1231 sh_mmcif_get_cmd12response(host, mrq->stop); 1232 mrq->stop->error = 0; 1233 break; 1234 case MMCIF_WAIT_FOR_READ_END: 1235 case MMCIF_WAIT_FOR_WRITE_END: 1236 if (host->sd_error) { 1237 mrq->data->error = sh_mmcif_error_manage(host); 1238 dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); 1239 } 1240 break; 1241 default: 1242 BUG(); 1243 } 1244 1245 if (wait) { 1246 schedule_delayed_work(&host->timeout_work, host->timeout); 1247 /* Wait for more data */ 1248 mutex_unlock(&host->thread_lock); 1249 return IRQ_HANDLED; 1250 } 1251 1252 if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 1253 struct mmc_data *data = mrq->data; 1254 if (!mrq->cmd->error && data && !data->error) 1255 data->bytes_xfered = 1256 data->blocks * data->blksz; 1257 1258 if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1259 sh_mmcif_stop_cmd(host, mrq); 1260 if (!mrq->stop->error) { 1261 schedule_delayed_work(&host->timeout_work, host->timeout); 1262 mutex_unlock(&host->thread_lock); 1263 return IRQ_HANDLED; 1264 } 1265 } 1266 } 1267 1268 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1269 host->state = STATE_IDLE; 1270 host->mrq = NULL; 1271 mmc_request_done(host->mmc, mrq); 1272 1273 mutex_unlock(&host->thread_lock); 1274 1275 return IRQ_HANDLED; 1276 } 1277 1278 static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1279 { 1280 struct sh_mmcif_host *host = dev_id; 1281 struct device *dev = sh_mmcif_host_to_dev(host); 1282 u32 state, mask; 1283 1284 state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1285 mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1286 if (host->ccs_enable) 1287 sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1288 else 1289 sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 1290 sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1291 1292 if (state & ~MASK_CLEAN) 1293 dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", 1294 state); 1295 1296 if (state & INT_ERR_STS || state & ~INT_ALL) { 1297 host->sd_error = true; 1298 dev_dbg(dev, "int err state = 0x%08x\n", state); 1299 } 1300 if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1301 if (!host->mrq) 1302 dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); 1303 if (!host->dma_active) 1304 return IRQ_WAKE_THREAD; 1305 else if (host->sd_error) 1306 sh_mmcif_dma_complete(host); 1307 } else { 1308 dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); 1309 } 1310 1311 return IRQ_HANDLED; 1312 } 1313 1314 static void sh_mmcif_timeout_work(struct work_struct *work) 1315 { 1316 struct delayed_work *d = to_delayed_work(work); 1317 struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1318 struct mmc_request *mrq = host->mrq; 1319 struct device *dev = sh_mmcif_host_to_dev(host); 1320 unsigned long flags; 1321 1322 if (host->dying) 1323 /* Don't run after mmc_remove_host() */ 1324 return; 1325 1326 spin_lock_irqsave(&host->lock, flags); 1327 if (host->state == STATE_IDLE) { 1328 spin_unlock_irqrestore(&host->lock, flags); 1329 return; 1330 } 1331 1332 dev_err(dev, "Timeout waiting for %u on CMD%u\n", 1333 host->wait_for, mrq->cmd->opcode); 1334 1335 host->state = STATE_TIMEOUT; 1336 spin_unlock_irqrestore(&host->lock, flags); 1337 1338 /* 1339 * Handle races with cancel_delayed_work(), unless 1340 * cancel_delayed_work_sync() is used 1341 */ 1342 switch (host->wait_for) { 1343 case MMCIF_WAIT_FOR_CMD: 1344 mrq->cmd->error = sh_mmcif_error_manage(host); 1345 break; 1346 case MMCIF_WAIT_FOR_STOP: 1347 mrq->stop->error = sh_mmcif_error_manage(host); 1348 break; 1349 case MMCIF_WAIT_FOR_MREAD: 1350 case MMCIF_WAIT_FOR_MWRITE: 1351 case MMCIF_WAIT_FOR_READ: 1352 case MMCIF_WAIT_FOR_WRITE: 1353 case MMCIF_WAIT_FOR_READ_END: 1354 case MMCIF_WAIT_FOR_WRITE_END: 1355 mrq->data->error = sh_mmcif_error_manage(host); 1356 break; 1357 default: 1358 BUG(); 1359 } 1360 1361 host->state = STATE_IDLE; 1362 host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1363 host->mrq = NULL; 1364 mmc_request_done(host->mmc, mrq); 1365 } 1366 1367 static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 1368 { 1369 struct device *dev = sh_mmcif_host_to_dev(host); 1370 struct sh_mmcif_plat_data *pd = dev->platform_data; 1371 struct mmc_host *mmc = host->mmc; 1372 1373 mmc_regulator_get_supply(mmc); 1374 1375 if (!pd) 1376 return; 1377 1378 if (!mmc->ocr_avail) 1379 mmc->ocr_avail = pd->ocr; 1380 else if (pd->ocr) 1381 dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 1382 } 1383 1384 static int sh_mmcif_probe(struct platform_device *pdev) 1385 { 1386 int ret = 0, irq[2]; 1387 struct mmc_host *mmc; 1388 struct sh_mmcif_host *host; 1389 struct device *dev = &pdev->dev; 1390 struct sh_mmcif_plat_data *pd = dev->platform_data; 1391 struct resource *res; 1392 void __iomem *reg; 1393 const char *name; 1394 1395 irq[0] = platform_get_irq(pdev, 0); 1396 irq[1] = platform_get_irq_optional(pdev, 1); 1397 if (irq[0] < 0) 1398 return -ENXIO; 1399 1400 res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1401 reg = devm_ioremap_resource(dev, res); 1402 if (IS_ERR(reg)) 1403 return PTR_ERR(reg); 1404 1405 mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 1406 if (!mmc) 1407 return -ENOMEM; 1408 1409 ret = mmc_of_parse(mmc); 1410 if (ret < 0) 1411 goto err_host; 1412 1413 host = mmc_priv(mmc); 1414 host->mmc = mmc; 1415 host->addr = reg; 1416 host->timeout = msecs_to_jiffies(10000); 1417 host->ccs_enable = true; 1418 host->clk_ctrl2_enable = false; 1419 1420 host->pd = pdev; 1421 1422 spin_lock_init(&host->lock); 1423 1424 mmc->ops = &sh_mmcif_ops; 1425 sh_mmcif_init_ocr(host); 1426 1427 mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1428 mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 1429 mmc->max_busy_timeout = 10000; 1430 1431 if (pd && pd->caps) 1432 mmc->caps |= pd->caps; 1433 mmc->max_segs = 32; 1434 mmc->max_blk_size = 512; 1435 mmc->max_req_size = PAGE_SIZE * mmc->max_segs; 1436 mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1437 mmc->max_seg_size = mmc->max_req_size; 1438 1439 platform_set_drvdata(pdev, host); 1440 1441 host->clk = devm_clk_get(dev, NULL); 1442 if (IS_ERR(host->clk)) { 1443 ret = PTR_ERR(host->clk); 1444 dev_err(dev, "cannot get clock: %d\n", ret); 1445 goto err_host; 1446 } 1447 1448 ret = clk_prepare_enable(host->clk); 1449 if (ret < 0) 1450 goto err_host; 1451 1452 sh_mmcif_clk_setup(host); 1453 1454 pm_runtime_enable(dev); 1455 host->power = false; 1456 1457 ret = pm_runtime_get_sync(dev); 1458 if (ret < 0) 1459 goto err_clk; 1460 1461 INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); 1462 1463 sh_mmcif_sync_reset(host); 1464 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1465 1466 name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; 1467 ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, 1468 sh_mmcif_irqt, 0, name, host); 1469 if (ret) { 1470 dev_err(dev, "request_irq error (%s)\n", name); 1471 goto err_clk; 1472 } 1473 if (irq[1] >= 0) { 1474 ret = devm_request_threaded_irq(dev, irq[1], 1475 sh_mmcif_intr, sh_mmcif_irqt, 1476 0, "sh_mmc:int", host); 1477 if (ret) { 1478 dev_err(dev, "request_irq error (sh_mmc:int)\n"); 1479 goto err_clk; 1480 } 1481 } 1482 1483 mutex_init(&host->thread_lock); 1484 1485 ret = mmc_add_host(mmc); 1486 if (ret < 0) 1487 goto err_clk; 1488 1489 dev_pm_qos_expose_latency_limit(dev, 100); 1490 1491 dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", 1492 sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 1493 clk_get_rate(host->clk) / 1000000UL); 1494 1495 pm_runtime_put(dev); 1496 clk_disable_unprepare(host->clk); 1497 return ret; 1498 1499 err_clk: 1500 clk_disable_unprepare(host->clk); 1501 pm_runtime_put_sync(dev); 1502 pm_runtime_disable(dev); 1503 err_host: 1504 mmc_free_host(mmc); 1505 return ret; 1506 } 1507 1508 static int sh_mmcif_remove(struct platform_device *pdev) 1509 { 1510 struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1511 1512 host->dying = true; 1513 clk_prepare_enable(host->clk); 1514 pm_runtime_get_sync(&pdev->dev); 1515 1516 dev_pm_qos_hide_latency_limit(&pdev->dev); 1517 1518 mmc_remove_host(host->mmc); 1519 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1520 1521 /* 1522 * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1523 * mmc_remove_host() call above. But swapping order doesn't help either 1524 * (a query on the linux-mmc mailing list didn't bring any replies). 1525 */ 1526 cancel_delayed_work_sync(&host->timeout_work); 1527 1528 clk_disable_unprepare(host->clk); 1529 mmc_free_host(host->mmc); 1530 pm_runtime_put_sync(&pdev->dev); 1531 pm_runtime_disable(&pdev->dev); 1532 1533 return 0; 1534 } 1535 1536 #ifdef CONFIG_PM_SLEEP 1537 static int sh_mmcif_suspend(struct device *dev) 1538 { 1539 struct sh_mmcif_host *host = dev_get_drvdata(dev); 1540 1541 pm_runtime_get_sync(dev); 1542 sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1543 pm_runtime_put(dev); 1544 1545 return 0; 1546 } 1547 1548 static int sh_mmcif_resume(struct device *dev) 1549 { 1550 return 0; 1551 } 1552 #endif 1553 1554 static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1555 SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1556 }; 1557 1558 static struct platform_driver sh_mmcif_driver = { 1559 .probe = sh_mmcif_probe, 1560 .remove = sh_mmcif_remove, 1561 .driver = { 1562 .name = DRIVER_NAME, 1563 .pm = &sh_mmcif_dev_pm_ops, 1564 .of_match_table = sh_mmcif_of_match, 1565 }, 1566 }; 1567 1568 module_platform_driver(sh_mmcif_driver); 1569 1570 MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1571 MODULE_LICENSE("GPL v2"); 1572 MODULE_ALIAS("platform:" DRIVER_NAME); 1573 MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1574