1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 598047310eSGuennadi Liakhovetski #include <linux/mutex.h> 60a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 61e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 62efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 63faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 64d00cadacSGuennadi Liakhovetski #include <linux/sh_dma.h> 653b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6688b47679SPaul Gortmaker #include <linux/module.h> 67fdc50a94SYusuke Goda 68fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 69fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 70fdc50a94SYusuke Goda 71fdc50a94SYusuke Goda /* CE_CMD_SET */ 72fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 73fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 74fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 75fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 76fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 77fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 78fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 79fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 80fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 81fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 82fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 83fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 84fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 85fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 86fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 88fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 89fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 90fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 91fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 92fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 93555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 94fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 95fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 96fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 97fdc50a94SYusuke Goda 98fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 99fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 100fdc50a94SYusuke Goda 101fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 102fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 103fdc50a94SYusuke Goda 104fdc50a94SYusuke Goda /* CE_INT */ 105fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 106fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 107fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 108fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 109fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 110fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 111fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 112fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 113fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 114fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 115fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 116fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 117fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 118fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 119fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 120fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 121fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 122fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 123fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 124fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 125fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 126fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 127fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 128fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 129fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 130fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 131fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 132fdc50a94SYusuke Goda 1338af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 1348af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 1358af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 1368af50750SGuennadi Liakhovetski 137967bcb77SGuennadi Liakhovetski #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 138967bcb77SGuennadi Liakhovetski 139fdc50a94SYusuke Goda /* CE_INT_MASK */ 140fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 141fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 142fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 143fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 144fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 145fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 146fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 147fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 148fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 149fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 150fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 151fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 152fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 153fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 154fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 155fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 156fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 157fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 158fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 159fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 160fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 161fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 162fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 163fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 164fdc50a94SYusuke Goda 165ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 166ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 167967bcb77SGuennadi Liakhovetski MASK_MCRCSTO | MASK_MWDATTO | \ 168ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 169ee4b8887SGuennadi Liakhovetski 1708af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 1718af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \ 1728af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 1738af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE) 1748af50750SGuennadi Liakhovetski 175fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 176fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 177fdc50a94SYusuke Goda 178fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 179fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 180fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 181fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 182fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 183fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 184fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 185fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 186fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 187fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 188fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 189fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 190fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 191fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 192fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 193fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 194fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 195fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 196fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 197fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 198fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 199fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 200fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 201fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 202fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 203fdc50a94SYusuke Goda 204fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 205fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 206fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 207fdc50a94SYusuke Goda 2083b0beafcSGuennadi Liakhovetski enum mmcif_state { 2093b0beafcSGuennadi Liakhovetski STATE_IDLE, 2103b0beafcSGuennadi Liakhovetski STATE_REQUEST, 2113b0beafcSGuennadi Liakhovetski STATE_IOS, 2128047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2133b0beafcSGuennadi Liakhovetski }; 2143b0beafcSGuennadi Liakhovetski 215f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 216f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 217f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 218f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 219f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 220f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 221f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 222f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 223f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 224f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 225f985da17SGuennadi Liakhovetski }; 226f985da17SGuennadi Liakhovetski 227fdc50a94SYusuke Goda struct sh_mmcif_host { 228fdc50a94SYusuke Goda struct mmc_host *mmc; 229f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 230fdc50a94SYusuke Goda struct platform_device *pd; 231fdc50a94SYusuke Goda struct clk *hclk; 232fdc50a94SYusuke Goda unsigned int clk; 233fdc50a94SYusuke Goda int bus_width; 234555061f9STeppei Kamijou unsigned char timing; 235aa0787a9SGuennadi Liakhovetski bool sd_error; 236f985da17SGuennadi Liakhovetski bool dying; 237fdc50a94SYusuke Goda long timeout; 238fdc50a94SYusuke Goda void __iomem *addr; 239f985da17SGuennadi Liakhovetski u32 *pio_ptr; 240ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2413b0beafcSGuennadi Liakhovetski enum mmcif_state state; 242f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 243f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 244f985da17SGuennadi Liakhovetski size_t blocksize; 245f985da17SGuennadi Liakhovetski int sg_idx; 246f985da17SGuennadi Liakhovetski int sg_blkidx; 247faca6648SGuennadi Liakhovetski bool power; 248c9b0cef2SGuennadi Liakhovetski bool card_present; 249967bcb77SGuennadi Liakhovetski bool ccs_enable; /* Command Completion Signal support */ 2506d6fd367SGuennadi Liakhovetski bool clk_ctrl2_enable; 2518047310eSGuennadi Liakhovetski struct mutex thread_lock; 252fdc50a94SYusuke Goda 253a782d688SGuennadi Liakhovetski /* DMA support */ 254a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 255a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 256a782d688SGuennadi Liakhovetski struct completion dma_complete; 257f38f94c6SLinus Walleij bool dma_active; 258a782d688SGuennadi Liakhovetski }; 259fdc50a94SYusuke Goda 260fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 261fdc50a94SYusuke Goda unsigned int reg, u32 val) 262fdc50a94SYusuke Goda { 263487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 264fdc50a94SYusuke Goda } 265fdc50a94SYusuke Goda 266fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 267fdc50a94SYusuke Goda unsigned int reg, u32 val) 268fdc50a94SYusuke Goda { 269487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 270fdc50a94SYusuke Goda } 271fdc50a94SYusuke Goda 272a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 273a782d688SGuennadi Liakhovetski { 274a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2758047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 27669983404SGuennadi Liakhovetski 277a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 278a782d688SGuennadi Liakhovetski 2798047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 280a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 281a782d688SGuennadi Liakhovetski return; 282a782d688SGuennadi Liakhovetski 283a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 284a782d688SGuennadi Liakhovetski } 285a782d688SGuennadi Liakhovetski 286a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 287a782d688SGuennadi Liakhovetski { 28869983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 28969983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 290a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 291a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 292a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 293a782d688SGuennadi Liakhovetski int ret; 294a782d688SGuennadi Liakhovetski 29569983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 2961ed828dbSLinus Walleij DMA_FROM_DEVICE); 297a782d688SGuennadi Liakhovetski if (ret > 0) { 298f38f94c6SLinus Walleij host->dma_active = true; 29916052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 30005f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 301a782d688SGuennadi Liakhovetski } 302a782d688SGuennadi Liakhovetski 303a782d688SGuennadi Liakhovetski if (desc) { 304a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 305a782d688SGuennadi Liakhovetski desc->callback_param = host; 306a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 307a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 308a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 309a782d688SGuennadi Liakhovetski } 310a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 31169983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 312a782d688SGuennadi Liakhovetski 313a782d688SGuennadi Liakhovetski if (!desc) { 314a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 315a782d688SGuennadi Liakhovetski if (ret >= 0) 316a782d688SGuennadi Liakhovetski ret = -EIO; 317a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 318f38f94c6SLinus Walleij host->dma_active = false; 319a782d688SGuennadi Liakhovetski dma_release_channel(chan); 320a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 321a782d688SGuennadi Liakhovetski chan = host->chan_tx; 322a782d688SGuennadi Liakhovetski if (chan) { 323a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 324a782d688SGuennadi Liakhovetski dma_release_channel(chan); 325a782d688SGuennadi Liakhovetski } 326a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 327a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 328a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 329a782d688SGuennadi Liakhovetski } 330a782d688SGuennadi Liakhovetski 331a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 33269983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 333a782d688SGuennadi Liakhovetski } 334a782d688SGuennadi Liakhovetski 335a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 336a782d688SGuennadi Liakhovetski { 33769983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 33869983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 339a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 340a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 341a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 342a782d688SGuennadi Liakhovetski int ret; 343a782d688SGuennadi Liakhovetski 34469983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3451ed828dbSLinus Walleij DMA_TO_DEVICE); 346a782d688SGuennadi Liakhovetski if (ret > 0) { 347f38f94c6SLinus Walleij host->dma_active = true; 34816052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 34905f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 350a782d688SGuennadi Liakhovetski } 351a782d688SGuennadi Liakhovetski 352a782d688SGuennadi Liakhovetski if (desc) { 353a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 354a782d688SGuennadi Liakhovetski desc->callback_param = host; 355a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 356a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 357a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 358a782d688SGuennadi Liakhovetski } 359a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 36069983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 361a782d688SGuennadi Liakhovetski 362a782d688SGuennadi Liakhovetski if (!desc) { 363a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 364a782d688SGuennadi Liakhovetski if (ret >= 0) 365a782d688SGuennadi Liakhovetski ret = -EIO; 366a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 367f38f94c6SLinus Walleij host->dma_active = false; 368a782d688SGuennadi Liakhovetski dma_release_channel(chan); 369a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 370a782d688SGuennadi Liakhovetski chan = host->chan_rx; 371a782d688SGuennadi Liakhovetski if (chan) { 372a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 373a782d688SGuennadi Liakhovetski dma_release_channel(chan); 374a782d688SGuennadi Liakhovetski } 375a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 376a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 377a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 378a782d688SGuennadi Liakhovetski } 379a782d688SGuennadi Liakhovetski 380a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 381a782d688SGuennadi Liakhovetski desc, cookie); 382a782d688SGuennadi Liakhovetski } 383a782d688SGuennadi Liakhovetski 384e5a233cbSLaurent Pinchart static struct dma_chan * 385e5a233cbSLaurent Pinchart sh_mmcif_request_dma_one(struct sh_mmcif_host *host, 386e5a233cbSLaurent Pinchart struct sh_mmcif_plat_data *pdata, 387e5a233cbSLaurent Pinchart enum dma_transfer_direction direction) 388a782d688SGuennadi Liakhovetski { 3890e79f9aeSGuennadi Liakhovetski struct dma_slave_config cfg; 390e5a233cbSLaurent Pinchart struct dma_chan *chan; 391e5a233cbSLaurent Pinchart unsigned int slave_id; 392e5a233cbSLaurent Pinchart struct resource *res; 3930e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 3940e79f9aeSGuennadi Liakhovetski int ret; 3950e79f9aeSGuennadi Liakhovetski 396e5a233cbSLaurent Pinchart dma_cap_zero(mask); 397e5a233cbSLaurent Pinchart dma_cap_set(DMA_SLAVE, mask); 398e5a233cbSLaurent Pinchart 399e5a233cbSLaurent Pinchart if (pdata) 400e5a233cbSLaurent Pinchart slave_id = direction == DMA_MEM_TO_DEV 401e5a233cbSLaurent Pinchart ? pdata->slave_id_tx : pdata->slave_id_rx; 402e5a233cbSLaurent Pinchart else 403e5a233cbSLaurent Pinchart slave_id = 0; 404e5a233cbSLaurent Pinchart 405e5a233cbSLaurent Pinchart chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 406e5a233cbSLaurent Pinchart (void *)slave_id, &host->pd->dev, 407e5a233cbSLaurent Pinchart direction == DMA_MEM_TO_DEV ? "tx" : "rx"); 408e5a233cbSLaurent Pinchart 409e5a233cbSLaurent Pinchart dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__, 410e5a233cbSLaurent Pinchart direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); 411e5a233cbSLaurent Pinchart 412e5a233cbSLaurent Pinchart if (!chan) 413e5a233cbSLaurent Pinchart return NULL; 414e5a233cbSLaurent Pinchart 415e5a233cbSLaurent Pinchart res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 416e5a233cbSLaurent Pinchart 417e5a233cbSLaurent Pinchart /* In the OF case the driver will get the slave ID from the DT */ 418e5a233cbSLaurent Pinchart cfg.slave_id = slave_id; 419e5a233cbSLaurent Pinchart cfg.direction = direction; 420e5a233cbSLaurent Pinchart cfg.dst_addr = res->start + MMCIF_CE_DATA; 421e5a233cbSLaurent Pinchart cfg.src_addr = 0; 422e5a233cbSLaurent Pinchart ret = dmaengine_slave_config(chan, &cfg); 423e5a233cbSLaurent Pinchart if (ret < 0) { 424e5a233cbSLaurent Pinchart dma_release_channel(chan); 425e5a233cbSLaurent Pinchart return NULL; 426e5a233cbSLaurent Pinchart } 427e5a233cbSLaurent Pinchart 428e5a233cbSLaurent Pinchart return chan; 429e5a233cbSLaurent Pinchart } 430e5a233cbSLaurent Pinchart 431e5a233cbSLaurent Pinchart static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 432e5a233cbSLaurent Pinchart struct sh_mmcif_plat_data *pdata) 433e5a233cbSLaurent Pinchart { 434f38f94c6SLinus Walleij host->dma_active = false; 435a782d688SGuennadi Liakhovetski 436acd6d772SGuennadi Liakhovetski if (pdata) { 4370e79f9aeSGuennadi Liakhovetski if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 4380e79f9aeSGuennadi Liakhovetski return; 439acd6d772SGuennadi Liakhovetski } else if (!host->pd->dev.of_node) { 440acd6d772SGuennadi Liakhovetski return; 441acd6d772SGuennadi Liakhovetski } 442a782d688SGuennadi Liakhovetski 443a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 444e5a233cbSLaurent Pinchart host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); 445a782d688SGuennadi Liakhovetski if (!host->chan_tx) 446a782d688SGuennadi Liakhovetski return; 447a782d688SGuennadi Liakhovetski 448e5a233cbSLaurent Pinchart host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); 449e5a233cbSLaurent Pinchart if (!host->chan_rx) { 4500e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 4510e79f9aeSGuennadi Liakhovetski host->chan_tx = NULL; 452a782d688SGuennadi Liakhovetski } 453e5a233cbSLaurent Pinchart } 454a782d688SGuennadi Liakhovetski 455a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 456a782d688SGuennadi Liakhovetski { 457a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 458a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 459a782d688SGuennadi Liakhovetski if (host->chan_tx) { 460a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 461a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 462a782d688SGuennadi Liakhovetski dma_release_channel(chan); 463a782d688SGuennadi Liakhovetski } 464a782d688SGuennadi Liakhovetski if (host->chan_rx) { 465a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 466a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 467a782d688SGuennadi Liakhovetski dma_release_channel(chan); 468a782d688SGuennadi Liakhovetski } 469a782d688SGuennadi Liakhovetski 470f38f94c6SLinus Walleij host->dma_active = false; 471a782d688SGuennadi Liakhovetski } 472fdc50a94SYusuke Goda 473fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 474fdc50a94SYusuke Goda { 475fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 476bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 477fdc50a94SYusuke Goda 478fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 479fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 480fdc50a94SYusuke Goda 481fdc50a94SYusuke Goda if (!clk) 482fdc50a94SYusuke Goda return; 483bf68a812SGuennadi Liakhovetski if (sup_pclk && clk == host->clk) 484fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 485fdc50a94SYusuke Goda else 486fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 487f9388257SSimon Horman ((fls(DIV_ROUND_UP(host->clk, 488f9388257SSimon Horman clk) - 1) - 1) << 16)); 489fdc50a94SYusuke Goda 490fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 491fdc50a94SYusuke Goda } 492fdc50a94SYusuke Goda 493fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 494fdc50a94SYusuke Goda { 495fdc50a94SYusuke Goda u32 tmp; 496fdc50a94SYusuke Goda 497487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 498fdc50a94SYusuke Goda 499487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 500487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 501967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 502967bcb77SGuennadi Liakhovetski tmp |= SCCSTO_29; 5036d6fd367SGuennadi Liakhovetski if (host->clk_ctrl2_enable) 5046d6fd367SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 505fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 506967bcb77SGuennadi Liakhovetski SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 507fdc50a94SYusuke Goda /* byte swap on */ 508fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 509fdc50a94SYusuke Goda } 510fdc50a94SYusuke Goda 511fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 512fdc50a94SYusuke Goda { 513fdc50a94SYusuke Goda u32 state1, state2; 514ee4b8887SGuennadi Liakhovetski int ret, timeout; 515fdc50a94SYusuke Goda 516aa0787a9SGuennadi Liakhovetski host->sd_error = false; 517fdc50a94SYusuke Goda 518487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 519487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 520e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 521e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 522fdc50a94SYusuke Goda 523fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 524fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 525fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 526ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 527487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 528fdc50a94SYusuke Goda & STS1_CMDSEQ)) 529fdc50a94SYusuke Goda break; 530fdc50a94SYusuke Goda mdelay(1); 531fdc50a94SYusuke Goda } 532ee4b8887SGuennadi Liakhovetski if (!timeout) { 533ee4b8887SGuennadi Liakhovetski dev_err(&host->pd->dev, 534ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 535ee4b8887SGuennadi Liakhovetski return -EIO; 536ee4b8887SGuennadi Liakhovetski } 537fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 538e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 539fdc50a94SYusuke Goda return -EIO; 540fdc50a94SYusuke Goda } 541fdc50a94SYusuke Goda 542fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 543e475b270STeppei Kamijou dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", 544e475b270STeppei Kamijou host->state, host->wait_for); 545fdc50a94SYusuke Goda ret = -EIO; 546fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 547e475b270STeppei Kamijou dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", 548e475b270STeppei Kamijou host->state, host->wait_for); 549fdc50a94SYusuke Goda ret = -ETIMEDOUT; 550fdc50a94SYusuke Goda } else { 551e475b270STeppei Kamijou dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", 552e475b270STeppei Kamijou host->state, host->wait_for); 553fdc50a94SYusuke Goda ret = -EIO; 554fdc50a94SYusuke Goda } 555fdc50a94SYusuke Goda return ret; 556fdc50a94SYusuke Goda } 557fdc50a94SYusuke Goda 558f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 559f985da17SGuennadi Liakhovetski { 560f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 561f985da17SGuennadi Liakhovetski 562f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 563f985da17SGuennadi Liakhovetski 564f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 565f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 566f985da17SGuennadi Liakhovetski 567f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 568f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 569f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 570f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 571f985da17SGuennadi Liakhovetski } else { 572f985da17SGuennadi Liakhovetski host->pio_ptr = p; 573f985da17SGuennadi Liakhovetski } 574f985da17SGuennadi Liakhovetski 57599eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 576f985da17SGuennadi Liakhovetski } 577f985da17SGuennadi Liakhovetski 578f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 579fdc50a94SYusuke Goda struct mmc_request *mrq) 580fdc50a94SYusuke Goda { 581f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 582f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 583f985da17SGuennadi Liakhovetski 584f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 585fdc50a94SYusuke Goda 586fdc50a94SYusuke Goda /* buf read enable */ 587fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 588f985da17SGuennadi Liakhovetski } 589fdc50a94SYusuke Goda 590f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 591f985da17SGuennadi Liakhovetski { 592f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 593f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 594f985da17SGuennadi Liakhovetski int i; 595f985da17SGuennadi Liakhovetski 596f985da17SGuennadi Liakhovetski if (host->sd_error) { 597f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 598e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 599f985da17SGuennadi Liakhovetski return false; 600f985da17SGuennadi Liakhovetski } 601f985da17SGuennadi Liakhovetski 602f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 603487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 604fdc50a94SYusuke Goda 605fdc50a94SYusuke Goda /* buffer read end */ 606fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 607f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 608fdc50a94SYusuke Goda 609f985da17SGuennadi Liakhovetski return true; 610fdc50a94SYusuke Goda } 611fdc50a94SYusuke Goda 612f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 613fdc50a94SYusuke Goda struct mmc_request *mrq) 614fdc50a94SYusuke Goda { 615fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 616fdc50a94SYusuke Goda 617f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 618f985da17SGuennadi Liakhovetski return; 619f985da17SGuennadi Liakhovetski 620f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 621f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 622f985da17SGuennadi Liakhovetski 623f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 624f985da17SGuennadi Liakhovetski host->sg_idx = 0; 625f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 626f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6275df460b1SGuennadi Liakhovetski 628fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 629fdc50a94SYusuke Goda } 630fdc50a94SYusuke Goda 631f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 632f985da17SGuennadi Liakhovetski { 633f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 634f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 635f985da17SGuennadi Liakhovetski int i; 636f985da17SGuennadi Liakhovetski 637f985da17SGuennadi Liakhovetski if (host->sd_error) { 638f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 639e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 640f985da17SGuennadi Liakhovetski return false; 641f985da17SGuennadi Liakhovetski } 642f985da17SGuennadi Liakhovetski 643f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 644f985da17SGuennadi Liakhovetski 645f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 646f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 647f985da17SGuennadi Liakhovetski 648f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 649f985da17SGuennadi Liakhovetski return false; 650f985da17SGuennadi Liakhovetski 651f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 652f985da17SGuennadi Liakhovetski 653f985da17SGuennadi Liakhovetski return true; 654f985da17SGuennadi Liakhovetski } 655f985da17SGuennadi Liakhovetski 656f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 657fdc50a94SYusuke Goda struct mmc_request *mrq) 658fdc50a94SYusuke Goda { 659f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 660f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 661fdc50a94SYusuke Goda 662f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 663fdc50a94SYusuke Goda 664fdc50a94SYusuke Goda /* buf write enable */ 665f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 666f985da17SGuennadi Liakhovetski } 667fdc50a94SYusuke Goda 668f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 669f985da17SGuennadi Liakhovetski { 670f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 671f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 672f985da17SGuennadi Liakhovetski int i; 673f985da17SGuennadi Liakhovetski 674f985da17SGuennadi Liakhovetski if (host->sd_error) { 675f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 676e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 677f985da17SGuennadi Liakhovetski return false; 678f985da17SGuennadi Liakhovetski } 679f985da17SGuennadi Liakhovetski 680f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 681487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 682fdc50a94SYusuke Goda 683fdc50a94SYusuke Goda /* buffer write end */ 684fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 685f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 686fdc50a94SYusuke Goda 687f985da17SGuennadi Liakhovetski return true; 688fdc50a94SYusuke Goda } 689fdc50a94SYusuke Goda 690f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 691fdc50a94SYusuke Goda struct mmc_request *mrq) 692fdc50a94SYusuke Goda { 693fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 694fdc50a94SYusuke Goda 695f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 696f985da17SGuennadi Liakhovetski return; 697fdc50a94SYusuke Goda 698f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 699f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 700f985da17SGuennadi Liakhovetski 701f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 702f985da17SGuennadi Liakhovetski host->sg_idx = 0; 703f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 704f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 7055df460b1SGuennadi Liakhovetski 706fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 707fdc50a94SYusuke Goda } 708f985da17SGuennadi Liakhovetski 709f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 710f985da17SGuennadi Liakhovetski { 711f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 712f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 713f985da17SGuennadi Liakhovetski int i; 714f985da17SGuennadi Liakhovetski 715f985da17SGuennadi Liakhovetski if (host->sd_error) { 716f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 717e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 718f985da17SGuennadi Liakhovetski return false; 719fdc50a94SYusuke Goda } 720f985da17SGuennadi Liakhovetski 721f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 722f985da17SGuennadi Liakhovetski 723f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 724f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 725f985da17SGuennadi Liakhovetski 726f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 727f985da17SGuennadi Liakhovetski return false; 728f985da17SGuennadi Liakhovetski 729f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 730f985da17SGuennadi Liakhovetski 731f985da17SGuennadi Liakhovetski return true; 732fdc50a94SYusuke Goda } 733fdc50a94SYusuke Goda 734fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 735fdc50a94SYusuke Goda struct mmc_command *cmd) 736fdc50a94SYusuke Goda { 737fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 738487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 739487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 740487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 741487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 742fdc50a94SYusuke Goda } else 743487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 744fdc50a94SYusuke Goda } 745fdc50a94SYusuke Goda 746fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 747fdc50a94SYusuke Goda struct mmc_command *cmd) 748fdc50a94SYusuke Goda { 749487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 750fdc50a94SYusuke Goda } 751fdc50a94SYusuke Goda 752fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 75369983404SGuennadi Liakhovetski struct mmc_request *mrq) 754fdc50a94SYusuke Goda { 75569983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 75669983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 75769983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 758fdc50a94SYusuke Goda u32 tmp = 0; 759fdc50a94SYusuke Goda 760fdc50a94SYusuke Goda /* Response Type check */ 761fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 762fdc50a94SYusuke Goda case MMC_RSP_NONE: 763fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 764fdc50a94SYusuke Goda break; 765fdc50a94SYusuke Goda case MMC_RSP_R1: 766fdc50a94SYusuke Goda case MMC_RSP_R1B: 767fdc50a94SYusuke Goda case MMC_RSP_R3: 768fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 769fdc50a94SYusuke Goda break; 770fdc50a94SYusuke Goda case MMC_RSP_R2: 771fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 772fdc50a94SYusuke Goda break; 773fdc50a94SYusuke Goda default: 774e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 775fdc50a94SYusuke Goda break; 776fdc50a94SYusuke Goda } 777fdc50a94SYusuke Goda switch (opc) { 778fdc50a94SYusuke Goda /* RBSY */ 779a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 780fdc50a94SYusuke Goda case MMC_SWITCH: 781fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 782fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 783fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 784fdc50a94SYusuke Goda case MMC_ERASE: 785fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 786fdc50a94SYusuke Goda break; 787fdc50a94SYusuke Goda } 788fdc50a94SYusuke Goda /* WDAT / DATW */ 78969983404SGuennadi Liakhovetski if (data) { 790fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 791fdc50a94SYusuke Goda switch (host->bus_width) { 792fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 793fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 794fdc50a94SYusuke Goda break; 795fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 796fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 797fdc50a94SYusuke Goda break; 798fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 799fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 800fdc50a94SYusuke Goda break; 801fdc50a94SYusuke Goda default: 802e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 803fdc50a94SYusuke Goda break; 804fdc50a94SYusuke Goda } 805555061f9STeppei Kamijou switch (host->timing) { 806555061f9STeppei Kamijou case MMC_TIMING_UHS_DDR50: 807555061f9STeppei Kamijou /* 808555061f9STeppei Kamijou * MMC core will only set this timing, if the host 809555061f9STeppei Kamijou * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF 810555061f9STeppei Kamijou * implementations with this capability, e.g. sh73a0, 811555061f9STeppei Kamijou * will have to set it in their platform data. 812555061f9STeppei Kamijou */ 813555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 814555061f9STeppei Kamijou break; 815555061f9STeppei Kamijou } 816fdc50a94SYusuke Goda } 817fdc50a94SYusuke Goda /* DWEN */ 818fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 819fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 820fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 821fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 822fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 823fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 82469983404SGuennadi Liakhovetski data->blocks << 16); 825fdc50a94SYusuke Goda } 826fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 827fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 828fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 829fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 830fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 831fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 832fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 833fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 834fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 835fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 836fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 837fdc50a94SYusuke Goda 83869983404SGuennadi Liakhovetski return (opc << 24) | tmp; 839fdc50a94SYusuke Goda } 840fdc50a94SYusuke Goda 841e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 842fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 843fdc50a94SYusuke Goda { 844fdc50a94SYusuke Goda switch (opc) { 845fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 846f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 847f985da17SGuennadi Liakhovetski return 0; 848fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 849f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 850f985da17SGuennadi Liakhovetski return 0; 851fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 852f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 853f985da17SGuennadi Liakhovetski return 0; 854fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 855fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 856f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 857f985da17SGuennadi Liakhovetski return 0; 858fdc50a94SYusuke Goda default: 859e475b270STeppei Kamijou dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); 860ee4b8887SGuennadi Liakhovetski return -EINVAL; 861fdc50a94SYusuke Goda } 862fdc50a94SYusuke Goda } 863fdc50a94SYusuke Goda 864fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 865ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 866fdc50a94SYusuke Goda { 867ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 868f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 869f985da17SGuennadi Liakhovetski u32 mask; 870fdc50a94SYusuke Goda 871fdc50a94SYusuke Goda switch (opc) { 872ee4b8887SGuennadi Liakhovetski /* response busy check */ 873a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 874fdc50a94SYusuke Goda case MMC_SWITCH: 875fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 876fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 877fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 878fdc50a94SYusuke Goda case MMC_ERASE: 879ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 880fdc50a94SYusuke Goda break; 881fdc50a94SYusuke Goda default: 882ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 883fdc50a94SYusuke Goda break; 884fdc50a94SYusuke Goda } 885fdc50a94SYusuke Goda 886967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 887967bcb77SGuennadi Liakhovetski mask |= MASK_MCCSTO; 888967bcb77SGuennadi Liakhovetski 88969983404SGuennadi Liakhovetski if (mrq->data) { 890487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 891487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 892487d9fc5SMagnus Damm mrq->data->blksz); 893fdc50a94SYusuke Goda } 89469983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 895fdc50a94SYusuke Goda 896967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 897487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 898967bcb77SGuennadi Liakhovetski else 899967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 900487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 901fdc50a94SYusuke Goda /* set arg */ 902487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 903fdc50a94SYusuke Goda /* set cmd */ 904487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 905fdc50a94SYusuke Goda 906f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 907f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 908fdc50a94SYusuke Goda } 909fdc50a94SYusuke Goda 910fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 911ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 912fdc50a94SYusuke Goda { 91369983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 91469983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 915fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 91669983404SGuennadi Liakhovetski break; 91769983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 918fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 91969983404SGuennadi Liakhovetski break; 92069983404SGuennadi Liakhovetski default: 921e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 92269983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 923fdc50a94SYusuke Goda return; 924fdc50a94SYusuke Goda } 925fdc50a94SYusuke Goda 926f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 927fdc50a94SYusuke Goda } 928fdc50a94SYusuke Goda 929fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 930fdc50a94SYusuke Goda { 931fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9323b0beafcSGuennadi Liakhovetski unsigned long flags; 9333b0beafcSGuennadi Liakhovetski 9343b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9353b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 936e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 9373b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9383b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9393b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9403b0beafcSGuennadi Liakhovetski return; 9413b0beafcSGuennadi Liakhovetski } 9423b0beafcSGuennadi Liakhovetski 9433b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9443b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 945fdc50a94SYusuke Goda 946fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 947fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 9487541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 9497541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 9507541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 9517541ca98SLaurent Pinchart break; 952fdc50a94SYusuke Goda case MMC_APP_CMD: 95392ff0c5bSTeppei Kamijou case SD_IO_RW_DIRECT: 9543b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 955fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 956fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 957fdc50a94SYusuke Goda return; 958fdc50a94SYusuke Goda default: 959fdc50a94SYusuke Goda break; 960fdc50a94SYusuke Goda } 961fdc50a94SYusuke Goda 962f985da17SGuennadi Liakhovetski host->mrq = mrq; 963f985da17SGuennadi Liakhovetski 964f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 965fdc50a94SYusuke Goda } 966fdc50a94SYusuke Goda 967a6609267SGuennadi Liakhovetski static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 968a6609267SGuennadi Liakhovetski { 969ac0a2e98SUlf Hansson int ret = clk_prepare_enable(host->hclk); 970a6609267SGuennadi Liakhovetski 971a6609267SGuennadi Liakhovetski if (!ret) { 972a6609267SGuennadi Liakhovetski host->clk = clk_get_rate(host->hclk); 973a6609267SGuennadi Liakhovetski host->mmc->f_max = host->clk / 2; 974a6609267SGuennadi Liakhovetski host->mmc->f_min = host->clk / 512; 975a6609267SGuennadi Liakhovetski } 976a6609267SGuennadi Liakhovetski 977a6609267SGuennadi Liakhovetski return ret; 978a6609267SGuennadi Liakhovetski } 979a6609267SGuennadi Liakhovetski 9807d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 9817d17baa0SGuennadi Liakhovetski { 9827d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 9837d17baa0SGuennadi Liakhovetski 9847d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 9857d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 9867d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 9877d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 9887d17baa0SGuennadi Liakhovetski } 9897d17baa0SGuennadi Liakhovetski 990fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 991fdc50a94SYusuke Goda { 992fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9933b0beafcSGuennadi Liakhovetski unsigned long flags; 9943b0beafcSGuennadi Liakhovetski 9953b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9963b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 997e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 9983b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9993b0beafcSGuennadi Liakhovetski return; 10003b0beafcSGuennadi Liakhovetski } 10013b0beafcSGuennadi Liakhovetski 10023b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 10033b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 1004fdc50a94SYusuke Goda 1005f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 1006c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 1007faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 1008faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 1009c9b0cef2SGuennadi Liakhovetski host->card_present = true; 1010faca6648SGuennadi Liakhovetski } 10117d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1012f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 1013f5e0cec4SGuennadi Liakhovetski /* clock stop */ 1014f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 1015faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 1016c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 1017c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 1018c9b0cef2SGuennadi Liakhovetski host->card_present = false; 1019c9b0cef2SGuennadi Liakhovetski } 1020c9b0cef2SGuennadi Liakhovetski } 1021faca6648SGuennadi Liakhovetski if (host->power) { 1022f8a8ced7STeppei Kamijou pm_runtime_put_sync(&host->pd->dev); 1023ac0a2e98SUlf Hansson clk_disable_unprepare(host->hclk); 1024faca6648SGuennadi Liakhovetski host->power = false; 10257d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 10267d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1027faca6648SGuennadi Liakhovetski } 10283b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1029f5e0cec4SGuennadi Liakhovetski return; 1030fdc50a94SYusuke Goda } 1031fdc50a94SYusuke Goda 1032c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 1033c9b0cef2SGuennadi Liakhovetski if (!host->power) { 1034a6609267SGuennadi Liakhovetski sh_mmcif_clk_update(host); 1035c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 1036c9b0cef2SGuennadi Liakhovetski host->power = true; 1037c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 1038c9b0cef2SGuennadi Liakhovetski } 1039fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 1040c9b0cef2SGuennadi Liakhovetski } 1041fdc50a94SYusuke Goda 1042555061f9STeppei Kamijou host->timing = ios->timing; 1043fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10443b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1045fdc50a94SYusuke Goda } 1046fdc50a94SYusuke Goda 1047777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1048777271d0SArnd Hannemann { 1049777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1050777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1051e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1052e480606aSGuennadi Liakhovetski 1053e480606aSGuennadi Liakhovetski if (ret >= 0) 1054e480606aSGuennadi Liakhovetski return ret; 1055777271d0SArnd Hannemann 1056bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1057777271d0SArnd Hannemann return -ENOSYS; 1058777271d0SArnd Hannemann else 1059777271d0SArnd Hannemann return p->get_cd(host->pd); 1060777271d0SArnd Hannemann } 1061777271d0SArnd Hannemann 1062fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1063fdc50a94SYusuke Goda .request = sh_mmcif_request, 1064fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1065777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1066fdc50a94SYusuke Goda }; 1067fdc50a94SYusuke Goda 1068f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1069f985da17SGuennadi Liakhovetski { 1070f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 107169983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1072f985da17SGuennadi Liakhovetski long time; 1073f985da17SGuennadi Liakhovetski 1074f985da17SGuennadi Liakhovetski if (host->sd_error) { 1075f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1076f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1077f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1078f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1079f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1080f985da17SGuennadi Liakhovetski break; 1081f985da17SGuennadi Liakhovetski default: 1082f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1083f985da17SGuennadi Liakhovetski break; 1084f985da17SGuennadi Liakhovetski } 1085e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "CMD%d error %d\n", 1086e475b270STeppei Kamijou cmd->opcode, cmd->error); 1087aba9d646SGuennadi Liakhovetski host->sd_error = false; 1088f985da17SGuennadi Liakhovetski return false; 1089f985da17SGuennadi Liakhovetski } 1090f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1091f985da17SGuennadi Liakhovetski cmd->error = 0; 1092f985da17SGuennadi Liakhovetski return false; 1093f985da17SGuennadi Liakhovetski } 1094f985da17SGuennadi Liakhovetski 1095f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1096f985da17SGuennadi Liakhovetski 109769983404SGuennadi Liakhovetski if (!data) 1098f985da17SGuennadi Liakhovetski return false; 1099f985da17SGuennadi Liakhovetski 110090f1cb43SGuennadi Liakhovetski /* 110190f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to 110290f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active 110390f1cb43SGuennadi Liakhovetski */ 110490f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete); 110590f1cb43SGuennadi Liakhovetski 110669983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1107f985da17SGuennadi Liakhovetski if (host->chan_rx) 1108f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1109f985da17SGuennadi Liakhovetski } else { 1110f985da17SGuennadi Liakhovetski if (host->chan_tx) 1111f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1112f985da17SGuennadi Liakhovetski } 1113f985da17SGuennadi Liakhovetski 1114f985da17SGuennadi Liakhovetski if (!host->dma_active) { 111569983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 111699eb9d8dSGuennadi Liakhovetski return !data->error; 1117f985da17SGuennadi Liakhovetski } 1118f985da17SGuennadi Liakhovetski 1119f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1120f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1121f985da17SGuennadi Liakhovetski host->timeout); 1122eae30983STeppei Kamijou 1123eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1124eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1125eae30983STeppei Kamijou data->sg, data->sg_len, 1126eae30983STeppei Kamijou DMA_FROM_DEVICE); 1127eae30983STeppei Kamijou else 1128eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1129eae30983STeppei Kamijou data->sg, data->sg_len, 1130eae30983STeppei Kamijou DMA_TO_DEVICE); 1131eae30983STeppei Kamijou 1132f985da17SGuennadi Liakhovetski if (host->sd_error) { 1133f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1134f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1135f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 113669983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1137f985da17SGuennadi Liakhovetski } else if (!time) { 1138e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n"); 113969983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1140f985da17SGuennadi Liakhovetski } else if (time < 0) { 1141e475b270STeppei Kamijou dev_err(host->mmc->parent, 1142e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time); 114369983404SGuennadi Liakhovetski data->error = time; 1144f985da17SGuennadi Liakhovetski } 1145f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1146f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1147f985da17SGuennadi Liakhovetski host->dma_active = false; 1148f985da17SGuennadi Liakhovetski 1149eae30983STeppei Kamijou if (data->error) { 115069983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1151eae30983STeppei Kamijou /* Abort DMA */ 1152eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1153eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1154eae30983STeppei Kamijou else 1155eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1156eae30983STeppei Kamijou } 1157f985da17SGuennadi Liakhovetski 1158f985da17SGuennadi Liakhovetski return false; 1159f985da17SGuennadi Liakhovetski } 1160f985da17SGuennadi Liakhovetski 1161f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1162f985da17SGuennadi Liakhovetski { 1163f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 11648047310eSGuennadi Liakhovetski struct mmc_request *mrq; 11655df460b1SGuennadi Liakhovetski bool wait = false; 1166f985da17SGuennadi Liakhovetski 1167f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1168f985da17SGuennadi Liakhovetski 11698047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 11708047310eSGuennadi Liakhovetski 11718047310eSGuennadi Liakhovetski mrq = host->mrq; 11728047310eSGuennadi Liakhovetski if (!mrq) { 11738047310eSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 11748047310eSGuennadi Liakhovetski host->state, host->wait_for); 11758047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 11768047310eSGuennadi Liakhovetski return IRQ_HANDLED; 11778047310eSGuennadi Liakhovetski } 11788047310eSGuennadi Liakhovetski 1179f985da17SGuennadi Liakhovetski /* 1180f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1181f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1182f985da17SGuennadi Liakhovetski */ 1183f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1184f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1185f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 11868047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1187f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1188f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 11895df460b1SGuennadi Liakhovetski /* Wait for data? */ 11905df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1191f985da17SGuennadi Liakhovetski break; 1192f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 11935df460b1SGuennadi Liakhovetski /* Wait for more data? */ 11945df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1195f985da17SGuennadi Liakhovetski break; 1196f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 11975df460b1SGuennadi Liakhovetski /* Wait for data end? */ 11985df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1199f985da17SGuennadi Liakhovetski break; 1200f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 12015df460b1SGuennadi Liakhovetski /* Wait data to write? */ 12025df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1203f985da17SGuennadi Liakhovetski break; 1204f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 12055df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12065df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1207f985da17SGuennadi Liakhovetski break; 1208f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1209f985da17SGuennadi Liakhovetski if (host->sd_error) { 1210f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1211e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); 1212f985da17SGuennadi Liakhovetski break; 1213f985da17SGuennadi Liakhovetski } 1214f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1215f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1216f985da17SGuennadi Liakhovetski break; 1217f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1218f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1219e475b270STeppei Kamijou if (host->sd_error) { 122091ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1221e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); 1222e475b270STeppei Kamijou } 1223f985da17SGuennadi Liakhovetski break; 1224f985da17SGuennadi Liakhovetski default: 1225f985da17SGuennadi Liakhovetski BUG(); 1226f985da17SGuennadi Liakhovetski } 1227f985da17SGuennadi Liakhovetski 12285df460b1SGuennadi Liakhovetski if (wait) { 12295df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12305df460b1SGuennadi Liakhovetski /* Wait for more data */ 12318047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12325df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 12335df460b1SGuennadi Liakhovetski } 12345df460b1SGuennadi Liakhovetski 1235f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 123691ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 123769983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 123869983404SGuennadi Liakhovetski data->bytes_xfered = 123969983404SGuennadi Liakhovetski data->blocks * data->blksz; 1240f985da17SGuennadi Liakhovetski 124169983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1242f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 12435df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 12445df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12458047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1246f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1247f985da17SGuennadi Liakhovetski } 1248f985da17SGuennadi Liakhovetski } 12495df460b1SGuennadi Liakhovetski } 1250f985da17SGuennadi Liakhovetski 1251f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1252f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 125369983404SGuennadi Liakhovetski host->mrq = NULL; 1254f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1255f985da17SGuennadi Liakhovetski 12568047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12578047310eSGuennadi Liakhovetski 1258f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1259f985da17SGuennadi Liakhovetski } 1260f985da17SGuennadi Liakhovetski 1261fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1262fdc50a94SYusuke Goda { 1263fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1264967bcb77SGuennadi Liakhovetski u32 state, mask; 1265fdc50a94SYusuke Goda 1266487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1267967bcb77SGuennadi Liakhovetski mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1268967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 1269967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1270967bcb77SGuennadi Liakhovetski else 1271967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 12728af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1273fdc50a94SYusuke Goda 12748af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN) 12758af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", 12768af50750SGuennadi Liakhovetski state); 12778af50750SGuennadi Liakhovetski 12788af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) { 1279aa0787a9SGuennadi Liakhovetski host->sd_error = true; 12808af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); 1281fdc50a94SYusuke Goda } 1282f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 12838af50750SGuennadi Liakhovetski if (!host->mrq) 12848af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); 1285f985da17SGuennadi Liakhovetski if (!host->dma_active) 1286f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1287f985da17SGuennadi Liakhovetski else if (host->sd_error) 1288f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1289f985da17SGuennadi Liakhovetski } else { 1290aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1291f985da17SGuennadi Liakhovetski } 1292fdc50a94SYusuke Goda 1293fdc50a94SYusuke Goda return IRQ_HANDLED; 1294fdc50a94SYusuke Goda } 1295fdc50a94SYusuke Goda 1296f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1297f985da17SGuennadi Liakhovetski { 1298f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1299f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1300f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 13018047310eSGuennadi Liakhovetski unsigned long flags; 1302f985da17SGuennadi Liakhovetski 1303f985da17SGuennadi Liakhovetski if (host->dying) 1304f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1305f985da17SGuennadi Liakhovetski return; 1306f985da17SGuennadi Liakhovetski 1307e475b270STeppei Kamijou dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", 13088047310eSGuennadi Liakhovetski host->wait_for, mrq->cmd->opcode); 13098047310eSGuennadi Liakhovetski 13108047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 13118047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 13128047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13138047310eSGuennadi Liakhovetski return; 13148047310eSGuennadi Liakhovetski } 13158047310eSGuennadi Liakhovetski 13168047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 13178047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13188047310eSGuennadi Liakhovetski 1319f985da17SGuennadi Liakhovetski /* 1320f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1321f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1322f985da17SGuennadi Liakhovetski */ 1323f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1324f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1325f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1326f985da17SGuennadi Liakhovetski break; 1327f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1328f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1329f985da17SGuennadi Liakhovetski break; 1330f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1331f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1332f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1333f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1334f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1335f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 133669983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1337f985da17SGuennadi Liakhovetski break; 1338f985da17SGuennadi Liakhovetski default: 1339f985da17SGuennadi Liakhovetski BUG(); 1340f985da17SGuennadi Liakhovetski } 1341f985da17SGuennadi Liakhovetski 1342f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1343f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1344f985da17SGuennadi Liakhovetski host->mrq = NULL; 1345f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1346f985da17SGuennadi Liakhovetski } 1347f985da17SGuennadi Liakhovetski 13487d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 13497d17baa0SGuennadi Liakhovetski { 13507d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 13517d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 13527d17baa0SGuennadi Liakhovetski 13537d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 13547d17baa0SGuennadi Liakhovetski 1355bf68a812SGuennadi Liakhovetski if (!pd) 1356bf68a812SGuennadi Liakhovetski return; 1357bf68a812SGuennadi Liakhovetski 13587d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 13597d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 13607d17baa0SGuennadi Liakhovetski else if (pd->ocr) 13617d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 13627d17baa0SGuennadi Liakhovetski } 13637d17baa0SGuennadi Liakhovetski 1364c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1365fdc50a94SYusuke Goda { 1366fdc50a94SYusuke Goda int ret = 0, irq[2]; 1367fdc50a94SYusuke Goda struct mmc_host *mmc; 1368e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1369e1aae2ebSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1370fdc50a94SYusuke Goda struct resource *res; 1371fdc50a94SYusuke Goda void __iomem *reg; 13722cd5b3e0SShinya Kuribayashi const char *name; 1373fdc50a94SYusuke Goda 1374fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1375fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 13762cd5b3e0SShinya Kuribayashi if (irq[0] < 0) { 1377e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1378fdc50a94SYusuke Goda return -ENXIO; 1379fdc50a94SYusuke Goda } 1380fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1381fdc50a94SYusuke Goda if (!res) { 1382fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1383fdc50a94SYusuke Goda return -ENXIO; 1384fdc50a94SYusuke Goda } 1385fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1386fdc50a94SYusuke Goda if (!reg) { 1387fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1388fdc50a94SYusuke Goda return -ENOMEM; 1389fdc50a94SYusuke Goda } 1390e1aae2ebSGuennadi Liakhovetski 1391fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1392fdc50a94SYusuke Goda if (!mmc) { 1393fdc50a94SYusuke Goda ret = -ENOMEM; 1394e1aae2ebSGuennadi Liakhovetski goto ealloch; 1395fdc50a94SYusuke Goda } 13962c9054dcSSimon Baatz 13972c9054dcSSimon Baatz ret = mmc_of_parse(mmc); 13982c9054dcSSimon Baatz if (ret < 0) 13992c9054dcSSimon Baatz goto eofparse; 14002c9054dcSSimon Baatz 1401fdc50a94SYusuke Goda host = mmc_priv(mmc); 1402fdc50a94SYusuke Goda host->mmc = mmc; 1403fdc50a94SYusuke Goda host->addr = reg; 1404f9fd54f2STeppei Kamijou host->timeout = msecs_to_jiffies(1000); 1405967bcb77SGuennadi Liakhovetski host->ccs_enable = !pd || !pd->ccs_unsupported; 14066d6fd367SGuennadi Liakhovetski host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; 1407fdc50a94SYusuke Goda 1408fdc50a94SYusuke Goda host->pd = pdev; 1409fdc50a94SYusuke Goda 14103b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1411fdc50a94SYusuke Goda 1412fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 14137d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 14147d17baa0SGuennadi Liakhovetski 1415eca889f6SGuennadi Liakhovetski mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1416bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1417fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1418a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1419fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1420a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1421a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1422fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1423fdc50a94SYusuke Goda 1424fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1425a782d688SGuennadi Liakhovetski 1426faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1427faca6648SGuennadi Liakhovetski host->power = false; 1428faca6648SGuennadi Liakhovetski 1429047a9ce7SGuennadi Liakhovetski host->hclk = clk_get(&pdev->dev, NULL); 1430b289174fSGuennadi Liakhovetski if (IS_ERR(host->hclk)) { 1431b289174fSGuennadi Liakhovetski ret = PTR_ERR(host->hclk); 1432047a9ce7SGuennadi Liakhovetski dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 1433b289174fSGuennadi Liakhovetski goto eclkget; 1434b289174fSGuennadi Liakhovetski } 1435a6609267SGuennadi Liakhovetski ret = sh_mmcif_clk_update(host); 1436a6609267SGuennadi Liakhovetski if (ret < 0) 1437a6609267SGuennadi Liakhovetski goto eclkupdate; 1438b289174fSGuennadi Liakhovetski 1439faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1440faca6648SGuennadi Liakhovetski if (ret < 0) 1441e1aae2ebSGuennadi Liakhovetski goto eresume; 1442a782d688SGuennadi Liakhovetski 14435ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1444fdc50a94SYusuke Goda 1445b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 14463b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14473b0beafcSGuennadi Liakhovetski 14482cd5b3e0SShinya Kuribayashi name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; 14492cd5b3e0SShinya Kuribayashi ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host); 1450fdc50a94SYusuke Goda if (ret) { 14512cd5b3e0SShinya Kuribayashi dev_err(&pdev->dev, "request_irq error (%s)\n", name); 1452e1aae2ebSGuennadi Liakhovetski goto ereqirq0; 1453fdc50a94SYusuke Goda } 14542cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 14552cd5b3e0SShinya Kuribayashi ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 14562cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1457fdc50a94SYusuke Goda if (ret) { 1458e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1459e1aae2ebSGuennadi Liakhovetski goto ereqirq1; 1460fdc50a94SYusuke Goda } 14612cd5b3e0SShinya Kuribayashi } 1462fdc50a94SYusuke Goda 1463e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1464214fc309SLaurent Pinchart ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); 1465e480606aSGuennadi Liakhovetski if (ret < 0) 1466e480606aSGuennadi Liakhovetski goto erqcd; 1467e480606aSGuennadi Liakhovetski } 1468e480606aSGuennadi Liakhovetski 14698047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 14708047310eSGuennadi Liakhovetski 1471ac0a2e98SUlf Hansson clk_disable_unprepare(host->hclk); 14725ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 14735ba85d95SGuennadi Liakhovetski if (ret < 0) 1474e1aae2ebSGuennadi Liakhovetski goto emmcaddh; 1475fdc50a94SYusuke Goda 1476efe6a8adSRafael J. Wysocki dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1477efe6a8adSRafael J. Wysocki 1478e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1479e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1480487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1481fdc50a94SYusuke Goda return ret; 1482fdc50a94SYusuke Goda 1483e1aae2ebSGuennadi Liakhovetski emmcaddh: 1484e480606aSGuennadi Liakhovetski erqcd: 14852cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) 14865ba85d95SGuennadi Liakhovetski free_irq(irq[1], host); 1487e1aae2ebSGuennadi Liakhovetski ereqirq1: 14885ba85d95SGuennadi Liakhovetski free_irq(irq[0], host); 1489e1aae2ebSGuennadi Liakhovetski ereqirq0: 1490faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1491e1aae2ebSGuennadi Liakhovetski eresume: 1492ac0a2e98SUlf Hansson clk_disable_unprepare(host->hclk); 1493a6609267SGuennadi Liakhovetski eclkupdate: 1494b289174fSGuennadi Liakhovetski clk_put(host->hclk); 1495e1aae2ebSGuennadi Liakhovetski eclkget: 1496b289174fSGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 14972c9054dcSSimon Baatz eofparse: 1498fdc50a94SYusuke Goda mmc_free_host(mmc); 1499e1aae2ebSGuennadi Liakhovetski ealloch: 1500fdc50a94SYusuke Goda iounmap(reg); 1501fdc50a94SYusuke Goda return ret; 1502fdc50a94SYusuke Goda } 1503fdc50a94SYusuke Goda 15046e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1505fdc50a94SYusuke Goda { 1506fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1507fdc50a94SYusuke Goda int irq[2]; 1508fdc50a94SYusuke Goda 1509f985da17SGuennadi Liakhovetski host->dying = true; 1510ac0a2e98SUlf Hansson clk_prepare_enable(host->hclk); 1511faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1512aa0787a9SGuennadi Liakhovetski 1513efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1514efe6a8adSRafael J. Wysocki 1515faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 15163b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15173b0beafcSGuennadi Liakhovetski 1518f985da17SGuennadi Liakhovetski /* 1519f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1520f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1521f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1522f985da17SGuennadi Liakhovetski */ 1523f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1524f985da17SGuennadi Liakhovetski 1525aa0787a9SGuennadi Liakhovetski if (host->addr) 1526aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1527aa0787a9SGuennadi Liakhovetski 1528fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1529fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1530fdc50a94SYusuke Goda 1531fdc50a94SYusuke Goda free_irq(irq[0], host); 15322cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) 1533fdc50a94SYusuke Goda free_irq(irq[1], host); 1534fdc50a94SYusuke Goda 1535ac0a2e98SUlf Hansson clk_disable_unprepare(host->hclk); 1536fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1537faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1538faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1539fdc50a94SYusuke Goda 1540fdc50a94SYusuke Goda return 0; 1541fdc50a94SYusuke Goda } 1542fdc50a94SYusuke Goda 154351129f31SUlf Hansson #ifdef CONFIG_PM_SLEEP 1544faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1545faca6648SGuennadi Liakhovetski { 1546b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1547faca6648SGuennadi Liakhovetski 1548faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1549faca6648SGuennadi Liakhovetski 1550cb3ca1aeSUlf Hansson return 0; 1551faca6648SGuennadi Liakhovetski } 1552faca6648SGuennadi Liakhovetski 1553faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1554faca6648SGuennadi Liakhovetski { 1555cb3ca1aeSUlf Hansson return 0; 1556faca6648SGuennadi Liakhovetski } 155751129f31SUlf Hansson #endif 1558faca6648SGuennadi Liakhovetski 1559bf68a812SGuennadi Liakhovetski static const struct of_device_id mmcif_of_match[] = { 1560bf68a812SGuennadi Liakhovetski { .compatible = "renesas,sh-mmcif" }, 1561bf68a812SGuennadi Liakhovetski { } 1562bf68a812SGuennadi Liakhovetski }; 1563bf68a812SGuennadi Liakhovetski MODULE_DEVICE_TABLE(of, mmcif_of_match); 1564bf68a812SGuennadi Liakhovetski 1565faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 156651129f31SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1567faca6648SGuennadi Liakhovetski }; 1568faca6648SGuennadi Liakhovetski 1569fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1570fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1571fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1572fdc50a94SYusuke Goda .driver = { 1573fdc50a94SYusuke Goda .name = DRIVER_NAME, 1574faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1575bf68a812SGuennadi Liakhovetski .owner = THIS_MODULE, 1576bf68a812SGuennadi Liakhovetski .of_match_table = mmcif_of_match, 1577fdc50a94SYusuke Goda }, 1578fdc50a94SYusuke Goda }; 1579fdc50a94SYusuke Goda 1580d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1581fdc50a94SYusuke Goda 1582fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1583fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1584aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1585fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1586