1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 59a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 60e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 61efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 62faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 633b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6488b47679SPaul Gortmaker #include <linux/module.h> 65fdc50a94SYusuke Goda 66fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 67fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 68fdc50a94SYusuke Goda 69fdc50a94SYusuke Goda /* CE_CMD_SET */ 70fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 71fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 72fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 73fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 74fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 75fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 76fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 77fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 78fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 79fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 80fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 81fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 82fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 83fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 84fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 85fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 86fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 88fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 89fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 90fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 91fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 92fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 93fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 94fdc50a94SYusuke Goda 95fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 96fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 97fdc50a94SYusuke Goda 98fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 99fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 100fdc50a94SYusuke Goda 101fdc50a94SYusuke Goda /* CE_INT */ 102fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 103fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 104fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 105fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 106fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 107fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 108fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 109fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 110fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 111fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 112fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 113fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 114fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 115fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 116fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 117fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 118fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 119fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 120fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 121fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 122fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 123fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 124fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 125fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 126fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 127fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 128fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 129fdc50a94SYusuke Goda 130fdc50a94SYusuke Goda /* CE_INT_MASK */ 131fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 132fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 133fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 134fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 135fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 136fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 137fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 138fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 139fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 140fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 141fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 142fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 143fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 144fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 145fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 146fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 147fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 148fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 149fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 150fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 151fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 152fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 153fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 154fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 155fdc50a94SYusuke Goda 156ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 157ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 158ee4b8887SGuennadi Liakhovetski MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ 159ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 160ee4b8887SGuennadi Liakhovetski 161fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 162fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 163fdc50a94SYusuke Goda 164fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 165fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 166fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 167fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 168fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 169fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 170fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 171fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 172fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 173fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 174fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 175fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 176fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 177fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 178fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 179fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 180fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 181fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 182fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 183fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 184fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 185fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 186fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 187fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 188fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 189fdc50a94SYusuke Goda 190fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 191fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 192fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 193fdc50a94SYusuke Goda 1943b0beafcSGuennadi Liakhovetski enum mmcif_state { 1953b0beafcSGuennadi Liakhovetski STATE_IDLE, 1963b0beafcSGuennadi Liakhovetski STATE_REQUEST, 1973b0beafcSGuennadi Liakhovetski STATE_IOS, 1983b0beafcSGuennadi Liakhovetski }; 1993b0beafcSGuennadi Liakhovetski 200f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 201f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 202f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 203f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 204f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 205f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 206f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 207f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 208f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 209f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 210f985da17SGuennadi Liakhovetski }; 211f985da17SGuennadi Liakhovetski 212fdc50a94SYusuke Goda struct sh_mmcif_host { 213fdc50a94SYusuke Goda struct mmc_host *mmc; 214f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 215fdc50a94SYusuke Goda struct platform_device *pd; 216714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave dma_slave_tx; 217714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave dma_slave_rx; 218fdc50a94SYusuke Goda struct clk *hclk; 219fdc50a94SYusuke Goda unsigned int clk; 220fdc50a94SYusuke Goda int bus_width; 221aa0787a9SGuennadi Liakhovetski bool sd_error; 222f985da17SGuennadi Liakhovetski bool dying; 223fdc50a94SYusuke Goda long timeout; 224fdc50a94SYusuke Goda void __iomem *addr; 225f985da17SGuennadi Liakhovetski u32 *pio_ptr; 226ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2273b0beafcSGuennadi Liakhovetski enum mmcif_state state; 228f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 229f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 230f985da17SGuennadi Liakhovetski size_t blocksize; 231f985da17SGuennadi Liakhovetski int sg_idx; 232f985da17SGuennadi Liakhovetski int sg_blkidx; 233faca6648SGuennadi Liakhovetski bool power; 234c9b0cef2SGuennadi Liakhovetski bool card_present; 235fdc50a94SYusuke Goda 236a782d688SGuennadi Liakhovetski /* DMA support */ 237a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 238a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 239a782d688SGuennadi Liakhovetski struct completion dma_complete; 240f38f94c6SLinus Walleij bool dma_active; 241a782d688SGuennadi Liakhovetski }; 242fdc50a94SYusuke Goda 243fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 244fdc50a94SYusuke Goda unsigned int reg, u32 val) 245fdc50a94SYusuke Goda { 246487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 247fdc50a94SYusuke Goda } 248fdc50a94SYusuke Goda 249fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 250fdc50a94SYusuke Goda unsigned int reg, u32 val) 251fdc50a94SYusuke Goda { 252487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 253fdc50a94SYusuke Goda } 254fdc50a94SYusuke Goda 255a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 256a782d688SGuennadi Liakhovetski { 257a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 25869983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 25969983404SGuennadi Liakhovetski 260a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 261a782d688SGuennadi Liakhovetski 26269983404SGuennadi Liakhovetski if (WARN(!data, "%s: NULL data in DMA completion!\n", 263a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 264a782d688SGuennadi Liakhovetski return; 265a782d688SGuennadi Liakhovetski 26669983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) 2671ed828dbSLinus Walleij dma_unmap_sg(host->chan_rx->device->dev, 26869983404SGuennadi Liakhovetski data->sg, data->sg_len, 269a782d688SGuennadi Liakhovetski DMA_FROM_DEVICE); 270a782d688SGuennadi Liakhovetski else 2711ed828dbSLinus Walleij dma_unmap_sg(host->chan_tx->device->dev, 27269983404SGuennadi Liakhovetski data->sg, data->sg_len, 273a782d688SGuennadi Liakhovetski DMA_TO_DEVICE); 274a782d688SGuennadi Liakhovetski 275a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 276a782d688SGuennadi Liakhovetski } 277a782d688SGuennadi Liakhovetski 278a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 279a782d688SGuennadi Liakhovetski { 28069983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 28169983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 282a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 283a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 284a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 285a782d688SGuennadi Liakhovetski int ret; 286a782d688SGuennadi Liakhovetski 28769983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 2881ed828dbSLinus Walleij DMA_FROM_DEVICE); 289a782d688SGuennadi Liakhovetski if (ret > 0) { 290f38f94c6SLinus Walleij host->dma_active = true; 29116052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 29205f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 293a782d688SGuennadi Liakhovetski } 294a782d688SGuennadi Liakhovetski 295a782d688SGuennadi Liakhovetski if (desc) { 296a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 297a782d688SGuennadi Liakhovetski desc->callback_param = host; 298a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 299a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 300a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 301a782d688SGuennadi Liakhovetski } 302a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 30369983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 304a782d688SGuennadi Liakhovetski 305a782d688SGuennadi Liakhovetski if (!desc) { 306a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 307a782d688SGuennadi Liakhovetski if (ret >= 0) 308a782d688SGuennadi Liakhovetski ret = -EIO; 309a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 310f38f94c6SLinus Walleij host->dma_active = false; 311a782d688SGuennadi Liakhovetski dma_release_channel(chan); 312a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 313a782d688SGuennadi Liakhovetski chan = host->chan_tx; 314a782d688SGuennadi Liakhovetski if (chan) { 315a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 316a782d688SGuennadi Liakhovetski dma_release_channel(chan); 317a782d688SGuennadi Liakhovetski } 318a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 319a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 320a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 321a782d688SGuennadi Liakhovetski } 322a782d688SGuennadi Liakhovetski 323a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 32469983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 325a782d688SGuennadi Liakhovetski } 326a782d688SGuennadi Liakhovetski 327a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 328a782d688SGuennadi Liakhovetski { 32969983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 33069983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 331a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 332a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 333a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 334a782d688SGuennadi Liakhovetski int ret; 335a782d688SGuennadi Liakhovetski 33669983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3371ed828dbSLinus Walleij DMA_TO_DEVICE); 338a782d688SGuennadi Liakhovetski if (ret > 0) { 339f38f94c6SLinus Walleij host->dma_active = true; 34016052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 34105f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 342a782d688SGuennadi Liakhovetski } 343a782d688SGuennadi Liakhovetski 344a782d688SGuennadi Liakhovetski if (desc) { 345a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 346a782d688SGuennadi Liakhovetski desc->callback_param = host; 347a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 348a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 349a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 350a782d688SGuennadi Liakhovetski } 351a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 35269983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 353a782d688SGuennadi Liakhovetski 354a782d688SGuennadi Liakhovetski if (!desc) { 355a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 356a782d688SGuennadi Liakhovetski if (ret >= 0) 357a782d688SGuennadi Liakhovetski ret = -EIO; 358a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 359f38f94c6SLinus Walleij host->dma_active = false; 360a782d688SGuennadi Liakhovetski dma_release_channel(chan); 361a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 362a782d688SGuennadi Liakhovetski chan = host->chan_rx; 363a782d688SGuennadi Liakhovetski if (chan) { 364a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 365a782d688SGuennadi Liakhovetski dma_release_channel(chan); 366a782d688SGuennadi Liakhovetski } 367a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 368a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 369a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 370a782d688SGuennadi Liakhovetski } 371a782d688SGuennadi Liakhovetski 372a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 373a782d688SGuennadi Liakhovetski desc, cookie); 374a782d688SGuennadi Liakhovetski } 375a782d688SGuennadi Liakhovetski 376a782d688SGuennadi Liakhovetski static bool sh_mmcif_filter(struct dma_chan *chan, void *arg) 377a782d688SGuennadi Liakhovetski { 378a782d688SGuennadi Liakhovetski dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); 379a782d688SGuennadi Liakhovetski chan->private = arg; 380a782d688SGuennadi Liakhovetski return true; 381a782d688SGuennadi Liakhovetski } 382a782d688SGuennadi Liakhovetski 383a782d688SGuennadi Liakhovetski static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 384a782d688SGuennadi Liakhovetski struct sh_mmcif_plat_data *pdata) 385a782d688SGuennadi Liakhovetski { 386714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave *tx, *rx; 387f38f94c6SLinus Walleij host->dma_active = false; 388a782d688SGuennadi Liakhovetski 389bf68a812SGuennadi Liakhovetski if (!pdata) 390bf68a812SGuennadi Liakhovetski return; 391bf68a812SGuennadi Liakhovetski 392a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 393a782d688SGuennadi Liakhovetski if (pdata->dma) { 394714c4a6eSGuennadi Liakhovetski dev_warn(&host->pd->dev, 395714c4a6eSGuennadi Liakhovetski "Update your platform to use embedded DMA slave IDs\n"); 396714c4a6eSGuennadi Liakhovetski tx = &pdata->dma->chan_priv_tx; 397714c4a6eSGuennadi Liakhovetski rx = &pdata->dma->chan_priv_rx; 398714c4a6eSGuennadi Liakhovetski } else { 399714c4a6eSGuennadi Liakhovetski tx = &host->dma_slave_tx; 400714c4a6eSGuennadi Liakhovetski tx->slave_id = pdata->slave_id_tx; 401714c4a6eSGuennadi Liakhovetski rx = &host->dma_slave_rx; 402714c4a6eSGuennadi Liakhovetski rx->slave_id = pdata->slave_id_rx; 403714c4a6eSGuennadi Liakhovetski } 404714c4a6eSGuennadi Liakhovetski if (tx->slave_id > 0 && rx->slave_id > 0) { 405a782d688SGuennadi Liakhovetski dma_cap_mask_t mask; 406a782d688SGuennadi Liakhovetski 407a782d688SGuennadi Liakhovetski dma_cap_zero(mask); 408a782d688SGuennadi Liakhovetski dma_cap_set(DMA_SLAVE, mask); 409a782d688SGuennadi Liakhovetski 410714c4a6eSGuennadi Liakhovetski host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx); 411a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 412a782d688SGuennadi Liakhovetski host->chan_tx); 413a782d688SGuennadi Liakhovetski 414a782d688SGuennadi Liakhovetski if (!host->chan_tx) 415a782d688SGuennadi Liakhovetski return; 416a782d688SGuennadi Liakhovetski 417714c4a6eSGuennadi Liakhovetski host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx); 418a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 419a782d688SGuennadi Liakhovetski host->chan_rx); 420a782d688SGuennadi Liakhovetski 421a782d688SGuennadi Liakhovetski if (!host->chan_rx) { 422a782d688SGuennadi Liakhovetski dma_release_channel(host->chan_tx); 423a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 424a782d688SGuennadi Liakhovetski return; 425a782d688SGuennadi Liakhovetski } 426a782d688SGuennadi Liakhovetski 427a782d688SGuennadi Liakhovetski init_completion(&host->dma_complete); 428a782d688SGuennadi Liakhovetski } 429a782d688SGuennadi Liakhovetski } 430a782d688SGuennadi Liakhovetski 431a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 432a782d688SGuennadi Liakhovetski { 433a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 434a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 435a782d688SGuennadi Liakhovetski if (host->chan_tx) { 436a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 437a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 438a782d688SGuennadi Liakhovetski dma_release_channel(chan); 439a782d688SGuennadi Liakhovetski } 440a782d688SGuennadi Liakhovetski if (host->chan_rx) { 441a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 442a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 443a782d688SGuennadi Liakhovetski dma_release_channel(chan); 444a782d688SGuennadi Liakhovetski } 445a782d688SGuennadi Liakhovetski 446f38f94c6SLinus Walleij host->dma_active = false; 447a782d688SGuennadi Liakhovetski } 448fdc50a94SYusuke Goda 449fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 450fdc50a94SYusuke Goda { 451fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 452bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 453fdc50a94SYusuke Goda 454fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 455fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 456fdc50a94SYusuke Goda 457fdc50a94SYusuke Goda if (!clk) 458fdc50a94SYusuke Goda return; 459bf68a812SGuennadi Liakhovetski if (sup_pclk && clk == host->clk) 460fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 461fdc50a94SYusuke Goda else 462fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 463f9388257SSimon Horman ((fls(DIV_ROUND_UP(host->clk, 464f9388257SSimon Horman clk) - 1) - 1) << 16)); 465fdc50a94SYusuke Goda 466fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 467fdc50a94SYusuke Goda } 468fdc50a94SYusuke Goda 469fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 470fdc50a94SYusuke Goda { 471fdc50a94SYusuke Goda u32 tmp; 472fdc50a94SYusuke Goda 473487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 474fdc50a94SYusuke Goda 475487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 476487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 477fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 478fdc50a94SYusuke Goda SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 479fdc50a94SYusuke Goda /* byte swap on */ 480fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 481fdc50a94SYusuke Goda } 482fdc50a94SYusuke Goda 483fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 484fdc50a94SYusuke Goda { 485fdc50a94SYusuke Goda u32 state1, state2; 486ee4b8887SGuennadi Liakhovetski int ret, timeout; 487fdc50a94SYusuke Goda 488aa0787a9SGuennadi Liakhovetski host->sd_error = false; 489fdc50a94SYusuke Goda 490487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 491487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 492e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 493e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 494fdc50a94SYusuke Goda 495fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 496fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 497fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 498ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 499487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 500fdc50a94SYusuke Goda & STS1_CMDSEQ)) 501fdc50a94SYusuke Goda break; 502fdc50a94SYusuke Goda mdelay(1); 503fdc50a94SYusuke Goda } 504ee4b8887SGuennadi Liakhovetski if (!timeout) { 505ee4b8887SGuennadi Liakhovetski dev_err(&host->pd->dev, 506ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 507ee4b8887SGuennadi Liakhovetski return -EIO; 508ee4b8887SGuennadi Liakhovetski } 509fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 510e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 511fdc50a94SYusuke Goda return -EIO; 512fdc50a94SYusuke Goda } 513fdc50a94SYusuke Goda 514fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 515ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": CRC error\n"); 516fdc50a94SYusuke Goda ret = -EIO; 517fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 518ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Timeout\n"); 519fdc50a94SYusuke Goda ret = -ETIMEDOUT; 520fdc50a94SYusuke Goda } else { 521ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": End/Index error\n"); 522fdc50a94SYusuke Goda ret = -EIO; 523fdc50a94SYusuke Goda } 524fdc50a94SYusuke Goda return ret; 525fdc50a94SYusuke Goda } 526fdc50a94SYusuke Goda 527f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 528f985da17SGuennadi Liakhovetski { 529f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 530f985da17SGuennadi Liakhovetski 531f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 532f985da17SGuennadi Liakhovetski 533f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 534f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 535f985da17SGuennadi Liakhovetski 536f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 537f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 538f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 539f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 540f985da17SGuennadi Liakhovetski } else { 541f985da17SGuennadi Liakhovetski host->pio_ptr = p; 542f985da17SGuennadi Liakhovetski } 543f985da17SGuennadi Liakhovetski 544f985da17SGuennadi Liakhovetski if (host->sg_idx == data->sg_len) 545f985da17SGuennadi Liakhovetski return false; 546f985da17SGuennadi Liakhovetski 547f985da17SGuennadi Liakhovetski return true; 548f985da17SGuennadi Liakhovetski } 549f985da17SGuennadi Liakhovetski 550f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 551fdc50a94SYusuke Goda struct mmc_request *mrq) 552fdc50a94SYusuke Goda { 553f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 554f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 555f985da17SGuennadi Liakhovetski 556f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 557f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 558fdc50a94SYusuke Goda 559fdc50a94SYusuke Goda /* buf read enable */ 560fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 561f985da17SGuennadi Liakhovetski } 562fdc50a94SYusuke Goda 563f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 564f985da17SGuennadi Liakhovetski { 565f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 566f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 567f985da17SGuennadi Liakhovetski int i; 568f985da17SGuennadi Liakhovetski 569f985da17SGuennadi Liakhovetski if (host->sd_error) { 570f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 571f985da17SGuennadi Liakhovetski return false; 572f985da17SGuennadi Liakhovetski } 573f985da17SGuennadi Liakhovetski 574f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 575487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 576fdc50a94SYusuke Goda 577fdc50a94SYusuke Goda /* buffer read end */ 578fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 579f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 580fdc50a94SYusuke Goda 581f985da17SGuennadi Liakhovetski return true; 582fdc50a94SYusuke Goda } 583fdc50a94SYusuke Goda 584f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 585fdc50a94SYusuke Goda struct mmc_request *mrq) 586fdc50a94SYusuke Goda { 587fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 588fdc50a94SYusuke Goda 589f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 590f985da17SGuennadi Liakhovetski return; 591f985da17SGuennadi Liakhovetski 592f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 593f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 594f985da17SGuennadi Liakhovetski 595f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 596f985da17SGuennadi Liakhovetski host->sg_idx = 0; 597f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 598f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 599f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 600fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 601fdc50a94SYusuke Goda } 602fdc50a94SYusuke Goda 603f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 604f985da17SGuennadi Liakhovetski { 605f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 606f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 607f985da17SGuennadi Liakhovetski int i; 608f985da17SGuennadi Liakhovetski 609f985da17SGuennadi Liakhovetski if (host->sd_error) { 610f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 611f985da17SGuennadi Liakhovetski return false; 612f985da17SGuennadi Liakhovetski } 613f985da17SGuennadi Liakhovetski 614f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 615f985da17SGuennadi Liakhovetski 616f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 617f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 618f985da17SGuennadi Liakhovetski 619f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 620f985da17SGuennadi Liakhovetski return false; 621f985da17SGuennadi Liakhovetski 622f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 623f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 624f985da17SGuennadi Liakhovetski 625f985da17SGuennadi Liakhovetski return true; 626f985da17SGuennadi Liakhovetski } 627f985da17SGuennadi Liakhovetski 628f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 629fdc50a94SYusuke Goda struct mmc_request *mrq) 630fdc50a94SYusuke Goda { 631f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 632f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 633fdc50a94SYusuke Goda 634f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 635f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 636fdc50a94SYusuke Goda 637fdc50a94SYusuke Goda /* buf write enable */ 638f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 639f985da17SGuennadi Liakhovetski } 640fdc50a94SYusuke Goda 641f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 642f985da17SGuennadi Liakhovetski { 643f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 644f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 645f985da17SGuennadi Liakhovetski int i; 646f985da17SGuennadi Liakhovetski 647f985da17SGuennadi Liakhovetski if (host->sd_error) { 648f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 649f985da17SGuennadi Liakhovetski return false; 650f985da17SGuennadi Liakhovetski } 651f985da17SGuennadi Liakhovetski 652f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 653487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 654fdc50a94SYusuke Goda 655fdc50a94SYusuke Goda /* buffer write end */ 656fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 657f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 658fdc50a94SYusuke Goda 659f985da17SGuennadi Liakhovetski return true; 660fdc50a94SYusuke Goda } 661fdc50a94SYusuke Goda 662f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 663fdc50a94SYusuke Goda struct mmc_request *mrq) 664fdc50a94SYusuke Goda { 665fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 666fdc50a94SYusuke Goda 667f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 668f985da17SGuennadi Liakhovetski return; 669fdc50a94SYusuke Goda 670f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 671f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 672f985da17SGuennadi Liakhovetski 673f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 674f985da17SGuennadi Liakhovetski host->sg_idx = 0; 675f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 676f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 677f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 678fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 679fdc50a94SYusuke Goda } 680f985da17SGuennadi Liakhovetski 681f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 682f985da17SGuennadi Liakhovetski { 683f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 684f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 685f985da17SGuennadi Liakhovetski int i; 686f985da17SGuennadi Liakhovetski 687f985da17SGuennadi Liakhovetski if (host->sd_error) { 688f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 689f985da17SGuennadi Liakhovetski return false; 690fdc50a94SYusuke Goda } 691f985da17SGuennadi Liakhovetski 692f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 693f985da17SGuennadi Liakhovetski 694f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 695f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 696f985da17SGuennadi Liakhovetski 697f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 698f985da17SGuennadi Liakhovetski return false; 699f985da17SGuennadi Liakhovetski 700f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 701f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 702f985da17SGuennadi Liakhovetski 703f985da17SGuennadi Liakhovetski return true; 704fdc50a94SYusuke Goda } 705fdc50a94SYusuke Goda 706fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 707fdc50a94SYusuke Goda struct mmc_command *cmd) 708fdc50a94SYusuke Goda { 709fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 710487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 711487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 712487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 713487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 714fdc50a94SYusuke Goda } else 715487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 716fdc50a94SYusuke Goda } 717fdc50a94SYusuke Goda 718fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 719fdc50a94SYusuke Goda struct mmc_command *cmd) 720fdc50a94SYusuke Goda { 721487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 722fdc50a94SYusuke Goda } 723fdc50a94SYusuke Goda 724fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 72569983404SGuennadi Liakhovetski struct mmc_request *mrq) 726fdc50a94SYusuke Goda { 72769983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 72869983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 72969983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 730fdc50a94SYusuke Goda u32 tmp = 0; 731fdc50a94SYusuke Goda 732fdc50a94SYusuke Goda /* Response Type check */ 733fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 734fdc50a94SYusuke Goda case MMC_RSP_NONE: 735fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 736fdc50a94SYusuke Goda break; 737fdc50a94SYusuke Goda case MMC_RSP_R1: 738fdc50a94SYusuke Goda case MMC_RSP_R1B: 739fdc50a94SYusuke Goda case MMC_RSP_R3: 740fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 741fdc50a94SYusuke Goda break; 742fdc50a94SYusuke Goda case MMC_RSP_R2: 743fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 744fdc50a94SYusuke Goda break; 745fdc50a94SYusuke Goda default: 746e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 747fdc50a94SYusuke Goda break; 748fdc50a94SYusuke Goda } 749fdc50a94SYusuke Goda switch (opc) { 750fdc50a94SYusuke Goda /* RBSY */ 751fdc50a94SYusuke Goda case MMC_SWITCH: 752fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 753fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 754fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 755fdc50a94SYusuke Goda case MMC_ERASE: 756fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 757fdc50a94SYusuke Goda break; 758fdc50a94SYusuke Goda } 759fdc50a94SYusuke Goda /* WDAT / DATW */ 76069983404SGuennadi Liakhovetski if (data) { 761fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 762fdc50a94SYusuke Goda switch (host->bus_width) { 763fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 764fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 765fdc50a94SYusuke Goda break; 766fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 767fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 768fdc50a94SYusuke Goda break; 769fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 770fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 771fdc50a94SYusuke Goda break; 772fdc50a94SYusuke Goda default: 773e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 774fdc50a94SYusuke Goda break; 775fdc50a94SYusuke Goda } 776fdc50a94SYusuke Goda } 777fdc50a94SYusuke Goda /* DWEN */ 778fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 779fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 780fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 781fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 782fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 783fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 78469983404SGuennadi Liakhovetski data->blocks << 16); 785fdc50a94SYusuke Goda } 786fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 787fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 788fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 789fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 790fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 791fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 792fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 793fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 794fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 795fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 796fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 797fdc50a94SYusuke Goda 79869983404SGuennadi Liakhovetski return (opc << 24) | tmp; 799fdc50a94SYusuke Goda } 800fdc50a94SYusuke Goda 801e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 802fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 803fdc50a94SYusuke Goda { 804fdc50a94SYusuke Goda switch (opc) { 805fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 806f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 807f985da17SGuennadi Liakhovetski return 0; 808fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 809f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 810f985da17SGuennadi Liakhovetski return 0; 811fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 812f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 813f985da17SGuennadi Liakhovetski return 0; 814fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 815fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 816f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 817f985da17SGuennadi Liakhovetski return 0; 818fdc50a94SYusuke Goda default: 819e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 820ee4b8887SGuennadi Liakhovetski return -EINVAL; 821fdc50a94SYusuke Goda } 822fdc50a94SYusuke Goda } 823fdc50a94SYusuke Goda 824fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 825ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 826fdc50a94SYusuke Goda { 827ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 828f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 829f985da17SGuennadi Liakhovetski u32 mask; 830fdc50a94SYusuke Goda 831fdc50a94SYusuke Goda switch (opc) { 832ee4b8887SGuennadi Liakhovetski /* response busy check */ 833fdc50a94SYusuke Goda case MMC_SWITCH: 834fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 835fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 836fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 837fdc50a94SYusuke Goda case MMC_ERASE: 838ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 839fdc50a94SYusuke Goda break; 840fdc50a94SYusuke Goda default: 841ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 842fdc50a94SYusuke Goda break; 843fdc50a94SYusuke Goda } 844fdc50a94SYusuke Goda 84569983404SGuennadi Liakhovetski if (mrq->data) { 846487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 847487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 848487d9fc5SMagnus Damm mrq->data->blksz); 849fdc50a94SYusuke Goda } 85069983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 851fdc50a94SYusuke Goda 852487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 853487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 854fdc50a94SYusuke Goda /* set arg */ 855487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 856fdc50a94SYusuke Goda /* set cmd */ 857487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 858fdc50a94SYusuke Goda 859f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 860f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 861fdc50a94SYusuke Goda } 862fdc50a94SYusuke Goda 863fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 864ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 865fdc50a94SYusuke Goda { 86669983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 86769983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 868fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 86969983404SGuennadi Liakhovetski break; 87069983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 871fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 87269983404SGuennadi Liakhovetski break; 87369983404SGuennadi Liakhovetski default: 874e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 87569983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 876fdc50a94SYusuke Goda return; 877fdc50a94SYusuke Goda } 878fdc50a94SYusuke Goda 879f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 880f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 881fdc50a94SYusuke Goda } 882fdc50a94SYusuke Goda 883fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 884fdc50a94SYusuke Goda { 885fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 8863b0beafcSGuennadi Liakhovetski unsigned long flags; 8873b0beafcSGuennadi Liakhovetski 8883b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8893b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8903b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 8913b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 8923b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 8933b0beafcSGuennadi Liakhovetski return; 8943b0beafcSGuennadi Liakhovetski } 8953b0beafcSGuennadi Liakhovetski 8963b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 8973b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 898fdc50a94SYusuke Goda 899fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 900fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 9017541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 9027541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 9037541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 9047541ca98SLaurent Pinchart break; 905fdc50a94SYusuke Goda case MMC_APP_CMD: 9063b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 907fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 908fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 909fdc50a94SYusuke Goda return; 910fdc50a94SYusuke Goda default: 911fdc50a94SYusuke Goda break; 912fdc50a94SYusuke Goda } 913fdc50a94SYusuke Goda 914f985da17SGuennadi Liakhovetski host->mrq = mrq; 915f985da17SGuennadi Liakhovetski 916f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 917fdc50a94SYusuke Goda } 918fdc50a94SYusuke Goda 919a6609267SGuennadi Liakhovetski static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 920a6609267SGuennadi Liakhovetski { 921a6609267SGuennadi Liakhovetski int ret = clk_enable(host->hclk); 922a6609267SGuennadi Liakhovetski 923a6609267SGuennadi Liakhovetski if (!ret) { 924a6609267SGuennadi Liakhovetski host->clk = clk_get_rate(host->hclk); 925a6609267SGuennadi Liakhovetski host->mmc->f_max = host->clk / 2; 926a6609267SGuennadi Liakhovetski host->mmc->f_min = host->clk / 512; 927a6609267SGuennadi Liakhovetski } 928a6609267SGuennadi Liakhovetski 929a6609267SGuennadi Liakhovetski return ret; 930a6609267SGuennadi Liakhovetski } 931a6609267SGuennadi Liakhovetski 9327d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 9337d17baa0SGuennadi Liakhovetski { 9347d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 9357d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 9367d17baa0SGuennadi Liakhovetski 937bf68a812SGuennadi Liakhovetski if (pd && pd->set_pwr) 9387d17baa0SGuennadi Liakhovetski pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF); 9397d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 9407d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 9417d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 9427d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 9437d17baa0SGuennadi Liakhovetski } 9447d17baa0SGuennadi Liakhovetski 945fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 946fdc50a94SYusuke Goda { 947fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9483b0beafcSGuennadi Liakhovetski unsigned long flags; 9493b0beafcSGuennadi Liakhovetski 9503b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9513b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 9523b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9533b0beafcSGuennadi Liakhovetski return; 9543b0beafcSGuennadi Liakhovetski } 9553b0beafcSGuennadi Liakhovetski 9563b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 9573b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 958fdc50a94SYusuke Goda 959f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 960c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 961faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 962faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 963c9b0cef2SGuennadi Liakhovetski host->card_present = true; 964faca6648SGuennadi Liakhovetski } 9657d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 966f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 967f5e0cec4SGuennadi Liakhovetski /* clock stop */ 968f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 969faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 970c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 971c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 972c9b0cef2SGuennadi Liakhovetski host->card_present = false; 973c9b0cef2SGuennadi Liakhovetski } 974c9b0cef2SGuennadi Liakhovetski } 975faca6648SGuennadi Liakhovetski if (host->power) { 976faca6648SGuennadi Liakhovetski pm_runtime_put(&host->pd->dev); 977b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 978faca6648SGuennadi Liakhovetski host->power = false; 9797d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 9807d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 981faca6648SGuennadi Liakhovetski } 9823b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 983f5e0cec4SGuennadi Liakhovetski return; 984fdc50a94SYusuke Goda } 985fdc50a94SYusuke Goda 986c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 987c9b0cef2SGuennadi Liakhovetski if (!host->power) { 988a6609267SGuennadi Liakhovetski sh_mmcif_clk_update(host); 989c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 990c9b0cef2SGuennadi Liakhovetski host->power = true; 991c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 992c9b0cef2SGuennadi Liakhovetski } 993fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 994c9b0cef2SGuennadi Liakhovetski } 995fdc50a94SYusuke Goda 996fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 9973b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 998fdc50a94SYusuke Goda } 999fdc50a94SYusuke Goda 1000777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1001777271d0SArnd Hannemann { 1002777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1003777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1004e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1005e480606aSGuennadi Liakhovetski 1006e480606aSGuennadi Liakhovetski if (ret >= 0) 1007e480606aSGuennadi Liakhovetski return ret; 1008777271d0SArnd Hannemann 1009bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1010777271d0SArnd Hannemann return -ENOSYS; 1011777271d0SArnd Hannemann else 1012777271d0SArnd Hannemann return p->get_cd(host->pd); 1013777271d0SArnd Hannemann } 1014777271d0SArnd Hannemann 1015fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1016fdc50a94SYusuke Goda .request = sh_mmcif_request, 1017fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1018777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1019fdc50a94SYusuke Goda }; 1020fdc50a94SYusuke Goda 1021f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1022f985da17SGuennadi Liakhovetski { 1023f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 102469983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1025f985da17SGuennadi Liakhovetski long time; 1026f985da17SGuennadi Liakhovetski 1027f985da17SGuennadi Liakhovetski if (host->sd_error) { 1028f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1029f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1030f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1031f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1032f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1033f985da17SGuennadi Liakhovetski host->sd_error = false; 1034f985da17SGuennadi Liakhovetski break; 1035f985da17SGuennadi Liakhovetski default: 1036f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1037f985da17SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n", 1038f985da17SGuennadi Liakhovetski cmd->opcode, cmd->error); 1039f985da17SGuennadi Liakhovetski break; 1040f985da17SGuennadi Liakhovetski } 1041f985da17SGuennadi Liakhovetski return false; 1042f985da17SGuennadi Liakhovetski } 1043f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1044f985da17SGuennadi Liakhovetski cmd->error = 0; 1045f985da17SGuennadi Liakhovetski return false; 1046f985da17SGuennadi Liakhovetski } 1047f985da17SGuennadi Liakhovetski 1048f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1049f985da17SGuennadi Liakhovetski 105069983404SGuennadi Liakhovetski if (!data) 1051f985da17SGuennadi Liakhovetski return false; 1052f985da17SGuennadi Liakhovetski 105369983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1054f985da17SGuennadi Liakhovetski if (host->chan_rx) 1055f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1056f985da17SGuennadi Liakhovetski } else { 1057f985da17SGuennadi Liakhovetski if (host->chan_tx) 1058f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1059f985da17SGuennadi Liakhovetski } 1060f985da17SGuennadi Liakhovetski 1061f985da17SGuennadi Liakhovetski if (!host->dma_active) { 106269983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 106369983404SGuennadi Liakhovetski if (!data->error) 1064f985da17SGuennadi Liakhovetski return true; 1065f985da17SGuennadi Liakhovetski return false; 1066f985da17SGuennadi Liakhovetski } 1067f985da17SGuennadi Liakhovetski 1068f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1069f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1070f985da17SGuennadi Liakhovetski host->timeout); 1071f985da17SGuennadi Liakhovetski if (host->sd_error) { 1072f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1073f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1074f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 107569983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) 1076f985da17SGuennadi Liakhovetski dmaengine_terminate_all(host->chan_rx); 1077f985da17SGuennadi Liakhovetski else 1078f985da17SGuennadi Liakhovetski dmaengine_terminate_all(host->chan_tx); 107969983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1080f985da17SGuennadi Liakhovetski } else if (!time) { 108169983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1082f985da17SGuennadi Liakhovetski } else if (time < 0) { 108369983404SGuennadi Liakhovetski data->error = time; 1084f985da17SGuennadi Liakhovetski } 1085f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1086f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1087f985da17SGuennadi Liakhovetski host->dma_active = false; 1088f985da17SGuennadi Liakhovetski 108969983404SGuennadi Liakhovetski if (data->error) 109069983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1091f985da17SGuennadi Liakhovetski 1092f985da17SGuennadi Liakhovetski return false; 1093f985da17SGuennadi Liakhovetski } 1094f985da17SGuennadi Liakhovetski 1095f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1096f985da17SGuennadi Liakhovetski { 1097f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 1098f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 109969983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 1100f985da17SGuennadi Liakhovetski 1101f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1102f985da17SGuennadi Liakhovetski 1103f985da17SGuennadi Liakhovetski /* 1104f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1105f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1106f985da17SGuennadi Liakhovetski */ 1107f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1108f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1109f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 1110f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1111f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1112f985da17SGuennadi Liakhovetski if (sh_mmcif_end_cmd(host)) 1113f985da17SGuennadi Liakhovetski /* Wait for data */ 1114f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1115f985da17SGuennadi Liakhovetski break; 1116f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1117f985da17SGuennadi Liakhovetski if (sh_mmcif_mread_block(host)) 1118f985da17SGuennadi Liakhovetski /* Wait for more data */ 1119f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1120f985da17SGuennadi Liakhovetski break; 1121f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1122f985da17SGuennadi Liakhovetski if (sh_mmcif_read_block(host)) 1123f985da17SGuennadi Liakhovetski /* Wait for data end */ 1124f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1125f985da17SGuennadi Liakhovetski break; 1126f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1127f985da17SGuennadi Liakhovetski if (sh_mmcif_mwrite_block(host)) 1128f985da17SGuennadi Liakhovetski /* Wait data to write */ 1129f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1130f985da17SGuennadi Liakhovetski break; 1131f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1132f985da17SGuennadi Liakhovetski if (sh_mmcif_write_block(host)) 1133f985da17SGuennadi Liakhovetski /* Wait for data end */ 1134f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1135f985da17SGuennadi Liakhovetski break; 1136f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1137f985da17SGuennadi Liakhovetski if (host->sd_error) { 1138f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1139f985da17SGuennadi Liakhovetski break; 1140f985da17SGuennadi Liakhovetski } 1141f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1142f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1143f985da17SGuennadi Liakhovetski break; 1144f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1145f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1146f985da17SGuennadi Liakhovetski if (host->sd_error) 114769983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1148f985da17SGuennadi Liakhovetski break; 1149f985da17SGuennadi Liakhovetski default: 1150f985da17SGuennadi Liakhovetski BUG(); 1151f985da17SGuennadi Liakhovetski } 1152f985da17SGuennadi Liakhovetski 1153f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 115469983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 115569983404SGuennadi Liakhovetski data->bytes_xfered = 115669983404SGuennadi Liakhovetski data->blocks * data->blksz; 1157f985da17SGuennadi Liakhovetski 115869983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1159f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 1160f985da17SGuennadi Liakhovetski if (!mrq->stop->error) 1161f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1162f985da17SGuennadi Liakhovetski } 1163f985da17SGuennadi Liakhovetski } 1164f985da17SGuennadi Liakhovetski 1165f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1166f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 116769983404SGuennadi Liakhovetski host->mrq = NULL; 1168f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1169f985da17SGuennadi Liakhovetski 1170f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1171f985da17SGuennadi Liakhovetski } 1172f985da17SGuennadi Liakhovetski 1173fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1174fdc50a94SYusuke Goda { 1175fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1176aa0787a9SGuennadi Liakhovetski u32 state; 1177fdc50a94SYusuke Goda int err = 0; 1178fdc50a94SYusuke Goda 1179487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1180fdc50a94SYusuke Goda 11818a8284a9SGuennadi Liakhovetski if (state & INT_ERR_STS) { 11828a8284a9SGuennadi Liakhovetski /* error interrupts - process first */ 11838a8284a9SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 11848a8284a9SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 11858a8284a9SGuennadi Liakhovetski err = 1; 11868a8284a9SGuennadi Liakhovetski } else if (state & INT_RBSYE) { 1187487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1188487d9fc5SMagnus Damm ~(INT_RBSYE | INT_CRSPE)); 1189fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 1190fdc50a94SYusuke Goda } else if (state & INT_CRSPE) { 1191487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 1192fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 1193fdc50a94SYusuke Goda } else if (state & INT_BUFREN) { 1194487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 1195fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 1196fdc50a94SYusuke Goda } else if (state & INT_BUFWEN) { 1197487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 1198fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 1199fdc50a94SYusuke Goda } else if (state & INT_CMD12DRE) { 1200487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1201fdc50a94SYusuke Goda ~(INT_CMD12DRE | INT_CMD12RBE | 1202fdc50a94SYusuke Goda INT_CMD12CRE | INT_BUFRE)); 1203fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 1204fdc50a94SYusuke Goda } else if (state & INT_BUFRE) { 1205487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 1206fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 1207fdc50a94SYusuke Goda } else if (state & INT_DTRANE) { 1208487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); 1209fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 1210fdc50a94SYusuke Goda } else if (state & INT_CMD12RBE) { 1211487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1212fdc50a94SYusuke Goda ~(INT_CMD12RBE | INT_CMD12CRE)); 1213fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 1214fdc50a94SYusuke Goda } else { 1215faca6648SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 1216487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1217fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1218fdc50a94SYusuke Goda err = 1; 1219fdc50a94SYusuke Goda } 1220fdc50a94SYusuke Goda if (err) { 1221aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1222e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 1223fdc50a94SYusuke Goda } 1224f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1225f985da17SGuennadi Liakhovetski if (!host->dma_active) 1226f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1227f985da17SGuennadi Liakhovetski else if (host->sd_error) 1228f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1229f985da17SGuennadi Liakhovetski } else { 1230aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1231f985da17SGuennadi Liakhovetski } 1232fdc50a94SYusuke Goda 1233fdc50a94SYusuke Goda return IRQ_HANDLED; 1234fdc50a94SYusuke Goda } 1235fdc50a94SYusuke Goda 1236f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1237f985da17SGuennadi Liakhovetski { 1238f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1239f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1240f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 1241f985da17SGuennadi Liakhovetski 1242f985da17SGuennadi Liakhovetski if (host->dying) 1243f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1244f985da17SGuennadi Liakhovetski return; 1245f985da17SGuennadi Liakhovetski 1246f985da17SGuennadi Liakhovetski /* 1247f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1248f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1249f985da17SGuennadi Liakhovetski */ 1250f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1251f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1252f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1253f985da17SGuennadi Liakhovetski break; 1254f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1255f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1256f985da17SGuennadi Liakhovetski break; 1257f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1258f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1259f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1260f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1261f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1262f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 126369983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1264f985da17SGuennadi Liakhovetski break; 1265f985da17SGuennadi Liakhovetski default: 1266f985da17SGuennadi Liakhovetski BUG(); 1267f985da17SGuennadi Liakhovetski } 1268f985da17SGuennadi Liakhovetski 1269f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1270f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1271f985da17SGuennadi Liakhovetski host->mrq = NULL; 1272f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1273f985da17SGuennadi Liakhovetski } 1274f985da17SGuennadi Liakhovetski 12757d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 12767d17baa0SGuennadi Liakhovetski { 12777d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 12787d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 12797d17baa0SGuennadi Liakhovetski 12807d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 12817d17baa0SGuennadi Liakhovetski 1282bf68a812SGuennadi Liakhovetski if (!pd) 1283bf68a812SGuennadi Liakhovetski return; 1284bf68a812SGuennadi Liakhovetski 12857d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 12867d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 12877d17baa0SGuennadi Liakhovetski else if (pd->ocr) 12887d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 12897d17baa0SGuennadi Liakhovetski } 12907d17baa0SGuennadi Liakhovetski 1291fdc50a94SYusuke Goda static int __devinit sh_mmcif_probe(struct platform_device *pdev) 1292fdc50a94SYusuke Goda { 1293fdc50a94SYusuke Goda int ret = 0, irq[2]; 1294fdc50a94SYusuke Goda struct mmc_host *mmc; 1295e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1296e1aae2ebSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1297fdc50a94SYusuke Goda struct resource *res; 1298fdc50a94SYusuke Goda void __iomem *reg; 1299fdc50a94SYusuke Goda char clk_name[8]; 1300fdc50a94SYusuke Goda 1301fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1302fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1303fdc50a94SYusuke Goda if (irq[0] < 0 || irq[1] < 0) { 1304e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1305fdc50a94SYusuke Goda return -ENXIO; 1306fdc50a94SYusuke Goda } 1307fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1308fdc50a94SYusuke Goda if (!res) { 1309fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1310fdc50a94SYusuke Goda return -ENXIO; 1311fdc50a94SYusuke Goda } 1312fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1313fdc50a94SYusuke Goda if (!reg) { 1314fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1315fdc50a94SYusuke Goda return -ENOMEM; 1316fdc50a94SYusuke Goda } 1317e1aae2ebSGuennadi Liakhovetski 1318fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1319fdc50a94SYusuke Goda if (!mmc) { 1320fdc50a94SYusuke Goda ret = -ENOMEM; 1321e1aae2ebSGuennadi Liakhovetski goto ealloch; 1322fdc50a94SYusuke Goda } 1323fdc50a94SYusuke Goda host = mmc_priv(mmc); 1324fdc50a94SYusuke Goda host->mmc = mmc; 1325fdc50a94SYusuke Goda host->addr = reg; 1326fdc50a94SYusuke Goda host->timeout = 1000; 1327fdc50a94SYusuke Goda 1328fdc50a94SYusuke Goda host->pd = pdev; 1329fdc50a94SYusuke Goda 13303b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1331fdc50a94SYusuke Goda 1332fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 13337d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 13347d17baa0SGuennadi Liakhovetski 1335fdc50a94SYusuke Goda mmc->caps = MMC_CAP_MMC_HIGHSPEED; 1336bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1337fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1338a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1339fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1340a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1341a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1342fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1343fdc50a94SYusuke Goda 1344fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1345a782d688SGuennadi Liakhovetski 1346faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1347faca6648SGuennadi Liakhovetski host->power = false; 1348faca6648SGuennadi Liakhovetski 1349b289174fSGuennadi Liakhovetski snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 1350b289174fSGuennadi Liakhovetski host->hclk = clk_get(&pdev->dev, clk_name); 1351b289174fSGuennadi Liakhovetski if (IS_ERR(host->hclk)) { 1352b289174fSGuennadi Liakhovetski ret = PTR_ERR(host->hclk); 1353b289174fSGuennadi Liakhovetski dev_err(&pdev->dev, "cannot get clock \"%s\": %d\n", clk_name, ret); 1354b289174fSGuennadi Liakhovetski goto eclkget; 1355b289174fSGuennadi Liakhovetski } 1356a6609267SGuennadi Liakhovetski ret = sh_mmcif_clk_update(host); 1357a6609267SGuennadi Liakhovetski if (ret < 0) 1358a6609267SGuennadi Liakhovetski goto eclkupdate; 1359b289174fSGuennadi Liakhovetski 1360faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1361faca6648SGuennadi Liakhovetski if (ret < 0) 1362e1aae2ebSGuennadi Liakhovetski goto eresume; 1363a782d688SGuennadi Liakhovetski 13645ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1365fdc50a94SYusuke Goda 1366b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 13673b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 13683b0beafcSGuennadi Liakhovetski 1369f985da17SGuennadi Liakhovetski ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host); 1370fdc50a94SYusuke Goda if (ret) { 1371e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); 1372e1aae2ebSGuennadi Liakhovetski goto ereqirq0; 1373fdc50a94SYusuke Goda } 1374f985da17SGuennadi Liakhovetski ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host); 1375fdc50a94SYusuke Goda if (ret) { 1376e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1377e1aae2ebSGuennadi Liakhovetski goto ereqirq1; 1378fdc50a94SYusuke Goda } 1379fdc50a94SYusuke Goda 1380e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1381e480606aSGuennadi Liakhovetski ret = mmc_gpio_request_cd(mmc, pd->cd_gpio); 1382e480606aSGuennadi Liakhovetski if (ret < 0) 1383e480606aSGuennadi Liakhovetski goto erqcd; 1384e480606aSGuennadi Liakhovetski } 1385e480606aSGuennadi Liakhovetski 1386b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 13875ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 13885ba85d95SGuennadi Liakhovetski if (ret < 0) 1389e1aae2ebSGuennadi Liakhovetski goto emmcaddh; 1390fdc50a94SYusuke Goda 1391efe6a8adSRafael J. Wysocki dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1392efe6a8adSRafael J. Wysocki 1393e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1394e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1395487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1396fdc50a94SYusuke Goda return ret; 1397fdc50a94SYusuke Goda 1398e1aae2ebSGuennadi Liakhovetski emmcaddh: 1399e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) 1400e480606aSGuennadi Liakhovetski mmc_gpio_free_cd(mmc); 1401e480606aSGuennadi Liakhovetski erqcd: 14025ba85d95SGuennadi Liakhovetski free_irq(irq[1], host); 1403e1aae2ebSGuennadi Liakhovetski ereqirq1: 14045ba85d95SGuennadi Liakhovetski free_irq(irq[0], host); 1405e1aae2ebSGuennadi Liakhovetski ereqirq0: 1406faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1407e1aae2ebSGuennadi Liakhovetski eresume: 1408fdc50a94SYusuke Goda clk_disable(host->hclk); 1409a6609267SGuennadi Liakhovetski eclkupdate: 1410b289174fSGuennadi Liakhovetski clk_put(host->hclk); 1411e1aae2ebSGuennadi Liakhovetski eclkget: 1412b289174fSGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1413fdc50a94SYusuke Goda mmc_free_host(mmc); 1414e1aae2ebSGuennadi Liakhovetski ealloch: 1415fdc50a94SYusuke Goda iounmap(reg); 1416fdc50a94SYusuke Goda return ret; 1417fdc50a94SYusuke Goda } 1418fdc50a94SYusuke Goda 1419fdc50a94SYusuke Goda static int __devexit sh_mmcif_remove(struct platform_device *pdev) 1420fdc50a94SYusuke Goda { 1421fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1422e480606aSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1423fdc50a94SYusuke Goda int irq[2]; 1424fdc50a94SYusuke Goda 1425f985da17SGuennadi Liakhovetski host->dying = true; 1426b289174fSGuennadi Liakhovetski clk_enable(host->hclk); 1427faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1428aa0787a9SGuennadi Liakhovetski 1429efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1430efe6a8adSRafael J. Wysocki 1431e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) 1432e480606aSGuennadi Liakhovetski mmc_gpio_free_cd(host->mmc); 1433e480606aSGuennadi Liakhovetski 1434faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 14353b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14363b0beafcSGuennadi Liakhovetski 1437f985da17SGuennadi Liakhovetski /* 1438f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1439f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1440f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1441f985da17SGuennadi Liakhovetski */ 1442f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1443f985da17SGuennadi Liakhovetski 1444aa0787a9SGuennadi Liakhovetski if (host->addr) 1445aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1446aa0787a9SGuennadi Liakhovetski 1447fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1448fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1449fdc50a94SYusuke Goda 1450fdc50a94SYusuke Goda free_irq(irq[0], host); 1451fdc50a94SYusuke Goda free_irq(irq[1], host); 1452fdc50a94SYusuke Goda 1453aa0787a9SGuennadi Liakhovetski platform_set_drvdata(pdev, NULL); 1454aa0787a9SGuennadi Liakhovetski 1455fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1456faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1457b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 1458faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1459fdc50a94SYusuke Goda 1460fdc50a94SYusuke Goda return 0; 1461fdc50a94SYusuke Goda } 1462fdc50a94SYusuke Goda 1463faca6648SGuennadi Liakhovetski #ifdef CONFIG_PM 1464faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1465faca6648SGuennadi Liakhovetski { 1466b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1467faca6648SGuennadi Liakhovetski int ret = mmc_suspend_host(host->mmc); 1468faca6648SGuennadi Liakhovetski 1469b289174fSGuennadi Liakhovetski if (!ret) 1470faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1471faca6648SGuennadi Liakhovetski 1472faca6648SGuennadi Liakhovetski return ret; 1473faca6648SGuennadi Liakhovetski } 1474faca6648SGuennadi Liakhovetski 1475faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1476faca6648SGuennadi Liakhovetski { 1477b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1478faca6648SGuennadi Liakhovetski 1479faca6648SGuennadi Liakhovetski return mmc_resume_host(host->mmc); 1480faca6648SGuennadi Liakhovetski } 1481faca6648SGuennadi Liakhovetski #else 1482faca6648SGuennadi Liakhovetski #define sh_mmcif_suspend NULL 1483faca6648SGuennadi Liakhovetski #define sh_mmcif_resume NULL 1484faca6648SGuennadi Liakhovetski #endif /* CONFIG_PM */ 1485faca6648SGuennadi Liakhovetski 1486bf68a812SGuennadi Liakhovetski static const struct of_device_id mmcif_of_match[] = { 1487bf68a812SGuennadi Liakhovetski { .compatible = "renesas,sh-mmcif" }, 1488bf68a812SGuennadi Liakhovetski { } 1489bf68a812SGuennadi Liakhovetski }; 1490bf68a812SGuennadi Liakhovetski MODULE_DEVICE_TABLE(of, mmcif_of_match); 1491bf68a812SGuennadi Liakhovetski 1492faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1493faca6648SGuennadi Liakhovetski .suspend = sh_mmcif_suspend, 1494faca6648SGuennadi Liakhovetski .resume = sh_mmcif_resume, 1495faca6648SGuennadi Liakhovetski }; 1496faca6648SGuennadi Liakhovetski 1497fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1498fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1499fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1500fdc50a94SYusuke Goda .driver = { 1501fdc50a94SYusuke Goda .name = DRIVER_NAME, 1502faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1503bf68a812SGuennadi Liakhovetski .owner = THIS_MODULE, 1504bf68a812SGuennadi Liakhovetski .of_match_table = mmcif_of_match, 1505fdc50a94SYusuke Goda }, 1506fdc50a94SYusuke Goda }; 1507fdc50a94SYusuke Goda 1508d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1509fdc50a94SYusuke Goda 1510fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1511fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1512aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1513fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1514