1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 1986df1745SGuennadi Liakhovetski #include <linux/bitops.h> 20aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 21aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 22e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 23fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 24a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 25fdc50a94SYusuke Goda #include <linux/mmc/card.h> 26fdc50a94SYusuke Goda #include <linux/mmc/core.h> 27e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 28fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 29fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 30fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 31a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 32e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 33faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 343b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 3588b47679SPaul Gortmaker #include <linux/module.h> 36fdc50a94SYusuke Goda 37fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 38fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 39fdc50a94SYusuke Goda 40fdc50a94SYusuke Goda /* CE_CMD_SET */ 41fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 42fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 43fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 44fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 45fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 46fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 47fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 48fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 49fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 50fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 51fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 52fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 53fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 54fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 55fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 56fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 57fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 58fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 59fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 60fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 61fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 62fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 63fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 64fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 65fdc50a94SYusuke Goda 66fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 67fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 68fdc50a94SYusuke Goda 69fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 70fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 71fdc50a94SYusuke Goda 72fdc50a94SYusuke Goda /* CE_INT */ 73fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 74fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 75fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 76fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 77fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 78fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 79fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 80fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 81fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 82fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 83fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 84fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 85fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 86fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 87fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 88fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 89fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 90fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 91fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 92fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 93fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 94fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 95fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 96fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 97fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 98fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 99fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 100fdc50a94SYusuke Goda 101fdc50a94SYusuke Goda /* CE_INT_MASK */ 102fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 103fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 104fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 105fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 106fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 107fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 108fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 109fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 110fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 111fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 112fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 113fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 114fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 115fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 116fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 117fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 118fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 119fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 120fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 121fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 122fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 123fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 124fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 125fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 126fdc50a94SYusuke Goda 127fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 128fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 129fdc50a94SYusuke Goda 130fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 131fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 132fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 133fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 134fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 135fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 136fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 137fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 138fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 139fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 140fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 141fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 142fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 143fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 144fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 145fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 146fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 147fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 148fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 149fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 150fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 151fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 152fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 153fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 154fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 155fdc50a94SYusuke Goda 156fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 157fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 158fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 159fdc50a94SYusuke Goda 1603b0beafcSGuennadi Liakhovetski enum mmcif_state { 1613b0beafcSGuennadi Liakhovetski STATE_IDLE, 1623b0beafcSGuennadi Liakhovetski STATE_REQUEST, 1633b0beafcSGuennadi Liakhovetski STATE_IOS, 1643b0beafcSGuennadi Liakhovetski }; 1653b0beafcSGuennadi Liakhovetski 166fdc50a94SYusuke Goda struct sh_mmcif_host { 167fdc50a94SYusuke Goda struct mmc_host *mmc; 168fdc50a94SYusuke Goda struct mmc_data *data; 169fdc50a94SYusuke Goda struct platform_device *pd; 170714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave dma_slave_tx; 171714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave dma_slave_rx; 172fdc50a94SYusuke Goda struct clk *hclk; 173fdc50a94SYusuke Goda unsigned int clk; 174fdc50a94SYusuke Goda int bus_width; 175aa0787a9SGuennadi Liakhovetski bool sd_error; 176fdc50a94SYusuke Goda long timeout; 177fdc50a94SYusuke Goda void __iomem *addr; 178aa0787a9SGuennadi Liakhovetski struct completion intr_wait; 1793b0beafcSGuennadi Liakhovetski enum mmcif_state state; 1803b0beafcSGuennadi Liakhovetski spinlock_t lock; 181faca6648SGuennadi Liakhovetski bool power; 182c9b0cef2SGuennadi Liakhovetski bool card_present; 183fdc50a94SYusuke Goda 184a782d688SGuennadi Liakhovetski /* DMA support */ 185a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 186a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 187a782d688SGuennadi Liakhovetski struct completion dma_complete; 188f38f94c6SLinus Walleij bool dma_active; 189a782d688SGuennadi Liakhovetski }; 190fdc50a94SYusuke Goda 191fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 192fdc50a94SYusuke Goda unsigned int reg, u32 val) 193fdc50a94SYusuke Goda { 194487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 195fdc50a94SYusuke Goda } 196fdc50a94SYusuke Goda 197fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 198fdc50a94SYusuke Goda unsigned int reg, u32 val) 199fdc50a94SYusuke Goda { 200487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 201fdc50a94SYusuke Goda } 202fdc50a94SYusuke Goda 203a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 204a782d688SGuennadi Liakhovetski { 205a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 206a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 207a782d688SGuennadi Liakhovetski 208a782d688SGuennadi Liakhovetski if (WARN(!host->data, "%s: NULL data in DMA completion!\n", 209a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 210a782d688SGuennadi Liakhovetski return; 211a782d688SGuennadi Liakhovetski 212a782d688SGuennadi Liakhovetski if (host->data->flags & MMC_DATA_READ) 2131ed828dbSLinus Walleij dma_unmap_sg(host->chan_rx->device->dev, 2149dc3fb5eSLinus Walleij host->data->sg, host->data->sg_len, 215a782d688SGuennadi Liakhovetski DMA_FROM_DEVICE); 216a782d688SGuennadi Liakhovetski else 2171ed828dbSLinus Walleij dma_unmap_sg(host->chan_tx->device->dev, 2189dc3fb5eSLinus Walleij host->data->sg, host->data->sg_len, 219a782d688SGuennadi Liakhovetski DMA_TO_DEVICE); 220a782d688SGuennadi Liakhovetski 221a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 222a782d688SGuennadi Liakhovetski } 223a782d688SGuennadi Liakhovetski 224a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 225a782d688SGuennadi Liakhovetski { 226a782d688SGuennadi Liakhovetski struct scatterlist *sg = host->data->sg; 227a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 228a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 229a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 230a782d688SGuennadi Liakhovetski int ret; 231a782d688SGuennadi Liakhovetski 2321ed828dbSLinus Walleij ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len, 2331ed828dbSLinus Walleij DMA_FROM_DEVICE); 234a782d688SGuennadi Liakhovetski if (ret > 0) { 235f38f94c6SLinus Walleij host->dma_active = true; 236a782d688SGuennadi Liakhovetski desc = chan->device->device_prep_slave_sg(chan, sg, ret, 237a782d688SGuennadi Liakhovetski DMA_FROM_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 238a782d688SGuennadi Liakhovetski } 239a782d688SGuennadi Liakhovetski 240a782d688SGuennadi Liakhovetski if (desc) { 241a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 242a782d688SGuennadi Liakhovetski desc->callback_param = host; 243a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 244a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 245a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 246a782d688SGuennadi Liakhovetski } 247a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 248a782d688SGuennadi Liakhovetski __func__, host->data->sg_len, ret, cookie); 249a782d688SGuennadi Liakhovetski 250a782d688SGuennadi Liakhovetski if (!desc) { 251a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 252a782d688SGuennadi Liakhovetski if (ret >= 0) 253a782d688SGuennadi Liakhovetski ret = -EIO; 254a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 255f38f94c6SLinus Walleij host->dma_active = false; 256a782d688SGuennadi Liakhovetski dma_release_channel(chan); 257a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 258a782d688SGuennadi Liakhovetski chan = host->chan_tx; 259a782d688SGuennadi Liakhovetski if (chan) { 260a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 261a782d688SGuennadi Liakhovetski dma_release_channel(chan); 262a782d688SGuennadi Liakhovetski } 263a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 264a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 265a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 266a782d688SGuennadi Liakhovetski } 267a782d688SGuennadi Liakhovetski 268a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 269a782d688SGuennadi Liakhovetski desc, cookie, host->data->sg_len); 270a782d688SGuennadi Liakhovetski } 271a782d688SGuennadi Liakhovetski 272a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 273a782d688SGuennadi Liakhovetski { 274a782d688SGuennadi Liakhovetski struct scatterlist *sg = host->data->sg; 275a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 276a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 277a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 278a782d688SGuennadi Liakhovetski int ret; 279a782d688SGuennadi Liakhovetski 2801ed828dbSLinus Walleij ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len, 2811ed828dbSLinus Walleij DMA_TO_DEVICE); 282a782d688SGuennadi Liakhovetski if (ret > 0) { 283f38f94c6SLinus Walleij host->dma_active = true; 284a782d688SGuennadi Liakhovetski desc = chan->device->device_prep_slave_sg(chan, sg, ret, 285a782d688SGuennadi Liakhovetski DMA_TO_DEVICE, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 286a782d688SGuennadi Liakhovetski } 287a782d688SGuennadi Liakhovetski 288a782d688SGuennadi Liakhovetski if (desc) { 289a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 290a782d688SGuennadi Liakhovetski desc->callback_param = host; 291a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 292a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 293a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 294a782d688SGuennadi Liakhovetski } 295a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 296a782d688SGuennadi Liakhovetski __func__, host->data->sg_len, ret, cookie); 297a782d688SGuennadi Liakhovetski 298a782d688SGuennadi Liakhovetski if (!desc) { 299a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 300a782d688SGuennadi Liakhovetski if (ret >= 0) 301a782d688SGuennadi Liakhovetski ret = -EIO; 302a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 303f38f94c6SLinus Walleij host->dma_active = false; 304a782d688SGuennadi Liakhovetski dma_release_channel(chan); 305a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 306a782d688SGuennadi Liakhovetski chan = host->chan_rx; 307a782d688SGuennadi Liakhovetski if (chan) { 308a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 309a782d688SGuennadi Liakhovetski dma_release_channel(chan); 310a782d688SGuennadi Liakhovetski } 311a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 312a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 313a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 314a782d688SGuennadi Liakhovetski } 315a782d688SGuennadi Liakhovetski 316a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 317a782d688SGuennadi Liakhovetski desc, cookie); 318a782d688SGuennadi Liakhovetski } 319a782d688SGuennadi Liakhovetski 320a782d688SGuennadi Liakhovetski static bool sh_mmcif_filter(struct dma_chan *chan, void *arg) 321a782d688SGuennadi Liakhovetski { 322a782d688SGuennadi Liakhovetski dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); 323a782d688SGuennadi Liakhovetski chan->private = arg; 324a782d688SGuennadi Liakhovetski return true; 325a782d688SGuennadi Liakhovetski } 326a782d688SGuennadi Liakhovetski 327a782d688SGuennadi Liakhovetski static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 328a782d688SGuennadi Liakhovetski struct sh_mmcif_plat_data *pdata) 329a782d688SGuennadi Liakhovetski { 330714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave *tx, *rx; 331f38f94c6SLinus Walleij host->dma_active = false; 332a782d688SGuennadi Liakhovetski 333a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 334a782d688SGuennadi Liakhovetski if (pdata->dma) { 335714c4a6eSGuennadi Liakhovetski dev_warn(&host->pd->dev, 336714c4a6eSGuennadi Liakhovetski "Update your platform to use embedded DMA slave IDs\n"); 337714c4a6eSGuennadi Liakhovetski tx = &pdata->dma->chan_priv_tx; 338714c4a6eSGuennadi Liakhovetski rx = &pdata->dma->chan_priv_rx; 339714c4a6eSGuennadi Liakhovetski } else { 340714c4a6eSGuennadi Liakhovetski tx = &host->dma_slave_tx; 341714c4a6eSGuennadi Liakhovetski tx->slave_id = pdata->slave_id_tx; 342714c4a6eSGuennadi Liakhovetski rx = &host->dma_slave_rx; 343714c4a6eSGuennadi Liakhovetski rx->slave_id = pdata->slave_id_rx; 344714c4a6eSGuennadi Liakhovetski } 345714c4a6eSGuennadi Liakhovetski if (tx->slave_id > 0 && rx->slave_id > 0) { 346a782d688SGuennadi Liakhovetski dma_cap_mask_t mask; 347a782d688SGuennadi Liakhovetski 348a782d688SGuennadi Liakhovetski dma_cap_zero(mask); 349a782d688SGuennadi Liakhovetski dma_cap_set(DMA_SLAVE, mask); 350a782d688SGuennadi Liakhovetski 351714c4a6eSGuennadi Liakhovetski host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx); 352a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 353a782d688SGuennadi Liakhovetski host->chan_tx); 354a782d688SGuennadi Liakhovetski 355a782d688SGuennadi Liakhovetski if (!host->chan_tx) 356a782d688SGuennadi Liakhovetski return; 357a782d688SGuennadi Liakhovetski 358714c4a6eSGuennadi Liakhovetski host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx); 359a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 360a782d688SGuennadi Liakhovetski host->chan_rx); 361a782d688SGuennadi Liakhovetski 362a782d688SGuennadi Liakhovetski if (!host->chan_rx) { 363a782d688SGuennadi Liakhovetski dma_release_channel(host->chan_tx); 364a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 365a782d688SGuennadi Liakhovetski return; 366a782d688SGuennadi Liakhovetski } 367a782d688SGuennadi Liakhovetski 368a782d688SGuennadi Liakhovetski init_completion(&host->dma_complete); 369a782d688SGuennadi Liakhovetski } 370a782d688SGuennadi Liakhovetski } 371a782d688SGuennadi Liakhovetski 372a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 373a782d688SGuennadi Liakhovetski { 374a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 375a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 376a782d688SGuennadi Liakhovetski if (host->chan_tx) { 377a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 378a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 379a782d688SGuennadi Liakhovetski dma_release_channel(chan); 380a782d688SGuennadi Liakhovetski } 381a782d688SGuennadi Liakhovetski if (host->chan_rx) { 382a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 383a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 384a782d688SGuennadi Liakhovetski dma_release_channel(chan); 385a782d688SGuennadi Liakhovetski } 386a782d688SGuennadi Liakhovetski 387f38f94c6SLinus Walleij host->dma_active = false; 388a782d688SGuennadi Liakhovetski } 389fdc50a94SYusuke Goda 390fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 391fdc50a94SYusuke Goda { 392fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 393fdc50a94SYusuke Goda 394fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 395fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 396fdc50a94SYusuke Goda 397fdc50a94SYusuke Goda if (!clk) 398fdc50a94SYusuke Goda return; 399fdc50a94SYusuke Goda if (p->sup_pclk && clk == host->clk) 400fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 401fdc50a94SYusuke Goda else 402fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 40386df1745SGuennadi Liakhovetski ((fls(host->clk / clk) - 1) << 16)); 404fdc50a94SYusuke Goda 405fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 406fdc50a94SYusuke Goda } 407fdc50a94SYusuke Goda 408fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 409fdc50a94SYusuke Goda { 410fdc50a94SYusuke Goda u32 tmp; 411fdc50a94SYusuke Goda 412487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 413fdc50a94SYusuke Goda 414487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 415487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 416fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 417fdc50a94SYusuke Goda SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 418fdc50a94SYusuke Goda /* byte swap on */ 419fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 420fdc50a94SYusuke Goda } 421fdc50a94SYusuke Goda 422fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 423fdc50a94SYusuke Goda { 424fdc50a94SYusuke Goda u32 state1, state2; 425fdc50a94SYusuke Goda int ret, timeout = 10000000; 426fdc50a94SYusuke Goda 427aa0787a9SGuennadi Liakhovetski host->sd_error = false; 428fdc50a94SYusuke Goda 429487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 430487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 431e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 432e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 433fdc50a94SYusuke Goda 434fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 435fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 436fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 437fdc50a94SYusuke Goda while (1) { 438fdc50a94SYusuke Goda timeout--; 439fdc50a94SYusuke Goda if (timeout < 0) { 440e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, 441e47bf32aSGuennadi Liakhovetski "Forceed end of command sequence timeout err\n"); 442fdc50a94SYusuke Goda return -EIO; 443fdc50a94SYusuke Goda } 444487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 445fdc50a94SYusuke Goda & STS1_CMDSEQ)) 446fdc50a94SYusuke Goda break; 447fdc50a94SYusuke Goda mdelay(1); 448fdc50a94SYusuke Goda } 449fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 450e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 451fdc50a94SYusuke Goda return -EIO; 452fdc50a94SYusuke Goda } 453fdc50a94SYusuke Goda 454fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 455e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Happened CRC error\n"); 456fdc50a94SYusuke Goda ret = -EIO; 457fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 458e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Happened Timeout error\n"); 459fdc50a94SYusuke Goda ret = -ETIMEDOUT; 460fdc50a94SYusuke Goda } else { 461e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Happened End/Index error\n"); 462fdc50a94SYusuke Goda ret = -EIO; 463fdc50a94SYusuke Goda } 464fdc50a94SYusuke Goda return ret; 465fdc50a94SYusuke Goda } 466fdc50a94SYusuke Goda 467fdc50a94SYusuke Goda static int sh_mmcif_single_read(struct sh_mmcif_host *host, 468fdc50a94SYusuke Goda struct mmc_request *mrq) 469fdc50a94SYusuke Goda { 470fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 471fdc50a94SYusuke Goda long time; 472fdc50a94SYusuke Goda u32 blocksize, i, *p = sg_virt(data->sg); 473fdc50a94SYusuke Goda 474fdc50a94SYusuke Goda /* buf read enable */ 475fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 476aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 477aa0787a9SGuennadi Liakhovetski host->timeout); 478aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 479fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 480fdc50a94SYusuke Goda 481fdc50a94SYusuke Goda blocksize = (BLOCK_SIZE_MASK & 482487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; 483fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 484487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 485fdc50a94SYusuke Goda 486fdc50a94SYusuke Goda /* buffer read end */ 487fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 488aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 489aa0787a9SGuennadi Liakhovetski host->timeout); 490aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 491fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 492fdc50a94SYusuke Goda 493fdc50a94SYusuke Goda return 0; 494fdc50a94SYusuke Goda } 495fdc50a94SYusuke Goda 496fdc50a94SYusuke Goda static int sh_mmcif_multi_read(struct sh_mmcif_host *host, 497fdc50a94SYusuke Goda struct mmc_request *mrq) 498fdc50a94SYusuke Goda { 499fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 500fdc50a94SYusuke Goda long time; 501fdc50a94SYusuke Goda u32 blocksize, i, j, sec, *p; 502fdc50a94SYusuke Goda 503487d9fc5SMagnus Damm blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, 504487d9fc5SMagnus Damm MMCIF_CE_BLOCK_SET); 505fdc50a94SYusuke Goda for (j = 0; j < data->sg_len; j++) { 506fdc50a94SYusuke Goda p = sg_virt(data->sg); 507fdc50a94SYusuke Goda for (sec = 0; sec < data->sg->length / blocksize; sec++) { 508fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 509fdc50a94SYusuke Goda /* buf read enable */ 510aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 511aa0787a9SGuennadi Liakhovetski host->timeout); 512fdc50a94SYusuke Goda 513aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 514fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 515fdc50a94SYusuke Goda 516fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 517487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, 518487d9fc5SMagnus Damm MMCIF_CE_DATA); 519fdc50a94SYusuke Goda } 520fdc50a94SYusuke Goda if (j < data->sg_len - 1) 521fdc50a94SYusuke Goda data->sg++; 522fdc50a94SYusuke Goda } 523fdc50a94SYusuke Goda return 0; 524fdc50a94SYusuke Goda } 525fdc50a94SYusuke Goda 526fdc50a94SYusuke Goda static int sh_mmcif_single_write(struct sh_mmcif_host *host, 527fdc50a94SYusuke Goda struct mmc_request *mrq) 528fdc50a94SYusuke Goda { 529fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 530fdc50a94SYusuke Goda long time; 531fdc50a94SYusuke Goda u32 blocksize, i, *p = sg_virt(data->sg); 532fdc50a94SYusuke Goda 533fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 534fdc50a94SYusuke Goda 535fdc50a94SYusuke Goda /* buf write enable */ 536aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 537aa0787a9SGuennadi Liakhovetski host->timeout); 538aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 539fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 540fdc50a94SYusuke Goda 541fdc50a94SYusuke Goda blocksize = (BLOCK_SIZE_MASK & 542487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; 543fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 544487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 545fdc50a94SYusuke Goda 546fdc50a94SYusuke Goda /* buffer write end */ 547fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 548fdc50a94SYusuke Goda 549aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 550aa0787a9SGuennadi Liakhovetski host->timeout); 551aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 552fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 553fdc50a94SYusuke Goda 554fdc50a94SYusuke Goda return 0; 555fdc50a94SYusuke Goda } 556fdc50a94SYusuke Goda 557fdc50a94SYusuke Goda static int sh_mmcif_multi_write(struct sh_mmcif_host *host, 558fdc50a94SYusuke Goda struct mmc_request *mrq) 559fdc50a94SYusuke Goda { 560fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 561fdc50a94SYusuke Goda long time; 562fdc50a94SYusuke Goda u32 i, sec, j, blocksize, *p; 563fdc50a94SYusuke Goda 564487d9fc5SMagnus Damm blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, 565487d9fc5SMagnus Damm MMCIF_CE_BLOCK_SET); 566fdc50a94SYusuke Goda 567fdc50a94SYusuke Goda for (j = 0; j < data->sg_len; j++) { 568fdc50a94SYusuke Goda p = sg_virt(data->sg); 569fdc50a94SYusuke Goda for (sec = 0; sec < data->sg->length / blocksize; sec++) { 570fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 571fdc50a94SYusuke Goda /* buf write enable*/ 572aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 573aa0787a9SGuennadi Liakhovetski host->timeout); 574fdc50a94SYusuke Goda 575aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 576fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 577fdc50a94SYusuke Goda 578fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 579487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, 580487d9fc5SMagnus Damm MMCIF_CE_DATA, *p++); 581fdc50a94SYusuke Goda } 582fdc50a94SYusuke Goda if (j < data->sg_len - 1) 583fdc50a94SYusuke Goda data->sg++; 584fdc50a94SYusuke Goda } 585fdc50a94SYusuke Goda return 0; 586fdc50a94SYusuke Goda } 587fdc50a94SYusuke Goda 588fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 589fdc50a94SYusuke Goda struct mmc_command *cmd) 590fdc50a94SYusuke Goda { 591fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 592487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 593487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 594487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 595487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 596fdc50a94SYusuke Goda } else 597487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 598fdc50a94SYusuke Goda } 599fdc50a94SYusuke Goda 600fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 601fdc50a94SYusuke Goda struct mmc_command *cmd) 602fdc50a94SYusuke Goda { 603487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 604fdc50a94SYusuke Goda } 605fdc50a94SYusuke Goda 606fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 607fdc50a94SYusuke Goda struct mmc_request *mrq, struct mmc_command *cmd, u32 opc) 608fdc50a94SYusuke Goda { 609fdc50a94SYusuke Goda u32 tmp = 0; 610fdc50a94SYusuke Goda 611fdc50a94SYusuke Goda /* Response Type check */ 612fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 613fdc50a94SYusuke Goda case MMC_RSP_NONE: 614fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 615fdc50a94SYusuke Goda break; 616fdc50a94SYusuke Goda case MMC_RSP_R1: 617fdc50a94SYusuke Goda case MMC_RSP_R1B: 618fdc50a94SYusuke Goda case MMC_RSP_R3: 619fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 620fdc50a94SYusuke Goda break; 621fdc50a94SYusuke Goda case MMC_RSP_R2: 622fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 623fdc50a94SYusuke Goda break; 624fdc50a94SYusuke Goda default: 625e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 626fdc50a94SYusuke Goda break; 627fdc50a94SYusuke Goda } 628fdc50a94SYusuke Goda switch (opc) { 629fdc50a94SYusuke Goda /* RBSY */ 630fdc50a94SYusuke Goda case MMC_SWITCH: 631fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 632fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 633fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 634fdc50a94SYusuke Goda case MMC_ERASE: 635fdc50a94SYusuke Goda case MMC_GEN_CMD: 636fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 637fdc50a94SYusuke Goda break; 638fdc50a94SYusuke Goda } 639fdc50a94SYusuke Goda /* WDAT / DATW */ 640fdc50a94SYusuke Goda if (host->data) { 641fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 642fdc50a94SYusuke Goda switch (host->bus_width) { 643fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 644fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 645fdc50a94SYusuke Goda break; 646fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 647fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 648fdc50a94SYusuke Goda break; 649fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 650fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 651fdc50a94SYusuke Goda break; 652fdc50a94SYusuke Goda default: 653e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 654fdc50a94SYusuke Goda break; 655fdc50a94SYusuke Goda } 656fdc50a94SYusuke Goda } 657fdc50a94SYusuke Goda /* DWEN */ 658fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 659fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 660fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 661fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 662fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 663fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 664fdc50a94SYusuke Goda mrq->data->blocks << 16); 665fdc50a94SYusuke Goda } 666fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 667fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 668fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 669fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 670fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 671fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 672fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 673fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 674fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 675fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 676fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 677fdc50a94SYusuke Goda 678fdc50a94SYusuke Goda return opc = ((opc << 24) | tmp); 679fdc50a94SYusuke Goda } 680fdc50a94SYusuke Goda 681e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 682fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 683fdc50a94SYusuke Goda { 684e47bf32aSGuennadi Liakhovetski int ret; 685fdc50a94SYusuke Goda 686fdc50a94SYusuke Goda switch (opc) { 687fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 688fdc50a94SYusuke Goda ret = sh_mmcif_multi_read(host, mrq); 689fdc50a94SYusuke Goda break; 690fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 691fdc50a94SYusuke Goda ret = sh_mmcif_multi_write(host, mrq); 692fdc50a94SYusuke Goda break; 693fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 694fdc50a94SYusuke Goda ret = sh_mmcif_single_write(host, mrq); 695fdc50a94SYusuke Goda break; 696fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 697fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 698fdc50a94SYusuke Goda ret = sh_mmcif_single_read(host, mrq); 699fdc50a94SYusuke Goda break; 700fdc50a94SYusuke Goda default: 701e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 702fdc50a94SYusuke Goda ret = -EINVAL; 703fdc50a94SYusuke Goda break; 704fdc50a94SYusuke Goda } 705fdc50a94SYusuke Goda return ret; 706fdc50a94SYusuke Goda } 707fdc50a94SYusuke Goda 708fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 709fdc50a94SYusuke Goda struct mmc_request *mrq, struct mmc_command *cmd) 710fdc50a94SYusuke Goda { 711fdc50a94SYusuke Goda long time; 712fdc50a94SYusuke Goda int ret = 0, mask = 0; 713fdc50a94SYusuke Goda u32 opc = cmd->opcode; 714fdc50a94SYusuke Goda 715fdc50a94SYusuke Goda switch (opc) { 716fdc50a94SYusuke Goda /* respons busy check */ 717fdc50a94SYusuke Goda case MMC_SWITCH: 718fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 719fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 720fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 721fdc50a94SYusuke Goda case MMC_ERASE: 722fdc50a94SYusuke Goda case MMC_GEN_CMD: 723fdc50a94SYusuke Goda mask = MASK_MRBSYE; 724fdc50a94SYusuke Goda break; 725fdc50a94SYusuke Goda default: 726fdc50a94SYusuke Goda mask = MASK_MCRSPE; 727fdc50a94SYusuke Goda break; 728fdc50a94SYusuke Goda } 729fdc50a94SYusuke Goda mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | 730fdc50a94SYusuke Goda MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | 731fdc50a94SYusuke Goda MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | 732fdc50a94SYusuke Goda MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; 733fdc50a94SYusuke Goda 734fdc50a94SYusuke Goda if (host->data) { 735487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 736487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 737487d9fc5SMagnus Damm mrq->data->blksz); 738fdc50a94SYusuke Goda } 739fdc50a94SYusuke Goda opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); 740fdc50a94SYusuke Goda 741487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 742487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 743fdc50a94SYusuke Goda /* set arg */ 744487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 745fdc50a94SYusuke Goda /* set cmd */ 746487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 747fdc50a94SYusuke Goda 748aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 749aa0787a9SGuennadi Liakhovetski host->timeout); 750aa0787a9SGuennadi Liakhovetski if (time <= 0) { 751fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 752fdc50a94SYusuke Goda return; 753fdc50a94SYusuke Goda } 754fdc50a94SYusuke Goda if (host->sd_error) { 755fdc50a94SYusuke Goda switch (cmd->opcode) { 756fdc50a94SYusuke Goda case MMC_ALL_SEND_CID: 757fdc50a94SYusuke Goda case MMC_SELECT_CARD: 758fdc50a94SYusuke Goda case MMC_APP_CMD: 759fdc50a94SYusuke Goda cmd->error = -ETIMEDOUT; 760fdc50a94SYusuke Goda break; 761fdc50a94SYusuke Goda default: 762e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n", 763e47bf32aSGuennadi Liakhovetski cmd->opcode); 764fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 765fdc50a94SYusuke Goda break; 766fdc50a94SYusuke Goda } 767aa0787a9SGuennadi Liakhovetski host->sd_error = false; 768fdc50a94SYusuke Goda return; 769fdc50a94SYusuke Goda } 770fdc50a94SYusuke Goda if (!(cmd->flags & MMC_RSP_PRESENT)) { 771e47bf32aSGuennadi Liakhovetski cmd->error = 0; 772fdc50a94SYusuke Goda return; 773fdc50a94SYusuke Goda } 774fdc50a94SYusuke Goda sh_mmcif_get_response(host, cmd); 775fdc50a94SYusuke Goda if (host->data) { 776f38f94c6SLinus Walleij if (!host->dma_active) { 777fdc50a94SYusuke Goda ret = sh_mmcif_data_trans(host, mrq, cmd->opcode); 778a782d688SGuennadi Liakhovetski } else { 779a782d688SGuennadi Liakhovetski long time = 780a782d688SGuennadi Liakhovetski wait_for_completion_interruptible_timeout(&host->dma_complete, 781a782d688SGuennadi Liakhovetski host->timeout); 782a782d688SGuennadi Liakhovetski if (!time) 783a782d688SGuennadi Liakhovetski ret = -ETIMEDOUT; 784a782d688SGuennadi Liakhovetski else if (time < 0) 785a782d688SGuennadi Liakhovetski ret = time; 786a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 787a782d688SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 788f38f94c6SLinus Walleij host->dma_active = false; 789a782d688SGuennadi Liakhovetski } 790fdc50a94SYusuke Goda if (ret < 0) 791fdc50a94SYusuke Goda mrq->data->bytes_xfered = 0; 792fdc50a94SYusuke Goda else 793fdc50a94SYusuke Goda mrq->data->bytes_xfered = 794fdc50a94SYusuke Goda mrq->data->blocks * mrq->data->blksz; 795fdc50a94SYusuke Goda } 796fdc50a94SYusuke Goda cmd->error = ret; 797fdc50a94SYusuke Goda } 798fdc50a94SYusuke Goda 799fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 800fdc50a94SYusuke Goda struct mmc_request *mrq, struct mmc_command *cmd) 801fdc50a94SYusuke Goda { 802fdc50a94SYusuke Goda long time; 803fdc50a94SYusuke Goda 804fdc50a94SYusuke Goda if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 805fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 806fdc50a94SYusuke Goda else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 807fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 808fdc50a94SYusuke Goda else { 809e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 810fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 811fdc50a94SYusuke Goda return; 812fdc50a94SYusuke Goda } 813fdc50a94SYusuke Goda 814aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 815aa0787a9SGuennadi Liakhovetski host->timeout); 816aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) { 817fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 818fdc50a94SYusuke Goda return; 819fdc50a94SYusuke Goda } 820fdc50a94SYusuke Goda sh_mmcif_get_cmd12response(host, cmd); 821fdc50a94SYusuke Goda cmd->error = 0; 822fdc50a94SYusuke Goda } 823fdc50a94SYusuke Goda 824fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 825fdc50a94SYusuke Goda { 826fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 8273b0beafcSGuennadi Liakhovetski unsigned long flags; 8283b0beafcSGuennadi Liakhovetski 8293b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8303b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8313b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 8323b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 8333b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 8343b0beafcSGuennadi Liakhovetski return; 8353b0beafcSGuennadi Liakhovetski } 8363b0beafcSGuennadi Liakhovetski 8373b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 8383b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 839fdc50a94SYusuke Goda 840fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 841fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 842fdc50a94SYusuke Goda case SD_IO_SEND_OP_COND: 843fdc50a94SYusuke Goda case MMC_APP_CMD: 8443b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 845fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 846fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 847fdc50a94SYusuke Goda return; 848fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 849fdc50a94SYusuke Goda if (!mrq->data) { 850fdc50a94SYusuke Goda /* send_if_cond cmd (not support) */ 8513b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 852fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 853fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 854fdc50a94SYusuke Goda return; 855fdc50a94SYusuke Goda } 856fdc50a94SYusuke Goda break; 857fdc50a94SYusuke Goda default: 858fdc50a94SYusuke Goda break; 859fdc50a94SYusuke Goda } 860fdc50a94SYusuke Goda host->data = mrq->data; 861a782d688SGuennadi Liakhovetski if (mrq->data) { 862a782d688SGuennadi Liakhovetski if (mrq->data->flags & MMC_DATA_READ) { 863a782d688SGuennadi Liakhovetski if (host->chan_rx) 864a782d688SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 865a782d688SGuennadi Liakhovetski } else { 866a782d688SGuennadi Liakhovetski if (host->chan_tx) 867a782d688SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 868a782d688SGuennadi Liakhovetski } 869a782d688SGuennadi Liakhovetski } 870fdc50a94SYusuke Goda sh_mmcif_start_cmd(host, mrq, mrq->cmd); 871fdc50a94SYusuke Goda host->data = NULL; 872fdc50a94SYusuke Goda 8733b0beafcSGuennadi Liakhovetski if (!mrq->cmd->error && mrq->stop) 874fdc50a94SYusuke Goda sh_mmcif_stop_cmd(host, mrq, mrq->stop); 8753b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 876fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 877fdc50a94SYusuke Goda } 878fdc50a94SYusuke Goda 879fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 880fdc50a94SYusuke Goda { 881fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 882fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 8833b0beafcSGuennadi Liakhovetski unsigned long flags; 8843b0beafcSGuennadi Liakhovetski 8853b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8863b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8873b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 8883b0beafcSGuennadi Liakhovetski return; 8893b0beafcSGuennadi Liakhovetski } 8903b0beafcSGuennadi Liakhovetski 8913b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 8923b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 893fdc50a94SYusuke Goda 894f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 895c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 896faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 897faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 898c9b0cef2SGuennadi Liakhovetski host->card_present = true; 899faca6648SGuennadi Liakhovetski } 900f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 901f5e0cec4SGuennadi Liakhovetski /* clock stop */ 902f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 903faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 904c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 905c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 906c9b0cef2SGuennadi Liakhovetski host->card_present = false; 907c9b0cef2SGuennadi Liakhovetski } 908c9b0cef2SGuennadi Liakhovetski } 909faca6648SGuennadi Liakhovetski if (host->power) { 910faca6648SGuennadi Liakhovetski pm_runtime_put(&host->pd->dev); 911faca6648SGuennadi Liakhovetski host->power = false; 912f6bc41fbSGuennadi Liakhovetski if (p->down_pwr && ios->power_mode == MMC_POWER_OFF) 913f5e0cec4SGuennadi Liakhovetski p->down_pwr(host->pd); 914faca6648SGuennadi Liakhovetski } 9153b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 916f5e0cec4SGuennadi Liakhovetski return; 917fdc50a94SYusuke Goda } 918fdc50a94SYusuke Goda 919c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 920c9b0cef2SGuennadi Liakhovetski if (!host->power) { 921c9b0cef2SGuennadi Liakhovetski if (p->set_pwr) 922c9b0cef2SGuennadi Liakhovetski p->set_pwr(host->pd, ios->power_mode); 923c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 924c9b0cef2SGuennadi Liakhovetski host->power = true; 925c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 926c9b0cef2SGuennadi Liakhovetski } 927fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 928c9b0cef2SGuennadi Liakhovetski } 929fdc50a94SYusuke Goda 930fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 9313b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 932fdc50a94SYusuke Goda } 933fdc50a94SYusuke Goda 934777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 935777271d0SArnd Hannemann { 936777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 937777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 938777271d0SArnd Hannemann 939777271d0SArnd Hannemann if (!p->get_cd) 940777271d0SArnd Hannemann return -ENOSYS; 941777271d0SArnd Hannemann else 942777271d0SArnd Hannemann return p->get_cd(host->pd); 943777271d0SArnd Hannemann } 944777271d0SArnd Hannemann 945fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 946fdc50a94SYusuke Goda .request = sh_mmcif_request, 947fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 948777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 949fdc50a94SYusuke Goda }; 950fdc50a94SYusuke Goda 951fdc50a94SYusuke Goda static void sh_mmcif_detect(struct mmc_host *mmc) 952fdc50a94SYusuke Goda { 953fdc50a94SYusuke Goda mmc_detect_change(mmc, 0); 954fdc50a94SYusuke Goda } 955fdc50a94SYusuke Goda 956fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 957fdc50a94SYusuke Goda { 958fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 959aa0787a9SGuennadi Liakhovetski u32 state; 960fdc50a94SYusuke Goda int err = 0; 961fdc50a94SYusuke Goda 962487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 963fdc50a94SYusuke Goda 964fdc50a94SYusuke Goda if (state & INT_RBSYE) { 965487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 966487d9fc5SMagnus Damm ~(INT_RBSYE | INT_CRSPE)); 967fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 968fdc50a94SYusuke Goda } else if (state & INT_CRSPE) { 969487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 970fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 971fdc50a94SYusuke Goda } else if (state & INT_BUFREN) { 972487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 973fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 974fdc50a94SYusuke Goda } else if (state & INT_BUFWEN) { 975487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 976fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 977fdc50a94SYusuke Goda } else if (state & INT_CMD12DRE) { 978487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 979fdc50a94SYusuke Goda ~(INT_CMD12DRE | INT_CMD12RBE | 980fdc50a94SYusuke Goda INT_CMD12CRE | INT_BUFRE)); 981fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 982fdc50a94SYusuke Goda } else if (state & INT_BUFRE) { 983487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 984fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 985fdc50a94SYusuke Goda } else if (state & INT_DTRANE) { 986487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); 987fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 988fdc50a94SYusuke Goda } else if (state & INT_CMD12RBE) { 989487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 990fdc50a94SYusuke Goda ~(INT_CMD12RBE | INT_CMD12CRE)); 991fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 992fdc50a94SYusuke Goda } else if (state & INT_ERR_STS) { 993fdc50a94SYusuke Goda /* err interrupts */ 994487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 995fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 996fdc50a94SYusuke Goda err = 1; 997fdc50a94SYusuke Goda } else { 998faca6648SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 999487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1000fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1001fdc50a94SYusuke Goda err = 1; 1002fdc50a94SYusuke Goda } 1003fdc50a94SYusuke Goda if (err) { 1004aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1005e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 1006fdc50a94SYusuke Goda } 1007aa0787a9SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) 1008aa0787a9SGuennadi Liakhovetski complete(&host->intr_wait); 1009aa0787a9SGuennadi Liakhovetski else 1010aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1011fdc50a94SYusuke Goda 1012fdc50a94SYusuke Goda return IRQ_HANDLED; 1013fdc50a94SYusuke Goda } 1014fdc50a94SYusuke Goda 1015fdc50a94SYusuke Goda static int __devinit sh_mmcif_probe(struct platform_device *pdev) 1016fdc50a94SYusuke Goda { 1017fdc50a94SYusuke Goda int ret = 0, irq[2]; 1018fdc50a94SYusuke Goda struct mmc_host *mmc; 1019e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1020e47bf32aSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd; 1021fdc50a94SYusuke Goda struct resource *res; 1022fdc50a94SYusuke Goda void __iomem *reg; 1023fdc50a94SYusuke Goda char clk_name[8]; 1024fdc50a94SYusuke Goda 1025fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1026fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1027fdc50a94SYusuke Goda if (irq[0] < 0 || irq[1] < 0) { 1028e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1029fdc50a94SYusuke Goda return -ENXIO; 1030fdc50a94SYusuke Goda } 1031fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1032fdc50a94SYusuke Goda if (!res) { 1033fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1034fdc50a94SYusuke Goda return -ENXIO; 1035fdc50a94SYusuke Goda } 1036fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1037fdc50a94SYusuke Goda if (!reg) { 1038fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1039fdc50a94SYusuke Goda return -ENOMEM; 1040fdc50a94SYusuke Goda } 1041e47bf32aSGuennadi Liakhovetski pd = pdev->dev.platform_data; 1042fdc50a94SYusuke Goda if (!pd) { 1043fdc50a94SYusuke Goda dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); 1044fdc50a94SYusuke Goda ret = -ENXIO; 1045fdc50a94SYusuke Goda goto clean_up; 1046fdc50a94SYusuke Goda } 1047fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1048fdc50a94SYusuke Goda if (!mmc) { 1049fdc50a94SYusuke Goda ret = -ENOMEM; 1050fdc50a94SYusuke Goda goto clean_up; 1051fdc50a94SYusuke Goda } 1052fdc50a94SYusuke Goda host = mmc_priv(mmc); 1053fdc50a94SYusuke Goda host->mmc = mmc; 1054fdc50a94SYusuke Goda host->addr = reg; 1055fdc50a94SYusuke Goda host->timeout = 1000; 1056fdc50a94SYusuke Goda 1057fdc50a94SYusuke Goda snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 1058fdc50a94SYusuke Goda host->hclk = clk_get(&pdev->dev, clk_name); 1059fdc50a94SYusuke Goda if (IS_ERR(host->hclk)) { 1060fdc50a94SYusuke Goda dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 1061fdc50a94SYusuke Goda ret = PTR_ERR(host->hclk); 1062fdc50a94SYusuke Goda goto clean_up1; 1063fdc50a94SYusuke Goda } 1064fdc50a94SYusuke Goda clk_enable(host->hclk); 1065fdc50a94SYusuke Goda host->clk = clk_get_rate(host->hclk); 1066fdc50a94SYusuke Goda host->pd = pdev; 1067fdc50a94SYusuke Goda 1068aa0787a9SGuennadi Liakhovetski init_completion(&host->intr_wait); 10693b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1070fdc50a94SYusuke Goda 1071fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 1072fdc50a94SYusuke Goda mmc->f_max = host->clk; 1073fdc50a94SYusuke Goda /* close to 400KHz */ 1074fdc50a94SYusuke Goda if (mmc->f_max < 51200000) 1075fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 128; 1076fdc50a94SYusuke Goda else if (mmc->f_max < 102400000) 1077fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 256; 1078fdc50a94SYusuke Goda else 1079fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 512; 1080fdc50a94SYusuke Goda if (pd->ocr) 1081fdc50a94SYusuke Goda mmc->ocr_avail = pd->ocr; 1082fdc50a94SYusuke Goda mmc->caps = MMC_CAP_MMC_HIGHSPEED; 1083fdc50a94SYusuke Goda if (pd->caps) 1084fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1085a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1086fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1087a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1088a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1089fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1090fdc50a94SYusuke Goda 1091fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 1092fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1093a782d688SGuennadi Liakhovetski 1094faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1095faca6648SGuennadi Liakhovetski host->power = false; 1096faca6648SGuennadi Liakhovetski 1097faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1098faca6648SGuennadi Liakhovetski if (ret < 0) 1099faca6648SGuennadi Liakhovetski goto clean_up2; 1100a782d688SGuennadi Liakhovetski 1101fdc50a94SYusuke Goda mmc_add_host(mmc); 1102fdc50a94SYusuke Goda 11033b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 11043b0beafcSGuennadi Liakhovetski 1105fdc50a94SYusuke Goda ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host); 1106fdc50a94SYusuke Goda if (ret) { 1107e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); 1108faca6648SGuennadi Liakhovetski goto clean_up3; 1109fdc50a94SYusuke Goda } 1110fdc50a94SYusuke Goda ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host); 1111fdc50a94SYusuke Goda if (ret) { 1112fdc50a94SYusuke Goda free_irq(irq[0], host); 1113e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1114faca6648SGuennadi Liakhovetski goto clean_up3; 1115fdc50a94SYusuke Goda } 1116fdc50a94SYusuke Goda 1117fdc50a94SYusuke Goda sh_mmcif_detect(host->mmc); 1118fdc50a94SYusuke Goda 1119e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1120e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1121487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1122fdc50a94SYusuke Goda return ret; 1123fdc50a94SYusuke Goda 1124faca6648SGuennadi Liakhovetski clean_up3: 1125faca6648SGuennadi Liakhovetski mmc_remove_host(mmc); 1126faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1127fdc50a94SYusuke Goda clean_up2: 1128faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1129fdc50a94SYusuke Goda clk_disable(host->hclk); 1130fdc50a94SYusuke Goda clean_up1: 1131fdc50a94SYusuke Goda mmc_free_host(mmc); 1132fdc50a94SYusuke Goda clean_up: 1133fdc50a94SYusuke Goda if (reg) 1134fdc50a94SYusuke Goda iounmap(reg); 1135fdc50a94SYusuke Goda return ret; 1136fdc50a94SYusuke Goda } 1137fdc50a94SYusuke Goda 1138fdc50a94SYusuke Goda static int __devexit sh_mmcif_remove(struct platform_device *pdev) 1139fdc50a94SYusuke Goda { 1140fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1141fdc50a94SYusuke Goda int irq[2]; 1142fdc50a94SYusuke Goda 1143faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1144aa0787a9SGuennadi Liakhovetski 1145faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 11463b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 11473b0beafcSGuennadi Liakhovetski 1148aa0787a9SGuennadi Liakhovetski if (host->addr) 1149aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1150aa0787a9SGuennadi Liakhovetski 1151fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1152fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1153fdc50a94SYusuke Goda 1154fdc50a94SYusuke Goda free_irq(irq[0], host); 1155fdc50a94SYusuke Goda free_irq(irq[1], host); 1156fdc50a94SYusuke Goda 1157aa0787a9SGuennadi Liakhovetski platform_set_drvdata(pdev, NULL); 1158aa0787a9SGuennadi Liakhovetski 1159fdc50a94SYusuke Goda clk_disable(host->hclk); 1160fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1161faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1162faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1163fdc50a94SYusuke Goda 1164fdc50a94SYusuke Goda return 0; 1165fdc50a94SYusuke Goda } 1166fdc50a94SYusuke Goda 1167faca6648SGuennadi Liakhovetski #ifdef CONFIG_PM 1168faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1169faca6648SGuennadi Liakhovetski { 1170faca6648SGuennadi Liakhovetski struct platform_device *pdev = to_platform_device(dev); 1171faca6648SGuennadi Liakhovetski struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1172faca6648SGuennadi Liakhovetski int ret = mmc_suspend_host(host->mmc); 1173faca6648SGuennadi Liakhovetski 1174faca6648SGuennadi Liakhovetski if (!ret) { 1175faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1176faca6648SGuennadi Liakhovetski clk_disable(host->hclk); 1177faca6648SGuennadi Liakhovetski } 1178faca6648SGuennadi Liakhovetski 1179faca6648SGuennadi Liakhovetski return ret; 1180faca6648SGuennadi Liakhovetski } 1181faca6648SGuennadi Liakhovetski 1182faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1183faca6648SGuennadi Liakhovetski { 1184faca6648SGuennadi Liakhovetski struct platform_device *pdev = to_platform_device(dev); 1185faca6648SGuennadi Liakhovetski struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1186faca6648SGuennadi Liakhovetski 1187faca6648SGuennadi Liakhovetski clk_enable(host->hclk); 1188faca6648SGuennadi Liakhovetski 1189faca6648SGuennadi Liakhovetski return mmc_resume_host(host->mmc); 1190faca6648SGuennadi Liakhovetski } 1191faca6648SGuennadi Liakhovetski #else 1192faca6648SGuennadi Liakhovetski #define sh_mmcif_suspend NULL 1193faca6648SGuennadi Liakhovetski #define sh_mmcif_resume NULL 1194faca6648SGuennadi Liakhovetski #endif /* CONFIG_PM */ 1195faca6648SGuennadi Liakhovetski 1196faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1197faca6648SGuennadi Liakhovetski .suspend = sh_mmcif_suspend, 1198faca6648SGuennadi Liakhovetski .resume = sh_mmcif_resume, 1199faca6648SGuennadi Liakhovetski }; 1200faca6648SGuennadi Liakhovetski 1201fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1202fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1203fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1204fdc50a94SYusuke Goda .driver = { 1205fdc50a94SYusuke Goda .name = DRIVER_NAME, 1206faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1207fdc50a94SYusuke Goda }, 1208fdc50a94SYusuke Goda }; 1209fdc50a94SYusuke Goda 1210d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1211fdc50a94SYusuke Goda 1212fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1213fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1214aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1215fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1216