1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0 2fdc50a94SYusuke Goda /* 3fdc50a94SYusuke Goda * MMCIF eMMC driver. 4fdc50a94SYusuke Goda * 5fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 6fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 7fdc50a94SYusuke Goda */ 8fdc50a94SYusuke Goda 9f985da17SGuennadi Liakhovetski /* 10f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 11f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 12f985da17SGuennadi Liakhovetski * 13f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 14f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 15f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 16f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 17f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 18f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 19f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 20f985da17SGuennadi Liakhovetski * 21f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 22f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 23f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 24f985da17SGuennadi Liakhovetski * 25f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 26f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 27f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 28f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 29f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 30f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 31f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 32f985da17SGuennadi Liakhovetski * bottom half waiting state. 33f985da17SGuennadi Liakhovetski */ 34f985da17SGuennadi Liakhovetski 3586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 36aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 37aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 38e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 39fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 40a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 41fdc50a94SYusuke Goda #include <linux/mmc/card.h> 42fdc50a94SYusuke Goda #include <linux/mmc/core.h> 43e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 44fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 45fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 46fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 47e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 48bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 498047310eSGuennadi Liakhovetski #include <linux/mutex.h> 5089d49a70SKuninori Morimoto #include <linux/of_device.h> 51a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 52e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 53efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 54faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 55d00cadacSGuennadi Liakhovetski #include <linux/sh_dma.h> 563b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 5788b47679SPaul Gortmaker #include <linux/module.h> 58fdc50a94SYusuke Goda 59fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 60fdc50a94SYusuke Goda 61fdc50a94SYusuke Goda /* CE_CMD_SET */ 62fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 63fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 64fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 65fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 66fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 67fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 68fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 69fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 70fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 71fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 72fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 73fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 74fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 75fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 76fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 77fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 78fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 79fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 80fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 81fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 82fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 83555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 84fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 85fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 86fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 87fdc50a94SYusuke Goda 88fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 89fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 90fdc50a94SYusuke Goda 91fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 92fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 93fdc50a94SYusuke Goda 94fdc50a94SYusuke Goda /* CE_INT */ 95fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 96fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 97fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 98fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 99fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 100fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 101fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 102fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 103fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 104fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 105fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 106fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 107fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 108fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 109fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 110fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 111fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 112fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 113fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 114fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 115fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 116fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 117fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 118fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 119fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 120fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 121fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 122fdc50a94SYusuke Goda 1238af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 1248af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 1258af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 1268af50750SGuennadi Liakhovetski 127967bcb77SGuennadi Liakhovetski #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 128967bcb77SGuennadi Liakhovetski 129fdc50a94SYusuke Goda /* CE_INT_MASK */ 130fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 131fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 132fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 133fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 134fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 135fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 136fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 137fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 138fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 139fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 140fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 141fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 142fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 143fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 144fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 145fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 146fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 147fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 148fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 149fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 150fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 151fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 152fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 153fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 154fdc50a94SYusuke Goda 155ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 156ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 157967bcb77SGuennadi Liakhovetski MASK_MCRCSTO | MASK_MWDATTO | \ 158ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 159ee4b8887SGuennadi Liakhovetski 1608af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 1618af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \ 1628af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 1638af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE) 1648af50750SGuennadi Liakhovetski 165fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 166fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 167fdc50a94SYusuke Goda 168fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 169fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 170fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 171fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 172fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 173fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 174fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 175fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 176fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 177fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 178fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 179fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 180fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 181fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 182fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 183fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 184fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 185fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 186fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 187fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 188fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 189fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 190fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 191fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 192fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 193fdc50a94SYusuke Goda 194fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52 MHz */ 195fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20 MHz */ 196b9a349fdSGeert Uytterhoeven #define CLKDEV_INIT 400000 /* 400 kHz */ 197fdc50a94SYusuke Goda 1981b1a694dSKuninori Morimoto enum sh_mmcif_state { 1993b0beafcSGuennadi Liakhovetski STATE_IDLE, 2003b0beafcSGuennadi Liakhovetski STATE_REQUEST, 2013b0beafcSGuennadi Liakhovetski STATE_IOS, 2028047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2033b0beafcSGuennadi Liakhovetski }; 2043b0beafcSGuennadi Liakhovetski 2051b1a694dSKuninori Morimoto enum sh_mmcif_wait_for { 206f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 207f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 208f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 209f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 210f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 211f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 212f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 213f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 214f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 215f985da17SGuennadi Liakhovetski }; 216f985da17SGuennadi Liakhovetski 21789d49a70SKuninori Morimoto /* 21889d49a70SKuninori Morimoto * difference for each SoC 21989d49a70SKuninori Morimoto */ 220fdc50a94SYusuke Goda struct sh_mmcif_host { 221fdc50a94SYusuke Goda struct mmc_host *mmc; 222f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 223fdc50a94SYusuke Goda struct platform_device *pd; 2246aed678bSKuninori Morimoto struct clk *clk; 225fdc50a94SYusuke Goda int bus_width; 226555061f9STeppei Kamijou unsigned char timing; 227aa0787a9SGuennadi Liakhovetski bool sd_error; 228f985da17SGuennadi Liakhovetski bool dying; 229fdc50a94SYusuke Goda long timeout; 230fdc50a94SYusuke Goda void __iomem *addr; 231f985da17SGuennadi Liakhovetski u32 *pio_ptr; 232ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2331b1a694dSKuninori Morimoto enum sh_mmcif_state state; 2341b1a694dSKuninori Morimoto enum sh_mmcif_wait_for wait_for; 235f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 236f985da17SGuennadi Liakhovetski size_t blocksize; 237f985da17SGuennadi Liakhovetski int sg_idx; 238f985da17SGuennadi Liakhovetski int sg_blkidx; 239faca6648SGuennadi Liakhovetski bool power; 240967bcb77SGuennadi Liakhovetski bool ccs_enable; /* Command Completion Signal support */ 2416d6fd367SGuennadi Liakhovetski bool clk_ctrl2_enable; 2428047310eSGuennadi Liakhovetski struct mutex thread_lock; 24389d49a70SKuninori Morimoto u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ 244fdc50a94SYusuke Goda 245a782d688SGuennadi Liakhovetski /* DMA support */ 246a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 247a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 248a782d688SGuennadi Liakhovetski struct completion dma_complete; 249f38f94c6SLinus Walleij bool dma_active; 250a782d688SGuennadi Liakhovetski }; 251fdc50a94SYusuke Goda 2521b1a694dSKuninori Morimoto static const struct of_device_id sh_mmcif_of_match[] = { 25370830b41SKuninori Morimoto { .compatible = "renesas,sh-mmcif" }, 25470830b41SKuninori Morimoto { } 25570830b41SKuninori Morimoto }; 2561b1a694dSKuninori Morimoto MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); 25770830b41SKuninori Morimoto 258585c3a5aSKuninori Morimoto #define sh_mmcif_host_to_dev(host) (&host->pd->dev) 259585c3a5aSKuninori Morimoto 260fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 261fdc50a94SYusuke Goda unsigned int reg, u32 val) 262fdc50a94SYusuke Goda { 263487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 264fdc50a94SYusuke Goda } 265fdc50a94SYusuke Goda 266fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 267fdc50a94SYusuke Goda unsigned int reg, u32 val) 268fdc50a94SYusuke Goda { 269487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 270fdc50a94SYusuke Goda } 271fdc50a94SYusuke Goda 2721b1a694dSKuninori Morimoto static void sh_mmcif_dma_complete(void *arg) 273a782d688SGuennadi Liakhovetski { 274a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2758047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 276585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 27769983404SGuennadi Liakhovetski 278585c3a5aSKuninori Morimoto dev_dbg(dev, "Command completed\n"); 279a782d688SGuennadi Liakhovetski 2808047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 281585c3a5aSKuninori Morimoto dev_name(dev))) 282a782d688SGuennadi Liakhovetski return; 283a782d688SGuennadi Liakhovetski 284a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 285a782d688SGuennadi Liakhovetski } 286a782d688SGuennadi Liakhovetski 287a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 288a782d688SGuennadi Liakhovetski { 28969983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 29069983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 291a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 292a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 293585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 294a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 295a782d688SGuennadi Liakhovetski int ret; 296a782d688SGuennadi Liakhovetski 29769983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 2981ed828dbSLinus Walleij DMA_FROM_DEVICE); 299a782d688SGuennadi Liakhovetski if (ret > 0) { 300f38f94c6SLinus Walleij host->dma_active = true; 30116052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 30205f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 303a782d688SGuennadi Liakhovetski } 304a782d688SGuennadi Liakhovetski 305a782d688SGuennadi Liakhovetski if (desc) { 3061b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete; 307a782d688SGuennadi Liakhovetski desc->callback_param = host; 308a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 309a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 310a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 311a782d688SGuennadi Liakhovetski } 312585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 31369983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 314a782d688SGuennadi Liakhovetski 315a782d688SGuennadi Liakhovetski if (!desc) { 316a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 317a782d688SGuennadi Liakhovetski if (ret >= 0) 318a782d688SGuennadi Liakhovetski ret = -EIO; 319a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 320f38f94c6SLinus Walleij host->dma_active = false; 321a782d688SGuennadi Liakhovetski dma_release_channel(chan); 322a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 323a782d688SGuennadi Liakhovetski chan = host->chan_tx; 324a782d688SGuennadi Liakhovetski if (chan) { 325a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 326a782d688SGuennadi Liakhovetski dma_release_channel(chan); 327a782d688SGuennadi Liakhovetski } 328585c3a5aSKuninori Morimoto dev_warn(dev, 329a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 330a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 331a782d688SGuennadi Liakhovetski } 332a782d688SGuennadi Liakhovetski 333585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 33469983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 335a782d688SGuennadi Liakhovetski } 336a782d688SGuennadi Liakhovetski 337a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 338a782d688SGuennadi Liakhovetski { 33969983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 34069983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 341a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 342a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 343585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 344a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 345a782d688SGuennadi Liakhovetski int ret; 346a782d688SGuennadi Liakhovetski 34769983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3481ed828dbSLinus Walleij DMA_TO_DEVICE); 349a782d688SGuennadi Liakhovetski if (ret > 0) { 350f38f94c6SLinus Walleij host->dma_active = true; 35116052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 35205f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 353a782d688SGuennadi Liakhovetski } 354a782d688SGuennadi Liakhovetski 355a782d688SGuennadi Liakhovetski if (desc) { 3561b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete; 357a782d688SGuennadi Liakhovetski desc->callback_param = host; 358a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 359a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 360a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 361a782d688SGuennadi Liakhovetski } 362585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 36369983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 364a782d688SGuennadi Liakhovetski 365a782d688SGuennadi Liakhovetski if (!desc) { 366a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 367a782d688SGuennadi Liakhovetski if (ret >= 0) 368a782d688SGuennadi Liakhovetski ret = -EIO; 369a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 370f38f94c6SLinus Walleij host->dma_active = false; 371a782d688SGuennadi Liakhovetski dma_release_channel(chan); 372a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 373a782d688SGuennadi Liakhovetski chan = host->chan_rx; 374a782d688SGuennadi Liakhovetski if (chan) { 375a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 376a782d688SGuennadi Liakhovetski dma_release_channel(chan); 377a782d688SGuennadi Liakhovetski } 378585c3a5aSKuninori Morimoto dev_warn(dev, 379a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 380a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 381a782d688SGuennadi Liakhovetski } 382a782d688SGuennadi Liakhovetski 383585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, 384a782d688SGuennadi Liakhovetski desc, cookie); 385a782d688SGuennadi Liakhovetski } 386a782d688SGuennadi Liakhovetski 387e5a233cbSLaurent Pinchart static struct dma_chan * 38827cbd7e8SArnd Bergmann sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) 389a782d688SGuennadi Liakhovetski { 3900e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 3910e79f9aeSGuennadi Liakhovetski 392e5a233cbSLaurent Pinchart dma_cap_zero(mask); 393e5a233cbSLaurent Pinchart dma_cap_set(DMA_SLAVE, mask); 39427cbd7e8SArnd Bergmann if (slave_id <= 0) 395e5a233cbSLaurent Pinchart return NULL; 396e5a233cbSLaurent Pinchart 39727cbd7e8SArnd Bergmann return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id); 39827cbd7e8SArnd Bergmann } 399e5a233cbSLaurent Pinchart 40027cbd7e8SArnd Bergmann static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, 40127cbd7e8SArnd Bergmann struct dma_chan *chan, 40227cbd7e8SArnd Bergmann enum dma_transfer_direction direction) 40327cbd7e8SArnd Bergmann { 40427cbd7e8SArnd Bergmann struct resource *res; 40527cbd7e8SArnd Bergmann struct dma_slave_config cfg = { 0, }; 40627cbd7e8SArnd Bergmann 40727cbd7e8SArnd Bergmann res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 408e5a233cbSLaurent Pinchart cfg.direction = direction; 409d25006e7SLaurent Pinchart 410e36152aaSLaurent Pinchart if (direction == DMA_DEV_TO_MEM) { 411d25006e7SLaurent Pinchart cfg.src_addr = res->start + MMCIF_CE_DATA; 412e36152aaSLaurent Pinchart cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 413e36152aaSLaurent Pinchart } else { 414e5a233cbSLaurent Pinchart cfg.dst_addr = res->start + MMCIF_CE_DATA; 415e36152aaSLaurent Pinchart cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 416e36152aaSLaurent Pinchart } 417d25006e7SLaurent Pinchart 41827cbd7e8SArnd Bergmann return dmaengine_slave_config(chan, &cfg); 419e5a233cbSLaurent Pinchart } 420e5a233cbSLaurent Pinchart 42127cbd7e8SArnd Bergmann static void sh_mmcif_request_dma(struct sh_mmcif_host *host) 422e5a233cbSLaurent Pinchart { 423585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 424f38f94c6SLinus Walleij host->dma_active = false; 425a782d688SGuennadi Liakhovetski 426a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 42727cbd7e8SArnd Bergmann if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) { 42827cbd7e8SArnd Bergmann struct sh_mmcif_plat_data *pdata = dev->platform_data; 42927cbd7e8SArnd Bergmann 43027cbd7e8SArnd Bergmann host->chan_tx = sh_mmcif_request_dma_pdata(host, 43127cbd7e8SArnd Bergmann pdata->slave_id_tx); 43227cbd7e8SArnd Bergmann host->chan_rx = sh_mmcif_request_dma_pdata(host, 43327cbd7e8SArnd Bergmann pdata->slave_id_rx); 43427cbd7e8SArnd Bergmann } else { 435b67b4517SPeter Ujfalusi host->chan_tx = dma_request_chan(dev, "tx"); 436b67b4517SPeter Ujfalusi if (IS_ERR(host->chan_tx)) 437b67b4517SPeter Ujfalusi host->chan_tx = NULL; 438b67b4517SPeter Ujfalusi host->chan_rx = dma_request_chan(dev, "rx"); 439b67b4517SPeter Ujfalusi if (IS_ERR(host->chan_rx)) 440b67b4517SPeter Ujfalusi host->chan_rx = NULL; 44127cbd7e8SArnd Bergmann } 44227cbd7e8SArnd Bergmann dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, 44327cbd7e8SArnd Bergmann host->chan_rx); 44427cbd7e8SArnd Bergmann 44527cbd7e8SArnd Bergmann if (!host->chan_tx || !host->chan_rx || 44627cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || 44727cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) 44827cbd7e8SArnd Bergmann goto error; 44927cbd7e8SArnd Bergmann 450a782d688SGuennadi Liakhovetski return; 451a782d688SGuennadi Liakhovetski 45227cbd7e8SArnd Bergmann error: 45327cbd7e8SArnd Bergmann if (host->chan_tx) 4540e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 45527cbd7e8SArnd Bergmann if (host->chan_rx) 45627cbd7e8SArnd Bergmann dma_release_channel(host->chan_rx); 45727cbd7e8SArnd Bergmann host->chan_tx = host->chan_rx = NULL; 458e5a233cbSLaurent Pinchart } 459a782d688SGuennadi Liakhovetski 460a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 461a782d688SGuennadi Liakhovetski { 462a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 463a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 464a782d688SGuennadi Liakhovetski if (host->chan_tx) { 465a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 466a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 467a782d688SGuennadi Liakhovetski dma_release_channel(chan); 468a782d688SGuennadi Liakhovetski } 469a782d688SGuennadi Liakhovetski if (host->chan_rx) { 470a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 471a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 472a782d688SGuennadi Liakhovetski dma_release_channel(chan); 473a782d688SGuennadi Liakhovetski } 474a782d688SGuennadi Liakhovetski 475f38f94c6SLinus Walleij host->dma_active = false; 476a782d688SGuennadi Liakhovetski } 477fdc50a94SYusuke Goda 478fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 479fdc50a94SYusuke Goda { 480585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 481585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *p = dev->platform_data; 482bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 4836aed678bSKuninori Morimoto unsigned int current_clk = clk_get_rate(host->clk); 48489d49a70SKuninori Morimoto unsigned int clkdiv; 485fdc50a94SYusuke Goda 486fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 487fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 488fdc50a94SYusuke Goda 489fdc50a94SYusuke Goda if (!clk) 490fdc50a94SYusuke Goda return; 491fdc50a94SYusuke Goda 49289d49a70SKuninori Morimoto if (host->clkdiv_map) { 49389d49a70SKuninori Morimoto unsigned int freq, best_freq, myclk, div, diff_min, diff; 49489d49a70SKuninori Morimoto int i; 49589d49a70SKuninori Morimoto 49689d49a70SKuninori Morimoto clkdiv = 0; 49789d49a70SKuninori Morimoto diff_min = ~0; 49889d49a70SKuninori Morimoto best_freq = 0; 49989d49a70SKuninori Morimoto for (i = 31; i >= 0; i--) { 50089d49a70SKuninori Morimoto if (!((1 << i) & host->clkdiv_map)) 50189d49a70SKuninori Morimoto continue; 50289d49a70SKuninori Morimoto 50389d49a70SKuninori Morimoto /* 50489d49a70SKuninori Morimoto * clk = parent_freq / div 50589d49a70SKuninori Morimoto * -> parent_freq = clk x div 50689d49a70SKuninori Morimoto */ 50789d49a70SKuninori Morimoto 50889d49a70SKuninori Morimoto div = 1 << (i + 1); 50989d49a70SKuninori Morimoto freq = clk_round_rate(host->clk, clk * div); 51089d49a70SKuninori Morimoto myclk = freq / div; 51189d49a70SKuninori Morimoto diff = (myclk > clk) ? myclk - clk : clk - myclk; 51289d49a70SKuninori Morimoto 51389d49a70SKuninori Morimoto if (diff <= diff_min) { 51489d49a70SKuninori Morimoto best_freq = freq; 51589d49a70SKuninori Morimoto clkdiv = i; 51689d49a70SKuninori Morimoto diff_min = diff; 51789d49a70SKuninori Morimoto } 51889d49a70SKuninori Morimoto } 51989d49a70SKuninori Morimoto 52089d49a70SKuninori Morimoto dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", 52189d49a70SKuninori Morimoto (best_freq / (1 << (clkdiv + 1))), clk, 52289d49a70SKuninori Morimoto best_freq, clkdiv); 52389d49a70SKuninori Morimoto 52489d49a70SKuninori Morimoto clk_set_rate(host->clk, best_freq); 52589d49a70SKuninori Morimoto clkdiv = clkdiv << 16; 52689d49a70SKuninori Morimoto } else if (sup_pclk && clk == current_clk) { 52789d49a70SKuninori Morimoto clkdiv = CLK_SUP_PCLK; 52889d49a70SKuninori Morimoto } else { 52989d49a70SKuninori Morimoto clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; 53089d49a70SKuninori Morimoto } 53189d49a70SKuninori Morimoto 53289d49a70SKuninori Morimoto sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); 533fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 534fdc50a94SYusuke Goda } 535fdc50a94SYusuke Goda 536fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 537fdc50a94SYusuke Goda { 538fdc50a94SYusuke Goda u32 tmp; 539fdc50a94SYusuke Goda 540487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 541fdc50a94SYusuke Goda 542487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 543487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 544967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 545967bcb77SGuennadi Liakhovetski tmp |= SCCSTO_29; 5466d6fd367SGuennadi Liakhovetski if (host->clk_ctrl2_enable) 5476d6fd367SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 548fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 549967bcb77SGuennadi Liakhovetski SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 550fdc50a94SYusuke Goda /* byte swap on */ 551fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 552fdc50a94SYusuke Goda } 553fdc50a94SYusuke Goda 554fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 555fdc50a94SYusuke Goda { 556585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 557fdc50a94SYusuke Goda u32 state1, state2; 558ee4b8887SGuennadi Liakhovetski int ret, timeout; 559fdc50a94SYusuke Goda 560aa0787a9SGuennadi Liakhovetski host->sd_error = false; 561fdc50a94SYusuke Goda 562487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 563487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 564585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); 565585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); 566fdc50a94SYusuke Goda 567fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 568fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 569fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 57052e00b84SUlf Hansson for (timeout = 10000; timeout; timeout--) { 571487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 572fdc50a94SYusuke Goda & STS1_CMDSEQ)) 573fdc50a94SYusuke Goda break; 574fdc50a94SYusuke Goda mdelay(1); 575fdc50a94SYusuke Goda } 576ee4b8887SGuennadi Liakhovetski if (!timeout) { 577585c3a5aSKuninori Morimoto dev_err(dev, 578ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 579ee4b8887SGuennadi Liakhovetski return -EIO; 580ee4b8887SGuennadi Liakhovetski } 581fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 582585c3a5aSKuninori Morimoto dev_dbg(dev, "Forced end of command sequence\n"); 583fdc50a94SYusuke Goda return -EIO; 584fdc50a94SYusuke Goda } 585fdc50a94SYusuke Goda 586fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 587585c3a5aSKuninori Morimoto dev_err(dev, " CRC error: state %u, wait %u\n", 588e475b270STeppei Kamijou host->state, host->wait_for); 589fdc50a94SYusuke Goda ret = -EIO; 590fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 591585c3a5aSKuninori Morimoto dev_err(dev, " Timeout: state %u, wait %u\n", 592e475b270STeppei Kamijou host->state, host->wait_for); 593fdc50a94SYusuke Goda ret = -ETIMEDOUT; 594fdc50a94SYusuke Goda } else { 595585c3a5aSKuninori Morimoto dev_dbg(dev, " End/Index error: state %u, wait %u\n", 596e475b270STeppei Kamijou host->state, host->wait_for); 597fdc50a94SYusuke Goda ret = -EIO; 598fdc50a94SYusuke Goda } 599fdc50a94SYusuke Goda return ret; 600fdc50a94SYusuke Goda } 601fdc50a94SYusuke Goda 602f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 603f985da17SGuennadi Liakhovetski { 604f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 605f985da17SGuennadi Liakhovetski 606f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 607f985da17SGuennadi Liakhovetski 608f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 609f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 610f985da17SGuennadi Liakhovetski 611f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 612f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 613f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 614f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 615f985da17SGuennadi Liakhovetski } else { 616f985da17SGuennadi Liakhovetski host->pio_ptr = p; 617f985da17SGuennadi Liakhovetski } 618f985da17SGuennadi Liakhovetski 61999eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 620f985da17SGuennadi Liakhovetski } 621f985da17SGuennadi Liakhovetski 622f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 623fdc50a94SYusuke Goda struct mmc_request *mrq) 624fdc50a94SYusuke Goda { 625f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 626f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 627f985da17SGuennadi Liakhovetski 628f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 629fdc50a94SYusuke Goda 630fdc50a94SYusuke Goda /* buf read enable */ 631fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 632f985da17SGuennadi Liakhovetski } 633fdc50a94SYusuke Goda 634f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 635f985da17SGuennadi Liakhovetski { 636585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 637f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 638f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 639f985da17SGuennadi Liakhovetski int i; 640f985da17SGuennadi Liakhovetski 641f985da17SGuennadi Liakhovetski if (host->sd_error) { 642f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 643585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 644f985da17SGuennadi Liakhovetski return false; 645f985da17SGuennadi Liakhovetski } 646f985da17SGuennadi Liakhovetski 647f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 648487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 649fdc50a94SYusuke Goda 650fdc50a94SYusuke Goda /* buffer read end */ 651fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 652f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 653fdc50a94SYusuke Goda 654f985da17SGuennadi Liakhovetski return true; 655fdc50a94SYusuke Goda } 656fdc50a94SYusuke Goda 657f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 658fdc50a94SYusuke Goda struct mmc_request *mrq) 659fdc50a94SYusuke Goda { 660fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 661fdc50a94SYusuke Goda 662f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 663f985da17SGuennadi Liakhovetski return; 664f985da17SGuennadi Liakhovetski 665f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 666f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 667f985da17SGuennadi Liakhovetski 668f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 669f985da17SGuennadi Liakhovetski host->sg_idx = 0; 670f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 671f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6725df460b1SGuennadi Liakhovetski 673fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 674fdc50a94SYusuke Goda } 675fdc50a94SYusuke Goda 676f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 677f985da17SGuennadi Liakhovetski { 678585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 679f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 680f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 681f985da17SGuennadi Liakhovetski int i; 682f985da17SGuennadi Liakhovetski 683f985da17SGuennadi Liakhovetski if (host->sd_error) { 684f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 685585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 686f985da17SGuennadi Liakhovetski return false; 687f985da17SGuennadi Liakhovetski } 688f985da17SGuennadi Liakhovetski 689f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 690f985da17SGuennadi Liakhovetski 691f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 692f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 693f985da17SGuennadi Liakhovetski 694f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 695f985da17SGuennadi Liakhovetski return false; 696f985da17SGuennadi Liakhovetski 697f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 698f985da17SGuennadi Liakhovetski 699f985da17SGuennadi Liakhovetski return true; 700f985da17SGuennadi Liakhovetski } 701f985da17SGuennadi Liakhovetski 702f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 703fdc50a94SYusuke Goda struct mmc_request *mrq) 704fdc50a94SYusuke Goda { 705f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 706f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 707fdc50a94SYusuke Goda 708f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 709fdc50a94SYusuke Goda 710fdc50a94SYusuke Goda /* buf write enable */ 711f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 712f985da17SGuennadi Liakhovetski } 713fdc50a94SYusuke Goda 714f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 715f985da17SGuennadi Liakhovetski { 716585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 717f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 718f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 719f985da17SGuennadi Liakhovetski int i; 720f985da17SGuennadi Liakhovetski 721f985da17SGuennadi Liakhovetski if (host->sd_error) { 722f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 723585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 724f985da17SGuennadi Liakhovetski return false; 725f985da17SGuennadi Liakhovetski } 726f985da17SGuennadi Liakhovetski 727f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 728487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 729fdc50a94SYusuke Goda 730fdc50a94SYusuke Goda /* buffer write end */ 731fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 732f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 733fdc50a94SYusuke Goda 734f985da17SGuennadi Liakhovetski return true; 735fdc50a94SYusuke Goda } 736fdc50a94SYusuke Goda 737f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 738fdc50a94SYusuke Goda struct mmc_request *mrq) 739fdc50a94SYusuke Goda { 740fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 741fdc50a94SYusuke Goda 742f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 743f985da17SGuennadi Liakhovetski return; 744fdc50a94SYusuke Goda 745f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 746f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 747f985da17SGuennadi Liakhovetski 748f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 749f985da17SGuennadi Liakhovetski host->sg_idx = 0; 750f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 751f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 7525df460b1SGuennadi Liakhovetski 753fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 754fdc50a94SYusuke Goda } 755f985da17SGuennadi Liakhovetski 756f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 757f985da17SGuennadi Liakhovetski { 758585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 759f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 760f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 761f985da17SGuennadi Liakhovetski int i; 762f985da17SGuennadi Liakhovetski 763f985da17SGuennadi Liakhovetski if (host->sd_error) { 764f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 765585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 766f985da17SGuennadi Liakhovetski return false; 767fdc50a94SYusuke Goda } 768f985da17SGuennadi Liakhovetski 769f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 770f985da17SGuennadi Liakhovetski 771f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 772f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 773f985da17SGuennadi Liakhovetski 774f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 775f985da17SGuennadi Liakhovetski return false; 776f985da17SGuennadi Liakhovetski 777f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 778f985da17SGuennadi Liakhovetski 779f985da17SGuennadi Liakhovetski return true; 780fdc50a94SYusuke Goda } 781fdc50a94SYusuke Goda 782fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 783fdc50a94SYusuke Goda struct mmc_command *cmd) 784fdc50a94SYusuke Goda { 785fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 786487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 787487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 788487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 789487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 790fdc50a94SYusuke Goda } else 791487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 792fdc50a94SYusuke Goda } 793fdc50a94SYusuke Goda 794fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 795fdc50a94SYusuke Goda struct mmc_command *cmd) 796fdc50a94SYusuke Goda { 797487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 798fdc50a94SYusuke Goda } 799fdc50a94SYusuke Goda 800fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 80169983404SGuennadi Liakhovetski struct mmc_request *mrq) 802fdc50a94SYusuke Goda { 803585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 80469983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 80569983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 80669983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 807fdc50a94SYusuke Goda u32 tmp = 0; 808fdc50a94SYusuke Goda 809fdc50a94SYusuke Goda /* Response Type check */ 810fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 811fdc50a94SYusuke Goda case MMC_RSP_NONE: 812fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 813fdc50a94SYusuke Goda break; 814fdc50a94SYusuke Goda case MMC_RSP_R1: 815fdc50a94SYusuke Goda case MMC_RSP_R3: 816fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 817fdc50a94SYusuke Goda break; 8185b1c29bcSUlf Hansson case MMC_RSP_R1B: 8195b1c29bcSUlf Hansson tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B; 8205b1c29bcSUlf Hansson break; 821fdc50a94SYusuke Goda case MMC_RSP_R2: 822fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 823fdc50a94SYusuke Goda break; 824fdc50a94SYusuke Goda default: 825585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported response type.\n"); 826fdc50a94SYusuke Goda break; 827fdc50a94SYusuke Goda } 8285b1c29bcSUlf Hansson 829fdc50a94SYusuke Goda /* WDAT / DATW */ 83069983404SGuennadi Liakhovetski if (data) { 831fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 832fdc50a94SYusuke Goda switch (host->bus_width) { 833fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 834fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 835fdc50a94SYusuke Goda break; 836fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 837fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 838fdc50a94SYusuke Goda break; 839fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 840fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 841fdc50a94SYusuke Goda break; 842fdc50a94SYusuke Goda default: 843585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported bus width.\n"); 844fdc50a94SYusuke Goda break; 845fdc50a94SYusuke Goda } 846555061f9STeppei Kamijou switch (host->timing) { 8474039ff47SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 848555061f9STeppei Kamijou /* 849555061f9STeppei Kamijou * MMC core will only set this timing, if the host 8504039ff47SSeungwon Jeon * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 8514039ff47SSeungwon Jeon * capability. MMCIF implementations with this 8524039ff47SSeungwon Jeon * capability, e.g. sh73a0, will have to set it 8534039ff47SSeungwon Jeon * in their platform data. 854555061f9STeppei Kamijou */ 855555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 856555061f9STeppei Kamijou break; 857555061f9STeppei Kamijou } 858fdc50a94SYusuke Goda } 859fdc50a94SYusuke Goda /* DWEN */ 860fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 861fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 862fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 863fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 864fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 865fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 86669983404SGuennadi Liakhovetski data->blocks << 16); 867fdc50a94SYusuke Goda } 868fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 869fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 870fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 871fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 872fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 873fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 874fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 875fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 876fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 877fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 878fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 879fdc50a94SYusuke Goda 88069983404SGuennadi Liakhovetski return (opc << 24) | tmp; 881fdc50a94SYusuke Goda } 882fdc50a94SYusuke Goda 883e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 884fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 885fdc50a94SYusuke Goda { 886585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 887585c3a5aSKuninori Morimoto 888fdc50a94SYusuke Goda switch (opc) { 889fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 890f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 891f985da17SGuennadi Liakhovetski return 0; 892fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 893f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 894f985da17SGuennadi Liakhovetski return 0; 895fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 896f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 897f985da17SGuennadi Liakhovetski return 0; 898fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 899fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 900f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 901f985da17SGuennadi Liakhovetski return 0; 902fdc50a94SYusuke Goda default: 903585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported CMD%d\n", opc); 904ee4b8887SGuennadi Liakhovetski return -EINVAL; 905fdc50a94SYusuke Goda } 906fdc50a94SYusuke Goda } 907fdc50a94SYusuke Goda 908fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 909ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 910fdc50a94SYusuke Goda { 911ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 912659032dcSColin Ian King u32 opc; 9135b1c29bcSUlf Hansson u32 mask = 0; 914dbb42d96SKouichi Tomita unsigned long flags; 915fdc50a94SYusuke Goda 9165b1c29bcSUlf Hansson if (cmd->flags & MMC_RSP_BUSY) 917ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 9185b1c29bcSUlf Hansson else 919ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 920fdc50a94SYusuke Goda 921967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 922967bcb77SGuennadi Liakhovetski mask |= MASK_MCCSTO; 923967bcb77SGuennadi Liakhovetski 92469983404SGuennadi Liakhovetski if (mrq->data) { 925487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 926487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 927487d9fc5SMagnus Damm mrq->data->blksz); 928fdc50a94SYusuke Goda } 92969983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 930fdc50a94SYusuke Goda 931967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 932487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 933967bcb77SGuennadi Liakhovetski else 934967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 935487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 936fdc50a94SYusuke Goda /* set arg */ 937487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 938fdc50a94SYusuke Goda /* set cmd */ 939dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 940487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 941fdc50a94SYusuke Goda 942f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 943f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 944dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 945fdc50a94SYusuke Goda } 946fdc50a94SYusuke Goda 947fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 948ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 949fdc50a94SYusuke Goda { 950585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 951585c3a5aSKuninori Morimoto 95269983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 95369983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 954fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 95569983404SGuennadi Liakhovetski break; 95669983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 957fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 95869983404SGuennadi Liakhovetski break; 95969983404SGuennadi Liakhovetski default: 960585c3a5aSKuninori Morimoto dev_err(dev, "unsupported stop cmd\n"); 96169983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 962fdc50a94SYusuke Goda return; 963fdc50a94SYusuke Goda } 964fdc50a94SYusuke Goda 965f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 966fdc50a94SYusuke Goda } 967fdc50a94SYusuke Goda 968fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 969fdc50a94SYusuke Goda { 970fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 971585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 9723b0beafcSGuennadi Liakhovetski unsigned long flags; 9733b0beafcSGuennadi Liakhovetski 9743b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9753b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 976585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 977585c3a5aSKuninori Morimoto __func__, host->state); 9783b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9793b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9803b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9813b0beafcSGuennadi Liakhovetski return; 9823b0beafcSGuennadi Liakhovetski } 9833b0beafcSGuennadi Liakhovetski 9843b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9853b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 986fdc50a94SYusuke Goda 987f985da17SGuennadi Liakhovetski host->mrq = mrq; 988f985da17SGuennadi Liakhovetski 989f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 990fdc50a94SYusuke Goda } 991fdc50a94SYusuke Goda 9929bb09a30SKuninori Morimoto static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) 993a6609267SGuennadi Liakhovetski { 99489d49a70SKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 99589d49a70SKuninori Morimoto 99689d49a70SKuninori Morimoto if (host->mmc->f_max) { 99789d49a70SKuninori Morimoto unsigned int f_max, f_min = 0, f_min_old; 99889d49a70SKuninori Morimoto 99989d49a70SKuninori Morimoto f_max = host->mmc->f_max; 100089d49a70SKuninori Morimoto for (f_min_old = f_max; f_min_old > 2;) { 100189d49a70SKuninori Morimoto f_min = clk_round_rate(host->clk, f_min_old / 2); 100289d49a70SKuninori Morimoto if (f_min == f_min_old) 100389d49a70SKuninori Morimoto break; 100489d49a70SKuninori Morimoto f_min_old = f_min; 100589d49a70SKuninori Morimoto } 100689d49a70SKuninori Morimoto 100789d49a70SKuninori Morimoto /* 100889d49a70SKuninori Morimoto * This driver assumes this SoC is R-Car Gen2 or later 100989d49a70SKuninori Morimoto */ 101089d49a70SKuninori Morimoto host->clkdiv_map = 0x3ff; 101189d49a70SKuninori Morimoto 101289d49a70SKuninori Morimoto host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); 101389d49a70SKuninori Morimoto host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); 101489d49a70SKuninori Morimoto } else { 10156aed678bSKuninori Morimoto unsigned int clk = clk_get_rate(host->clk); 10166aed678bSKuninori Morimoto 10176aed678bSKuninori Morimoto host->mmc->f_max = clk / 2; 10186aed678bSKuninori Morimoto host->mmc->f_min = clk / 512; 1019a6609267SGuennadi Liakhovetski } 1020a6609267SGuennadi Liakhovetski 102189d49a70SKuninori Morimoto dev_dbg(dev, "clk max/min = %d/%d\n", 102289d49a70SKuninori Morimoto host->mmc->f_max, host->mmc->f_min); 102389d49a70SKuninori Morimoto } 102489d49a70SKuninori Morimoto 1025fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1026fdc50a94SYusuke Goda { 1027fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 1028585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 10293b0beafcSGuennadi Liakhovetski unsigned long flags; 10303b0beafcSGuennadi Liakhovetski 10313b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 10323b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 1033585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 1034585c3a5aSKuninori Morimoto __func__, host->state); 10353b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 10363b0beafcSGuennadi Liakhovetski return; 10373b0beafcSGuennadi Liakhovetski } 10383b0beafcSGuennadi Liakhovetski 10393b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 10403b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 1041fdc50a94SYusuke Goda 10424caf653aSUlf Hansson switch (ios->power_mode) { 10434caf653aSUlf Hansson case MMC_POWER_UP: 104433a31ceaSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 104533a31ceaSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1046c9b0cef2SGuennadi Liakhovetski if (!host->power) { 10479bb09a30SKuninori Morimoto clk_prepare_enable(host->clk); 1048585c3a5aSKuninori Morimoto pm_runtime_get_sync(dev); 1049c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 10504caf653aSUlf Hansson sh_mmcif_request_dma(host); 10514caf653aSUlf Hansson host->power = true; 1052c9b0cef2SGuennadi Liakhovetski } 10534caf653aSUlf Hansson break; 10544caf653aSUlf Hansson case MMC_POWER_OFF: 105533a31ceaSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 105633a31ceaSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 10574caf653aSUlf Hansson if (host->power) { 10584caf653aSUlf Hansson sh_mmcif_clock_control(host, 0); 10594caf653aSUlf Hansson sh_mmcif_release_dma(host); 10604caf653aSUlf Hansson pm_runtime_put(dev); 10614caf653aSUlf Hansson clk_disable_unprepare(host->clk); 10624caf653aSUlf Hansson host->power = false; 10634caf653aSUlf Hansson } 10644caf653aSUlf Hansson break; 10654caf653aSUlf Hansson case MMC_POWER_ON: 1066fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 10674caf653aSUlf Hansson break; 1068c9b0cef2SGuennadi Liakhovetski } 1069fdc50a94SYusuke Goda 1070555061f9STeppei Kamijou host->timing = ios->timing; 1071fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10723b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1073fdc50a94SYusuke Goda } 1074fdc50a94SYusuke Goda 10751586cbb3SJulia Lawall static const struct mmc_host_ops sh_mmcif_ops = { 1076fdc50a94SYusuke Goda .request = sh_mmcif_request, 1077fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 10785957eebaSUlf Hansson .get_cd = mmc_gpio_get_cd, 1079fdc50a94SYusuke Goda }; 1080fdc50a94SYusuke Goda 1081f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1082f985da17SGuennadi Liakhovetski { 1083f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 108469983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1085585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1086f985da17SGuennadi Liakhovetski long time; 1087f985da17SGuennadi Liakhovetski 1088f985da17SGuennadi Liakhovetski if (host->sd_error) { 1089f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1090f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1091f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1092f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1093f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1094f985da17SGuennadi Liakhovetski break; 1095f985da17SGuennadi Liakhovetski default: 1096f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1097f985da17SGuennadi Liakhovetski break; 1098f985da17SGuennadi Liakhovetski } 1099585c3a5aSKuninori Morimoto dev_dbg(dev, "CMD%d error %d\n", 1100e475b270STeppei Kamijou cmd->opcode, cmd->error); 1101aba9d646SGuennadi Liakhovetski host->sd_error = false; 1102f985da17SGuennadi Liakhovetski return false; 1103f985da17SGuennadi Liakhovetski } 1104f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1105f985da17SGuennadi Liakhovetski cmd->error = 0; 1106f985da17SGuennadi Liakhovetski return false; 1107f985da17SGuennadi Liakhovetski } 1108f985da17SGuennadi Liakhovetski 1109f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1110f985da17SGuennadi Liakhovetski 111169983404SGuennadi Liakhovetski if (!data) 1112f985da17SGuennadi Liakhovetski return false; 1113f985da17SGuennadi Liakhovetski 111490f1cb43SGuennadi Liakhovetski /* 111590f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to 111690f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active 111790f1cb43SGuennadi Liakhovetski */ 111890f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete); 111990f1cb43SGuennadi Liakhovetski 112069983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1121f985da17SGuennadi Liakhovetski if (host->chan_rx) 1122f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1123f985da17SGuennadi Liakhovetski } else { 1124f985da17SGuennadi Liakhovetski if (host->chan_tx) 1125f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1126f985da17SGuennadi Liakhovetski } 1127f985da17SGuennadi Liakhovetski 1128f985da17SGuennadi Liakhovetski if (!host->dma_active) { 112969983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 113099eb9d8dSGuennadi Liakhovetski return !data->error; 1131f985da17SGuennadi Liakhovetski } 1132f985da17SGuennadi Liakhovetski 1133f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1134f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1135f985da17SGuennadi Liakhovetski host->timeout); 1136eae30983STeppei Kamijou 1137eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1138eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1139eae30983STeppei Kamijou data->sg, data->sg_len, 1140eae30983STeppei Kamijou DMA_FROM_DEVICE); 1141eae30983STeppei Kamijou else 1142eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1143eae30983STeppei Kamijou data->sg, data->sg_len, 1144eae30983STeppei Kamijou DMA_TO_DEVICE); 1145eae30983STeppei Kamijou 1146f985da17SGuennadi Liakhovetski if (host->sd_error) { 1147f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1148f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1149f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 115069983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1151f985da17SGuennadi Liakhovetski } else if (!time) { 1152e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n"); 115369983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1154f985da17SGuennadi Liakhovetski } else if (time < 0) { 1155e475b270STeppei Kamijou dev_err(host->mmc->parent, 1156e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time); 115769983404SGuennadi Liakhovetski data->error = time; 1158f985da17SGuennadi Liakhovetski } 1159f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1160f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1161f985da17SGuennadi Liakhovetski host->dma_active = false; 1162f985da17SGuennadi Liakhovetski 1163eae30983STeppei Kamijou if (data->error) { 116469983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1165eae30983STeppei Kamijou /* Abort DMA */ 1166eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1167eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1168eae30983STeppei Kamijou else 1169eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1170eae30983STeppei Kamijou } 1171f985da17SGuennadi Liakhovetski 1172f985da17SGuennadi Liakhovetski return false; 1173f985da17SGuennadi Liakhovetski } 1174f985da17SGuennadi Liakhovetski 1175f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1176f985da17SGuennadi Liakhovetski { 1177f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 11788047310eSGuennadi Liakhovetski struct mmc_request *mrq; 1179585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 11805df460b1SGuennadi Liakhovetski bool wait = false; 1181dbb42d96SKouichi Tomita unsigned long flags; 1182dbb42d96SKouichi Tomita int wait_work; 1183dbb42d96SKouichi Tomita 1184dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 1185dbb42d96SKouichi Tomita wait_work = host->wait_for; 1186dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 1187f985da17SGuennadi Liakhovetski 1188f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1189f985da17SGuennadi Liakhovetski 11908047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 11918047310eSGuennadi Liakhovetski 11928047310eSGuennadi Liakhovetski mrq = host->mrq; 11938047310eSGuennadi Liakhovetski if (!mrq) { 1194585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 11958047310eSGuennadi Liakhovetski host->state, host->wait_for); 11968047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 11978047310eSGuennadi Liakhovetski return IRQ_HANDLED; 11988047310eSGuennadi Liakhovetski } 11998047310eSGuennadi Liakhovetski 1200f985da17SGuennadi Liakhovetski /* 1201f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1202f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1203f985da17SGuennadi Liakhovetski */ 1204dbb42d96SKouichi Tomita switch (wait_work) { 1205f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1206f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 12078047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1208f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1209f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 12105df460b1SGuennadi Liakhovetski /* Wait for data? */ 12115df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1212f985da17SGuennadi Liakhovetski break; 1213f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 12145df460b1SGuennadi Liakhovetski /* Wait for more data? */ 12155df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1216f985da17SGuennadi Liakhovetski break; 1217f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 12185df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12195df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1220f985da17SGuennadi Liakhovetski break; 1221f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 12225df460b1SGuennadi Liakhovetski /* Wait data to write? */ 12235df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1224f985da17SGuennadi Liakhovetski break; 1225f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 12265df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12275df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1228f985da17SGuennadi Liakhovetski break; 1229f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1230f985da17SGuennadi Liakhovetski if (host->sd_error) { 1231f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1232585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); 1233f985da17SGuennadi Liakhovetski break; 1234f985da17SGuennadi Liakhovetski } 1235f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1236f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1237f985da17SGuennadi Liakhovetski break; 1238f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1239f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1240e475b270STeppei Kamijou if (host->sd_error) { 124191ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1242585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); 1243e475b270STeppei Kamijou } 1244f985da17SGuennadi Liakhovetski break; 1245f985da17SGuennadi Liakhovetski default: 1246f985da17SGuennadi Liakhovetski BUG(); 1247f985da17SGuennadi Liakhovetski } 1248f985da17SGuennadi Liakhovetski 12495df460b1SGuennadi Liakhovetski if (wait) { 12505df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12515df460b1SGuennadi Liakhovetski /* Wait for more data */ 12528047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12535df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 12545df460b1SGuennadi Liakhovetski } 12555df460b1SGuennadi Liakhovetski 1256f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 125791ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 125869983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 125969983404SGuennadi Liakhovetski data->bytes_xfered = 126069983404SGuennadi Liakhovetski data->blocks * data->blksz; 1261f985da17SGuennadi Liakhovetski 126269983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1263f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 12645df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 12655df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12668047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1267f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1268f985da17SGuennadi Liakhovetski } 1269f985da17SGuennadi Liakhovetski } 12705df460b1SGuennadi Liakhovetski } 1271f985da17SGuennadi Liakhovetski 1272f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1273f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 127469983404SGuennadi Liakhovetski host->mrq = NULL; 1275f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1276f985da17SGuennadi Liakhovetski 12778047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12788047310eSGuennadi Liakhovetski 1279f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1280f985da17SGuennadi Liakhovetski } 1281f985da17SGuennadi Liakhovetski 1282fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1283fdc50a94SYusuke Goda { 1284fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1285585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1286967bcb77SGuennadi Liakhovetski u32 state, mask; 1287fdc50a94SYusuke Goda 1288487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1289967bcb77SGuennadi Liakhovetski mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1290967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 1291967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1292967bcb77SGuennadi Liakhovetski else 1293967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 12948af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1295fdc50a94SYusuke Goda 12968af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN) 1297585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", 12988af50750SGuennadi Liakhovetski state); 12998af50750SGuennadi Liakhovetski 13008af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) { 1301aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1302585c3a5aSKuninori Morimoto dev_dbg(dev, "int err state = 0x%08x\n", state); 1303fdc50a94SYusuke Goda } 1304f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 13058af50750SGuennadi Liakhovetski if (!host->mrq) 1306585c3a5aSKuninori Morimoto dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); 1307f985da17SGuennadi Liakhovetski if (!host->dma_active) 1308f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1309f985da17SGuennadi Liakhovetski else if (host->sd_error) 13101b1a694dSKuninori Morimoto sh_mmcif_dma_complete(host); 1311f985da17SGuennadi Liakhovetski } else { 1312585c3a5aSKuninori Morimoto dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); 1313f985da17SGuennadi Liakhovetski } 1314fdc50a94SYusuke Goda 1315fdc50a94SYusuke Goda return IRQ_HANDLED; 1316fdc50a94SYusuke Goda } 1317fdc50a94SYusuke Goda 13181b1a694dSKuninori Morimoto static void sh_mmcif_timeout_work(struct work_struct *work) 1319f985da17SGuennadi Liakhovetski { 13201046a811SGeliang Tang struct delayed_work *d = to_delayed_work(work); 1321f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1322f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 1323585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 13248047310eSGuennadi Liakhovetski unsigned long flags; 1325f985da17SGuennadi Liakhovetski 1326f985da17SGuennadi Liakhovetski if (host->dying) 1327f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1328f985da17SGuennadi Liakhovetski return; 1329f985da17SGuennadi Liakhovetski 13308047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 13318047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 13328047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13338047310eSGuennadi Liakhovetski return; 13348047310eSGuennadi Liakhovetski } 13358047310eSGuennadi Liakhovetski 1336585c3a5aSKuninori Morimoto dev_err(dev, "Timeout waiting for %u on CMD%u\n", 13374cbd5224SKouichi Tomita host->wait_for, mrq->cmd->opcode); 13384cbd5224SKouichi Tomita 13398047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 13408047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13418047310eSGuennadi Liakhovetski 1342f985da17SGuennadi Liakhovetski /* 1343f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1344f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1345f985da17SGuennadi Liakhovetski */ 1346f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1347f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1348f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1349f985da17SGuennadi Liakhovetski break; 1350f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1351f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1352f985da17SGuennadi Liakhovetski break; 1353f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1354f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1355f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1356f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1357f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1358f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 135969983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1360f985da17SGuennadi Liakhovetski break; 1361f985da17SGuennadi Liakhovetski default: 1362f985da17SGuennadi Liakhovetski BUG(); 1363f985da17SGuennadi Liakhovetski } 1364f985da17SGuennadi Liakhovetski 1365f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1366f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1367f985da17SGuennadi Liakhovetski host->mrq = NULL; 1368f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1369f985da17SGuennadi Liakhovetski } 1370f985da17SGuennadi Liakhovetski 13717d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 13727d17baa0SGuennadi Liakhovetski { 1373585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1374585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 13757d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 13767d17baa0SGuennadi Liakhovetski 13777d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 13787d17baa0SGuennadi Liakhovetski 1379bf68a812SGuennadi Liakhovetski if (!pd) 1380bf68a812SGuennadi Liakhovetski return; 1381bf68a812SGuennadi Liakhovetski 13827d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 13837d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 13847d17baa0SGuennadi Liakhovetski else if (pd->ocr) 13857d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 13867d17baa0SGuennadi Liakhovetski } 13877d17baa0SGuennadi Liakhovetski 1388c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1389fdc50a94SYusuke Goda { 1390fdc50a94SYusuke Goda int ret = 0, irq[2]; 1391fdc50a94SYusuke Goda struct mmc_host *mmc; 1392e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 139360985c39SKuninori Morimoto struct device *dev = &pdev->dev; 139460985c39SKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 1395fdc50a94SYusuke Goda void __iomem *reg; 13962cd5b3e0SShinya Kuribayashi const char *name; 1397fdc50a94SYusuke Goda 1398fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1399faf97b84SGeert Uytterhoeven irq[1] = platform_get_irq_optional(pdev, 1); 1400faf97b84SGeert Uytterhoeven if (irq[0] < 0) 1401fdc50a94SYusuke Goda return -ENXIO; 140218f55fccSBen Dooks 140334ac4509SYangtao Li reg = devm_platform_ioremap_resource(pdev, 0); 140418f55fccSBen Dooks if (IS_ERR(reg)) 140518f55fccSBen Dooks return PTR_ERR(reg); 1406e1aae2ebSGuennadi Liakhovetski 140760985c39SKuninori Morimoto mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 140818f55fccSBen Dooks if (!mmc) 140918f55fccSBen Dooks return -ENOMEM; 14102c9054dcSSimon Baatz 14112c9054dcSSimon Baatz ret = mmc_of_parse(mmc); 14122c9054dcSSimon Baatz if (ret < 0) 141346991005SBen Dooks goto err_host; 14142c9054dcSSimon Baatz 1415fdc50a94SYusuke Goda host = mmc_priv(mmc); 1416fdc50a94SYusuke Goda host->mmc = mmc; 1417fdc50a94SYusuke Goda host->addr = reg; 1418bad4371dSTakeshi Kihara host->timeout = msecs_to_jiffies(10000); 14198020f711SUlf Hansson host->ccs_enable = true; 1420dba4bb48SUlf Hansson host->clk_ctrl2_enable = false; 1421fdc50a94SYusuke Goda 1422fdc50a94SYusuke Goda host->pd = pdev; 1423fdc50a94SYusuke Goda 14243b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1425fdc50a94SYusuke Goda 1426fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 14277d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 14287d17baa0SGuennadi Liakhovetski 1429eca889f6SGuennadi Liakhovetski mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1430dab3a28bSUlf Hansson mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 1431549646a9SUlf Hansson mmc->max_busy_timeout = 10000; 1432dab3a28bSUlf Hansson 1433bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1434fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1435a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1436fdc50a94SYusuke Goda mmc->max_blk_size = 512; 143709cbfeafSKirill A. Shutemov mmc->max_req_size = PAGE_SIZE * mmc->max_segs; 1438a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1439fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1440fdc50a94SYusuke Goda 1441fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1442a782d688SGuennadi Liakhovetski 14436aed678bSKuninori Morimoto host->clk = devm_clk_get(dev, NULL); 14446aed678bSKuninori Morimoto if (IS_ERR(host->clk)) { 14456aed678bSKuninori Morimoto ret = PTR_ERR(host->clk); 144660985c39SKuninori Morimoto dev_err(dev, "cannot get clock: %d\n", ret); 144788ac2a2cSUlf Hansson goto err_host; 1448b289174fSGuennadi Liakhovetski } 14499bb09a30SKuninori Morimoto 14509bb09a30SKuninori Morimoto ret = clk_prepare_enable(host->clk); 1451a6609267SGuennadi Liakhovetski if (ret < 0) 145288ac2a2cSUlf Hansson goto err_host; 1453b289174fSGuennadi Liakhovetski 14549bb09a30SKuninori Morimoto sh_mmcif_clk_setup(host); 14559bb09a30SKuninori Morimoto 145688ac2a2cSUlf Hansson pm_runtime_enable(dev); 145788ac2a2cSUlf Hansson host->power = false; 145888ac2a2cSUlf Hansson 145988ac2a2cSUlf Hansson ret = pm_runtime_get_sync(dev); 1460faca6648SGuennadi Liakhovetski if (ret < 0) 146146991005SBen Dooks goto err_clk; 1462a782d688SGuennadi Liakhovetski 14631b1a694dSKuninori Morimoto INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); 1464fdc50a94SYusuke Goda 1465b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 14663b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14673b0beafcSGuennadi Liakhovetski 146860985c39SKuninori Morimoto name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; 146960985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, 14706f4789e6SBen Dooks sh_mmcif_irqt, 0, name, host); 1471fdc50a94SYusuke Goda if (ret) { 147260985c39SKuninori Morimoto dev_err(dev, "request_irq error (%s)\n", name); 147311a80852SBen Dooks goto err_clk; 1474fdc50a94SYusuke Goda } 14752cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 147660985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[1], 14776f4789e6SBen Dooks sh_mmcif_intr, sh_mmcif_irqt, 14782cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1479fdc50a94SYusuke Goda if (ret) { 148060985c39SKuninori Morimoto dev_err(dev, "request_irq error (sh_mmc:int)\n"); 148111a80852SBen Dooks goto err_clk; 1482fdc50a94SYusuke Goda } 14832cd5b3e0SShinya Kuribayashi } 1484fdc50a94SYusuke Goda 14858047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 14868047310eSGuennadi Liakhovetski 14875ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 14885ba85d95SGuennadi Liakhovetski if (ret < 0) 14897f67f3a2SBen Dooks goto err_clk; 1490fdc50a94SYusuke Goda 149160985c39SKuninori Morimoto dev_pm_qos_expose_latency_limit(dev, 100); 1492efe6a8adSRafael J. Wysocki 149360985c39SKuninori Morimoto dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", 1494ce7eb688SBen Dooks sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 14956aed678bSKuninori Morimoto clk_get_rate(host->clk) / 1000000UL); 1496ce7eb688SBen Dooks 149788ac2a2cSUlf Hansson pm_runtime_put(dev); 14986aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1499fdc50a94SYusuke Goda return ret; 1500fdc50a94SYusuke Goda 150146991005SBen Dooks err_clk: 15026aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 150388ac2a2cSUlf Hansson pm_runtime_put_sync(dev); 150460985c39SKuninori Morimoto pm_runtime_disable(dev); 150546991005SBen Dooks err_host: 1506fdc50a94SYusuke Goda mmc_free_host(mmc); 1507fdc50a94SYusuke Goda return ret; 1508fdc50a94SYusuke Goda } 1509fdc50a94SYusuke Goda 15106e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1511fdc50a94SYusuke Goda { 1512fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1513fdc50a94SYusuke Goda 1514f985da17SGuennadi Liakhovetski host->dying = true; 15156aed678bSKuninori Morimoto clk_prepare_enable(host->clk); 1516faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1517aa0787a9SGuennadi Liakhovetski 1518efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1519efe6a8adSRafael J. Wysocki 1520faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 15213b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15223b0beafcSGuennadi Liakhovetski 1523f985da17SGuennadi Liakhovetski /* 1524f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1525f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1526f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1527f985da17SGuennadi Liakhovetski */ 1528f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1529f985da17SGuennadi Liakhovetski 15306aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1531fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1532faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1533faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1534fdc50a94SYusuke Goda 1535fdc50a94SYusuke Goda return 0; 1536fdc50a94SYusuke Goda } 1537fdc50a94SYusuke Goda 153851129f31SUlf Hansson #ifdef CONFIG_PM_SLEEP 1539faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1540faca6648SGuennadi Liakhovetski { 1541b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1542faca6648SGuennadi Liakhovetski 15435afc30fcSKoji Matsuoka pm_runtime_get_sync(dev); 1544faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15455afc30fcSKoji Matsuoka pm_runtime_put(dev); 1546faca6648SGuennadi Liakhovetski 1547cb3ca1aeSUlf Hansson return 0; 1548faca6648SGuennadi Liakhovetski } 1549faca6648SGuennadi Liakhovetski 1550faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1551faca6648SGuennadi Liakhovetski { 1552cb3ca1aeSUlf Hansson return 0; 1553faca6648SGuennadi Liakhovetski } 155451129f31SUlf Hansson #endif 1555faca6648SGuennadi Liakhovetski 1556faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 155751129f31SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1558faca6648SGuennadi Liakhovetski }; 1559faca6648SGuennadi Liakhovetski 1560fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1561fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1562fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1563fdc50a94SYusuke Goda .driver = { 1564fdc50a94SYusuke Goda .name = DRIVER_NAME, 1565faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 15661b1a694dSKuninori Morimoto .of_match_table = sh_mmcif_of_match, 1567fdc50a94SYusuke Goda }, 1568fdc50a94SYusuke Goda }; 1569fdc50a94SYusuke Goda 1570d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1571fdc50a94SYusuke Goda 1572fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1573f707079dSWolfram Sang MODULE_LICENSE("GPL v2"); 1574aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1575fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1576