1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 598047310eSGuennadi Liakhovetski #include <linux/mutex.h> 60a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 61e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 62efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 63faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 643b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6588b47679SPaul Gortmaker #include <linux/module.h> 66fdc50a94SYusuke Goda 67fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 68fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 69fdc50a94SYusuke Goda 70fdc50a94SYusuke Goda /* CE_CMD_SET */ 71fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 72fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 73fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 74fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 75fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 76fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 77fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 78fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 79fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 80fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 81fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 82fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 83fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 84fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 85fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 86fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 88fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 89fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 90fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 91fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 92555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 93fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 94fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 95fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 96fdc50a94SYusuke Goda 97fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 98fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 99fdc50a94SYusuke Goda 100fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 101fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 102fdc50a94SYusuke Goda 103fdc50a94SYusuke Goda /* CE_INT */ 104fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 105fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 106fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 107fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 108fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 109fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 110fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 111fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 112fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 113fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 114fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 115fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 116fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 117fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 118fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 119fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 120fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 121fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 122fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 123fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 124fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 125fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 126fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 127fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 128fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 129fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 130fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 131fdc50a94SYusuke Goda 132fdc50a94SYusuke Goda /* CE_INT_MASK */ 133fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 134fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 135fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 136fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 137fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 138fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 139fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 140fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 141fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 142fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 143fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 144fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 145fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 146fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 147fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 148fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 149fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 150fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 151fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 152fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 153fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 154fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 155fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 156fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 157fdc50a94SYusuke Goda 158ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 159ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 160ee4b8887SGuennadi Liakhovetski MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ 161ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 162ee4b8887SGuennadi Liakhovetski 163fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 164fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 165fdc50a94SYusuke Goda 166fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 167fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 168fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 169fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 170fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 171fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 172fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 173fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 174fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 175fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 176fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 177fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 178fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 179fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 180fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 181fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 182fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 183fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 184fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 185fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 186fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 187fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 188fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 189fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 190fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 191fdc50a94SYusuke Goda 192fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 193fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 194fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 195fdc50a94SYusuke Goda 1963b0beafcSGuennadi Liakhovetski enum mmcif_state { 1973b0beafcSGuennadi Liakhovetski STATE_IDLE, 1983b0beafcSGuennadi Liakhovetski STATE_REQUEST, 1993b0beafcSGuennadi Liakhovetski STATE_IOS, 2008047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2013b0beafcSGuennadi Liakhovetski }; 2023b0beafcSGuennadi Liakhovetski 203f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 204f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 205f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 206f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 207f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 208f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 209f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 210f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 211f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 212f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 213f985da17SGuennadi Liakhovetski }; 214f985da17SGuennadi Liakhovetski 215fdc50a94SYusuke Goda struct sh_mmcif_host { 216fdc50a94SYusuke Goda struct mmc_host *mmc; 217f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 218fdc50a94SYusuke Goda struct platform_device *pd; 219fdc50a94SYusuke Goda struct clk *hclk; 220fdc50a94SYusuke Goda unsigned int clk; 221fdc50a94SYusuke Goda int bus_width; 222555061f9STeppei Kamijou unsigned char timing; 223aa0787a9SGuennadi Liakhovetski bool sd_error; 224f985da17SGuennadi Liakhovetski bool dying; 225fdc50a94SYusuke Goda long timeout; 226fdc50a94SYusuke Goda void __iomem *addr; 227f985da17SGuennadi Liakhovetski u32 *pio_ptr; 228ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2293b0beafcSGuennadi Liakhovetski enum mmcif_state state; 230f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 231f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 232f985da17SGuennadi Liakhovetski size_t blocksize; 233f985da17SGuennadi Liakhovetski int sg_idx; 234f985da17SGuennadi Liakhovetski int sg_blkidx; 235faca6648SGuennadi Liakhovetski bool power; 236c9b0cef2SGuennadi Liakhovetski bool card_present; 2378047310eSGuennadi Liakhovetski struct mutex thread_lock; 238fdc50a94SYusuke Goda 239a782d688SGuennadi Liakhovetski /* DMA support */ 240a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 241a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 242a782d688SGuennadi Liakhovetski struct completion dma_complete; 243f38f94c6SLinus Walleij bool dma_active; 244a782d688SGuennadi Liakhovetski }; 245fdc50a94SYusuke Goda 246fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 247fdc50a94SYusuke Goda unsigned int reg, u32 val) 248fdc50a94SYusuke Goda { 249487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 250fdc50a94SYusuke Goda } 251fdc50a94SYusuke Goda 252fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 253fdc50a94SYusuke Goda unsigned int reg, u32 val) 254fdc50a94SYusuke Goda { 255487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 256fdc50a94SYusuke Goda } 257fdc50a94SYusuke Goda 258a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 259a782d688SGuennadi Liakhovetski { 260a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2618047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 26269983404SGuennadi Liakhovetski 263a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 264a782d688SGuennadi Liakhovetski 2658047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 266a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 267a782d688SGuennadi Liakhovetski return; 268a782d688SGuennadi Liakhovetski 269a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 270a782d688SGuennadi Liakhovetski } 271a782d688SGuennadi Liakhovetski 272a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 273a782d688SGuennadi Liakhovetski { 27469983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 27569983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 276a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 277a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 278a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 279a782d688SGuennadi Liakhovetski int ret; 280a782d688SGuennadi Liakhovetski 28169983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 2821ed828dbSLinus Walleij DMA_FROM_DEVICE); 283a782d688SGuennadi Liakhovetski if (ret > 0) { 284f38f94c6SLinus Walleij host->dma_active = true; 28516052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 28605f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 287a782d688SGuennadi Liakhovetski } 288a782d688SGuennadi Liakhovetski 289a782d688SGuennadi Liakhovetski if (desc) { 290a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 291a782d688SGuennadi Liakhovetski desc->callback_param = host; 292a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 293a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 294a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 295a782d688SGuennadi Liakhovetski } 296a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 29769983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 298a782d688SGuennadi Liakhovetski 299a782d688SGuennadi Liakhovetski if (!desc) { 300a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 301a782d688SGuennadi Liakhovetski if (ret >= 0) 302a782d688SGuennadi Liakhovetski ret = -EIO; 303a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 304f38f94c6SLinus Walleij host->dma_active = false; 305a782d688SGuennadi Liakhovetski dma_release_channel(chan); 306a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 307a782d688SGuennadi Liakhovetski chan = host->chan_tx; 308a782d688SGuennadi Liakhovetski if (chan) { 309a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 310a782d688SGuennadi Liakhovetski dma_release_channel(chan); 311a782d688SGuennadi Liakhovetski } 312a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 313a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 314a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 315a782d688SGuennadi Liakhovetski } 316a782d688SGuennadi Liakhovetski 317a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 31869983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 319a782d688SGuennadi Liakhovetski } 320a782d688SGuennadi Liakhovetski 321a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 322a782d688SGuennadi Liakhovetski { 32369983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 32469983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 325a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 326a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 327a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 328a782d688SGuennadi Liakhovetski int ret; 329a782d688SGuennadi Liakhovetski 33069983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3311ed828dbSLinus Walleij DMA_TO_DEVICE); 332a782d688SGuennadi Liakhovetski if (ret > 0) { 333f38f94c6SLinus Walleij host->dma_active = true; 33416052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 33505f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 336a782d688SGuennadi Liakhovetski } 337a782d688SGuennadi Liakhovetski 338a782d688SGuennadi Liakhovetski if (desc) { 339a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 340a782d688SGuennadi Liakhovetski desc->callback_param = host; 341a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 342a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 343a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 344a782d688SGuennadi Liakhovetski } 345a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 34669983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 347a782d688SGuennadi Liakhovetski 348a782d688SGuennadi Liakhovetski if (!desc) { 349a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 350a782d688SGuennadi Liakhovetski if (ret >= 0) 351a782d688SGuennadi Liakhovetski ret = -EIO; 352a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 353f38f94c6SLinus Walleij host->dma_active = false; 354a782d688SGuennadi Liakhovetski dma_release_channel(chan); 355a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 356a782d688SGuennadi Liakhovetski chan = host->chan_rx; 357a782d688SGuennadi Liakhovetski if (chan) { 358a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 359a782d688SGuennadi Liakhovetski dma_release_channel(chan); 360a782d688SGuennadi Liakhovetski } 361a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 362a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 363a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 364a782d688SGuennadi Liakhovetski } 365a782d688SGuennadi Liakhovetski 366a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 367a782d688SGuennadi Liakhovetski desc, cookie); 368a782d688SGuennadi Liakhovetski } 369a782d688SGuennadi Liakhovetski 370a782d688SGuennadi Liakhovetski static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 371a782d688SGuennadi Liakhovetski struct sh_mmcif_plat_data *pdata) 372a782d688SGuennadi Liakhovetski { 3730e79f9aeSGuennadi Liakhovetski struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 3740e79f9aeSGuennadi Liakhovetski struct dma_slave_config cfg; 3750e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 3760e79f9aeSGuennadi Liakhovetski int ret; 3770e79f9aeSGuennadi Liakhovetski 378f38f94c6SLinus Walleij host->dma_active = false; 379a782d688SGuennadi Liakhovetski 380bf68a812SGuennadi Liakhovetski if (!pdata) 381bf68a812SGuennadi Liakhovetski return; 382bf68a812SGuennadi Liakhovetski 3830e79f9aeSGuennadi Liakhovetski if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 3840e79f9aeSGuennadi Liakhovetski return; 385a782d688SGuennadi Liakhovetski 386a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 387a782d688SGuennadi Liakhovetski dma_cap_zero(mask); 388a782d688SGuennadi Liakhovetski dma_cap_set(DMA_SLAVE, mask); 389a782d688SGuennadi Liakhovetski 3900e79f9aeSGuennadi Liakhovetski host->chan_tx = dma_request_channel(mask, shdma_chan_filter, 3910e79f9aeSGuennadi Liakhovetski (void *)pdata->slave_id_tx); 392a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 393a782d688SGuennadi Liakhovetski host->chan_tx); 394a782d688SGuennadi Liakhovetski 395a782d688SGuennadi Liakhovetski if (!host->chan_tx) 396a782d688SGuennadi Liakhovetski return; 397a782d688SGuennadi Liakhovetski 3980e79f9aeSGuennadi Liakhovetski cfg.slave_id = pdata->slave_id_tx; 3990e79f9aeSGuennadi Liakhovetski cfg.direction = DMA_MEM_TO_DEV; 4000e79f9aeSGuennadi Liakhovetski cfg.dst_addr = res->start + MMCIF_CE_DATA; 4010e79f9aeSGuennadi Liakhovetski cfg.src_addr = 0; 4020e79f9aeSGuennadi Liakhovetski ret = dmaengine_slave_config(host->chan_tx, &cfg); 4030e79f9aeSGuennadi Liakhovetski if (ret < 0) 4040e79f9aeSGuennadi Liakhovetski goto ecfgtx; 4050e79f9aeSGuennadi Liakhovetski 4060e79f9aeSGuennadi Liakhovetski host->chan_rx = dma_request_channel(mask, shdma_chan_filter, 4070e79f9aeSGuennadi Liakhovetski (void *)pdata->slave_id_rx); 408a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 409a782d688SGuennadi Liakhovetski host->chan_rx); 410a782d688SGuennadi Liakhovetski 4110e79f9aeSGuennadi Liakhovetski if (!host->chan_rx) 4120e79f9aeSGuennadi Liakhovetski goto erqrx; 4130e79f9aeSGuennadi Liakhovetski 4140e79f9aeSGuennadi Liakhovetski cfg.slave_id = pdata->slave_id_rx; 4150e79f9aeSGuennadi Liakhovetski cfg.direction = DMA_DEV_TO_MEM; 4160e79f9aeSGuennadi Liakhovetski cfg.dst_addr = 0; 4170e79f9aeSGuennadi Liakhovetski cfg.src_addr = res->start + MMCIF_CE_DATA; 4180e79f9aeSGuennadi Liakhovetski ret = dmaengine_slave_config(host->chan_rx, &cfg); 4190e79f9aeSGuennadi Liakhovetski if (ret < 0) 4200e79f9aeSGuennadi Liakhovetski goto ecfgrx; 421a782d688SGuennadi Liakhovetski 422a782d688SGuennadi Liakhovetski init_completion(&host->dma_complete); 4230e79f9aeSGuennadi Liakhovetski 4240e79f9aeSGuennadi Liakhovetski return; 4250e79f9aeSGuennadi Liakhovetski 4260e79f9aeSGuennadi Liakhovetski ecfgrx: 4270e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_rx); 4280e79f9aeSGuennadi Liakhovetski host->chan_rx = NULL; 4290e79f9aeSGuennadi Liakhovetski erqrx: 4300e79f9aeSGuennadi Liakhovetski ecfgtx: 4310e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 4320e79f9aeSGuennadi Liakhovetski host->chan_tx = NULL; 433a782d688SGuennadi Liakhovetski } 434a782d688SGuennadi Liakhovetski 435a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 436a782d688SGuennadi Liakhovetski { 437a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 438a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 439a782d688SGuennadi Liakhovetski if (host->chan_tx) { 440a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 441a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 442a782d688SGuennadi Liakhovetski dma_release_channel(chan); 443a782d688SGuennadi Liakhovetski } 444a782d688SGuennadi Liakhovetski if (host->chan_rx) { 445a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 446a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 447a782d688SGuennadi Liakhovetski dma_release_channel(chan); 448a782d688SGuennadi Liakhovetski } 449a782d688SGuennadi Liakhovetski 450f38f94c6SLinus Walleij host->dma_active = false; 451a782d688SGuennadi Liakhovetski } 452fdc50a94SYusuke Goda 453fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 454fdc50a94SYusuke Goda { 455fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 456bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 457fdc50a94SYusuke Goda 458fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 459fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 460fdc50a94SYusuke Goda 461fdc50a94SYusuke Goda if (!clk) 462fdc50a94SYusuke Goda return; 463bf68a812SGuennadi Liakhovetski if (sup_pclk && clk == host->clk) 464fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 465fdc50a94SYusuke Goda else 466fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 467f9388257SSimon Horman ((fls(DIV_ROUND_UP(host->clk, 468f9388257SSimon Horman clk) - 1) - 1) << 16)); 469fdc50a94SYusuke Goda 470fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 471fdc50a94SYusuke Goda } 472fdc50a94SYusuke Goda 473fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 474fdc50a94SYusuke Goda { 475fdc50a94SYusuke Goda u32 tmp; 476fdc50a94SYusuke Goda 477487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 478fdc50a94SYusuke Goda 479487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 480487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 481fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 482fdc50a94SYusuke Goda SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 483fdc50a94SYusuke Goda /* byte swap on */ 484fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 485fdc50a94SYusuke Goda } 486fdc50a94SYusuke Goda 487fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 488fdc50a94SYusuke Goda { 489fdc50a94SYusuke Goda u32 state1, state2; 490ee4b8887SGuennadi Liakhovetski int ret, timeout; 491fdc50a94SYusuke Goda 492aa0787a9SGuennadi Liakhovetski host->sd_error = false; 493fdc50a94SYusuke Goda 494487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 495487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 496e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 497e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 498fdc50a94SYusuke Goda 499fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 500fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 501fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 502ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 503487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 504fdc50a94SYusuke Goda & STS1_CMDSEQ)) 505fdc50a94SYusuke Goda break; 506fdc50a94SYusuke Goda mdelay(1); 507fdc50a94SYusuke Goda } 508ee4b8887SGuennadi Liakhovetski if (!timeout) { 509ee4b8887SGuennadi Liakhovetski dev_err(&host->pd->dev, 510ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 511ee4b8887SGuennadi Liakhovetski return -EIO; 512ee4b8887SGuennadi Liakhovetski } 513fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 514e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 515fdc50a94SYusuke Goda return -EIO; 516fdc50a94SYusuke Goda } 517fdc50a94SYusuke Goda 518fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 519ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": CRC error\n"); 520fdc50a94SYusuke Goda ret = -EIO; 521fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 522ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Timeout\n"); 523fdc50a94SYusuke Goda ret = -ETIMEDOUT; 524fdc50a94SYusuke Goda } else { 525ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": End/Index error\n"); 526fdc50a94SYusuke Goda ret = -EIO; 527fdc50a94SYusuke Goda } 528fdc50a94SYusuke Goda return ret; 529fdc50a94SYusuke Goda } 530fdc50a94SYusuke Goda 531f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 532f985da17SGuennadi Liakhovetski { 533f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 534f985da17SGuennadi Liakhovetski 535f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 536f985da17SGuennadi Liakhovetski 537f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 538f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 539f985da17SGuennadi Liakhovetski 540f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 541f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 542f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 543f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 544f985da17SGuennadi Liakhovetski } else { 545f985da17SGuennadi Liakhovetski host->pio_ptr = p; 546f985da17SGuennadi Liakhovetski } 547f985da17SGuennadi Liakhovetski 54899eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 549f985da17SGuennadi Liakhovetski } 550f985da17SGuennadi Liakhovetski 551f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 552fdc50a94SYusuke Goda struct mmc_request *mrq) 553fdc50a94SYusuke Goda { 554f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 555f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 556f985da17SGuennadi Liakhovetski 557f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 558fdc50a94SYusuke Goda 559fdc50a94SYusuke Goda /* buf read enable */ 560fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 561f985da17SGuennadi Liakhovetski } 562fdc50a94SYusuke Goda 563f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 564f985da17SGuennadi Liakhovetski { 565f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 566f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 567f985da17SGuennadi Liakhovetski int i; 568f985da17SGuennadi Liakhovetski 569f985da17SGuennadi Liakhovetski if (host->sd_error) { 570f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 571f985da17SGuennadi Liakhovetski return false; 572f985da17SGuennadi Liakhovetski } 573f985da17SGuennadi Liakhovetski 574f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 575487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 576fdc50a94SYusuke Goda 577fdc50a94SYusuke Goda /* buffer read end */ 578fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 579f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 580fdc50a94SYusuke Goda 581f985da17SGuennadi Liakhovetski return true; 582fdc50a94SYusuke Goda } 583fdc50a94SYusuke Goda 584f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 585fdc50a94SYusuke Goda struct mmc_request *mrq) 586fdc50a94SYusuke Goda { 587fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 588fdc50a94SYusuke Goda 589f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 590f985da17SGuennadi Liakhovetski return; 591f985da17SGuennadi Liakhovetski 592f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 593f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 594f985da17SGuennadi Liakhovetski 595f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 596f985da17SGuennadi Liakhovetski host->sg_idx = 0; 597f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 598f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 5995df460b1SGuennadi Liakhovetski 600fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 601fdc50a94SYusuke Goda } 602fdc50a94SYusuke Goda 603f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 604f985da17SGuennadi Liakhovetski { 605f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 606f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 607f985da17SGuennadi Liakhovetski int i; 608f985da17SGuennadi Liakhovetski 609f985da17SGuennadi Liakhovetski if (host->sd_error) { 610f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 611f985da17SGuennadi Liakhovetski return false; 612f985da17SGuennadi Liakhovetski } 613f985da17SGuennadi Liakhovetski 614f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 615f985da17SGuennadi Liakhovetski 616f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 617f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 618f985da17SGuennadi Liakhovetski 619f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 620f985da17SGuennadi Liakhovetski return false; 621f985da17SGuennadi Liakhovetski 622f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 623f985da17SGuennadi Liakhovetski 624f985da17SGuennadi Liakhovetski return true; 625f985da17SGuennadi Liakhovetski } 626f985da17SGuennadi Liakhovetski 627f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 628fdc50a94SYusuke Goda struct mmc_request *mrq) 629fdc50a94SYusuke Goda { 630f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 631f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 632fdc50a94SYusuke Goda 633f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 634fdc50a94SYusuke Goda 635fdc50a94SYusuke Goda /* buf write enable */ 636f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 637f985da17SGuennadi Liakhovetski } 638fdc50a94SYusuke Goda 639f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 640f985da17SGuennadi Liakhovetski { 641f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 642f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 643f985da17SGuennadi Liakhovetski int i; 644f985da17SGuennadi Liakhovetski 645f985da17SGuennadi Liakhovetski if (host->sd_error) { 646f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 647f985da17SGuennadi Liakhovetski return false; 648f985da17SGuennadi Liakhovetski } 649f985da17SGuennadi Liakhovetski 650f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 651487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 652fdc50a94SYusuke Goda 653fdc50a94SYusuke Goda /* buffer write end */ 654fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 655f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 656fdc50a94SYusuke Goda 657f985da17SGuennadi Liakhovetski return true; 658fdc50a94SYusuke Goda } 659fdc50a94SYusuke Goda 660f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 661fdc50a94SYusuke Goda struct mmc_request *mrq) 662fdc50a94SYusuke Goda { 663fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 664fdc50a94SYusuke Goda 665f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 666f985da17SGuennadi Liakhovetski return; 667fdc50a94SYusuke Goda 668f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 669f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 670f985da17SGuennadi Liakhovetski 671f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 672f985da17SGuennadi Liakhovetski host->sg_idx = 0; 673f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 674f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6755df460b1SGuennadi Liakhovetski 676fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 677fdc50a94SYusuke Goda } 678f985da17SGuennadi Liakhovetski 679f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 680f985da17SGuennadi Liakhovetski { 681f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 682f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 683f985da17SGuennadi Liakhovetski int i; 684f985da17SGuennadi Liakhovetski 685f985da17SGuennadi Liakhovetski if (host->sd_error) { 686f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 687f985da17SGuennadi Liakhovetski return false; 688fdc50a94SYusuke Goda } 689f985da17SGuennadi Liakhovetski 690f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 691f985da17SGuennadi Liakhovetski 692f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 693f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 694f985da17SGuennadi Liakhovetski 695f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 696f985da17SGuennadi Liakhovetski return false; 697f985da17SGuennadi Liakhovetski 698f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 699f985da17SGuennadi Liakhovetski 700f985da17SGuennadi Liakhovetski return true; 701fdc50a94SYusuke Goda } 702fdc50a94SYusuke Goda 703fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 704fdc50a94SYusuke Goda struct mmc_command *cmd) 705fdc50a94SYusuke Goda { 706fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 707487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 708487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 709487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 710487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 711fdc50a94SYusuke Goda } else 712487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 713fdc50a94SYusuke Goda } 714fdc50a94SYusuke Goda 715fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 716fdc50a94SYusuke Goda struct mmc_command *cmd) 717fdc50a94SYusuke Goda { 718487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 719fdc50a94SYusuke Goda } 720fdc50a94SYusuke Goda 721fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 72269983404SGuennadi Liakhovetski struct mmc_request *mrq) 723fdc50a94SYusuke Goda { 72469983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 72569983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 72669983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 727fdc50a94SYusuke Goda u32 tmp = 0; 728fdc50a94SYusuke Goda 729fdc50a94SYusuke Goda /* Response Type check */ 730fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 731fdc50a94SYusuke Goda case MMC_RSP_NONE: 732fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 733fdc50a94SYusuke Goda break; 734fdc50a94SYusuke Goda case MMC_RSP_R1: 735fdc50a94SYusuke Goda case MMC_RSP_R1B: 736fdc50a94SYusuke Goda case MMC_RSP_R3: 737fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 738fdc50a94SYusuke Goda break; 739fdc50a94SYusuke Goda case MMC_RSP_R2: 740fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 741fdc50a94SYusuke Goda break; 742fdc50a94SYusuke Goda default: 743e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 744fdc50a94SYusuke Goda break; 745fdc50a94SYusuke Goda } 746fdc50a94SYusuke Goda switch (opc) { 747fdc50a94SYusuke Goda /* RBSY */ 748a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 749fdc50a94SYusuke Goda case MMC_SWITCH: 750fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 751fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 752fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 753fdc50a94SYusuke Goda case MMC_ERASE: 754fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 755fdc50a94SYusuke Goda break; 756fdc50a94SYusuke Goda } 757fdc50a94SYusuke Goda /* WDAT / DATW */ 75869983404SGuennadi Liakhovetski if (data) { 759fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 760fdc50a94SYusuke Goda switch (host->bus_width) { 761fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 762fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 763fdc50a94SYusuke Goda break; 764fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 765fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 766fdc50a94SYusuke Goda break; 767fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 768fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 769fdc50a94SYusuke Goda break; 770fdc50a94SYusuke Goda default: 771e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 772fdc50a94SYusuke Goda break; 773fdc50a94SYusuke Goda } 774555061f9STeppei Kamijou switch (host->timing) { 775555061f9STeppei Kamijou case MMC_TIMING_UHS_DDR50: 776555061f9STeppei Kamijou /* 777555061f9STeppei Kamijou * MMC core will only set this timing, if the host 778555061f9STeppei Kamijou * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF 779555061f9STeppei Kamijou * implementations with this capability, e.g. sh73a0, 780555061f9STeppei Kamijou * will have to set it in their platform data. 781555061f9STeppei Kamijou */ 782555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 783555061f9STeppei Kamijou break; 784555061f9STeppei Kamijou } 785fdc50a94SYusuke Goda } 786fdc50a94SYusuke Goda /* DWEN */ 787fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 788fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 789fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 790fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 791fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 792fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 79369983404SGuennadi Liakhovetski data->blocks << 16); 794fdc50a94SYusuke Goda } 795fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 796fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 797fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 798fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 799fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 800fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 801fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 802fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 803fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 804fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 805fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 806fdc50a94SYusuke Goda 80769983404SGuennadi Liakhovetski return (opc << 24) | tmp; 808fdc50a94SYusuke Goda } 809fdc50a94SYusuke Goda 810e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 811fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 812fdc50a94SYusuke Goda { 813fdc50a94SYusuke Goda switch (opc) { 814fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 815f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 816f985da17SGuennadi Liakhovetski return 0; 817fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 818f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 819f985da17SGuennadi Liakhovetski return 0; 820fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 821f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 822f985da17SGuennadi Liakhovetski return 0; 823fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 824fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 825f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 826f985da17SGuennadi Liakhovetski return 0; 827fdc50a94SYusuke Goda default: 828e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 829ee4b8887SGuennadi Liakhovetski return -EINVAL; 830fdc50a94SYusuke Goda } 831fdc50a94SYusuke Goda } 832fdc50a94SYusuke Goda 833fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 834ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 835fdc50a94SYusuke Goda { 836ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 837f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 838f985da17SGuennadi Liakhovetski u32 mask; 839fdc50a94SYusuke Goda 840fdc50a94SYusuke Goda switch (opc) { 841ee4b8887SGuennadi Liakhovetski /* response busy check */ 842a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 843fdc50a94SYusuke Goda case MMC_SWITCH: 844fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 845fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 846fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 847fdc50a94SYusuke Goda case MMC_ERASE: 848ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 849fdc50a94SYusuke Goda break; 850fdc50a94SYusuke Goda default: 851ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 852fdc50a94SYusuke Goda break; 853fdc50a94SYusuke Goda } 854fdc50a94SYusuke Goda 85569983404SGuennadi Liakhovetski if (mrq->data) { 856487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 857487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 858487d9fc5SMagnus Damm mrq->data->blksz); 859fdc50a94SYusuke Goda } 86069983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 861fdc50a94SYusuke Goda 862487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 863487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 864fdc50a94SYusuke Goda /* set arg */ 865487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 866fdc50a94SYusuke Goda /* set cmd */ 867487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 868fdc50a94SYusuke Goda 869f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 870f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 871fdc50a94SYusuke Goda } 872fdc50a94SYusuke Goda 873fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 874ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 875fdc50a94SYusuke Goda { 87669983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 87769983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 878fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 87969983404SGuennadi Liakhovetski break; 88069983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 881fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 88269983404SGuennadi Liakhovetski break; 88369983404SGuennadi Liakhovetski default: 884e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 88569983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 886fdc50a94SYusuke Goda return; 887fdc50a94SYusuke Goda } 888fdc50a94SYusuke Goda 889f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 890fdc50a94SYusuke Goda } 891fdc50a94SYusuke Goda 892fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 893fdc50a94SYusuke Goda { 894fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 8953b0beafcSGuennadi Liakhovetski unsigned long flags; 8963b0beafcSGuennadi Liakhovetski 8973b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8983b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8993b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9003b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9013b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9023b0beafcSGuennadi Liakhovetski return; 9033b0beafcSGuennadi Liakhovetski } 9043b0beafcSGuennadi Liakhovetski 9053b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9063b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 907fdc50a94SYusuke Goda 908fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 909fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 9107541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 9117541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 9127541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 9137541ca98SLaurent Pinchart break; 914fdc50a94SYusuke Goda case MMC_APP_CMD: 91592ff0c5bSTeppei Kamijou case SD_IO_RW_DIRECT: 9163b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 917fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 918fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 919fdc50a94SYusuke Goda return; 920fdc50a94SYusuke Goda default: 921fdc50a94SYusuke Goda break; 922fdc50a94SYusuke Goda } 923fdc50a94SYusuke Goda 924f985da17SGuennadi Liakhovetski host->mrq = mrq; 925f985da17SGuennadi Liakhovetski 926f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 927fdc50a94SYusuke Goda } 928fdc50a94SYusuke Goda 929a6609267SGuennadi Liakhovetski static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 930a6609267SGuennadi Liakhovetski { 931a6609267SGuennadi Liakhovetski int ret = clk_enable(host->hclk); 932a6609267SGuennadi Liakhovetski 933a6609267SGuennadi Liakhovetski if (!ret) { 934a6609267SGuennadi Liakhovetski host->clk = clk_get_rate(host->hclk); 935a6609267SGuennadi Liakhovetski host->mmc->f_max = host->clk / 2; 936a6609267SGuennadi Liakhovetski host->mmc->f_min = host->clk / 512; 937a6609267SGuennadi Liakhovetski } 938a6609267SGuennadi Liakhovetski 939a6609267SGuennadi Liakhovetski return ret; 940a6609267SGuennadi Liakhovetski } 941a6609267SGuennadi Liakhovetski 9427d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 9437d17baa0SGuennadi Liakhovetski { 9447d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 9457d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 9467d17baa0SGuennadi Liakhovetski 947bf68a812SGuennadi Liakhovetski if (pd && pd->set_pwr) 9487d17baa0SGuennadi Liakhovetski pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF); 9497d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 9507d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 9517d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 9527d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 9537d17baa0SGuennadi Liakhovetski } 9547d17baa0SGuennadi Liakhovetski 955fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 956fdc50a94SYusuke Goda { 957fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9583b0beafcSGuennadi Liakhovetski unsigned long flags; 9593b0beafcSGuennadi Liakhovetski 9603b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9613b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 9623b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9633b0beafcSGuennadi Liakhovetski return; 9643b0beafcSGuennadi Liakhovetski } 9653b0beafcSGuennadi Liakhovetski 9663b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 9673b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 968fdc50a94SYusuke Goda 969f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 970c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 971faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 972faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 973c9b0cef2SGuennadi Liakhovetski host->card_present = true; 974faca6648SGuennadi Liakhovetski } 9757d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 976f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 977f5e0cec4SGuennadi Liakhovetski /* clock stop */ 978f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 979faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 980c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 981c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 982c9b0cef2SGuennadi Liakhovetski host->card_present = false; 983c9b0cef2SGuennadi Liakhovetski } 984c9b0cef2SGuennadi Liakhovetski } 985faca6648SGuennadi Liakhovetski if (host->power) { 986f8a8ced7STeppei Kamijou pm_runtime_put_sync(&host->pd->dev); 987b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 988faca6648SGuennadi Liakhovetski host->power = false; 9897d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 9907d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 991faca6648SGuennadi Liakhovetski } 9923b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 993f5e0cec4SGuennadi Liakhovetski return; 994fdc50a94SYusuke Goda } 995fdc50a94SYusuke Goda 996c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 997c9b0cef2SGuennadi Liakhovetski if (!host->power) { 998a6609267SGuennadi Liakhovetski sh_mmcif_clk_update(host); 999c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 1000c9b0cef2SGuennadi Liakhovetski host->power = true; 1001c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 1002c9b0cef2SGuennadi Liakhovetski } 1003fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 1004c9b0cef2SGuennadi Liakhovetski } 1005fdc50a94SYusuke Goda 1006555061f9STeppei Kamijou host->timing = ios->timing; 1007fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10083b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1009fdc50a94SYusuke Goda } 1010fdc50a94SYusuke Goda 1011777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1012777271d0SArnd Hannemann { 1013777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1014777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1015e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1016e480606aSGuennadi Liakhovetski 1017e480606aSGuennadi Liakhovetski if (ret >= 0) 1018e480606aSGuennadi Liakhovetski return ret; 1019777271d0SArnd Hannemann 1020bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1021777271d0SArnd Hannemann return -ENOSYS; 1022777271d0SArnd Hannemann else 1023777271d0SArnd Hannemann return p->get_cd(host->pd); 1024777271d0SArnd Hannemann } 1025777271d0SArnd Hannemann 1026fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1027fdc50a94SYusuke Goda .request = sh_mmcif_request, 1028fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1029777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1030fdc50a94SYusuke Goda }; 1031fdc50a94SYusuke Goda 1032f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1033f985da17SGuennadi Liakhovetski { 1034f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 103569983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1036f985da17SGuennadi Liakhovetski long time; 1037f985da17SGuennadi Liakhovetski 1038f985da17SGuennadi Liakhovetski if (host->sd_error) { 1039f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1040f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1041f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1042f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1043f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1044f985da17SGuennadi Liakhovetski break; 1045f985da17SGuennadi Liakhovetski default: 1046f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1047f985da17SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n", 1048f985da17SGuennadi Liakhovetski cmd->opcode, cmd->error); 1049f985da17SGuennadi Liakhovetski break; 1050f985da17SGuennadi Liakhovetski } 1051aba9d646SGuennadi Liakhovetski host->sd_error = false; 1052f985da17SGuennadi Liakhovetski return false; 1053f985da17SGuennadi Liakhovetski } 1054f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1055f985da17SGuennadi Liakhovetski cmd->error = 0; 1056f985da17SGuennadi Liakhovetski return false; 1057f985da17SGuennadi Liakhovetski } 1058f985da17SGuennadi Liakhovetski 1059f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1060f985da17SGuennadi Liakhovetski 106169983404SGuennadi Liakhovetski if (!data) 1062f985da17SGuennadi Liakhovetski return false; 1063f985da17SGuennadi Liakhovetski 106469983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1065f985da17SGuennadi Liakhovetski if (host->chan_rx) 1066f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1067f985da17SGuennadi Liakhovetski } else { 1068f985da17SGuennadi Liakhovetski if (host->chan_tx) 1069f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1070f985da17SGuennadi Liakhovetski } 1071f985da17SGuennadi Liakhovetski 1072f985da17SGuennadi Liakhovetski if (!host->dma_active) { 107369983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 107499eb9d8dSGuennadi Liakhovetski return !data->error; 1075f985da17SGuennadi Liakhovetski } 1076f985da17SGuennadi Liakhovetski 1077f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1078f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1079f985da17SGuennadi Liakhovetski host->timeout); 1080eae30983STeppei Kamijou 1081eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1082eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1083eae30983STeppei Kamijou data->sg, data->sg_len, 1084eae30983STeppei Kamijou DMA_FROM_DEVICE); 1085eae30983STeppei Kamijou else 1086eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1087eae30983STeppei Kamijou data->sg, data->sg_len, 1088eae30983STeppei Kamijou DMA_TO_DEVICE); 1089eae30983STeppei Kamijou 1090f985da17SGuennadi Liakhovetski if (host->sd_error) { 1091f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1092f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1093f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 109469983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1095f985da17SGuennadi Liakhovetski } else if (!time) { 109669983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1097f985da17SGuennadi Liakhovetski } else if (time < 0) { 109869983404SGuennadi Liakhovetski data->error = time; 1099f985da17SGuennadi Liakhovetski } 1100f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1101f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1102f985da17SGuennadi Liakhovetski host->dma_active = false; 1103f985da17SGuennadi Liakhovetski 1104eae30983STeppei Kamijou if (data->error) { 110569983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1106eae30983STeppei Kamijou /* Abort DMA */ 1107eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1108eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1109eae30983STeppei Kamijou else 1110eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1111eae30983STeppei Kamijou } 1112f985da17SGuennadi Liakhovetski 1113f985da17SGuennadi Liakhovetski return false; 1114f985da17SGuennadi Liakhovetski } 1115f985da17SGuennadi Liakhovetski 1116f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1117f985da17SGuennadi Liakhovetski { 1118f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 11198047310eSGuennadi Liakhovetski struct mmc_request *mrq; 11205df460b1SGuennadi Liakhovetski bool wait = false; 1121f985da17SGuennadi Liakhovetski 1122f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1123f985da17SGuennadi Liakhovetski 11248047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 11258047310eSGuennadi Liakhovetski 11268047310eSGuennadi Liakhovetski mrq = host->mrq; 11278047310eSGuennadi Liakhovetski if (!mrq) { 11288047310eSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 11298047310eSGuennadi Liakhovetski host->state, host->wait_for); 11308047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 11318047310eSGuennadi Liakhovetski return IRQ_HANDLED; 11328047310eSGuennadi Liakhovetski } 11338047310eSGuennadi Liakhovetski 1134f985da17SGuennadi Liakhovetski /* 1135f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1136f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1137f985da17SGuennadi Liakhovetski */ 1138f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1139f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1140f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 11418047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1142f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1143f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 11445df460b1SGuennadi Liakhovetski /* Wait for data? */ 11455df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1146f985da17SGuennadi Liakhovetski break; 1147f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 11485df460b1SGuennadi Liakhovetski /* Wait for more data? */ 11495df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1150f985da17SGuennadi Liakhovetski break; 1151f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 11525df460b1SGuennadi Liakhovetski /* Wait for data end? */ 11535df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1154f985da17SGuennadi Liakhovetski break; 1155f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 11565df460b1SGuennadi Liakhovetski /* Wait data to write? */ 11575df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1158f985da17SGuennadi Liakhovetski break; 1159f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 11605df460b1SGuennadi Liakhovetski /* Wait for data end? */ 11615df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1162f985da17SGuennadi Liakhovetski break; 1163f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1164f985da17SGuennadi Liakhovetski if (host->sd_error) { 1165f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1166f985da17SGuennadi Liakhovetski break; 1167f985da17SGuennadi Liakhovetski } 1168f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1169f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1170f985da17SGuennadi Liakhovetski break; 1171f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1172f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1173f985da17SGuennadi Liakhovetski if (host->sd_error) 117491ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1175f985da17SGuennadi Liakhovetski break; 1176f985da17SGuennadi Liakhovetski default: 1177f985da17SGuennadi Liakhovetski BUG(); 1178f985da17SGuennadi Liakhovetski } 1179f985da17SGuennadi Liakhovetski 11805df460b1SGuennadi Liakhovetski if (wait) { 11815df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 11825df460b1SGuennadi Liakhovetski /* Wait for more data */ 11838047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 11845df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 11855df460b1SGuennadi Liakhovetski } 11865df460b1SGuennadi Liakhovetski 1187f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 118891ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 118969983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 119069983404SGuennadi Liakhovetski data->bytes_xfered = 119169983404SGuennadi Liakhovetski data->blocks * data->blksz; 1192f985da17SGuennadi Liakhovetski 119369983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1194f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 11955df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 11965df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 11978047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1198f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1199f985da17SGuennadi Liakhovetski } 1200f985da17SGuennadi Liakhovetski } 12015df460b1SGuennadi Liakhovetski } 1202f985da17SGuennadi Liakhovetski 1203f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1204f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 120569983404SGuennadi Liakhovetski host->mrq = NULL; 1206f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1207f985da17SGuennadi Liakhovetski 12088047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12098047310eSGuennadi Liakhovetski 1210f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1211f985da17SGuennadi Liakhovetski } 1212f985da17SGuennadi Liakhovetski 1213fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1214fdc50a94SYusuke Goda { 1215fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1216aa0787a9SGuennadi Liakhovetski u32 state; 1217fdc50a94SYusuke Goda int err = 0; 1218fdc50a94SYusuke Goda 1219487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1220fdc50a94SYusuke Goda 12218a8284a9SGuennadi Liakhovetski if (state & INT_ERR_STS) { 12228a8284a9SGuennadi Liakhovetski /* error interrupts - process first */ 12238a8284a9SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 12248a8284a9SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 12258a8284a9SGuennadi Liakhovetski err = 1; 12268a8284a9SGuennadi Liakhovetski } else if (state & INT_RBSYE) { 1227487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1228487d9fc5SMagnus Damm ~(INT_RBSYE | INT_CRSPE)); 1229fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 1230fdc50a94SYusuke Goda } else if (state & INT_CRSPE) { 1231487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 1232fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 1233fdc50a94SYusuke Goda } else if (state & INT_BUFREN) { 1234487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 1235fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 1236fdc50a94SYusuke Goda } else if (state & INT_BUFWEN) { 1237487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 1238fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 1239fdc50a94SYusuke Goda } else if (state & INT_CMD12DRE) { 1240487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1241fdc50a94SYusuke Goda ~(INT_CMD12DRE | INT_CMD12RBE | 1242fdc50a94SYusuke Goda INT_CMD12CRE | INT_BUFRE)); 1243fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 1244fdc50a94SYusuke Goda } else if (state & INT_BUFRE) { 1245487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 1246fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 1247fdc50a94SYusuke Goda } else if (state & INT_DTRANE) { 12487a7eb328SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 12497a7eb328SGuennadi Liakhovetski ~(INT_CMD12DRE | INT_CMD12RBE | 12507a7eb328SGuennadi Liakhovetski INT_CMD12CRE | INT_DTRANE)); 1251fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 1252fdc50a94SYusuke Goda } else if (state & INT_CMD12RBE) { 1253487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1254fdc50a94SYusuke Goda ~(INT_CMD12RBE | INT_CMD12CRE)); 1255fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 1256fdc50a94SYusuke Goda } else { 1257faca6648SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 1258487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1259fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1260fdc50a94SYusuke Goda err = 1; 1261fdc50a94SYusuke Goda } 1262fdc50a94SYusuke Goda if (err) { 1263aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1264e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 1265fdc50a94SYusuke Goda } 1266f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1267f985da17SGuennadi Liakhovetski if (!host->dma_active) 1268f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1269f985da17SGuennadi Liakhovetski else if (host->sd_error) 1270f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1271f985da17SGuennadi Liakhovetski } else { 1272aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1273f985da17SGuennadi Liakhovetski } 1274fdc50a94SYusuke Goda 1275fdc50a94SYusuke Goda return IRQ_HANDLED; 1276fdc50a94SYusuke Goda } 1277fdc50a94SYusuke Goda 1278f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1279f985da17SGuennadi Liakhovetski { 1280f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1281f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1282f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 12838047310eSGuennadi Liakhovetski unsigned long flags; 1284f985da17SGuennadi Liakhovetski 1285f985da17SGuennadi Liakhovetski if (host->dying) 1286f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1287f985da17SGuennadi Liakhovetski return; 1288f985da17SGuennadi Liakhovetski 12898047310eSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Timeout waiting for %u, opcode %u\n", 12908047310eSGuennadi Liakhovetski host->wait_for, mrq->cmd->opcode); 12918047310eSGuennadi Liakhovetski 12928047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 12938047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 12948047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 12958047310eSGuennadi Liakhovetski return; 12968047310eSGuennadi Liakhovetski } 12978047310eSGuennadi Liakhovetski 12988047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 12998047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13008047310eSGuennadi Liakhovetski 1301f985da17SGuennadi Liakhovetski /* 1302f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1303f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1304f985da17SGuennadi Liakhovetski */ 1305f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1306f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1307f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1308f985da17SGuennadi Liakhovetski break; 1309f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1310f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1311f985da17SGuennadi Liakhovetski break; 1312f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1313f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1314f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1315f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1316f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1317f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 131869983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1319f985da17SGuennadi Liakhovetski break; 1320f985da17SGuennadi Liakhovetski default: 1321f985da17SGuennadi Liakhovetski BUG(); 1322f985da17SGuennadi Liakhovetski } 1323f985da17SGuennadi Liakhovetski 1324f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1325f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1326f985da17SGuennadi Liakhovetski host->mrq = NULL; 1327f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1328f985da17SGuennadi Liakhovetski } 1329f985da17SGuennadi Liakhovetski 13307d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 13317d17baa0SGuennadi Liakhovetski { 13327d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 13337d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 13347d17baa0SGuennadi Liakhovetski 13357d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 13367d17baa0SGuennadi Liakhovetski 1337bf68a812SGuennadi Liakhovetski if (!pd) 1338bf68a812SGuennadi Liakhovetski return; 1339bf68a812SGuennadi Liakhovetski 13407d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 13417d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 13427d17baa0SGuennadi Liakhovetski else if (pd->ocr) 13437d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 13447d17baa0SGuennadi Liakhovetski } 13457d17baa0SGuennadi Liakhovetski 1346c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1347fdc50a94SYusuke Goda { 1348fdc50a94SYusuke Goda int ret = 0, irq[2]; 1349fdc50a94SYusuke Goda struct mmc_host *mmc; 1350e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1351e1aae2ebSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1352fdc50a94SYusuke Goda struct resource *res; 1353fdc50a94SYusuke Goda void __iomem *reg; 13542cd5b3e0SShinya Kuribayashi const char *name; 1355fdc50a94SYusuke Goda 1356fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1357fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 13582cd5b3e0SShinya Kuribayashi if (irq[0] < 0) { 1359e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1360fdc50a94SYusuke Goda return -ENXIO; 1361fdc50a94SYusuke Goda } 1362fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1363fdc50a94SYusuke Goda if (!res) { 1364fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1365fdc50a94SYusuke Goda return -ENXIO; 1366fdc50a94SYusuke Goda } 1367fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1368fdc50a94SYusuke Goda if (!reg) { 1369fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1370fdc50a94SYusuke Goda return -ENOMEM; 1371fdc50a94SYusuke Goda } 1372e1aae2ebSGuennadi Liakhovetski 1373fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1374fdc50a94SYusuke Goda if (!mmc) { 1375fdc50a94SYusuke Goda ret = -ENOMEM; 1376e1aae2ebSGuennadi Liakhovetski goto ealloch; 1377fdc50a94SYusuke Goda } 1378fdc50a94SYusuke Goda host = mmc_priv(mmc); 1379fdc50a94SYusuke Goda host->mmc = mmc; 1380fdc50a94SYusuke Goda host->addr = reg; 1381f9fd54f2STeppei Kamijou host->timeout = msecs_to_jiffies(1000); 1382fdc50a94SYusuke Goda 1383fdc50a94SYusuke Goda host->pd = pdev; 1384fdc50a94SYusuke Goda 13853b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1386fdc50a94SYusuke Goda 1387fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 13887d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 13897d17baa0SGuennadi Liakhovetski 1390a812ba0fSTeppei Kamijou mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1391bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1392fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1393a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1394fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1395a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1396a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1397fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1398fdc50a94SYusuke Goda 1399fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1400a782d688SGuennadi Liakhovetski 1401faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1402faca6648SGuennadi Liakhovetski host->power = false; 1403faca6648SGuennadi Liakhovetski 1404047a9ce7SGuennadi Liakhovetski host->hclk = clk_get(&pdev->dev, NULL); 1405b289174fSGuennadi Liakhovetski if (IS_ERR(host->hclk)) { 1406b289174fSGuennadi Liakhovetski ret = PTR_ERR(host->hclk); 1407047a9ce7SGuennadi Liakhovetski dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 1408b289174fSGuennadi Liakhovetski goto eclkget; 1409b289174fSGuennadi Liakhovetski } 1410a6609267SGuennadi Liakhovetski ret = sh_mmcif_clk_update(host); 1411a6609267SGuennadi Liakhovetski if (ret < 0) 1412a6609267SGuennadi Liakhovetski goto eclkupdate; 1413b289174fSGuennadi Liakhovetski 1414faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1415faca6648SGuennadi Liakhovetski if (ret < 0) 1416e1aae2ebSGuennadi Liakhovetski goto eresume; 1417a782d688SGuennadi Liakhovetski 14185ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1419fdc50a94SYusuke Goda 1420b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 14213b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14223b0beafcSGuennadi Liakhovetski 14232cd5b3e0SShinya Kuribayashi name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; 14242cd5b3e0SShinya Kuribayashi ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host); 1425fdc50a94SYusuke Goda if (ret) { 14262cd5b3e0SShinya Kuribayashi dev_err(&pdev->dev, "request_irq error (%s)\n", name); 1427e1aae2ebSGuennadi Liakhovetski goto ereqirq0; 1428fdc50a94SYusuke Goda } 14292cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 14302cd5b3e0SShinya Kuribayashi ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 14312cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1432fdc50a94SYusuke Goda if (ret) { 1433e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1434e1aae2ebSGuennadi Liakhovetski goto ereqirq1; 1435fdc50a94SYusuke Goda } 14362cd5b3e0SShinya Kuribayashi } 1437fdc50a94SYusuke Goda 1438e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1439e480606aSGuennadi Liakhovetski ret = mmc_gpio_request_cd(mmc, pd->cd_gpio); 1440e480606aSGuennadi Liakhovetski if (ret < 0) 1441e480606aSGuennadi Liakhovetski goto erqcd; 1442e480606aSGuennadi Liakhovetski } 1443e480606aSGuennadi Liakhovetski 14448047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 14458047310eSGuennadi Liakhovetski 1446b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 14475ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 14485ba85d95SGuennadi Liakhovetski if (ret < 0) 1449e1aae2ebSGuennadi Liakhovetski goto emmcaddh; 1450fdc50a94SYusuke Goda 1451efe6a8adSRafael J. Wysocki dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1452efe6a8adSRafael J. Wysocki 1453e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1454e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1455487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1456fdc50a94SYusuke Goda return ret; 1457fdc50a94SYusuke Goda 1458e1aae2ebSGuennadi Liakhovetski emmcaddh: 1459e480606aSGuennadi Liakhovetski erqcd: 14602cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) 14615ba85d95SGuennadi Liakhovetski free_irq(irq[1], host); 1462e1aae2ebSGuennadi Liakhovetski ereqirq1: 14635ba85d95SGuennadi Liakhovetski free_irq(irq[0], host); 1464e1aae2ebSGuennadi Liakhovetski ereqirq0: 1465faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1466e1aae2ebSGuennadi Liakhovetski eresume: 1467fdc50a94SYusuke Goda clk_disable(host->hclk); 1468a6609267SGuennadi Liakhovetski eclkupdate: 1469b289174fSGuennadi Liakhovetski clk_put(host->hclk); 1470e1aae2ebSGuennadi Liakhovetski eclkget: 1471b289174fSGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1472fdc50a94SYusuke Goda mmc_free_host(mmc); 1473e1aae2ebSGuennadi Liakhovetski ealloch: 1474fdc50a94SYusuke Goda iounmap(reg); 1475fdc50a94SYusuke Goda return ret; 1476fdc50a94SYusuke Goda } 1477fdc50a94SYusuke Goda 14786e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1479fdc50a94SYusuke Goda { 1480fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1481fdc50a94SYusuke Goda int irq[2]; 1482fdc50a94SYusuke Goda 1483f985da17SGuennadi Liakhovetski host->dying = true; 1484b289174fSGuennadi Liakhovetski clk_enable(host->hclk); 1485faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1486aa0787a9SGuennadi Liakhovetski 1487efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1488efe6a8adSRafael J. Wysocki 1489faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 14903b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14913b0beafcSGuennadi Liakhovetski 1492f985da17SGuennadi Liakhovetski /* 1493f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1494f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1495f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1496f985da17SGuennadi Liakhovetski */ 1497f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1498f985da17SGuennadi Liakhovetski 1499aa0787a9SGuennadi Liakhovetski if (host->addr) 1500aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1501aa0787a9SGuennadi Liakhovetski 1502fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1503fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1504fdc50a94SYusuke Goda 1505fdc50a94SYusuke Goda free_irq(irq[0], host); 15062cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) 1507fdc50a94SYusuke Goda free_irq(irq[1], host); 1508fdc50a94SYusuke Goda 1509aa0787a9SGuennadi Liakhovetski platform_set_drvdata(pdev, NULL); 1510aa0787a9SGuennadi Liakhovetski 1511a0d28ba0SGuennadi Liakhovetski clk_disable(host->hclk); 1512fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1513faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1514faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1515fdc50a94SYusuke Goda 1516fdc50a94SYusuke Goda return 0; 1517fdc50a94SYusuke Goda } 1518fdc50a94SYusuke Goda 1519faca6648SGuennadi Liakhovetski #ifdef CONFIG_PM 1520faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1521faca6648SGuennadi Liakhovetski { 1522b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1523faca6648SGuennadi Liakhovetski int ret = mmc_suspend_host(host->mmc); 1524faca6648SGuennadi Liakhovetski 1525b289174fSGuennadi Liakhovetski if (!ret) 1526faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1527faca6648SGuennadi Liakhovetski 1528faca6648SGuennadi Liakhovetski return ret; 1529faca6648SGuennadi Liakhovetski } 1530faca6648SGuennadi Liakhovetski 1531faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1532faca6648SGuennadi Liakhovetski { 1533b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1534faca6648SGuennadi Liakhovetski 1535faca6648SGuennadi Liakhovetski return mmc_resume_host(host->mmc); 1536faca6648SGuennadi Liakhovetski } 1537faca6648SGuennadi Liakhovetski #else 1538faca6648SGuennadi Liakhovetski #define sh_mmcif_suspend NULL 1539faca6648SGuennadi Liakhovetski #define sh_mmcif_resume NULL 1540faca6648SGuennadi Liakhovetski #endif /* CONFIG_PM */ 1541faca6648SGuennadi Liakhovetski 1542bf68a812SGuennadi Liakhovetski static const struct of_device_id mmcif_of_match[] = { 1543bf68a812SGuennadi Liakhovetski { .compatible = "renesas,sh-mmcif" }, 1544bf68a812SGuennadi Liakhovetski { } 1545bf68a812SGuennadi Liakhovetski }; 1546bf68a812SGuennadi Liakhovetski MODULE_DEVICE_TABLE(of, mmcif_of_match); 1547bf68a812SGuennadi Liakhovetski 1548faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1549faca6648SGuennadi Liakhovetski .suspend = sh_mmcif_suspend, 1550faca6648SGuennadi Liakhovetski .resume = sh_mmcif_resume, 1551faca6648SGuennadi Liakhovetski }; 1552faca6648SGuennadi Liakhovetski 1553fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1554fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1555fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1556fdc50a94SYusuke Goda .driver = { 1557fdc50a94SYusuke Goda .name = DRIVER_NAME, 1558faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1559bf68a812SGuennadi Liakhovetski .owner = THIS_MODULE, 1560bf68a812SGuennadi Liakhovetski .of_match_table = mmcif_of_match, 1561fdc50a94SYusuke Goda }, 1562fdc50a94SYusuke Goda }; 1563fdc50a94SYusuke Goda 1564d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1565fdc50a94SYusuke Goda 1566fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1567fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1568aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1569fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1570