1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 598047310eSGuennadi Liakhovetski #include <linux/mutex.h> 60a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 61e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 62efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 63faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 643b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6588b47679SPaul Gortmaker #include <linux/module.h> 66fdc50a94SYusuke Goda 67fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 68fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 69fdc50a94SYusuke Goda 70fdc50a94SYusuke Goda /* CE_CMD_SET */ 71fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 72fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 73fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 74fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 75fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 76fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 77fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 78fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 79fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 80fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 81fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 82fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 83fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 84fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 85fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 86fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 88fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 89fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 90fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 91fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 92555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 93fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 94fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 95fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 96fdc50a94SYusuke Goda 97fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 98fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 99fdc50a94SYusuke Goda 100fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 101fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 102fdc50a94SYusuke Goda 103fdc50a94SYusuke Goda /* CE_INT */ 104fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 105fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 106fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 107fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 108fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 109fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 110fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 111fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 112fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 113fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 114fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 115fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 116fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 117fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 118fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 119fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 120fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 121fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 122fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 123fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 124fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 125fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 126fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 127fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 128fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 129fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 130fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 131fdc50a94SYusuke Goda 1328af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 1338af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 1348af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 1358af50750SGuennadi Liakhovetski 136fdc50a94SYusuke Goda /* CE_INT_MASK */ 137fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 138fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 139fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 140fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 141fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 142fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 143fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 144fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 145fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 146fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 147fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 148fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 149fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 150fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 151fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 152fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 153fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 154fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 155fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 156fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 157fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 158fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 159fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 160fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 161fdc50a94SYusuke Goda 162ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 163ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 164ee4b8887SGuennadi Liakhovetski MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ 165ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 166ee4b8887SGuennadi Liakhovetski 1678af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 1688af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \ 1698af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 1708af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE) 1718af50750SGuennadi Liakhovetski 172fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 173fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 174fdc50a94SYusuke Goda 175fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 176fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 177fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 178fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 179fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 180fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 181fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 182fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 183fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 184fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 185fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 186fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 187fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 188fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 189fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 190fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 191fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 192fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 193fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 194fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 195fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 196fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 197fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 198fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 199fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 200fdc50a94SYusuke Goda 201fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 202fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 203fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 204fdc50a94SYusuke Goda 2053b0beafcSGuennadi Liakhovetski enum mmcif_state { 2063b0beafcSGuennadi Liakhovetski STATE_IDLE, 2073b0beafcSGuennadi Liakhovetski STATE_REQUEST, 2083b0beafcSGuennadi Liakhovetski STATE_IOS, 2098047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2103b0beafcSGuennadi Liakhovetski }; 2113b0beafcSGuennadi Liakhovetski 212f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 213f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 214f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 215f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 216f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 217f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 218f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 219f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 220f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 221f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 222f985da17SGuennadi Liakhovetski }; 223f985da17SGuennadi Liakhovetski 224fdc50a94SYusuke Goda struct sh_mmcif_host { 225fdc50a94SYusuke Goda struct mmc_host *mmc; 226f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 227fdc50a94SYusuke Goda struct platform_device *pd; 228fdc50a94SYusuke Goda struct clk *hclk; 229fdc50a94SYusuke Goda unsigned int clk; 230fdc50a94SYusuke Goda int bus_width; 231555061f9STeppei Kamijou unsigned char timing; 232aa0787a9SGuennadi Liakhovetski bool sd_error; 233f985da17SGuennadi Liakhovetski bool dying; 234fdc50a94SYusuke Goda long timeout; 235fdc50a94SYusuke Goda void __iomem *addr; 236f985da17SGuennadi Liakhovetski u32 *pio_ptr; 237ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2383b0beafcSGuennadi Liakhovetski enum mmcif_state state; 239f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 240f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 241f985da17SGuennadi Liakhovetski size_t blocksize; 242f985da17SGuennadi Liakhovetski int sg_idx; 243f985da17SGuennadi Liakhovetski int sg_blkidx; 244faca6648SGuennadi Liakhovetski bool power; 245c9b0cef2SGuennadi Liakhovetski bool card_present; 2468047310eSGuennadi Liakhovetski struct mutex thread_lock; 247fdc50a94SYusuke Goda 248a782d688SGuennadi Liakhovetski /* DMA support */ 249a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 250a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 251a782d688SGuennadi Liakhovetski struct completion dma_complete; 252f38f94c6SLinus Walleij bool dma_active; 253a782d688SGuennadi Liakhovetski }; 254fdc50a94SYusuke Goda 255fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 256fdc50a94SYusuke Goda unsigned int reg, u32 val) 257fdc50a94SYusuke Goda { 258487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 259fdc50a94SYusuke Goda } 260fdc50a94SYusuke Goda 261fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 262fdc50a94SYusuke Goda unsigned int reg, u32 val) 263fdc50a94SYusuke Goda { 264487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 265fdc50a94SYusuke Goda } 266fdc50a94SYusuke Goda 267a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 268a782d688SGuennadi Liakhovetski { 269a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2708047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 27169983404SGuennadi Liakhovetski 272a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 273a782d688SGuennadi Liakhovetski 2748047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 275a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 276a782d688SGuennadi Liakhovetski return; 277a782d688SGuennadi Liakhovetski 278a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 279a782d688SGuennadi Liakhovetski } 280a782d688SGuennadi Liakhovetski 281a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 282a782d688SGuennadi Liakhovetski { 28369983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 28469983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 285a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 286a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 287a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 288a782d688SGuennadi Liakhovetski int ret; 289a782d688SGuennadi Liakhovetski 29069983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 2911ed828dbSLinus Walleij DMA_FROM_DEVICE); 292a782d688SGuennadi Liakhovetski if (ret > 0) { 293f38f94c6SLinus Walleij host->dma_active = true; 29416052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 29505f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 296a782d688SGuennadi Liakhovetski } 297a782d688SGuennadi Liakhovetski 298a782d688SGuennadi Liakhovetski if (desc) { 299a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 300a782d688SGuennadi Liakhovetski desc->callback_param = host; 301a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 302a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 303a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 304a782d688SGuennadi Liakhovetski } 305a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 30669983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 307a782d688SGuennadi Liakhovetski 308a782d688SGuennadi Liakhovetski if (!desc) { 309a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 310a782d688SGuennadi Liakhovetski if (ret >= 0) 311a782d688SGuennadi Liakhovetski ret = -EIO; 312a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 313f38f94c6SLinus Walleij host->dma_active = false; 314a782d688SGuennadi Liakhovetski dma_release_channel(chan); 315a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 316a782d688SGuennadi Liakhovetski chan = host->chan_tx; 317a782d688SGuennadi Liakhovetski if (chan) { 318a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 319a782d688SGuennadi Liakhovetski dma_release_channel(chan); 320a782d688SGuennadi Liakhovetski } 321a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 322a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 323a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 324a782d688SGuennadi Liakhovetski } 325a782d688SGuennadi Liakhovetski 326a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 32769983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 328a782d688SGuennadi Liakhovetski } 329a782d688SGuennadi Liakhovetski 330a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 331a782d688SGuennadi Liakhovetski { 33269983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 33369983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 334a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 335a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 336a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 337a782d688SGuennadi Liakhovetski int ret; 338a782d688SGuennadi Liakhovetski 33969983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3401ed828dbSLinus Walleij DMA_TO_DEVICE); 341a782d688SGuennadi Liakhovetski if (ret > 0) { 342f38f94c6SLinus Walleij host->dma_active = true; 34316052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 34405f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 345a782d688SGuennadi Liakhovetski } 346a782d688SGuennadi Liakhovetski 347a782d688SGuennadi Liakhovetski if (desc) { 348a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 349a782d688SGuennadi Liakhovetski desc->callback_param = host; 350a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 351a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 352a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 353a782d688SGuennadi Liakhovetski } 354a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 35569983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 356a782d688SGuennadi Liakhovetski 357a782d688SGuennadi Liakhovetski if (!desc) { 358a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 359a782d688SGuennadi Liakhovetski if (ret >= 0) 360a782d688SGuennadi Liakhovetski ret = -EIO; 361a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 362f38f94c6SLinus Walleij host->dma_active = false; 363a782d688SGuennadi Liakhovetski dma_release_channel(chan); 364a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 365a782d688SGuennadi Liakhovetski chan = host->chan_rx; 366a782d688SGuennadi Liakhovetski if (chan) { 367a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 368a782d688SGuennadi Liakhovetski dma_release_channel(chan); 369a782d688SGuennadi Liakhovetski } 370a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 371a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 372a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 373a782d688SGuennadi Liakhovetski } 374a782d688SGuennadi Liakhovetski 375a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 376a782d688SGuennadi Liakhovetski desc, cookie); 377a782d688SGuennadi Liakhovetski } 378a782d688SGuennadi Liakhovetski 379a782d688SGuennadi Liakhovetski static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 380a782d688SGuennadi Liakhovetski struct sh_mmcif_plat_data *pdata) 381a782d688SGuennadi Liakhovetski { 3820e79f9aeSGuennadi Liakhovetski struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 3830e79f9aeSGuennadi Liakhovetski struct dma_slave_config cfg; 3840e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 3850e79f9aeSGuennadi Liakhovetski int ret; 3860e79f9aeSGuennadi Liakhovetski 387f38f94c6SLinus Walleij host->dma_active = false; 388a782d688SGuennadi Liakhovetski 389bf68a812SGuennadi Liakhovetski if (!pdata) 390bf68a812SGuennadi Liakhovetski return; 391bf68a812SGuennadi Liakhovetski 3920e79f9aeSGuennadi Liakhovetski if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 3930e79f9aeSGuennadi Liakhovetski return; 394a782d688SGuennadi Liakhovetski 395a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 396a782d688SGuennadi Liakhovetski dma_cap_zero(mask); 397a782d688SGuennadi Liakhovetski dma_cap_set(DMA_SLAVE, mask); 398a782d688SGuennadi Liakhovetski 3990e79f9aeSGuennadi Liakhovetski host->chan_tx = dma_request_channel(mask, shdma_chan_filter, 4000e79f9aeSGuennadi Liakhovetski (void *)pdata->slave_id_tx); 401a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 402a782d688SGuennadi Liakhovetski host->chan_tx); 403a782d688SGuennadi Liakhovetski 404a782d688SGuennadi Liakhovetski if (!host->chan_tx) 405a782d688SGuennadi Liakhovetski return; 406a782d688SGuennadi Liakhovetski 4070e79f9aeSGuennadi Liakhovetski cfg.slave_id = pdata->slave_id_tx; 4080e79f9aeSGuennadi Liakhovetski cfg.direction = DMA_MEM_TO_DEV; 4090e79f9aeSGuennadi Liakhovetski cfg.dst_addr = res->start + MMCIF_CE_DATA; 4100e79f9aeSGuennadi Liakhovetski cfg.src_addr = 0; 4110e79f9aeSGuennadi Liakhovetski ret = dmaengine_slave_config(host->chan_tx, &cfg); 4120e79f9aeSGuennadi Liakhovetski if (ret < 0) 4130e79f9aeSGuennadi Liakhovetski goto ecfgtx; 4140e79f9aeSGuennadi Liakhovetski 4150e79f9aeSGuennadi Liakhovetski host->chan_rx = dma_request_channel(mask, shdma_chan_filter, 4160e79f9aeSGuennadi Liakhovetski (void *)pdata->slave_id_rx); 417a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 418a782d688SGuennadi Liakhovetski host->chan_rx); 419a782d688SGuennadi Liakhovetski 4200e79f9aeSGuennadi Liakhovetski if (!host->chan_rx) 4210e79f9aeSGuennadi Liakhovetski goto erqrx; 4220e79f9aeSGuennadi Liakhovetski 4230e79f9aeSGuennadi Liakhovetski cfg.slave_id = pdata->slave_id_rx; 4240e79f9aeSGuennadi Liakhovetski cfg.direction = DMA_DEV_TO_MEM; 4250e79f9aeSGuennadi Liakhovetski cfg.dst_addr = 0; 4260e79f9aeSGuennadi Liakhovetski cfg.src_addr = res->start + MMCIF_CE_DATA; 4270e79f9aeSGuennadi Liakhovetski ret = dmaengine_slave_config(host->chan_rx, &cfg); 4280e79f9aeSGuennadi Liakhovetski if (ret < 0) 4290e79f9aeSGuennadi Liakhovetski goto ecfgrx; 430a782d688SGuennadi Liakhovetski 4310e79f9aeSGuennadi Liakhovetski return; 4320e79f9aeSGuennadi Liakhovetski 4330e79f9aeSGuennadi Liakhovetski ecfgrx: 4340e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_rx); 4350e79f9aeSGuennadi Liakhovetski host->chan_rx = NULL; 4360e79f9aeSGuennadi Liakhovetski erqrx: 4370e79f9aeSGuennadi Liakhovetski ecfgtx: 4380e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 4390e79f9aeSGuennadi Liakhovetski host->chan_tx = NULL; 440a782d688SGuennadi Liakhovetski } 441a782d688SGuennadi Liakhovetski 442a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 443a782d688SGuennadi Liakhovetski { 444a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 445a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 446a782d688SGuennadi Liakhovetski if (host->chan_tx) { 447a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 448a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 449a782d688SGuennadi Liakhovetski dma_release_channel(chan); 450a782d688SGuennadi Liakhovetski } 451a782d688SGuennadi Liakhovetski if (host->chan_rx) { 452a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 453a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 454a782d688SGuennadi Liakhovetski dma_release_channel(chan); 455a782d688SGuennadi Liakhovetski } 456a782d688SGuennadi Liakhovetski 457f38f94c6SLinus Walleij host->dma_active = false; 458a782d688SGuennadi Liakhovetski } 459fdc50a94SYusuke Goda 460fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 461fdc50a94SYusuke Goda { 462fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 463bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 464fdc50a94SYusuke Goda 465fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 466fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 467fdc50a94SYusuke Goda 468fdc50a94SYusuke Goda if (!clk) 469fdc50a94SYusuke Goda return; 470bf68a812SGuennadi Liakhovetski if (sup_pclk && clk == host->clk) 471fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 472fdc50a94SYusuke Goda else 473fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 474f9388257SSimon Horman ((fls(DIV_ROUND_UP(host->clk, 475f9388257SSimon Horman clk) - 1) - 1) << 16)); 476fdc50a94SYusuke Goda 477fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 478fdc50a94SYusuke Goda } 479fdc50a94SYusuke Goda 480fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 481fdc50a94SYusuke Goda { 482fdc50a94SYusuke Goda u32 tmp; 483fdc50a94SYusuke Goda 484487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 485fdc50a94SYusuke Goda 486487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 487487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 488fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 489fdc50a94SYusuke Goda SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 490fdc50a94SYusuke Goda /* byte swap on */ 491fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 492fdc50a94SYusuke Goda } 493fdc50a94SYusuke Goda 494fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 495fdc50a94SYusuke Goda { 496fdc50a94SYusuke Goda u32 state1, state2; 497ee4b8887SGuennadi Liakhovetski int ret, timeout; 498fdc50a94SYusuke Goda 499aa0787a9SGuennadi Liakhovetski host->sd_error = false; 500fdc50a94SYusuke Goda 501487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 502487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 503e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 504e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 505fdc50a94SYusuke Goda 506fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 507fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 508fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 509ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 510487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 511fdc50a94SYusuke Goda & STS1_CMDSEQ)) 512fdc50a94SYusuke Goda break; 513fdc50a94SYusuke Goda mdelay(1); 514fdc50a94SYusuke Goda } 515ee4b8887SGuennadi Liakhovetski if (!timeout) { 516ee4b8887SGuennadi Liakhovetski dev_err(&host->pd->dev, 517ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 518ee4b8887SGuennadi Liakhovetski return -EIO; 519ee4b8887SGuennadi Liakhovetski } 520fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 521e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 522fdc50a94SYusuke Goda return -EIO; 523fdc50a94SYusuke Goda } 524fdc50a94SYusuke Goda 525fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 526e475b270STeppei Kamijou dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", 527e475b270STeppei Kamijou host->state, host->wait_for); 528fdc50a94SYusuke Goda ret = -EIO; 529fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 530e475b270STeppei Kamijou dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", 531e475b270STeppei Kamijou host->state, host->wait_for); 532fdc50a94SYusuke Goda ret = -ETIMEDOUT; 533fdc50a94SYusuke Goda } else { 534e475b270STeppei Kamijou dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", 535e475b270STeppei Kamijou host->state, host->wait_for); 536fdc50a94SYusuke Goda ret = -EIO; 537fdc50a94SYusuke Goda } 538fdc50a94SYusuke Goda return ret; 539fdc50a94SYusuke Goda } 540fdc50a94SYusuke Goda 541f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 542f985da17SGuennadi Liakhovetski { 543f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 544f985da17SGuennadi Liakhovetski 545f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 546f985da17SGuennadi Liakhovetski 547f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 548f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 549f985da17SGuennadi Liakhovetski 550f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 551f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 552f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 553f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 554f985da17SGuennadi Liakhovetski } else { 555f985da17SGuennadi Liakhovetski host->pio_ptr = p; 556f985da17SGuennadi Liakhovetski } 557f985da17SGuennadi Liakhovetski 55899eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 559f985da17SGuennadi Liakhovetski } 560f985da17SGuennadi Liakhovetski 561f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 562fdc50a94SYusuke Goda struct mmc_request *mrq) 563fdc50a94SYusuke Goda { 564f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 565f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 566f985da17SGuennadi Liakhovetski 567f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 568fdc50a94SYusuke Goda 569fdc50a94SYusuke Goda /* buf read enable */ 570fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 571f985da17SGuennadi Liakhovetski } 572fdc50a94SYusuke Goda 573f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 574f985da17SGuennadi Liakhovetski { 575f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 576f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 577f985da17SGuennadi Liakhovetski int i; 578f985da17SGuennadi Liakhovetski 579f985da17SGuennadi Liakhovetski if (host->sd_error) { 580f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 581e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 582f985da17SGuennadi Liakhovetski return false; 583f985da17SGuennadi Liakhovetski } 584f985da17SGuennadi Liakhovetski 585f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 586487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 587fdc50a94SYusuke Goda 588fdc50a94SYusuke Goda /* buffer read end */ 589fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 590f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 591fdc50a94SYusuke Goda 592f985da17SGuennadi Liakhovetski return true; 593fdc50a94SYusuke Goda } 594fdc50a94SYusuke Goda 595f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 596fdc50a94SYusuke Goda struct mmc_request *mrq) 597fdc50a94SYusuke Goda { 598fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 599fdc50a94SYusuke Goda 600f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 601f985da17SGuennadi Liakhovetski return; 602f985da17SGuennadi Liakhovetski 603f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 604f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 605f985da17SGuennadi Liakhovetski 606f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 607f985da17SGuennadi Liakhovetski host->sg_idx = 0; 608f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 609f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6105df460b1SGuennadi Liakhovetski 611fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 612fdc50a94SYusuke Goda } 613fdc50a94SYusuke Goda 614f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 615f985da17SGuennadi Liakhovetski { 616f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 617f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 618f985da17SGuennadi Liakhovetski int i; 619f985da17SGuennadi Liakhovetski 620f985da17SGuennadi Liakhovetski if (host->sd_error) { 621f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 622e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 623f985da17SGuennadi Liakhovetski return false; 624f985da17SGuennadi Liakhovetski } 625f985da17SGuennadi Liakhovetski 626f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 627f985da17SGuennadi Liakhovetski 628f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 629f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 630f985da17SGuennadi Liakhovetski 631f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 632f985da17SGuennadi Liakhovetski return false; 633f985da17SGuennadi Liakhovetski 634f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 635f985da17SGuennadi Liakhovetski 636f985da17SGuennadi Liakhovetski return true; 637f985da17SGuennadi Liakhovetski } 638f985da17SGuennadi Liakhovetski 639f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 640fdc50a94SYusuke Goda struct mmc_request *mrq) 641fdc50a94SYusuke Goda { 642f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 643f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 644fdc50a94SYusuke Goda 645f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 646fdc50a94SYusuke Goda 647fdc50a94SYusuke Goda /* buf write enable */ 648f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 649f985da17SGuennadi Liakhovetski } 650fdc50a94SYusuke Goda 651f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 652f985da17SGuennadi Liakhovetski { 653f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 654f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 655f985da17SGuennadi Liakhovetski int i; 656f985da17SGuennadi Liakhovetski 657f985da17SGuennadi Liakhovetski if (host->sd_error) { 658f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 659e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 660f985da17SGuennadi Liakhovetski return false; 661f985da17SGuennadi Liakhovetski } 662f985da17SGuennadi Liakhovetski 663f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 664487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 665fdc50a94SYusuke Goda 666fdc50a94SYusuke Goda /* buffer write end */ 667fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 668f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 669fdc50a94SYusuke Goda 670f985da17SGuennadi Liakhovetski return true; 671fdc50a94SYusuke Goda } 672fdc50a94SYusuke Goda 673f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 674fdc50a94SYusuke Goda struct mmc_request *mrq) 675fdc50a94SYusuke Goda { 676fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 677fdc50a94SYusuke Goda 678f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 679f985da17SGuennadi Liakhovetski return; 680fdc50a94SYusuke Goda 681f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 682f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 683f985da17SGuennadi Liakhovetski 684f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 685f985da17SGuennadi Liakhovetski host->sg_idx = 0; 686f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 687f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6885df460b1SGuennadi Liakhovetski 689fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 690fdc50a94SYusuke Goda } 691f985da17SGuennadi Liakhovetski 692f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 693f985da17SGuennadi Liakhovetski { 694f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 695f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 696f985da17SGuennadi Liakhovetski int i; 697f985da17SGuennadi Liakhovetski 698f985da17SGuennadi Liakhovetski if (host->sd_error) { 699f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 700e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 701f985da17SGuennadi Liakhovetski return false; 702fdc50a94SYusuke Goda } 703f985da17SGuennadi Liakhovetski 704f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 705f985da17SGuennadi Liakhovetski 706f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 707f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 708f985da17SGuennadi Liakhovetski 709f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 710f985da17SGuennadi Liakhovetski return false; 711f985da17SGuennadi Liakhovetski 712f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 713f985da17SGuennadi Liakhovetski 714f985da17SGuennadi Liakhovetski return true; 715fdc50a94SYusuke Goda } 716fdc50a94SYusuke Goda 717fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 718fdc50a94SYusuke Goda struct mmc_command *cmd) 719fdc50a94SYusuke Goda { 720fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 721487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 722487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 723487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 724487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 725fdc50a94SYusuke Goda } else 726487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 727fdc50a94SYusuke Goda } 728fdc50a94SYusuke Goda 729fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 730fdc50a94SYusuke Goda struct mmc_command *cmd) 731fdc50a94SYusuke Goda { 732487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 733fdc50a94SYusuke Goda } 734fdc50a94SYusuke Goda 735fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 73669983404SGuennadi Liakhovetski struct mmc_request *mrq) 737fdc50a94SYusuke Goda { 73869983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 73969983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 74069983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 741fdc50a94SYusuke Goda u32 tmp = 0; 742fdc50a94SYusuke Goda 743fdc50a94SYusuke Goda /* Response Type check */ 744fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 745fdc50a94SYusuke Goda case MMC_RSP_NONE: 746fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 747fdc50a94SYusuke Goda break; 748fdc50a94SYusuke Goda case MMC_RSP_R1: 749fdc50a94SYusuke Goda case MMC_RSP_R1B: 750fdc50a94SYusuke Goda case MMC_RSP_R3: 751fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 752fdc50a94SYusuke Goda break; 753fdc50a94SYusuke Goda case MMC_RSP_R2: 754fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 755fdc50a94SYusuke Goda break; 756fdc50a94SYusuke Goda default: 757e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 758fdc50a94SYusuke Goda break; 759fdc50a94SYusuke Goda } 760fdc50a94SYusuke Goda switch (opc) { 761fdc50a94SYusuke Goda /* RBSY */ 762a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 763fdc50a94SYusuke Goda case MMC_SWITCH: 764fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 765fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 766fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 767fdc50a94SYusuke Goda case MMC_ERASE: 768fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 769fdc50a94SYusuke Goda break; 770fdc50a94SYusuke Goda } 771fdc50a94SYusuke Goda /* WDAT / DATW */ 77269983404SGuennadi Liakhovetski if (data) { 773fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 774fdc50a94SYusuke Goda switch (host->bus_width) { 775fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 776fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 777fdc50a94SYusuke Goda break; 778fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 779fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 780fdc50a94SYusuke Goda break; 781fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 782fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 783fdc50a94SYusuke Goda break; 784fdc50a94SYusuke Goda default: 785e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 786fdc50a94SYusuke Goda break; 787fdc50a94SYusuke Goda } 788555061f9STeppei Kamijou switch (host->timing) { 789555061f9STeppei Kamijou case MMC_TIMING_UHS_DDR50: 790555061f9STeppei Kamijou /* 791555061f9STeppei Kamijou * MMC core will only set this timing, if the host 792555061f9STeppei Kamijou * advertises the MMC_CAP_UHS_DDR50 capability. MMCIF 793555061f9STeppei Kamijou * implementations with this capability, e.g. sh73a0, 794555061f9STeppei Kamijou * will have to set it in their platform data. 795555061f9STeppei Kamijou */ 796555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 797555061f9STeppei Kamijou break; 798555061f9STeppei Kamijou } 799fdc50a94SYusuke Goda } 800fdc50a94SYusuke Goda /* DWEN */ 801fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 802fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 803fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 804fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 805fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 806fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 80769983404SGuennadi Liakhovetski data->blocks << 16); 808fdc50a94SYusuke Goda } 809fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 810fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 811fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 812fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 813fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 814fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 815fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 816fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 817fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 818fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 819fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 820fdc50a94SYusuke Goda 82169983404SGuennadi Liakhovetski return (opc << 24) | tmp; 822fdc50a94SYusuke Goda } 823fdc50a94SYusuke Goda 824e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 825fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 826fdc50a94SYusuke Goda { 827fdc50a94SYusuke Goda switch (opc) { 828fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 829f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 830f985da17SGuennadi Liakhovetski return 0; 831fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 832f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 833f985da17SGuennadi Liakhovetski return 0; 834fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 835f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 836f985da17SGuennadi Liakhovetski return 0; 837fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 838fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 839f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 840f985da17SGuennadi Liakhovetski return 0; 841fdc50a94SYusuke Goda default: 842e475b270STeppei Kamijou dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); 843ee4b8887SGuennadi Liakhovetski return -EINVAL; 844fdc50a94SYusuke Goda } 845fdc50a94SYusuke Goda } 846fdc50a94SYusuke Goda 847fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 848ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 849fdc50a94SYusuke Goda { 850ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 851f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 852f985da17SGuennadi Liakhovetski u32 mask; 853fdc50a94SYusuke Goda 854fdc50a94SYusuke Goda switch (opc) { 855ee4b8887SGuennadi Liakhovetski /* response busy check */ 856a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 857fdc50a94SYusuke Goda case MMC_SWITCH: 858fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 859fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 860fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 861fdc50a94SYusuke Goda case MMC_ERASE: 862ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 863fdc50a94SYusuke Goda break; 864fdc50a94SYusuke Goda default: 865ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 866fdc50a94SYusuke Goda break; 867fdc50a94SYusuke Goda } 868fdc50a94SYusuke Goda 86969983404SGuennadi Liakhovetski if (mrq->data) { 870487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 871487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 872487d9fc5SMagnus Damm mrq->data->blksz); 873fdc50a94SYusuke Goda } 87469983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 875fdc50a94SYusuke Goda 876487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 877487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 878fdc50a94SYusuke Goda /* set arg */ 879487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 880fdc50a94SYusuke Goda /* set cmd */ 881487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 882fdc50a94SYusuke Goda 883f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 884f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 885fdc50a94SYusuke Goda } 886fdc50a94SYusuke Goda 887fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 888ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 889fdc50a94SYusuke Goda { 89069983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 89169983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 892fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 89369983404SGuennadi Liakhovetski break; 89469983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 895fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 89669983404SGuennadi Liakhovetski break; 89769983404SGuennadi Liakhovetski default: 898e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 89969983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 900fdc50a94SYusuke Goda return; 901fdc50a94SYusuke Goda } 902fdc50a94SYusuke Goda 903f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 904fdc50a94SYusuke Goda } 905fdc50a94SYusuke Goda 906fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 907fdc50a94SYusuke Goda { 908fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9093b0beafcSGuennadi Liakhovetski unsigned long flags; 9103b0beafcSGuennadi Liakhovetski 9113b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9123b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 913e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 9143b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9153b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9163b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9173b0beafcSGuennadi Liakhovetski return; 9183b0beafcSGuennadi Liakhovetski } 9193b0beafcSGuennadi Liakhovetski 9203b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9213b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 922fdc50a94SYusuke Goda 923fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 924fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 9257541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 9267541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 9277541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 9287541ca98SLaurent Pinchart break; 929fdc50a94SYusuke Goda case MMC_APP_CMD: 93092ff0c5bSTeppei Kamijou case SD_IO_RW_DIRECT: 9313b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 932fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 933fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 934fdc50a94SYusuke Goda return; 935fdc50a94SYusuke Goda default: 936fdc50a94SYusuke Goda break; 937fdc50a94SYusuke Goda } 938fdc50a94SYusuke Goda 939f985da17SGuennadi Liakhovetski host->mrq = mrq; 940f985da17SGuennadi Liakhovetski 941f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 942fdc50a94SYusuke Goda } 943fdc50a94SYusuke Goda 944a6609267SGuennadi Liakhovetski static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 945a6609267SGuennadi Liakhovetski { 946a6609267SGuennadi Liakhovetski int ret = clk_enable(host->hclk); 947a6609267SGuennadi Liakhovetski 948a6609267SGuennadi Liakhovetski if (!ret) { 949a6609267SGuennadi Liakhovetski host->clk = clk_get_rate(host->hclk); 950a6609267SGuennadi Liakhovetski host->mmc->f_max = host->clk / 2; 951a6609267SGuennadi Liakhovetski host->mmc->f_min = host->clk / 512; 952a6609267SGuennadi Liakhovetski } 953a6609267SGuennadi Liakhovetski 954a6609267SGuennadi Liakhovetski return ret; 955a6609267SGuennadi Liakhovetski } 956a6609267SGuennadi Liakhovetski 9577d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 9587d17baa0SGuennadi Liakhovetski { 9597d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 9607d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 9617d17baa0SGuennadi Liakhovetski 962bf68a812SGuennadi Liakhovetski if (pd && pd->set_pwr) 9637d17baa0SGuennadi Liakhovetski pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF); 9647d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 9657d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 9667d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 9677d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 9687d17baa0SGuennadi Liakhovetski } 9697d17baa0SGuennadi Liakhovetski 970fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 971fdc50a94SYusuke Goda { 972fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9733b0beafcSGuennadi Liakhovetski unsigned long flags; 9743b0beafcSGuennadi Liakhovetski 9753b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9763b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 977e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 9783b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9793b0beafcSGuennadi Liakhovetski return; 9803b0beafcSGuennadi Liakhovetski } 9813b0beafcSGuennadi Liakhovetski 9823b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 9833b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 984fdc50a94SYusuke Goda 985f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 986c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 987faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 988faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 989c9b0cef2SGuennadi Liakhovetski host->card_present = true; 990faca6648SGuennadi Liakhovetski } 9917d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 992f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 993f5e0cec4SGuennadi Liakhovetski /* clock stop */ 994f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 995faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 996c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 997c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 998c9b0cef2SGuennadi Liakhovetski host->card_present = false; 999c9b0cef2SGuennadi Liakhovetski } 1000c9b0cef2SGuennadi Liakhovetski } 1001faca6648SGuennadi Liakhovetski if (host->power) { 1002f8a8ced7STeppei Kamijou pm_runtime_put_sync(&host->pd->dev); 1003b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 1004faca6648SGuennadi Liakhovetski host->power = false; 10057d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 10067d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1007faca6648SGuennadi Liakhovetski } 10083b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1009f5e0cec4SGuennadi Liakhovetski return; 1010fdc50a94SYusuke Goda } 1011fdc50a94SYusuke Goda 1012c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 1013c9b0cef2SGuennadi Liakhovetski if (!host->power) { 1014a6609267SGuennadi Liakhovetski sh_mmcif_clk_update(host); 1015c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 1016c9b0cef2SGuennadi Liakhovetski host->power = true; 1017c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 1018c9b0cef2SGuennadi Liakhovetski } 1019fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 1020c9b0cef2SGuennadi Liakhovetski } 1021fdc50a94SYusuke Goda 1022555061f9STeppei Kamijou host->timing = ios->timing; 1023fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10243b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1025fdc50a94SYusuke Goda } 1026fdc50a94SYusuke Goda 1027777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1028777271d0SArnd Hannemann { 1029777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1030777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1031e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1032e480606aSGuennadi Liakhovetski 1033e480606aSGuennadi Liakhovetski if (ret >= 0) 1034e480606aSGuennadi Liakhovetski return ret; 1035777271d0SArnd Hannemann 1036bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1037777271d0SArnd Hannemann return -ENOSYS; 1038777271d0SArnd Hannemann else 1039777271d0SArnd Hannemann return p->get_cd(host->pd); 1040777271d0SArnd Hannemann } 1041777271d0SArnd Hannemann 1042fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1043fdc50a94SYusuke Goda .request = sh_mmcif_request, 1044fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1045777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1046fdc50a94SYusuke Goda }; 1047fdc50a94SYusuke Goda 1048f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1049f985da17SGuennadi Liakhovetski { 1050f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 105169983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1052f985da17SGuennadi Liakhovetski long time; 1053f985da17SGuennadi Liakhovetski 1054f985da17SGuennadi Liakhovetski if (host->sd_error) { 1055f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1056f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1057f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1058f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1059f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1060f985da17SGuennadi Liakhovetski break; 1061f985da17SGuennadi Liakhovetski default: 1062f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1063f985da17SGuennadi Liakhovetski break; 1064f985da17SGuennadi Liakhovetski } 1065e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "CMD%d error %d\n", 1066e475b270STeppei Kamijou cmd->opcode, cmd->error); 1067aba9d646SGuennadi Liakhovetski host->sd_error = false; 1068f985da17SGuennadi Liakhovetski return false; 1069f985da17SGuennadi Liakhovetski } 1070f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1071f985da17SGuennadi Liakhovetski cmd->error = 0; 1072f985da17SGuennadi Liakhovetski return false; 1073f985da17SGuennadi Liakhovetski } 1074f985da17SGuennadi Liakhovetski 1075f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1076f985da17SGuennadi Liakhovetski 107769983404SGuennadi Liakhovetski if (!data) 1078f985da17SGuennadi Liakhovetski return false; 1079f985da17SGuennadi Liakhovetski 108090f1cb43SGuennadi Liakhovetski /* 108190f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to 108290f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active 108390f1cb43SGuennadi Liakhovetski */ 108490f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete); 108590f1cb43SGuennadi Liakhovetski 108669983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1087f985da17SGuennadi Liakhovetski if (host->chan_rx) 1088f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1089f985da17SGuennadi Liakhovetski } else { 1090f985da17SGuennadi Liakhovetski if (host->chan_tx) 1091f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1092f985da17SGuennadi Liakhovetski } 1093f985da17SGuennadi Liakhovetski 1094f985da17SGuennadi Liakhovetski if (!host->dma_active) { 109569983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 109699eb9d8dSGuennadi Liakhovetski return !data->error; 1097f985da17SGuennadi Liakhovetski } 1098f985da17SGuennadi Liakhovetski 1099f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1100f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1101f985da17SGuennadi Liakhovetski host->timeout); 1102eae30983STeppei Kamijou 1103eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1104eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1105eae30983STeppei Kamijou data->sg, data->sg_len, 1106eae30983STeppei Kamijou DMA_FROM_DEVICE); 1107eae30983STeppei Kamijou else 1108eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1109eae30983STeppei Kamijou data->sg, data->sg_len, 1110eae30983STeppei Kamijou DMA_TO_DEVICE); 1111eae30983STeppei Kamijou 1112f985da17SGuennadi Liakhovetski if (host->sd_error) { 1113f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1114f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1115f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 111669983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1117f985da17SGuennadi Liakhovetski } else if (!time) { 1118e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n"); 111969983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1120f985da17SGuennadi Liakhovetski } else if (time < 0) { 1121e475b270STeppei Kamijou dev_err(host->mmc->parent, 1122e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time); 112369983404SGuennadi Liakhovetski data->error = time; 1124f985da17SGuennadi Liakhovetski } 1125f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1126f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1127f985da17SGuennadi Liakhovetski host->dma_active = false; 1128f985da17SGuennadi Liakhovetski 1129eae30983STeppei Kamijou if (data->error) { 113069983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1131eae30983STeppei Kamijou /* Abort DMA */ 1132eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1133eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1134eae30983STeppei Kamijou else 1135eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1136eae30983STeppei Kamijou } 1137f985da17SGuennadi Liakhovetski 1138f985da17SGuennadi Liakhovetski return false; 1139f985da17SGuennadi Liakhovetski } 1140f985da17SGuennadi Liakhovetski 1141f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1142f985da17SGuennadi Liakhovetski { 1143f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 11448047310eSGuennadi Liakhovetski struct mmc_request *mrq; 11455df460b1SGuennadi Liakhovetski bool wait = false; 1146f985da17SGuennadi Liakhovetski 1147f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1148f985da17SGuennadi Liakhovetski 11498047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 11508047310eSGuennadi Liakhovetski 11518047310eSGuennadi Liakhovetski mrq = host->mrq; 11528047310eSGuennadi Liakhovetski if (!mrq) { 11538047310eSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 11548047310eSGuennadi Liakhovetski host->state, host->wait_for); 11558047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 11568047310eSGuennadi Liakhovetski return IRQ_HANDLED; 11578047310eSGuennadi Liakhovetski } 11588047310eSGuennadi Liakhovetski 1159f985da17SGuennadi Liakhovetski /* 1160f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1161f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1162f985da17SGuennadi Liakhovetski */ 1163f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1164f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1165f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 11668047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1167f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1168f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 11695df460b1SGuennadi Liakhovetski /* Wait for data? */ 11705df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1171f985da17SGuennadi Liakhovetski break; 1172f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 11735df460b1SGuennadi Liakhovetski /* Wait for more data? */ 11745df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1175f985da17SGuennadi Liakhovetski break; 1176f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 11775df460b1SGuennadi Liakhovetski /* Wait for data end? */ 11785df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1179f985da17SGuennadi Liakhovetski break; 1180f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 11815df460b1SGuennadi Liakhovetski /* Wait data to write? */ 11825df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1183f985da17SGuennadi Liakhovetski break; 1184f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 11855df460b1SGuennadi Liakhovetski /* Wait for data end? */ 11865df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1187f985da17SGuennadi Liakhovetski break; 1188f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1189f985da17SGuennadi Liakhovetski if (host->sd_error) { 1190f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1191e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); 1192f985da17SGuennadi Liakhovetski break; 1193f985da17SGuennadi Liakhovetski } 1194f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1195f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1196f985da17SGuennadi Liakhovetski break; 1197f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1198f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1199e475b270STeppei Kamijou if (host->sd_error) { 120091ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1201e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); 1202e475b270STeppei Kamijou } 1203f985da17SGuennadi Liakhovetski break; 1204f985da17SGuennadi Liakhovetski default: 1205f985da17SGuennadi Liakhovetski BUG(); 1206f985da17SGuennadi Liakhovetski } 1207f985da17SGuennadi Liakhovetski 12085df460b1SGuennadi Liakhovetski if (wait) { 12095df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12105df460b1SGuennadi Liakhovetski /* Wait for more data */ 12118047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12125df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 12135df460b1SGuennadi Liakhovetski } 12145df460b1SGuennadi Liakhovetski 1215f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 121691ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 121769983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 121869983404SGuennadi Liakhovetski data->bytes_xfered = 121969983404SGuennadi Liakhovetski data->blocks * data->blksz; 1220f985da17SGuennadi Liakhovetski 122169983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1222f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 12235df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 12245df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12258047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1226f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1227f985da17SGuennadi Liakhovetski } 1228f985da17SGuennadi Liakhovetski } 12295df460b1SGuennadi Liakhovetski } 1230f985da17SGuennadi Liakhovetski 1231f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1232f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 123369983404SGuennadi Liakhovetski host->mrq = NULL; 1234f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1235f985da17SGuennadi Liakhovetski 12368047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12378047310eSGuennadi Liakhovetski 1238f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1239f985da17SGuennadi Liakhovetski } 1240f985da17SGuennadi Liakhovetski 1241fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1242fdc50a94SYusuke Goda { 1243fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1244aa0787a9SGuennadi Liakhovetski u32 state; 1245fdc50a94SYusuke Goda 1246487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 12478af50750SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 12488af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1249fdc50a94SYusuke Goda 12508af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN) 12518af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", 12528af50750SGuennadi Liakhovetski state); 12538af50750SGuennadi Liakhovetski 12548af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) { 1255aa0787a9SGuennadi Liakhovetski host->sd_error = true; 12568af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); 1257fdc50a94SYusuke Goda } 1258f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 12598af50750SGuennadi Liakhovetski if (!host->mrq) 12608af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); 1261f985da17SGuennadi Liakhovetski if (!host->dma_active) 1262f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1263f985da17SGuennadi Liakhovetski else if (host->sd_error) 1264f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1265f985da17SGuennadi Liakhovetski } else { 1266aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1267f985da17SGuennadi Liakhovetski } 1268fdc50a94SYusuke Goda 1269fdc50a94SYusuke Goda return IRQ_HANDLED; 1270fdc50a94SYusuke Goda } 1271fdc50a94SYusuke Goda 1272f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1273f985da17SGuennadi Liakhovetski { 1274f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1275f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1276f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 12778047310eSGuennadi Liakhovetski unsigned long flags; 1278f985da17SGuennadi Liakhovetski 1279f985da17SGuennadi Liakhovetski if (host->dying) 1280f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1281f985da17SGuennadi Liakhovetski return; 1282f985da17SGuennadi Liakhovetski 1283e475b270STeppei Kamijou dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", 12848047310eSGuennadi Liakhovetski host->wait_for, mrq->cmd->opcode); 12858047310eSGuennadi Liakhovetski 12868047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 12878047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 12888047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 12898047310eSGuennadi Liakhovetski return; 12908047310eSGuennadi Liakhovetski } 12918047310eSGuennadi Liakhovetski 12928047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 12938047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 12948047310eSGuennadi Liakhovetski 1295f985da17SGuennadi Liakhovetski /* 1296f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1297f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1298f985da17SGuennadi Liakhovetski */ 1299f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1300f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1301f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1302f985da17SGuennadi Liakhovetski break; 1303f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1304f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1305f985da17SGuennadi Liakhovetski break; 1306f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1307f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1308f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1309f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1310f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1311f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 131269983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1313f985da17SGuennadi Liakhovetski break; 1314f985da17SGuennadi Liakhovetski default: 1315f985da17SGuennadi Liakhovetski BUG(); 1316f985da17SGuennadi Liakhovetski } 1317f985da17SGuennadi Liakhovetski 1318f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1319f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1320f985da17SGuennadi Liakhovetski host->mrq = NULL; 1321f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1322f985da17SGuennadi Liakhovetski } 1323f985da17SGuennadi Liakhovetski 13247d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 13257d17baa0SGuennadi Liakhovetski { 13267d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 13277d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 13287d17baa0SGuennadi Liakhovetski 13297d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 13307d17baa0SGuennadi Liakhovetski 1331bf68a812SGuennadi Liakhovetski if (!pd) 1332bf68a812SGuennadi Liakhovetski return; 1333bf68a812SGuennadi Liakhovetski 13347d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 13357d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 13367d17baa0SGuennadi Liakhovetski else if (pd->ocr) 13377d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 13387d17baa0SGuennadi Liakhovetski } 13397d17baa0SGuennadi Liakhovetski 1340c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1341fdc50a94SYusuke Goda { 1342fdc50a94SYusuke Goda int ret = 0, irq[2]; 1343fdc50a94SYusuke Goda struct mmc_host *mmc; 1344e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1345e1aae2ebSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1346fdc50a94SYusuke Goda struct resource *res; 1347fdc50a94SYusuke Goda void __iomem *reg; 13482cd5b3e0SShinya Kuribayashi const char *name; 1349fdc50a94SYusuke Goda 1350fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1351fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 13522cd5b3e0SShinya Kuribayashi if (irq[0] < 0) { 1353e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1354fdc50a94SYusuke Goda return -ENXIO; 1355fdc50a94SYusuke Goda } 1356fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1357fdc50a94SYusuke Goda if (!res) { 1358fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1359fdc50a94SYusuke Goda return -ENXIO; 1360fdc50a94SYusuke Goda } 1361fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1362fdc50a94SYusuke Goda if (!reg) { 1363fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1364fdc50a94SYusuke Goda return -ENOMEM; 1365fdc50a94SYusuke Goda } 1366e1aae2ebSGuennadi Liakhovetski 1367fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1368fdc50a94SYusuke Goda if (!mmc) { 1369fdc50a94SYusuke Goda ret = -ENOMEM; 1370e1aae2ebSGuennadi Liakhovetski goto ealloch; 1371fdc50a94SYusuke Goda } 1372fdc50a94SYusuke Goda host = mmc_priv(mmc); 1373fdc50a94SYusuke Goda host->mmc = mmc; 1374fdc50a94SYusuke Goda host->addr = reg; 1375f9fd54f2STeppei Kamijou host->timeout = msecs_to_jiffies(1000); 1376fdc50a94SYusuke Goda 1377fdc50a94SYusuke Goda host->pd = pdev; 1378fdc50a94SYusuke Goda 13793b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1380fdc50a94SYusuke Goda 1381fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 13827d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 13837d17baa0SGuennadi Liakhovetski 1384a812ba0fSTeppei Kamijou mmc->caps = MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1385bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1386fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1387a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1388fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1389a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1390a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1391fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1392fdc50a94SYusuke Goda 1393fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1394a782d688SGuennadi Liakhovetski 1395faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1396faca6648SGuennadi Liakhovetski host->power = false; 1397faca6648SGuennadi Liakhovetski 1398047a9ce7SGuennadi Liakhovetski host->hclk = clk_get(&pdev->dev, NULL); 1399b289174fSGuennadi Liakhovetski if (IS_ERR(host->hclk)) { 1400b289174fSGuennadi Liakhovetski ret = PTR_ERR(host->hclk); 1401047a9ce7SGuennadi Liakhovetski dev_err(&pdev->dev, "cannot get clock: %d\n", ret); 1402b289174fSGuennadi Liakhovetski goto eclkget; 1403b289174fSGuennadi Liakhovetski } 1404a6609267SGuennadi Liakhovetski ret = sh_mmcif_clk_update(host); 1405a6609267SGuennadi Liakhovetski if (ret < 0) 1406a6609267SGuennadi Liakhovetski goto eclkupdate; 1407b289174fSGuennadi Liakhovetski 1408faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1409faca6648SGuennadi Liakhovetski if (ret < 0) 1410e1aae2ebSGuennadi Liakhovetski goto eresume; 1411a782d688SGuennadi Liakhovetski 14125ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1413fdc50a94SYusuke Goda 1414b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 14153b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14163b0beafcSGuennadi Liakhovetski 14172cd5b3e0SShinya Kuribayashi name = irq[1] < 0 ? dev_name(&pdev->dev) : "sh_mmc:error"; 14182cd5b3e0SShinya Kuribayashi ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, name, host); 1419fdc50a94SYusuke Goda if (ret) { 14202cd5b3e0SShinya Kuribayashi dev_err(&pdev->dev, "request_irq error (%s)\n", name); 1421e1aae2ebSGuennadi Liakhovetski goto ereqirq0; 1422fdc50a94SYusuke Goda } 14232cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 14242cd5b3e0SShinya Kuribayashi ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 14252cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1426fdc50a94SYusuke Goda if (ret) { 1427e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1428e1aae2ebSGuennadi Liakhovetski goto ereqirq1; 1429fdc50a94SYusuke Goda } 14302cd5b3e0SShinya Kuribayashi } 1431fdc50a94SYusuke Goda 1432e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1433e480606aSGuennadi Liakhovetski ret = mmc_gpio_request_cd(mmc, pd->cd_gpio); 1434e480606aSGuennadi Liakhovetski if (ret < 0) 1435e480606aSGuennadi Liakhovetski goto erqcd; 1436e480606aSGuennadi Liakhovetski } 1437e480606aSGuennadi Liakhovetski 14388047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 14398047310eSGuennadi Liakhovetski 1440b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 14415ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 14425ba85d95SGuennadi Liakhovetski if (ret < 0) 1443e1aae2ebSGuennadi Liakhovetski goto emmcaddh; 1444fdc50a94SYusuke Goda 1445efe6a8adSRafael J. Wysocki dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1446efe6a8adSRafael J. Wysocki 1447e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1448e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1449487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1450fdc50a94SYusuke Goda return ret; 1451fdc50a94SYusuke Goda 1452e1aae2ebSGuennadi Liakhovetski emmcaddh: 1453e480606aSGuennadi Liakhovetski erqcd: 14542cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) 14555ba85d95SGuennadi Liakhovetski free_irq(irq[1], host); 1456e1aae2ebSGuennadi Liakhovetski ereqirq1: 14575ba85d95SGuennadi Liakhovetski free_irq(irq[0], host); 1458e1aae2ebSGuennadi Liakhovetski ereqirq0: 1459faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1460e1aae2ebSGuennadi Liakhovetski eresume: 1461fdc50a94SYusuke Goda clk_disable(host->hclk); 1462a6609267SGuennadi Liakhovetski eclkupdate: 1463b289174fSGuennadi Liakhovetski clk_put(host->hclk); 1464e1aae2ebSGuennadi Liakhovetski eclkget: 1465b289174fSGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1466fdc50a94SYusuke Goda mmc_free_host(mmc); 1467e1aae2ebSGuennadi Liakhovetski ealloch: 1468fdc50a94SYusuke Goda iounmap(reg); 1469fdc50a94SYusuke Goda return ret; 1470fdc50a94SYusuke Goda } 1471fdc50a94SYusuke Goda 14726e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1473fdc50a94SYusuke Goda { 1474fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1475fdc50a94SYusuke Goda int irq[2]; 1476fdc50a94SYusuke Goda 1477f985da17SGuennadi Liakhovetski host->dying = true; 1478b289174fSGuennadi Liakhovetski clk_enable(host->hclk); 1479faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1480aa0787a9SGuennadi Liakhovetski 1481efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1482efe6a8adSRafael J. Wysocki 1483faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 14843b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14853b0beafcSGuennadi Liakhovetski 1486f985da17SGuennadi Liakhovetski /* 1487f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1488f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1489f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1490f985da17SGuennadi Liakhovetski */ 1491f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1492f985da17SGuennadi Liakhovetski 1493aa0787a9SGuennadi Liakhovetski if (host->addr) 1494aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1495aa0787a9SGuennadi Liakhovetski 1496fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1497fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1498fdc50a94SYusuke Goda 1499fdc50a94SYusuke Goda free_irq(irq[0], host); 15002cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) 1501fdc50a94SYusuke Goda free_irq(irq[1], host); 1502fdc50a94SYusuke Goda 1503aa0787a9SGuennadi Liakhovetski platform_set_drvdata(pdev, NULL); 1504aa0787a9SGuennadi Liakhovetski 1505a0d28ba0SGuennadi Liakhovetski clk_disable(host->hclk); 1506fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1507faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1508faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1509fdc50a94SYusuke Goda 1510fdc50a94SYusuke Goda return 0; 1511fdc50a94SYusuke Goda } 1512fdc50a94SYusuke Goda 1513faca6648SGuennadi Liakhovetski #ifdef CONFIG_PM 1514faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1515faca6648SGuennadi Liakhovetski { 1516b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1517faca6648SGuennadi Liakhovetski int ret = mmc_suspend_host(host->mmc); 1518faca6648SGuennadi Liakhovetski 1519b289174fSGuennadi Liakhovetski if (!ret) 1520faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1521faca6648SGuennadi Liakhovetski 1522faca6648SGuennadi Liakhovetski return ret; 1523faca6648SGuennadi Liakhovetski } 1524faca6648SGuennadi Liakhovetski 1525faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1526faca6648SGuennadi Liakhovetski { 1527b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1528faca6648SGuennadi Liakhovetski 1529faca6648SGuennadi Liakhovetski return mmc_resume_host(host->mmc); 1530faca6648SGuennadi Liakhovetski } 1531faca6648SGuennadi Liakhovetski #else 1532faca6648SGuennadi Liakhovetski #define sh_mmcif_suspend NULL 1533faca6648SGuennadi Liakhovetski #define sh_mmcif_resume NULL 1534faca6648SGuennadi Liakhovetski #endif /* CONFIG_PM */ 1535faca6648SGuennadi Liakhovetski 1536bf68a812SGuennadi Liakhovetski static const struct of_device_id mmcif_of_match[] = { 1537bf68a812SGuennadi Liakhovetski { .compatible = "renesas,sh-mmcif" }, 1538bf68a812SGuennadi Liakhovetski { } 1539bf68a812SGuennadi Liakhovetski }; 1540bf68a812SGuennadi Liakhovetski MODULE_DEVICE_TABLE(of, mmcif_of_match); 1541bf68a812SGuennadi Liakhovetski 1542faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1543faca6648SGuennadi Liakhovetski .suspend = sh_mmcif_suspend, 1544faca6648SGuennadi Liakhovetski .resume = sh_mmcif_resume, 1545faca6648SGuennadi Liakhovetski }; 1546faca6648SGuennadi Liakhovetski 1547fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1548fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1549fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1550fdc50a94SYusuke Goda .driver = { 1551fdc50a94SYusuke Goda .name = DRIVER_NAME, 1552faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1553bf68a812SGuennadi Liakhovetski .owner = THIS_MODULE, 1554bf68a812SGuennadi Liakhovetski .of_match_table = mmcif_of_match, 1555fdc50a94SYusuke Goda }, 1556fdc50a94SYusuke Goda }; 1557fdc50a94SYusuke Goda 1558d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1559fdc50a94SYusuke Goda 1560fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1561fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1562aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1563fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1564