1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 59a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 60e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 61efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 62faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 633b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6488b47679SPaul Gortmaker #include <linux/module.h> 65fdc50a94SYusuke Goda 66fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 67fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 68fdc50a94SYusuke Goda 69fdc50a94SYusuke Goda /* CE_CMD_SET */ 70fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 71fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 72fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 73fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 74fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 75fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 76fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 77fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 78fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 79fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 80fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 81fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 82fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 83fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 84fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 85fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 86fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 88fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 89fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 90fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 91fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 92fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 93fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 94fdc50a94SYusuke Goda 95fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 96fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 97fdc50a94SYusuke Goda 98fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 99fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 100fdc50a94SYusuke Goda 101fdc50a94SYusuke Goda /* CE_INT */ 102fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 103fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 104fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 105fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 106fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 107fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 108fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 109fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 110fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 111fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 112fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 113fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 114fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 115fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 116fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 117fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 118fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 119fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 120fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 121fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 122fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 123fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 124fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 125fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 126fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 127fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 128fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 129fdc50a94SYusuke Goda 130fdc50a94SYusuke Goda /* CE_INT_MASK */ 131fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 132fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 133fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 134fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 135fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 136fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 137fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 138fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 139fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 140fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 141fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 142fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 143fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 144fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 145fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 146fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 147fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 148fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 149fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 150fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 151fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 152fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 153fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 154fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 155fdc50a94SYusuke Goda 156ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 157ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 158ee4b8887SGuennadi Liakhovetski MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ 159ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 160ee4b8887SGuennadi Liakhovetski 161fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 162fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 163fdc50a94SYusuke Goda 164fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 165fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 166fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 167fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 168fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 169fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 170fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 171fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 172fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 173fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 174fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 175fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 176fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 177fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 178fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 179fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 180fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 181fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 182fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 183fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 184fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 185fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 186fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 187fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 188fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 189fdc50a94SYusuke Goda 190fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 191fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 192fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 193fdc50a94SYusuke Goda 1943b0beafcSGuennadi Liakhovetski enum mmcif_state { 1953b0beafcSGuennadi Liakhovetski STATE_IDLE, 1963b0beafcSGuennadi Liakhovetski STATE_REQUEST, 1973b0beafcSGuennadi Liakhovetski STATE_IOS, 1983b0beafcSGuennadi Liakhovetski }; 1993b0beafcSGuennadi Liakhovetski 200f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 201f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 202f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 203f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 204f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 205f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 206f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 207f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 208f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 209f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 210f985da17SGuennadi Liakhovetski }; 211f985da17SGuennadi Liakhovetski 212fdc50a94SYusuke Goda struct sh_mmcif_host { 213fdc50a94SYusuke Goda struct mmc_host *mmc; 214f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 215fdc50a94SYusuke Goda struct platform_device *pd; 216fdc50a94SYusuke Goda struct clk *hclk; 217fdc50a94SYusuke Goda unsigned int clk; 218fdc50a94SYusuke Goda int bus_width; 219aa0787a9SGuennadi Liakhovetski bool sd_error; 220f985da17SGuennadi Liakhovetski bool dying; 221fdc50a94SYusuke Goda long timeout; 222fdc50a94SYusuke Goda void __iomem *addr; 223f985da17SGuennadi Liakhovetski u32 *pio_ptr; 224ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2253b0beafcSGuennadi Liakhovetski enum mmcif_state state; 226f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 227f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 228f985da17SGuennadi Liakhovetski size_t blocksize; 229f985da17SGuennadi Liakhovetski int sg_idx; 230f985da17SGuennadi Liakhovetski int sg_blkidx; 231faca6648SGuennadi Liakhovetski bool power; 232c9b0cef2SGuennadi Liakhovetski bool card_present; 233fdc50a94SYusuke Goda 234a782d688SGuennadi Liakhovetski /* DMA support */ 235a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 236a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 237a782d688SGuennadi Liakhovetski struct completion dma_complete; 238f38f94c6SLinus Walleij bool dma_active; 239a782d688SGuennadi Liakhovetski }; 240fdc50a94SYusuke Goda 241fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 242fdc50a94SYusuke Goda unsigned int reg, u32 val) 243fdc50a94SYusuke Goda { 244487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 245fdc50a94SYusuke Goda } 246fdc50a94SYusuke Goda 247fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 248fdc50a94SYusuke Goda unsigned int reg, u32 val) 249fdc50a94SYusuke Goda { 250487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 251fdc50a94SYusuke Goda } 252fdc50a94SYusuke Goda 253a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 254a782d688SGuennadi Liakhovetski { 255a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 25669983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 25769983404SGuennadi Liakhovetski 258a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 259a782d688SGuennadi Liakhovetski 26069983404SGuennadi Liakhovetski if (WARN(!data, "%s: NULL data in DMA completion!\n", 261a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 262a782d688SGuennadi Liakhovetski return; 263a782d688SGuennadi Liakhovetski 26469983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) 2651ed828dbSLinus Walleij dma_unmap_sg(host->chan_rx->device->dev, 26669983404SGuennadi Liakhovetski data->sg, data->sg_len, 267a782d688SGuennadi Liakhovetski DMA_FROM_DEVICE); 268a782d688SGuennadi Liakhovetski else 2691ed828dbSLinus Walleij dma_unmap_sg(host->chan_tx->device->dev, 27069983404SGuennadi Liakhovetski data->sg, data->sg_len, 271a782d688SGuennadi Liakhovetski DMA_TO_DEVICE); 272a782d688SGuennadi Liakhovetski 273a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 274a782d688SGuennadi Liakhovetski } 275a782d688SGuennadi Liakhovetski 276a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 277a782d688SGuennadi Liakhovetski { 27869983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 27969983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 280a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 281a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 282a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 283a782d688SGuennadi Liakhovetski int ret; 284a782d688SGuennadi Liakhovetski 28569983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 2861ed828dbSLinus Walleij DMA_FROM_DEVICE); 287a782d688SGuennadi Liakhovetski if (ret > 0) { 288f38f94c6SLinus Walleij host->dma_active = true; 28916052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 29005f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 291a782d688SGuennadi Liakhovetski } 292a782d688SGuennadi Liakhovetski 293a782d688SGuennadi Liakhovetski if (desc) { 294a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 295a782d688SGuennadi Liakhovetski desc->callback_param = host; 296a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 297a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 298a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 299a782d688SGuennadi Liakhovetski } 300a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 30169983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 302a782d688SGuennadi Liakhovetski 303a782d688SGuennadi Liakhovetski if (!desc) { 304a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 305a782d688SGuennadi Liakhovetski if (ret >= 0) 306a782d688SGuennadi Liakhovetski ret = -EIO; 307a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 308f38f94c6SLinus Walleij host->dma_active = false; 309a782d688SGuennadi Liakhovetski dma_release_channel(chan); 310a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 311a782d688SGuennadi Liakhovetski chan = host->chan_tx; 312a782d688SGuennadi Liakhovetski if (chan) { 313a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 314a782d688SGuennadi Liakhovetski dma_release_channel(chan); 315a782d688SGuennadi Liakhovetski } 316a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 317a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 318a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 319a782d688SGuennadi Liakhovetski } 320a782d688SGuennadi Liakhovetski 321a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 32269983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 323a782d688SGuennadi Liakhovetski } 324a782d688SGuennadi Liakhovetski 325a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 326a782d688SGuennadi Liakhovetski { 32769983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 32869983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 329a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 330a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 331a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 332a782d688SGuennadi Liakhovetski int ret; 333a782d688SGuennadi Liakhovetski 33469983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3351ed828dbSLinus Walleij DMA_TO_DEVICE); 336a782d688SGuennadi Liakhovetski if (ret > 0) { 337f38f94c6SLinus Walleij host->dma_active = true; 33816052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 33905f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 340a782d688SGuennadi Liakhovetski } 341a782d688SGuennadi Liakhovetski 342a782d688SGuennadi Liakhovetski if (desc) { 343a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 344a782d688SGuennadi Liakhovetski desc->callback_param = host; 345a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 346a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 347a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 348a782d688SGuennadi Liakhovetski } 349a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 35069983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 351a782d688SGuennadi Liakhovetski 352a782d688SGuennadi Liakhovetski if (!desc) { 353a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 354a782d688SGuennadi Liakhovetski if (ret >= 0) 355a782d688SGuennadi Liakhovetski ret = -EIO; 356a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 357f38f94c6SLinus Walleij host->dma_active = false; 358a782d688SGuennadi Liakhovetski dma_release_channel(chan); 359a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 360a782d688SGuennadi Liakhovetski chan = host->chan_rx; 361a782d688SGuennadi Liakhovetski if (chan) { 362a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 363a782d688SGuennadi Liakhovetski dma_release_channel(chan); 364a782d688SGuennadi Liakhovetski } 365a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 366a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 367a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 368a782d688SGuennadi Liakhovetski } 369a782d688SGuennadi Liakhovetski 370a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 371a782d688SGuennadi Liakhovetski desc, cookie); 372a782d688SGuennadi Liakhovetski } 373a782d688SGuennadi Liakhovetski 374a782d688SGuennadi Liakhovetski static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 375a782d688SGuennadi Liakhovetski struct sh_mmcif_plat_data *pdata) 376a782d688SGuennadi Liakhovetski { 3770e79f9aeSGuennadi Liakhovetski struct resource *res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 3780e79f9aeSGuennadi Liakhovetski struct dma_slave_config cfg; 3790e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 3800e79f9aeSGuennadi Liakhovetski int ret; 3810e79f9aeSGuennadi Liakhovetski 382f38f94c6SLinus Walleij host->dma_active = false; 383a782d688SGuennadi Liakhovetski 384bf68a812SGuennadi Liakhovetski if (!pdata) 385bf68a812SGuennadi Liakhovetski return; 386bf68a812SGuennadi Liakhovetski 3870e79f9aeSGuennadi Liakhovetski if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 3880e79f9aeSGuennadi Liakhovetski return; 389a782d688SGuennadi Liakhovetski 390a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 391a782d688SGuennadi Liakhovetski dma_cap_zero(mask); 392a782d688SGuennadi Liakhovetski dma_cap_set(DMA_SLAVE, mask); 393a782d688SGuennadi Liakhovetski 3940e79f9aeSGuennadi Liakhovetski host->chan_tx = dma_request_channel(mask, shdma_chan_filter, 3950e79f9aeSGuennadi Liakhovetski (void *)pdata->slave_id_tx); 396a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 397a782d688SGuennadi Liakhovetski host->chan_tx); 398a782d688SGuennadi Liakhovetski 399a782d688SGuennadi Liakhovetski if (!host->chan_tx) 400a782d688SGuennadi Liakhovetski return; 401a782d688SGuennadi Liakhovetski 4020e79f9aeSGuennadi Liakhovetski cfg.slave_id = pdata->slave_id_tx; 4030e79f9aeSGuennadi Liakhovetski cfg.direction = DMA_MEM_TO_DEV; 4040e79f9aeSGuennadi Liakhovetski cfg.dst_addr = res->start + MMCIF_CE_DATA; 4050e79f9aeSGuennadi Liakhovetski cfg.src_addr = 0; 4060e79f9aeSGuennadi Liakhovetski ret = dmaengine_slave_config(host->chan_tx, &cfg); 4070e79f9aeSGuennadi Liakhovetski if (ret < 0) 4080e79f9aeSGuennadi Liakhovetski goto ecfgtx; 4090e79f9aeSGuennadi Liakhovetski 4100e79f9aeSGuennadi Liakhovetski host->chan_rx = dma_request_channel(mask, shdma_chan_filter, 4110e79f9aeSGuennadi Liakhovetski (void *)pdata->slave_id_rx); 412a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 413a782d688SGuennadi Liakhovetski host->chan_rx); 414a782d688SGuennadi Liakhovetski 4150e79f9aeSGuennadi Liakhovetski if (!host->chan_rx) 4160e79f9aeSGuennadi Liakhovetski goto erqrx; 4170e79f9aeSGuennadi Liakhovetski 4180e79f9aeSGuennadi Liakhovetski cfg.slave_id = pdata->slave_id_rx; 4190e79f9aeSGuennadi Liakhovetski cfg.direction = DMA_DEV_TO_MEM; 4200e79f9aeSGuennadi Liakhovetski cfg.dst_addr = 0; 4210e79f9aeSGuennadi Liakhovetski cfg.src_addr = res->start + MMCIF_CE_DATA; 4220e79f9aeSGuennadi Liakhovetski ret = dmaengine_slave_config(host->chan_rx, &cfg); 4230e79f9aeSGuennadi Liakhovetski if (ret < 0) 4240e79f9aeSGuennadi Liakhovetski goto ecfgrx; 425a782d688SGuennadi Liakhovetski 426a782d688SGuennadi Liakhovetski init_completion(&host->dma_complete); 4270e79f9aeSGuennadi Liakhovetski 4280e79f9aeSGuennadi Liakhovetski return; 4290e79f9aeSGuennadi Liakhovetski 4300e79f9aeSGuennadi Liakhovetski ecfgrx: 4310e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_rx); 4320e79f9aeSGuennadi Liakhovetski host->chan_rx = NULL; 4330e79f9aeSGuennadi Liakhovetski erqrx: 4340e79f9aeSGuennadi Liakhovetski ecfgtx: 4350e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 4360e79f9aeSGuennadi Liakhovetski host->chan_tx = NULL; 437a782d688SGuennadi Liakhovetski } 438a782d688SGuennadi Liakhovetski 439a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 440a782d688SGuennadi Liakhovetski { 441a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 442a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 443a782d688SGuennadi Liakhovetski if (host->chan_tx) { 444a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 445a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 446a782d688SGuennadi Liakhovetski dma_release_channel(chan); 447a782d688SGuennadi Liakhovetski } 448a782d688SGuennadi Liakhovetski if (host->chan_rx) { 449a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 450a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 451a782d688SGuennadi Liakhovetski dma_release_channel(chan); 452a782d688SGuennadi Liakhovetski } 453a782d688SGuennadi Liakhovetski 454f38f94c6SLinus Walleij host->dma_active = false; 455a782d688SGuennadi Liakhovetski } 456fdc50a94SYusuke Goda 457fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 458fdc50a94SYusuke Goda { 459fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 460bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 461fdc50a94SYusuke Goda 462fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 463fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 464fdc50a94SYusuke Goda 465fdc50a94SYusuke Goda if (!clk) 466fdc50a94SYusuke Goda return; 467bf68a812SGuennadi Liakhovetski if (sup_pclk && clk == host->clk) 468fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 469fdc50a94SYusuke Goda else 470fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 471f9388257SSimon Horman ((fls(DIV_ROUND_UP(host->clk, 472f9388257SSimon Horman clk) - 1) - 1) << 16)); 473fdc50a94SYusuke Goda 474fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 475fdc50a94SYusuke Goda } 476fdc50a94SYusuke Goda 477fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 478fdc50a94SYusuke Goda { 479fdc50a94SYusuke Goda u32 tmp; 480fdc50a94SYusuke Goda 481487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 482fdc50a94SYusuke Goda 483487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 484487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 485fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 486fdc50a94SYusuke Goda SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 487fdc50a94SYusuke Goda /* byte swap on */ 488fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 489fdc50a94SYusuke Goda } 490fdc50a94SYusuke Goda 491fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 492fdc50a94SYusuke Goda { 493fdc50a94SYusuke Goda u32 state1, state2; 494ee4b8887SGuennadi Liakhovetski int ret, timeout; 495fdc50a94SYusuke Goda 496aa0787a9SGuennadi Liakhovetski host->sd_error = false; 497fdc50a94SYusuke Goda 498487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 499487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 500e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 501e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 502fdc50a94SYusuke Goda 503fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 504fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 505fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 506ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 507487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 508fdc50a94SYusuke Goda & STS1_CMDSEQ)) 509fdc50a94SYusuke Goda break; 510fdc50a94SYusuke Goda mdelay(1); 511fdc50a94SYusuke Goda } 512ee4b8887SGuennadi Liakhovetski if (!timeout) { 513ee4b8887SGuennadi Liakhovetski dev_err(&host->pd->dev, 514ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 515ee4b8887SGuennadi Liakhovetski return -EIO; 516ee4b8887SGuennadi Liakhovetski } 517fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 518e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 519fdc50a94SYusuke Goda return -EIO; 520fdc50a94SYusuke Goda } 521fdc50a94SYusuke Goda 522fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 523ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": CRC error\n"); 524fdc50a94SYusuke Goda ret = -EIO; 525fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 526ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Timeout\n"); 527fdc50a94SYusuke Goda ret = -ETIMEDOUT; 528fdc50a94SYusuke Goda } else { 529ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": End/Index error\n"); 530fdc50a94SYusuke Goda ret = -EIO; 531fdc50a94SYusuke Goda } 532fdc50a94SYusuke Goda return ret; 533fdc50a94SYusuke Goda } 534fdc50a94SYusuke Goda 535f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 536f985da17SGuennadi Liakhovetski { 537f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 538f985da17SGuennadi Liakhovetski 539f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 540f985da17SGuennadi Liakhovetski 541f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 542f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 543f985da17SGuennadi Liakhovetski 544f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 545f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 546f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 547f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 548f985da17SGuennadi Liakhovetski } else { 549f985da17SGuennadi Liakhovetski host->pio_ptr = p; 550f985da17SGuennadi Liakhovetski } 551f985da17SGuennadi Liakhovetski 552f985da17SGuennadi Liakhovetski if (host->sg_idx == data->sg_len) 553f985da17SGuennadi Liakhovetski return false; 554f985da17SGuennadi Liakhovetski 555f985da17SGuennadi Liakhovetski return true; 556f985da17SGuennadi Liakhovetski } 557f985da17SGuennadi Liakhovetski 558f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 559fdc50a94SYusuke Goda struct mmc_request *mrq) 560fdc50a94SYusuke Goda { 561f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 562f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 563f985da17SGuennadi Liakhovetski 564f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 565f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 566fdc50a94SYusuke Goda 567fdc50a94SYusuke Goda /* buf read enable */ 568fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 569f985da17SGuennadi Liakhovetski } 570fdc50a94SYusuke Goda 571f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 572f985da17SGuennadi Liakhovetski { 573f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 574f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 575f985da17SGuennadi Liakhovetski int i; 576f985da17SGuennadi Liakhovetski 577f985da17SGuennadi Liakhovetski if (host->sd_error) { 578f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 579f985da17SGuennadi Liakhovetski return false; 580f985da17SGuennadi Liakhovetski } 581f985da17SGuennadi Liakhovetski 582f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 583487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 584fdc50a94SYusuke Goda 585fdc50a94SYusuke Goda /* buffer read end */ 586fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 587f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 588fdc50a94SYusuke Goda 589f985da17SGuennadi Liakhovetski return true; 590fdc50a94SYusuke Goda } 591fdc50a94SYusuke Goda 592f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 593fdc50a94SYusuke Goda struct mmc_request *mrq) 594fdc50a94SYusuke Goda { 595fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 596fdc50a94SYusuke Goda 597f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 598f985da17SGuennadi Liakhovetski return; 599f985da17SGuennadi Liakhovetski 600f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 601f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 602f985da17SGuennadi Liakhovetski 603f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 604f985da17SGuennadi Liakhovetski host->sg_idx = 0; 605f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 606f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 607f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 608fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 609fdc50a94SYusuke Goda } 610fdc50a94SYusuke Goda 611f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 612f985da17SGuennadi Liakhovetski { 613f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 614f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 615f985da17SGuennadi Liakhovetski int i; 616f985da17SGuennadi Liakhovetski 617f985da17SGuennadi Liakhovetski if (host->sd_error) { 618f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 619f985da17SGuennadi Liakhovetski return false; 620f985da17SGuennadi Liakhovetski } 621f985da17SGuennadi Liakhovetski 622f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 623f985da17SGuennadi Liakhovetski 624f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 625f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 626f985da17SGuennadi Liakhovetski 627f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 628f985da17SGuennadi Liakhovetski return false; 629f985da17SGuennadi Liakhovetski 630f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 631f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 632f985da17SGuennadi Liakhovetski 633f985da17SGuennadi Liakhovetski return true; 634f985da17SGuennadi Liakhovetski } 635f985da17SGuennadi Liakhovetski 636f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 637fdc50a94SYusuke Goda struct mmc_request *mrq) 638fdc50a94SYusuke Goda { 639f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 640f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 641fdc50a94SYusuke Goda 642f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 643f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 644fdc50a94SYusuke Goda 645fdc50a94SYusuke Goda /* buf write enable */ 646f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 647f985da17SGuennadi Liakhovetski } 648fdc50a94SYusuke Goda 649f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 650f985da17SGuennadi Liakhovetski { 651f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 652f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 653f985da17SGuennadi Liakhovetski int i; 654f985da17SGuennadi Liakhovetski 655f985da17SGuennadi Liakhovetski if (host->sd_error) { 656f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 657f985da17SGuennadi Liakhovetski return false; 658f985da17SGuennadi Liakhovetski } 659f985da17SGuennadi Liakhovetski 660f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 661487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 662fdc50a94SYusuke Goda 663fdc50a94SYusuke Goda /* buffer write end */ 664fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 665f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 666fdc50a94SYusuke Goda 667f985da17SGuennadi Liakhovetski return true; 668fdc50a94SYusuke Goda } 669fdc50a94SYusuke Goda 670f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 671fdc50a94SYusuke Goda struct mmc_request *mrq) 672fdc50a94SYusuke Goda { 673fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 674fdc50a94SYusuke Goda 675f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 676f985da17SGuennadi Liakhovetski return; 677fdc50a94SYusuke Goda 678f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 679f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 680f985da17SGuennadi Liakhovetski 681f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 682f985da17SGuennadi Liakhovetski host->sg_idx = 0; 683f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 684f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 685f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 686fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 687fdc50a94SYusuke Goda } 688f985da17SGuennadi Liakhovetski 689f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 690f985da17SGuennadi Liakhovetski { 691f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 692f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 693f985da17SGuennadi Liakhovetski int i; 694f985da17SGuennadi Liakhovetski 695f985da17SGuennadi Liakhovetski if (host->sd_error) { 696f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 697f985da17SGuennadi Liakhovetski return false; 698fdc50a94SYusuke Goda } 699f985da17SGuennadi Liakhovetski 700f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 701f985da17SGuennadi Liakhovetski 702f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 703f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 704f985da17SGuennadi Liakhovetski 705f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 706f985da17SGuennadi Liakhovetski return false; 707f985da17SGuennadi Liakhovetski 708f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 709f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 710f985da17SGuennadi Liakhovetski 711f985da17SGuennadi Liakhovetski return true; 712fdc50a94SYusuke Goda } 713fdc50a94SYusuke Goda 714fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 715fdc50a94SYusuke Goda struct mmc_command *cmd) 716fdc50a94SYusuke Goda { 717fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 718487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 719487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 720487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 721487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 722fdc50a94SYusuke Goda } else 723487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 724fdc50a94SYusuke Goda } 725fdc50a94SYusuke Goda 726fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 727fdc50a94SYusuke Goda struct mmc_command *cmd) 728fdc50a94SYusuke Goda { 729487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 730fdc50a94SYusuke Goda } 731fdc50a94SYusuke Goda 732fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 73369983404SGuennadi Liakhovetski struct mmc_request *mrq) 734fdc50a94SYusuke Goda { 73569983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 73669983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 73769983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 738fdc50a94SYusuke Goda u32 tmp = 0; 739fdc50a94SYusuke Goda 740fdc50a94SYusuke Goda /* Response Type check */ 741fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 742fdc50a94SYusuke Goda case MMC_RSP_NONE: 743fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 744fdc50a94SYusuke Goda break; 745fdc50a94SYusuke Goda case MMC_RSP_R1: 746fdc50a94SYusuke Goda case MMC_RSP_R1B: 747fdc50a94SYusuke Goda case MMC_RSP_R3: 748fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 749fdc50a94SYusuke Goda break; 750fdc50a94SYusuke Goda case MMC_RSP_R2: 751fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 752fdc50a94SYusuke Goda break; 753fdc50a94SYusuke Goda default: 754e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 755fdc50a94SYusuke Goda break; 756fdc50a94SYusuke Goda } 757fdc50a94SYusuke Goda switch (opc) { 758fdc50a94SYusuke Goda /* RBSY */ 759fdc50a94SYusuke Goda case MMC_SWITCH: 760fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 761fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 762fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 763fdc50a94SYusuke Goda case MMC_ERASE: 764fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 765fdc50a94SYusuke Goda break; 766fdc50a94SYusuke Goda } 767fdc50a94SYusuke Goda /* WDAT / DATW */ 76869983404SGuennadi Liakhovetski if (data) { 769fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 770fdc50a94SYusuke Goda switch (host->bus_width) { 771fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 772fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 773fdc50a94SYusuke Goda break; 774fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 775fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 776fdc50a94SYusuke Goda break; 777fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 778fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 779fdc50a94SYusuke Goda break; 780fdc50a94SYusuke Goda default: 781e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 782fdc50a94SYusuke Goda break; 783fdc50a94SYusuke Goda } 784fdc50a94SYusuke Goda } 785fdc50a94SYusuke Goda /* DWEN */ 786fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 787fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 788fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 789fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 790fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 791fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 79269983404SGuennadi Liakhovetski data->blocks << 16); 793fdc50a94SYusuke Goda } 794fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 795fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 796fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 797fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 798fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 799fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 800fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 801fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 802fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 803fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 804fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 805fdc50a94SYusuke Goda 80669983404SGuennadi Liakhovetski return (opc << 24) | tmp; 807fdc50a94SYusuke Goda } 808fdc50a94SYusuke Goda 809e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 810fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 811fdc50a94SYusuke Goda { 812fdc50a94SYusuke Goda switch (opc) { 813fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 814f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 815f985da17SGuennadi Liakhovetski return 0; 816fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 817f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 818f985da17SGuennadi Liakhovetski return 0; 819fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 820f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 821f985da17SGuennadi Liakhovetski return 0; 822fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 823fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 824f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 825f985da17SGuennadi Liakhovetski return 0; 826fdc50a94SYusuke Goda default: 827e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 828ee4b8887SGuennadi Liakhovetski return -EINVAL; 829fdc50a94SYusuke Goda } 830fdc50a94SYusuke Goda } 831fdc50a94SYusuke Goda 832fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 833ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 834fdc50a94SYusuke Goda { 835ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 836f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 837f985da17SGuennadi Liakhovetski u32 mask; 838fdc50a94SYusuke Goda 839fdc50a94SYusuke Goda switch (opc) { 840ee4b8887SGuennadi Liakhovetski /* response busy check */ 841fdc50a94SYusuke Goda case MMC_SWITCH: 842fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 843fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 844fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 845fdc50a94SYusuke Goda case MMC_ERASE: 846ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 847fdc50a94SYusuke Goda break; 848fdc50a94SYusuke Goda default: 849ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 850fdc50a94SYusuke Goda break; 851fdc50a94SYusuke Goda } 852fdc50a94SYusuke Goda 85369983404SGuennadi Liakhovetski if (mrq->data) { 854487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 855487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 856487d9fc5SMagnus Damm mrq->data->blksz); 857fdc50a94SYusuke Goda } 85869983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 859fdc50a94SYusuke Goda 860487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 861487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 862fdc50a94SYusuke Goda /* set arg */ 863487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 864fdc50a94SYusuke Goda /* set cmd */ 865487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 866fdc50a94SYusuke Goda 867f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 868f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 869fdc50a94SYusuke Goda } 870fdc50a94SYusuke Goda 871fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 872ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 873fdc50a94SYusuke Goda { 87469983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 87569983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 876fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 87769983404SGuennadi Liakhovetski break; 87869983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 879fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 88069983404SGuennadi Liakhovetski break; 88169983404SGuennadi Liakhovetski default: 882e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 88369983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 884fdc50a94SYusuke Goda return; 885fdc50a94SYusuke Goda } 886fdc50a94SYusuke Goda 887f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 888f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 889fdc50a94SYusuke Goda } 890fdc50a94SYusuke Goda 891fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 892fdc50a94SYusuke Goda { 893fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 8943b0beafcSGuennadi Liakhovetski unsigned long flags; 8953b0beafcSGuennadi Liakhovetski 8963b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8973b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8983b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 8993b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9003b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9013b0beafcSGuennadi Liakhovetski return; 9023b0beafcSGuennadi Liakhovetski } 9033b0beafcSGuennadi Liakhovetski 9043b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9053b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 906fdc50a94SYusuke Goda 907fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 908fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 9097541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 9107541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 9117541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 9127541ca98SLaurent Pinchart break; 913fdc50a94SYusuke Goda case MMC_APP_CMD: 9143b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 915fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 916fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 917fdc50a94SYusuke Goda return; 918fdc50a94SYusuke Goda default: 919fdc50a94SYusuke Goda break; 920fdc50a94SYusuke Goda } 921fdc50a94SYusuke Goda 922f985da17SGuennadi Liakhovetski host->mrq = mrq; 923f985da17SGuennadi Liakhovetski 924f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 925fdc50a94SYusuke Goda } 926fdc50a94SYusuke Goda 927a6609267SGuennadi Liakhovetski static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 928a6609267SGuennadi Liakhovetski { 929a6609267SGuennadi Liakhovetski int ret = clk_enable(host->hclk); 930a6609267SGuennadi Liakhovetski 931a6609267SGuennadi Liakhovetski if (!ret) { 932a6609267SGuennadi Liakhovetski host->clk = clk_get_rate(host->hclk); 933a6609267SGuennadi Liakhovetski host->mmc->f_max = host->clk / 2; 934a6609267SGuennadi Liakhovetski host->mmc->f_min = host->clk / 512; 935a6609267SGuennadi Liakhovetski } 936a6609267SGuennadi Liakhovetski 937a6609267SGuennadi Liakhovetski return ret; 938a6609267SGuennadi Liakhovetski } 939a6609267SGuennadi Liakhovetski 9407d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 9417d17baa0SGuennadi Liakhovetski { 9427d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 9437d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 9447d17baa0SGuennadi Liakhovetski 945bf68a812SGuennadi Liakhovetski if (pd && pd->set_pwr) 9467d17baa0SGuennadi Liakhovetski pd->set_pwr(host->pd, ios->power_mode != MMC_POWER_OFF); 9477d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 9487d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 9497d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 9507d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 9517d17baa0SGuennadi Liakhovetski } 9527d17baa0SGuennadi Liakhovetski 953fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 954fdc50a94SYusuke Goda { 955fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9563b0beafcSGuennadi Liakhovetski unsigned long flags; 9573b0beafcSGuennadi Liakhovetski 9583b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9593b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 9603b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9613b0beafcSGuennadi Liakhovetski return; 9623b0beafcSGuennadi Liakhovetski } 9633b0beafcSGuennadi Liakhovetski 9643b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 9653b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 966fdc50a94SYusuke Goda 967f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 968c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 969faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 970faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 971c9b0cef2SGuennadi Liakhovetski host->card_present = true; 972faca6648SGuennadi Liakhovetski } 9737d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 974f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 975f5e0cec4SGuennadi Liakhovetski /* clock stop */ 976f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 977faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 978c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 979c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 980c9b0cef2SGuennadi Liakhovetski host->card_present = false; 981c9b0cef2SGuennadi Liakhovetski } 982c9b0cef2SGuennadi Liakhovetski } 983faca6648SGuennadi Liakhovetski if (host->power) { 984faca6648SGuennadi Liakhovetski pm_runtime_put(&host->pd->dev); 985b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 986faca6648SGuennadi Liakhovetski host->power = false; 9877d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 9887d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 989faca6648SGuennadi Liakhovetski } 9903b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 991f5e0cec4SGuennadi Liakhovetski return; 992fdc50a94SYusuke Goda } 993fdc50a94SYusuke Goda 994c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 995c9b0cef2SGuennadi Liakhovetski if (!host->power) { 996a6609267SGuennadi Liakhovetski sh_mmcif_clk_update(host); 997c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 998c9b0cef2SGuennadi Liakhovetski host->power = true; 999c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 1000c9b0cef2SGuennadi Liakhovetski } 1001fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 1002c9b0cef2SGuennadi Liakhovetski } 1003fdc50a94SYusuke Goda 1004fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10053b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1006fdc50a94SYusuke Goda } 1007fdc50a94SYusuke Goda 1008777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1009777271d0SArnd Hannemann { 1010777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1011777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1012e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1013e480606aSGuennadi Liakhovetski 1014e480606aSGuennadi Liakhovetski if (ret >= 0) 1015e480606aSGuennadi Liakhovetski return ret; 1016777271d0SArnd Hannemann 1017bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1018777271d0SArnd Hannemann return -ENOSYS; 1019777271d0SArnd Hannemann else 1020777271d0SArnd Hannemann return p->get_cd(host->pd); 1021777271d0SArnd Hannemann } 1022777271d0SArnd Hannemann 1023fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1024fdc50a94SYusuke Goda .request = sh_mmcif_request, 1025fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1026777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1027fdc50a94SYusuke Goda }; 1028fdc50a94SYusuke Goda 1029f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1030f985da17SGuennadi Liakhovetski { 1031f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 103269983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1033f985da17SGuennadi Liakhovetski long time; 1034f985da17SGuennadi Liakhovetski 1035f985da17SGuennadi Liakhovetski if (host->sd_error) { 1036f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1037f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1038f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1039f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1040f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1041f985da17SGuennadi Liakhovetski host->sd_error = false; 1042f985da17SGuennadi Liakhovetski break; 1043f985da17SGuennadi Liakhovetski default: 1044f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1045f985da17SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n", 1046f985da17SGuennadi Liakhovetski cmd->opcode, cmd->error); 1047f985da17SGuennadi Liakhovetski break; 1048f985da17SGuennadi Liakhovetski } 1049f985da17SGuennadi Liakhovetski return false; 1050f985da17SGuennadi Liakhovetski } 1051f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1052f985da17SGuennadi Liakhovetski cmd->error = 0; 1053f985da17SGuennadi Liakhovetski return false; 1054f985da17SGuennadi Liakhovetski } 1055f985da17SGuennadi Liakhovetski 1056f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1057f985da17SGuennadi Liakhovetski 105869983404SGuennadi Liakhovetski if (!data) 1059f985da17SGuennadi Liakhovetski return false; 1060f985da17SGuennadi Liakhovetski 106169983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1062f985da17SGuennadi Liakhovetski if (host->chan_rx) 1063f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1064f985da17SGuennadi Liakhovetski } else { 1065f985da17SGuennadi Liakhovetski if (host->chan_tx) 1066f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1067f985da17SGuennadi Liakhovetski } 1068f985da17SGuennadi Liakhovetski 1069f985da17SGuennadi Liakhovetski if (!host->dma_active) { 107069983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 107169983404SGuennadi Liakhovetski if (!data->error) 1072f985da17SGuennadi Liakhovetski return true; 1073f985da17SGuennadi Liakhovetski return false; 1074f985da17SGuennadi Liakhovetski } 1075f985da17SGuennadi Liakhovetski 1076f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1077f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1078f985da17SGuennadi Liakhovetski host->timeout); 1079f985da17SGuennadi Liakhovetski if (host->sd_error) { 1080f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1081f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1082f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 108369983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) 1084f985da17SGuennadi Liakhovetski dmaengine_terminate_all(host->chan_rx); 1085f985da17SGuennadi Liakhovetski else 1086f985da17SGuennadi Liakhovetski dmaengine_terminate_all(host->chan_tx); 108769983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1088f985da17SGuennadi Liakhovetski } else if (!time) { 108969983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1090f985da17SGuennadi Liakhovetski } else if (time < 0) { 109169983404SGuennadi Liakhovetski data->error = time; 1092f985da17SGuennadi Liakhovetski } 1093f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1094f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1095f985da17SGuennadi Liakhovetski host->dma_active = false; 1096f985da17SGuennadi Liakhovetski 109769983404SGuennadi Liakhovetski if (data->error) 109869983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1099f985da17SGuennadi Liakhovetski 1100f985da17SGuennadi Liakhovetski return false; 1101f985da17SGuennadi Liakhovetski } 1102f985da17SGuennadi Liakhovetski 1103f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1104f985da17SGuennadi Liakhovetski { 1105f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 1106f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 110769983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 1108f985da17SGuennadi Liakhovetski 1109f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1110f985da17SGuennadi Liakhovetski 1111f985da17SGuennadi Liakhovetski /* 1112f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1113f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1114f985da17SGuennadi Liakhovetski */ 1115f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1116f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1117f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 1118f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1119f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1120f985da17SGuennadi Liakhovetski if (sh_mmcif_end_cmd(host)) 1121f985da17SGuennadi Liakhovetski /* Wait for data */ 1122f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1123f985da17SGuennadi Liakhovetski break; 1124f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1125f985da17SGuennadi Liakhovetski if (sh_mmcif_mread_block(host)) 1126f985da17SGuennadi Liakhovetski /* Wait for more data */ 1127f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1128f985da17SGuennadi Liakhovetski break; 1129f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1130f985da17SGuennadi Liakhovetski if (sh_mmcif_read_block(host)) 1131f985da17SGuennadi Liakhovetski /* Wait for data end */ 1132f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1133f985da17SGuennadi Liakhovetski break; 1134f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1135f985da17SGuennadi Liakhovetski if (sh_mmcif_mwrite_block(host)) 1136f985da17SGuennadi Liakhovetski /* Wait data to write */ 1137f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1138f985da17SGuennadi Liakhovetski break; 1139f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1140f985da17SGuennadi Liakhovetski if (sh_mmcif_write_block(host)) 1141f985da17SGuennadi Liakhovetski /* Wait for data end */ 1142f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1143f985da17SGuennadi Liakhovetski break; 1144f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1145f985da17SGuennadi Liakhovetski if (host->sd_error) { 1146f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1147f985da17SGuennadi Liakhovetski break; 1148f985da17SGuennadi Liakhovetski } 1149f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1150f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1151f985da17SGuennadi Liakhovetski break; 1152f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1153f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1154f985da17SGuennadi Liakhovetski if (host->sd_error) 115569983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1156f985da17SGuennadi Liakhovetski break; 1157f985da17SGuennadi Liakhovetski default: 1158f985da17SGuennadi Liakhovetski BUG(); 1159f985da17SGuennadi Liakhovetski } 1160f985da17SGuennadi Liakhovetski 1161f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 116269983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 116369983404SGuennadi Liakhovetski data->bytes_xfered = 116469983404SGuennadi Liakhovetski data->blocks * data->blksz; 1165f985da17SGuennadi Liakhovetski 116669983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1167f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 1168f985da17SGuennadi Liakhovetski if (!mrq->stop->error) 1169f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1170f985da17SGuennadi Liakhovetski } 1171f985da17SGuennadi Liakhovetski } 1172f985da17SGuennadi Liakhovetski 1173f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1174f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 117569983404SGuennadi Liakhovetski host->mrq = NULL; 1176f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1177f985da17SGuennadi Liakhovetski 1178f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1179f985da17SGuennadi Liakhovetski } 1180f985da17SGuennadi Liakhovetski 1181fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1182fdc50a94SYusuke Goda { 1183fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1184aa0787a9SGuennadi Liakhovetski u32 state; 1185fdc50a94SYusuke Goda int err = 0; 1186fdc50a94SYusuke Goda 1187487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1188fdc50a94SYusuke Goda 11898a8284a9SGuennadi Liakhovetski if (state & INT_ERR_STS) { 11908a8284a9SGuennadi Liakhovetski /* error interrupts - process first */ 11918a8284a9SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 11928a8284a9SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 11938a8284a9SGuennadi Liakhovetski err = 1; 11948a8284a9SGuennadi Liakhovetski } else if (state & INT_RBSYE) { 1195487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1196487d9fc5SMagnus Damm ~(INT_RBSYE | INT_CRSPE)); 1197fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 1198fdc50a94SYusuke Goda } else if (state & INT_CRSPE) { 1199487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 1200fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 1201fdc50a94SYusuke Goda } else if (state & INT_BUFREN) { 1202487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 1203fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 1204fdc50a94SYusuke Goda } else if (state & INT_BUFWEN) { 1205487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 1206fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 1207fdc50a94SYusuke Goda } else if (state & INT_CMD12DRE) { 1208487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1209fdc50a94SYusuke Goda ~(INT_CMD12DRE | INT_CMD12RBE | 1210fdc50a94SYusuke Goda INT_CMD12CRE | INT_BUFRE)); 1211fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 1212fdc50a94SYusuke Goda } else if (state & INT_BUFRE) { 1213487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 1214fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 1215fdc50a94SYusuke Goda } else if (state & INT_DTRANE) { 12167a7eb328SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 12177a7eb328SGuennadi Liakhovetski ~(INT_CMD12DRE | INT_CMD12RBE | 12187a7eb328SGuennadi Liakhovetski INT_CMD12CRE | INT_DTRANE)); 1219fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 1220fdc50a94SYusuke Goda } else if (state & INT_CMD12RBE) { 1221487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1222fdc50a94SYusuke Goda ~(INT_CMD12RBE | INT_CMD12CRE)); 1223fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 1224fdc50a94SYusuke Goda } else { 1225faca6648SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 1226487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1227fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1228fdc50a94SYusuke Goda err = 1; 1229fdc50a94SYusuke Goda } 1230fdc50a94SYusuke Goda if (err) { 1231aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1232e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 1233fdc50a94SYusuke Goda } 1234f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1235f985da17SGuennadi Liakhovetski if (!host->dma_active) 1236f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1237f985da17SGuennadi Liakhovetski else if (host->sd_error) 1238f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1239f985da17SGuennadi Liakhovetski } else { 1240aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1241f985da17SGuennadi Liakhovetski } 1242fdc50a94SYusuke Goda 1243fdc50a94SYusuke Goda return IRQ_HANDLED; 1244fdc50a94SYusuke Goda } 1245fdc50a94SYusuke Goda 1246f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1247f985da17SGuennadi Liakhovetski { 1248f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1249f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1250f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 1251f985da17SGuennadi Liakhovetski 1252f985da17SGuennadi Liakhovetski if (host->dying) 1253f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1254f985da17SGuennadi Liakhovetski return; 1255f985da17SGuennadi Liakhovetski 1256f985da17SGuennadi Liakhovetski /* 1257f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1258f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1259f985da17SGuennadi Liakhovetski */ 1260f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1261f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1262f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1263f985da17SGuennadi Liakhovetski break; 1264f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1265f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1266f985da17SGuennadi Liakhovetski break; 1267f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1268f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1269f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1270f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1271f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1272f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 127369983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1274f985da17SGuennadi Liakhovetski break; 1275f985da17SGuennadi Liakhovetski default: 1276f985da17SGuennadi Liakhovetski BUG(); 1277f985da17SGuennadi Liakhovetski } 1278f985da17SGuennadi Liakhovetski 1279f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1280f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1281f985da17SGuennadi Liakhovetski host->mrq = NULL; 1282f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1283f985da17SGuennadi Liakhovetski } 1284f985da17SGuennadi Liakhovetski 12857d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 12867d17baa0SGuennadi Liakhovetski { 12877d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 12887d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 12897d17baa0SGuennadi Liakhovetski 12907d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 12917d17baa0SGuennadi Liakhovetski 1292bf68a812SGuennadi Liakhovetski if (!pd) 1293bf68a812SGuennadi Liakhovetski return; 1294bf68a812SGuennadi Liakhovetski 12957d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 12967d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 12977d17baa0SGuennadi Liakhovetski else if (pd->ocr) 12987d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 12997d17baa0SGuennadi Liakhovetski } 13007d17baa0SGuennadi Liakhovetski 1301fdc50a94SYusuke Goda static int __devinit sh_mmcif_probe(struct platform_device *pdev) 1302fdc50a94SYusuke Goda { 1303fdc50a94SYusuke Goda int ret = 0, irq[2]; 1304fdc50a94SYusuke Goda struct mmc_host *mmc; 1305e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1306e1aae2ebSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1307fdc50a94SYusuke Goda struct resource *res; 1308fdc50a94SYusuke Goda void __iomem *reg; 1309fdc50a94SYusuke Goda char clk_name[8]; 1310fdc50a94SYusuke Goda 1311fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1312fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1313fdc50a94SYusuke Goda if (irq[0] < 0 || irq[1] < 0) { 1314e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1315fdc50a94SYusuke Goda return -ENXIO; 1316fdc50a94SYusuke Goda } 1317fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1318fdc50a94SYusuke Goda if (!res) { 1319fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1320fdc50a94SYusuke Goda return -ENXIO; 1321fdc50a94SYusuke Goda } 1322fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1323fdc50a94SYusuke Goda if (!reg) { 1324fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1325fdc50a94SYusuke Goda return -ENOMEM; 1326fdc50a94SYusuke Goda } 1327e1aae2ebSGuennadi Liakhovetski 1328fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1329fdc50a94SYusuke Goda if (!mmc) { 1330fdc50a94SYusuke Goda ret = -ENOMEM; 1331e1aae2ebSGuennadi Liakhovetski goto ealloch; 1332fdc50a94SYusuke Goda } 1333fdc50a94SYusuke Goda host = mmc_priv(mmc); 1334fdc50a94SYusuke Goda host->mmc = mmc; 1335fdc50a94SYusuke Goda host->addr = reg; 1336fdc50a94SYusuke Goda host->timeout = 1000; 1337fdc50a94SYusuke Goda 1338fdc50a94SYusuke Goda host->pd = pdev; 1339fdc50a94SYusuke Goda 13403b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1341fdc50a94SYusuke Goda 1342fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 13437d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 13447d17baa0SGuennadi Liakhovetski 1345fdc50a94SYusuke Goda mmc->caps = MMC_CAP_MMC_HIGHSPEED; 1346bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1347fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1348a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1349fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1350a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1351a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1352fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1353fdc50a94SYusuke Goda 1354fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1355a782d688SGuennadi Liakhovetski 1356faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1357faca6648SGuennadi Liakhovetski host->power = false; 1358faca6648SGuennadi Liakhovetski 1359b289174fSGuennadi Liakhovetski snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 1360b289174fSGuennadi Liakhovetski host->hclk = clk_get(&pdev->dev, clk_name); 1361b289174fSGuennadi Liakhovetski if (IS_ERR(host->hclk)) { 1362b289174fSGuennadi Liakhovetski ret = PTR_ERR(host->hclk); 1363b289174fSGuennadi Liakhovetski dev_err(&pdev->dev, "cannot get clock \"%s\": %d\n", clk_name, ret); 1364b289174fSGuennadi Liakhovetski goto eclkget; 1365b289174fSGuennadi Liakhovetski } 1366a6609267SGuennadi Liakhovetski ret = sh_mmcif_clk_update(host); 1367a6609267SGuennadi Liakhovetski if (ret < 0) 1368a6609267SGuennadi Liakhovetski goto eclkupdate; 1369b289174fSGuennadi Liakhovetski 1370faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1371faca6648SGuennadi Liakhovetski if (ret < 0) 1372e1aae2ebSGuennadi Liakhovetski goto eresume; 1373a782d688SGuennadi Liakhovetski 13745ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1375fdc50a94SYusuke Goda 1376b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 13773b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 13783b0beafcSGuennadi Liakhovetski 1379f985da17SGuennadi Liakhovetski ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host); 1380fdc50a94SYusuke Goda if (ret) { 1381e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); 1382e1aae2ebSGuennadi Liakhovetski goto ereqirq0; 1383fdc50a94SYusuke Goda } 1384f985da17SGuennadi Liakhovetski ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host); 1385fdc50a94SYusuke Goda if (ret) { 1386e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1387e1aae2ebSGuennadi Liakhovetski goto ereqirq1; 1388fdc50a94SYusuke Goda } 1389fdc50a94SYusuke Goda 1390e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1391e480606aSGuennadi Liakhovetski ret = mmc_gpio_request_cd(mmc, pd->cd_gpio); 1392e480606aSGuennadi Liakhovetski if (ret < 0) 1393e480606aSGuennadi Liakhovetski goto erqcd; 1394e480606aSGuennadi Liakhovetski } 1395e480606aSGuennadi Liakhovetski 1396b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 13975ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 13985ba85d95SGuennadi Liakhovetski if (ret < 0) 1399e1aae2ebSGuennadi Liakhovetski goto emmcaddh; 1400fdc50a94SYusuke Goda 1401efe6a8adSRafael J. Wysocki dev_pm_qos_expose_latency_limit(&pdev->dev, 100); 1402efe6a8adSRafael J. Wysocki 1403e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1404e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1405487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1406fdc50a94SYusuke Goda return ret; 1407fdc50a94SYusuke Goda 1408e1aae2ebSGuennadi Liakhovetski emmcaddh: 1409e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) 1410e480606aSGuennadi Liakhovetski mmc_gpio_free_cd(mmc); 1411e480606aSGuennadi Liakhovetski erqcd: 14125ba85d95SGuennadi Liakhovetski free_irq(irq[1], host); 1413e1aae2ebSGuennadi Liakhovetski ereqirq1: 14145ba85d95SGuennadi Liakhovetski free_irq(irq[0], host); 1415e1aae2ebSGuennadi Liakhovetski ereqirq0: 1416faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1417e1aae2ebSGuennadi Liakhovetski eresume: 1418fdc50a94SYusuke Goda clk_disable(host->hclk); 1419a6609267SGuennadi Liakhovetski eclkupdate: 1420b289174fSGuennadi Liakhovetski clk_put(host->hclk); 1421e1aae2ebSGuennadi Liakhovetski eclkget: 1422b289174fSGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1423fdc50a94SYusuke Goda mmc_free_host(mmc); 1424e1aae2ebSGuennadi Liakhovetski ealloch: 1425fdc50a94SYusuke Goda iounmap(reg); 1426fdc50a94SYusuke Goda return ret; 1427fdc50a94SYusuke Goda } 1428fdc50a94SYusuke Goda 1429fdc50a94SYusuke Goda static int __devexit sh_mmcif_remove(struct platform_device *pdev) 1430fdc50a94SYusuke Goda { 1431fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1432e480606aSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = pdev->dev.platform_data; 1433fdc50a94SYusuke Goda int irq[2]; 1434fdc50a94SYusuke Goda 1435f985da17SGuennadi Liakhovetski host->dying = true; 1436b289174fSGuennadi Liakhovetski clk_enable(host->hclk); 1437faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1438aa0787a9SGuennadi Liakhovetski 1439efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1440efe6a8adSRafael J. Wysocki 1441e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) 1442e480606aSGuennadi Liakhovetski mmc_gpio_free_cd(host->mmc); 1443e480606aSGuennadi Liakhovetski 1444faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 14453b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14463b0beafcSGuennadi Liakhovetski 1447f985da17SGuennadi Liakhovetski /* 1448f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1449f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1450f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1451f985da17SGuennadi Liakhovetski */ 1452f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1453f985da17SGuennadi Liakhovetski 1454aa0787a9SGuennadi Liakhovetski if (host->addr) 1455aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1456aa0787a9SGuennadi Liakhovetski 1457fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1458fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1459fdc50a94SYusuke Goda 1460fdc50a94SYusuke Goda free_irq(irq[0], host); 1461fdc50a94SYusuke Goda free_irq(irq[1], host); 1462fdc50a94SYusuke Goda 1463aa0787a9SGuennadi Liakhovetski platform_set_drvdata(pdev, NULL); 1464aa0787a9SGuennadi Liakhovetski 1465fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1466faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1467b289174fSGuennadi Liakhovetski clk_disable(host->hclk); 1468faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1469fdc50a94SYusuke Goda 1470fdc50a94SYusuke Goda return 0; 1471fdc50a94SYusuke Goda } 1472fdc50a94SYusuke Goda 1473faca6648SGuennadi Liakhovetski #ifdef CONFIG_PM 1474faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1475faca6648SGuennadi Liakhovetski { 1476b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1477faca6648SGuennadi Liakhovetski int ret = mmc_suspend_host(host->mmc); 1478faca6648SGuennadi Liakhovetski 1479b289174fSGuennadi Liakhovetski if (!ret) 1480faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1481faca6648SGuennadi Liakhovetski 1482faca6648SGuennadi Liakhovetski return ret; 1483faca6648SGuennadi Liakhovetski } 1484faca6648SGuennadi Liakhovetski 1485faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1486faca6648SGuennadi Liakhovetski { 1487b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1488faca6648SGuennadi Liakhovetski 1489faca6648SGuennadi Liakhovetski return mmc_resume_host(host->mmc); 1490faca6648SGuennadi Liakhovetski } 1491faca6648SGuennadi Liakhovetski #else 1492faca6648SGuennadi Liakhovetski #define sh_mmcif_suspend NULL 1493faca6648SGuennadi Liakhovetski #define sh_mmcif_resume NULL 1494faca6648SGuennadi Liakhovetski #endif /* CONFIG_PM */ 1495faca6648SGuennadi Liakhovetski 1496bf68a812SGuennadi Liakhovetski static const struct of_device_id mmcif_of_match[] = { 1497bf68a812SGuennadi Liakhovetski { .compatible = "renesas,sh-mmcif" }, 1498bf68a812SGuennadi Liakhovetski { } 1499bf68a812SGuennadi Liakhovetski }; 1500bf68a812SGuennadi Liakhovetski MODULE_DEVICE_TABLE(of, mmcif_of_match); 1501bf68a812SGuennadi Liakhovetski 1502faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1503faca6648SGuennadi Liakhovetski .suspend = sh_mmcif_suspend, 1504faca6648SGuennadi Liakhovetski .resume = sh_mmcif_resume, 1505faca6648SGuennadi Liakhovetski }; 1506faca6648SGuennadi Liakhovetski 1507fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1508fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1509fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1510fdc50a94SYusuke Goda .driver = { 1511fdc50a94SYusuke Goda .name = DRIVER_NAME, 1512faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1513bf68a812SGuennadi Liakhovetski .owner = THIS_MODULE, 1514bf68a812SGuennadi Liakhovetski .of_match_table = mmcif_of_match, 1515fdc50a94SYusuke Goda }, 1516fdc50a94SYusuke Goda }; 1517fdc50a94SYusuke Goda 1518d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1519fdc50a94SYusuke Goda 1520fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1521fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1522aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1523fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1524