1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 598047310eSGuennadi Liakhovetski #include <linux/mutex.h> 60a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 61e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 62efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 63faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 64d00cadacSGuennadi Liakhovetski #include <linux/sh_dma.h> 653b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6688b47679SPaul Gortmaker #include <linux/module.h> 67fdc50a94SYusuke Goda 68fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 69fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 70fdc50a94SYusuke Goda 71fdc50a94SYusuke Goda /* CE_CMD_SET */ 72fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 73fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 74fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 75fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 76fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 77fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 78fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 79fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 80fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 81fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 82fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 83fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 84fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 85fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 86fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 88fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 89fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 90fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 91fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 92fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 93555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 94fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 95fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 96fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 97fdc50a94SYusuke Goda 98fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 99fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 100fdc50a94SYusuke Goda 101fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 102fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 103fdc50a94SYusuke Goda 104fdc50a94SYusuke Goda /* CE_INT */ 105fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 106fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 107fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 108fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 109fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 110fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 111fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 112fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 113fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 114fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 115fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 116fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 117fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 118fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 119fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 120fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 121fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 122fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 123fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 124fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 125fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 126fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 127fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 128fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 129fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 130fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 131fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 132fdc50a94SYusuke Goda 1338af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 1348af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 1358af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 1368af50750SGuennadi Liakhovetski 137967bcb77SGuennadi Liakhovetski #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 138967bcb77SGuennadi Liakhovetski 139fdc50a94SYusuke Goda /* CE_INT_MASK */ 140fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 141fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 142fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 143fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 144fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 145fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 146fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 147fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 148fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 149fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 150fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 151fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 152fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 153fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 154fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 155fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 156fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 157fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 158fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 159fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 160fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 161fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 162fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 163fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 164fdc50a94SYusuke Goda 165ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 166ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 167967bcb77SGuennadi Liakhovetski MASK_MCRCSTO | MASK_MWDATTO | \ 168ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 169ee4b8887SGuennadi Liakhovetski 1708af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 1718af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \ 1728af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 1738af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE) 1748af50750SGuennadi Liakhovetski 175fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 176fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 177fdc50a94SYusuke Goda 178fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 179fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 180fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 181fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 182fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 183fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 184fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 185fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 186fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 187fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 188fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 189fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 190fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 191fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 192fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 193fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 194fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 195fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 196fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 197fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 198fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 199fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 200fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 201fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 202fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 203fdc50a94SYusuke Goda 204fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 205fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 206fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 207fdc50a94SYusuke Goda 2083b0beafcSGuennadi Liakhovetski enum mmcif_state { 2093b0beafcSGuennadi Liakhovetski STATE_IDLE, 2103b0beafcSGuennadi Liakhovetski STATE_REQUEST, 2113b0beafcSGuennadi Liakhovetski STATE_IOS, 2128047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2133b0beafcSGuennadi Liakhovetski }; 2143b0beafcSGuennadi Liakhovetski 215f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 216f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 217f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 218f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 219f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 220f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 221f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 222f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 223f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 224f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 225f985da17SGuennadi Liakhovetski }; 226f985da17SGuennadi Liakhovetski 227fdc50a94SYusuke Goda struct sh_mmcif_host { 228fdc50a94SYusuke Goda struct mmc_host *mmc; 229f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 230fdc50a94SYusuke Goda struct platform_device *pd; 231fdc50a94SYusuke Goda struct clk *hclk; 232fdc50a94SYusuke Goda unsigned int clk; 233fdc50a94SYusuke Goda int bus_width; 234555061f9STeppei Kamijou unsigned char timing; 235aa0787a9SGuennadi Liakhovetski bool sd_error; 236f985da17SGuennadi Liakhovetski bool dying; 237fdc50a94SYusuke Goda long timeout; 238fdc50a94SYusuke Goda void __iomem *addr; 239f985da17SGuennadi Liakhovetski u32 *pio_ptr; 240ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2413b0beafcSGuennadi Liakhovetski enum mmcif_state state; 242f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 243f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 244f985da17SGuennadi Liakhovetski size_t blocksize; 245f985da17SGuennadi Liakhovetski int sg_idx; 246f985da17SGuennadi Liakhovetski int sg_blkidx; 247faca6648SGuennadi Liakhovetski bool power; 248c9b0cef2SGuennadi Liakhovetski bool card_present; 249967bcb77SGuennadi Liakhovetski bool ccs_enable; /* Command Completion Signal support */ 2506d6fd367SGuennadi Liakhovetski bool clk_ctrl2_enable; 2518047310eSGuennadi Liakhovetski struct mutex thread_lock; 252fdc50a94SYusuke Goda 253a782d688SGuennadi Liakhovetski /* DMA support */ 254a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 255a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 256a782d688SGuennadi Liakhovetski struct completion dma_complete; 257f38f94c6SLinus Walleij bool dma_active; 258a782d688SGuennadi Liakhovetski }; 259fdc50a94SYusuke Goda 26070830b41SKuninori Morimoto static const struct of_device_id mmcif_of_match[] = { 26170830b41SKuninori Morimoto { .compatible = "renesas,sh-mmcif" }, 26270830b41SKuninori Morimoto { } 26370830b41SKuninori Morimoto }; 26470830b41SKuninori Morimoto MODULE_DEVICE_TABLE(of, mmcif_of_match); 26570830b41SKuninori Morimoto 266fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 267fdc50a94SYusuke Goda unsigned int reg, u32 val) 268fdc50a94SYusuke Goda { 269487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 270fdc50a94SYusuke Goda } 271fdc50a94SYusuke Goda 272fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 273fdc50a94SYusuke Goda unsigned int reg, u32 val) 274fdc50a94SYusuke Goda { 275487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 276fdc50a94SYusuke Goda } 277fdc50a94SYusuke Goda 278a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 279a782d688SGuennadi Liakhovetski { 280a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2818047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 28269983404SGuennadi Liakhovetski 283a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 284a782d688SGuennadi Liakhovetski 2858047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 286a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 287a782d688SGuennadi Liakhovetski return; 288a782d688SGuennadi Liakhovetski 289a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 290a782d688SGuennadi Liakhovetski } 291a782d688SGuennadi Liakhovetski 292a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 293a782d688SGuennadi Liakhovetski { 29469983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 29569983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 296a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 297a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 298a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 299a782d688SGuennadi Liakhovetski int ret; 300a782d688SGuennadi Liakhovetski 30169983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3021ed828dbSLinus Walleij DMA_FROM_DEVICE); 303a782d688SGuennadi Liakhovetski if (ret > 0) { 304f38f94c6SLinus Walleij host->dma_active = true; 30516052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 30605f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 307a782d688SGuennadi Liakhovetski } 308a782d688SGuennadi Liakhovetski 309a782d688SGuennadi Liakhovetski if (desc) { 310a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 311a782d688SGuennadi Liakhovetski desc->callback_param = host; 312a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 313a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 314a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 315a782d688SGuennadi Liakhovetski } 316a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 31769983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 318a782d688SGuennadi Liakhovetski 319a782d688SGuennadi Liakhovetski if (!desc) { 320a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 321a782d688SGuennadi Liakhovetski if (ret >= 0) 322a782d688SGuennadi Liakhovetski ret = -EIO; 323a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 324f38f94c6SLinus Walleij host->dma_active = false; 325a782d688SGuennadi Liakhovetski dma_release_channel(chan); 326a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 327a782d688SGuennadi Liakhovetski chan = host->chan_tx; 328a782d688SGuennadi Liakhovetski if (chan) { 329a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 330a782d688SGuennadi Liakhovetski dma_release_channel(chan); 331a782d688SGuennadi Liakhovetski } 332a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 333a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 334a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 335a782d688SGuennadi Liakhovetski } 336a782d688SGuennadi Liakhovetski 337a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 33869983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 339a782d688SGuennadi Liakhovetski } 340a782d688SGuennadi Liakhovetski 341a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 342a782d688SGuennadi Liakhovetski { 34369983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 34469983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 345a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 346a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 347a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 348a782d688SGuennadi Liakhovetski int ret; 349a782d688SGuennadi Liakhovetski 35069983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3511ed828dbSLinus Walleij DMA_TO_DEVICE); 352a782d688SGuennadi Liakhovetski if (ret > 0) { 353f38f94c6SLinus Walleij host->dma_active = true; 35416052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 35505f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 356a782d688SGuennadi Liakhovetski } 357a782d688SGuennadi Liakhovetski 358a782d688SGuennadi Liakhovetski if (desc) { 359a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 360a782d688SGuennadi Liakhovetski desc->callback_param = host; 361a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 362a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 363a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 364a782d688SGuennadi Liakhovetski } 365a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 36669983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 367a782d688SGuennadi Liakhovetski 368a782d688SGuennadi Liakhovetski if (!desc) { 369a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 370a782d688SGuennadi Liakhovetski if (ret >= 0) 371a782d688SGuennadi Liakhovetski ret = -EIO; 372a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 373f38f94c6SLinus Walleij host->dma_active = false; 374a782d688SGuennadi Liakhovetski dma_release_channel(chan); 375a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 376a782d688SGuennadi Liakhovetski chan = host->chan_rx; 377a782d688SGuennadi Liakhovetski if (chan) { 378a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 379a782d688SGuennadi Liakhovetski dma_release_channel(chan); 380a782d688SGuennadi Liakhovetski } 381a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 382a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 383a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 384a782d688SGuennadi Liakhovetski } 385a782d688SGuennadi Liakhovetski 386a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 387a782d688SGuennadi Liakhovetski desc, cookie); 388a782d688SGuennadi Liakhovetski } 389a782d688SGuennadi Liakhovetski 390e5a233cbSLaurent Pinchart static struct dma_chan * 391e5a233cbSLaurent Pinchart sh_mmcif_request_dma_one(struct sh_mmcif_host *host, 392e5a233cbSLaurent Pinchart struct sh_mmcif_plat_data *pdata, 393e5a233cbSLaurent Pinchart enum dma_transfer_direction direction) 394a782d688SGuennadi Liakhovetski { 395d25006e7SLaurent Pinchart struct dma_slave_config cfg = { 0, }; 396e5a233cbSLaurent Pinchart struct dma_chan *chan; 3975f48dd06SKuninori Morimoto void *slave_data = NULL; 398e5a233cbSLaurent Pinchart struct resource *res; 3990e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 4000e79f9aeSGuennadi Liakhovetski int ret; 4010e79f9aeSGuennadi Liakhovetski 402e5a233cbSLaurent Pinchart dma_cap_zero(mask); 403e5a233cbSLaurent Pinchart dma_cap_set(DMA_SLAVE, mask); 404e5a233cbSLaurent Pinchart 405e5a233cbSLaurent Pinchart if (pdata) 4065f48dd06SKuninori Morimoto slave_data = direction == DMA_MEM_TO_DEV ? 4075f48dd06SKuninori Morimoto (void *)pdata->slave_id_tx : 4085f48dd06SKuninori Morimoto (void *)pdata->slave_id_rx; 409e5a233cbSLaurent Pinchart 410e5a233cbSLaurent Pinchart chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 4115f48dd06SKuninori Morimoto slave_data, &host->pd->dev, 412e5a233cbSLaurent Pinchart direction == DMA_MEM_TO_DEV ? "tx" : "rx"); 413e5a233cbSLaurent Pinchart 414e5a233cbSLaurent Pinchart dev_dbg(&host->pd->dev, "%s: %s: got channel %p\n", __func__, 415e5a233cbSLaurent Pinchart direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); 416e5a233cbSLaurent Pinchart 417e5a233cbSLaurent Pinchart if (!chan) 418e5a233cbSLaurent Pinchart return NULL; 419e5a233cbSLaurent Pinchart 420e5a233cbSLaurent Pinchart res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 421e5a233cbSLaurent Pinchart 422e5a233cbSLaurent Pinchart cfg.direction = direction; 423d25006e7SLaurent Pinchart 424e36152aaSLaurent Pinchart if (direction == DMA_DEV_TO_MEM) { 425d25006e7SLaurent Pinchart cfg.src_addr = res->start + MMCIF_CE_DATA; 426e36152aaSLaurent Pinchart cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 427e36152aaSLaurent Pinchart } else { 428e5a233cbSLaurent Pinchart cfg.dst_addr = res->start + MMCIF_CE_DATA; 429e36152aaSLaurent Pinchart cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 430e36152aaSLaurent Pinchart } 431d25006e7SLaurent Pinchart 432e5a233cbSLaurent Pinchart ret = dmaengine_slave_config(chan, &cfg); 433e5a233cbSLaurent Pinchart if (ret < 0) { 434e5a233cbSLaurent Pinchart dma_release_channel(chan); 435e5a233cbSLaurent Pinchart return NULL; 436e5a233cbSLaurent Pinchart } 437e5a233cbSLaurent Pinchart 438e5a233cbSLaurent Pinchart return chan; 439e5a233cbSLaurent Pinchart } 440e5a233cbSLaurent Pinchart 441e5a233cbSLaurent Pinchart static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 442e5a233cbSLaurent Pinchart struct sh_mmcif_plat_data *pdata) 443e5a233cbSLaurent Pinchart { 444f38f94c6SLinus Walleij host->dma_active = false; 445a782d688SGuennadi Liakhovetski 446acd6d772SGuennadi Liakhovetski if (pdata) { 4470e79f9aeSGuennadi Liakhovetski if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 4480e79f9aeSGuennadi Liakhovetski return; 449acd6d772SGuennadi Liakhovetski } else if (!host->pd->dev.of_node) { 450acd6d772SGuennadi Liakhovetski return; 451acd6d772SGuennadi Liakhovetski } 452a782d688SGuennadi Liakhovetski 453a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 454e5a233cbSLaurent Pinchart host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); 455a782d688SGuennadi Liakhovetski if (!host->chan_tx) 456a782d688SGuennadi Liakhovetski return; 457a782d688SGuennadi Liakhovetski 458e5a233cbSLaurent Pinchart host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); 459e5a233cbSLaurent Pinchart if (!host->chan_rx) { 4600e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 4610e79f9aeSGuennadi Liakhovetski host->chan_tx = NULL; 462a782d688SGuennadi Liakhovetski } 463e5a233cbSLaurent Pinchart } 464a782d688SGuennadi Liakhovetski 465a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 466a782d688SGuennadi Liakhovetski { 467a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 468a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 469a782d688SGuennadi Liakhovetski if (host->chan_tx) { 470a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 471a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 472a782d688SGuennadi Liakhovetski dma_release_channel(chan); 473a782d688SGuennadi Liakhovetski } 474a782d688SGuennadi Liakhovetski if (host->chan_rx) { 475a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 476a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 477a782d688SGuennadi Liakhovetski dma_release_channel(chan); 478a782d688SGuennadi Liakhovetski } 479a782d688SGuennadi Liakhovetski 480f38f94c6SLinus Walleij host->dma_active = false; 481a782d688SGuennadi Liakhovetski } 482fdc50a94SYusuke Goda 483fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 484fdc50a94SYusuke Goda { 485fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 486bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 487fdc50a94SYusuke Goda 488fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 489fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 490fdc50a94SYusuke Goda 491fdc50a94SYusuke Goda if (!clk) 492fdc50a94SYusuke Goda return; 493bf68a812SGuennadi Liakhovetski if (sup_pclk && clk == host->clk) 494fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 495fdc50a94SYusuke Goda else 496fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 497f9388257SSimon Horman ((fls(DIV_ROUND_UP(host->clk, 498f9388257SSimon Horman clk) - 1) - 1) << 16)); 499fdc50a94SYusuke Goda 500fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 501fdc50a94SYusuke Goda } 502fdc50a94SYusuke Goda 503fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 504fdc50a94SYusuke Goda { 505fdc50a94SYusuke Goda u32 tmp; 506fdc50a94SYusuke Goda 507487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 508fdc50a94SYusuke Goda 509487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 510487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 511967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 512967bcb77SGuennadi Liakhovetski tmp |= SCCSTO_29; 5136d6fd367SGuennadi Liakhovetski if (host->clk_ctrl2_enable) 5146d6fd367SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 515fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 516967bcb77SGuennadi Liakhovetski SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 517fdc50a94SYusuke Goda /* byte swap on */ 518fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 519fdc50a94SYusuke Goda } 520fdc50a94SYusuke Goda 521fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 522fdc50a94SYusuke Goda { 523fdc50a94SYusuke Goda u32 state1, state2; 524ee4b8887SGuennadi Liakhovetski int ret, timeout; 525fdc50a94SYusuke Goda 526aa0787a9SGuennadi Liakhovetski host->sd_error = false; 527fdc50a94SYusuke Goda 528487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 529487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 530e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 531e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 532fdc50a94SYusuke Goda 533fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 534fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 535fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 536ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 537487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 538fdc50a94SYusuke Goda & STS1_CMDSEQ)) 539fdc50a94SYusuke Goda break; 540fdc50a94SYusuke Goda mdelay(1); 541fdc50a94SYusuke Goda } 542ee4b8887SGuennadi Liakhovetski if (!timeout) { 543ee4b8887SGuennadi Liakhovetski dev_err(&host->pd->dev, 544ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 545ee4b8887SGuennadi Liakhovetski return -EIO; 546ee4b8887SGuennadi Liakhovetski } 547fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 548e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 549fdc50a94SYusuke Goda return -EIO; 550fdc50a94SYusuke Goda } 551fdc50a94SYusuke Goda 552fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 553e475b270STeppei Kamijou dev_err(&host->pd->dev, " CRC error: state %u, wait %u\n", 554e475b270STeppei Kamijou host->state, host->wait_for); 555fdc50a94SYusuke Goda ret = -EIO; 556fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 557e475b270STeppei Kamijou dev_err(&host->pd->dev, " Timeout: state %u, wait %u\n", 558e475b270STeppei Kamijou host->state, host->wait_for); 559fdc50a94SYusuke Goda ret = -ETIMEDOUT; 560fdc50a94SYusuke Goda } else { 561e475b270STeppei Kamijou dev_dbg(&host->pd->dev, " End/Index error: state %u, wait %u\n", 562e475b270STeppei Kamijou host->state, host->wait_for); 563fdc50a94SYusuke Goda ret = -EIO; 564fdc50a94SYusuke Goda } 565fdc50a94SYusuke Goda return ret; 566fdc50a94SYusuke Goda } 567fdc50a94SYusuke Goda 568f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 569f985da17SGuennadi Liakhovetski { 570f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 571f985da17SGuennadi Liakhovetski 572f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 573f985da17SGuennadi Liakhovetski 574f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 575f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 576f985da17SGuennadi Liakhovetski 577f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 578f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 579f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 580f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 581f985da17SGuennadi Liakhovetski } else { 582f985da17SGuennadi Liakhovetski host->pio_ptr = p; 583f985da17SGuennadi Liakhovetski } 584f985da17SGuennadi Liakhovetski 58599eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 586f985da17SGuennadi Liakhovetski } 587f985da17SGuennadi Liakhovetski 588f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 589fdc50a94SYusuke Goda struct mmc_request *mrq) 590fdc50a94SYusuke Goda { 591f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 592f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 593f985da17SGuennadi Liakhovetski 594f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 595fdc50a94SYusuke Goda 596fdc50a94SYusuke Goda /* buf read enable */ 597fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 598f985da17SGuennadi Liakhovetski } 599fdc50a94SYusuke Goda 600f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 601f985da17SGuennadi Liakhovetski { 602f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 603f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 604f985da17SGuennadi Liakhovetski int i; 605f985da17SGuennadi Liakhovetski 606f985da17SGuennadi Liakhovetski if (host->sd_error) { 607f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 608e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 609f985da17SGuennadi Liakhovetski return false; 610f985da17SGuennadi Liakhovetski } 611f985da17SGuennadi Liakhovetski 612f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 613487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 614fdc50a94SYusuke Goda 615fdc50a94SYusuke Goda /* buffer read end */ 616fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 617f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 618fdc50a94SYusuke Goda 619f985da17SGuennadi Liakhovetski return true; 620fdc50a94SYusuke Goda } 621fdc50a94SYusuke Goda 622f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 623fdc50a94SYusuke Goda struct mmc_request *mrq) 624fdc50a94SYusuke Goda { 625fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 626fdc50a94SYusuke Goda 627f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 628f985da17SGuennadi Liakhovetski return; 629f985da17SGuennadi Liakhovetski 630f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 631f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 632f985da17SGuennadi Liakhovetski 633f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 634f985da17SGuennadi Liakhovetski host->sg_idx = 0; 635f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 636f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6375df460b1SGuennadi Liakhovetski 638fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 639fdc50a94SYusuke Goda } 640fdc50a94SYusuke Goda 641f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 642f985da17SGuennadi Liakhovetski { 643f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 644f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 645f985da17SGuennadi Liakhovetski int i; 646f985da17SGuennadi Liakhovetski 647f985da17SGuennadi Liakhovetski if (host->sd_error) { 648f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 649e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 650f985da17SGuennadi Liakhovetski return false; 651f985da17SGuennadi Liakhovetski } 652f985da17SGuennadi Liakhovetski 653f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 654f985da17SGuennadi Liakhovetski 655f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 656f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 657f985da17SGuennadi Liakhovetski 658f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 659f985da17SGuennadi Liakhovetski return false; 660f985da17SGuennadi Liakhovetski 661f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 662f985da17SGuennadi Liakhovetski 663f985da17SGuennadi Liakhovetski return true; 664f985da17SGuennadi Liakhovetski } 665f985da17SGuennadi Liakhovetski 666f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 667fdc50a94SYusuke Goda struct mmc_request *mrq) 668fdc50a94SYusuke Goda { 669f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 670f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 671fdc50a94SYusuke Goda 672f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 673fdc50a94SYusuke Goda 674fdc50a94SYusuke Goda /* buf write enable */ 675f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 676f985da17SGuennadi Liakhovetski } 677fdc50a94SYusuke Goda 678f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 679f985da17SGuennadi Liakhovetski { 680f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 681f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 682f985da17SGuennadi Liakhovetski int i; 683f985da17SGuennadi Liakhovetski 684f985da17SGuennadi Liakhovetski if (host->sd_error) { 685f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 686e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 687f985da17SGuennadi Liakhovetski return false; 688f985da17SGuennadi Liakhovetski } 689f985da17SGuennadi Liakhovetski 690f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 691487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 692fdc50a94SYusuke Goda 693fdc50a94SYusuke Goda /* buffer write end */ 694fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 695f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 696fdc50a94SYusuke Goda 697f985da17SGuennadi Liakhovetski return true; 698fdc50a94SYusuke Goda } 699fdc50a94SYusuke Goda 700f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 701fdc50a94SYusuke Goda struct mmc_request *mrq) 702fdc50a94SYusuke Goda { 703fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 704fdc50a94SYusuke Goda 705f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 706f985da17SGuennadi Liakhovetski return; 707fdc50a94SYusuke Goda 708f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 709f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 710f985da17SGuennadi Liakhovetski 711f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 712f985da17SGuennadi Liakhovetski host->sg_idx = 0; 713f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 714f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 7155df460b1SGuennadi Liakhovetski 716fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 717fdc50a94SYusuke Goda } 718f985da17SGuennadi Liakhovetski 719f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 720f985da17SGuennadi Liakhovetski { 721f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 722f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 723f985da17SGuennadi Liakhovetski int i; 724f985da17SGuennadi Liakhovetski 725f985da17SGuennadi Liakhovetski if (host->sd_error) { 726f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 727e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, data->error); 728f985da17SGuennadi Liakhovetski return false; 729fdc50a94SYusuke Goda } 730f985da17SGuennadi Liakhovetski 731f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 732f985da17SGuennadi Liakhovetski 733f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 734f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 735f985da17SGuennadi Liakhovetski 736f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 737f985da17SGuennadi Liakhovetski return false; 738f985da17SGuennadi Liakhovetski 739f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 740f985da17SGuennadi Liakhovetski 741f985da17SGuennadi Liakhovetski return true; 742fdc50a94SYusuke Goda } 743fdc50a94SYusuke Goda 744fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 745fdc50a94SYusuke Goda struct mmc_command *cmd) 746fdc50a94SYusuke Goda { 747fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 748487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 749487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 750487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 751487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 752fdc50a94SYusuke Goda } else 753487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 754fdc50a94SYusuke Goda } 755fdc50a94SYusuke Goda 756fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 757fdc50a94SYusuke Goda struct mmc_command *cmd) 758fdc50a94SYusuke Goda { 759487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 760fdc50a94SYusuke Goda } 761fdc50a94SYusuke Goda 762fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 76369983404SGuennadi Liakhovetski struct mmc_request *mrq) 764fdc50a94SYusuke Goda { 76569983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 76669983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 76769983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 768fdc50a94SYusuke Goda u32 tmp = 0; 769fdc50a94SYusuke Goda 770fdc50a94SYusuke Goda /* Response Type check */ 771fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 772fdc50a94SYusuke Goda case MMC_RSP_NONE: 773fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 774fdc50a94SYusuke Goda break; 775fdc50a94SYusuke Goda case MMC_RSP_R1: 776fdc50a94SYusuke Goda case MMC_RSP_R1B: 777fdc50a94SYusuke Goda case MMC_RSP_R3: 778fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 779fdc50a94SYusuke Goda break; 780fdc50a94SYusuke Goda case MMC_RSP_R2: 781fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 782fdc50a94SYusuke Goda break; 783fdc50a94SYusuke Goda default: 784e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 785fdc50a94SYusuke Goda break; 786fdc50a94SYusuke Goda } 787fdc50a94SYusuke Goda switch (opc) { 788fdc50a94SYusuke Goda /* RBSY */ 789a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 790fdc50a94SYusuke Goda case MMC_SWITCH: 791fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 792fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 793fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 794fdc50a94SYusuke Goda case MMC_ERASE: 795fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 796fdc50a94SYusuke Goda break; 797fdc50a94SYusuke Goda } 798fdc50a94SYusuke Goda /* WDAT / DATW */ 79969983404SGuennadi Liakhovetski if (data) { 800fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 801fdc50a94SYusuke Goda switch (host->bus_width) { 802fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 803fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 804fdc50a94SYusuke Goda break; 805fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 806fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 807fdc50a94SYusuke Goda break; 808fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 809fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 810fdc50a94SYusuke Goda break; 811fdc50a94SYusuke Goda default: 812e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 813fdc50a94SYusuke Goda break; 814fdc50a94SYusuke Goda } 815555061f9STeppei Kamijou switch (host->timing) { 8164039ff47SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 817555061f9STeppei Kamijou /* 818555061f9STeppei Kamijou * MMC core will only set this timing, if the host 8194039ff47SSeungwon Jeon * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 8204039ff47SSeungwon Jeon * capability. MMCIF implementations with this 8214039ff47SSeungwon Jeon * capability, e.g. sh73a0, will have to set it 8224039ff47SSeungwon Jeon * in their platform data. 823555061f9STeppei Kamijou */ 824555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 825555061f9STeppei Kamijou break; 826555061f9STeppei Kamijou } 827fdc50a94SYusuke Goda } 828fdc50a94SYusuke Goda /* DWEN */ 829fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 830fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 831fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 832fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 833fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 834fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 83569983404SGuennadi Liakhovetski data->blocks << 16); 836fdc50a94SYusuke Goda } 837fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 838fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 839fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 840fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 841fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 842fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 843fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 844fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 845fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 846fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 847fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 848fdc50a94SYusuke Goda 84969983404SGuennadi Liakhovetski return (opc << 24) | tmp; 850fdc50a94SYusuke Goda } 851fdc50a94SYusuke Goda 852e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 853fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 854fdc50a94SYusuke Goda { 855fdc50a94SYusuke Goda switch (opc) { 856fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 857f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 858f985da17SGuennadi Liakhovetski return 0; 859fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 860f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 861f985da17SGuennadi Liakhovetski return 0; 862fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 863f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 864f985da17SGuennadi Liakhovetski return 0; 865fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 866fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 867f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 868f985da17SGuennadi Liakhovetski return 0; 869fdc50a94SYusuke Goda default: 870e475b270STeppei Kamijou dev_err(&host->pd->dev, "Unsupported CMD%d\n", opc); 871ee4b8887SGuennadi Liakhovetski return -EINVAL; 872fdc50a94SYusuke Goda } 873fdc50a94SYusuke Goda } 874fdc50a94SYusuke Goda 875fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 876ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 877fdc50a94SYusuke Goda { 878ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 879f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 880f985da17SGuennadi Liakhovetski u32 mask; 881dbb42d96SKouichi Tomita unsigned long flags; 882fdc50a94SYusuke Goda 883fdc50a94SYusuke Goda switch (opc) { 884ee4b8887SGuennadi Liakhovetski /* response busy check */ 885a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 886fdc50a94SYusuke Goda case MMC_SWITCH: 887fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 888fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 889fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 890fdc50a94SYusuke Goda case MMC_ERASE: 891ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 892fdc50a94SYusuke Goda break; 893fdc50a94SYusuke Goda default: 894ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 895fdc50a94SYusuke Goda break; 896fdc50a94SYusuke Goda } 897fdc50a94SYusuke Goda 898967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 899967bcb77SGuennadi Liakhovetski mask |= MASK_MCCSTO; 900967bcb77SGuennadi Liakhovetski 90169983404SGuennadi Liakhovetski if (mrq->data) { 902487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 903487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 904487d9fc5SMagnus Damm mrq->data->blksz); 905fdc50a94SYusuke Goda } 90669983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 907fdc50a94SYusuke Goda 908967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 909487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 910967bcb77SGuennadi Liakhovetski else 911967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 912487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 913fdc50a94SYusuke Goda /* set arg */ 914487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 915fdc50a94SYusuke Goda /* set cmd */ 916dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 917487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 918fdc50a94SYusuke Goda 919f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 920f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 921dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 922fdc50a94SYusuke Goda } 923fdc50a94SYusuke Goda 924fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 925ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 926fdc50a94SYusuke Goda { 92769983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 92869983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 929fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 93069983404SGuennadi Liakhovetski break; 93169983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 932fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 93369983404SGuennadi Liakhovetski break; 93469983404SGuennadi Liakhovetski default: 935e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 93669983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 937fdc50a94SYusuke Goda return; 938fdc50a94SYusuke Goda } 939fdc50a94SYusuke Goda 940f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 941fdc50a94SYusuke Goda } 942fdc50a94SYusuke Goda 943fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 944fdc50a94SYusuke Goda { 945fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 9463b0beafcSGuennadi Liakhovetski unsigned long flags; 9473b0beafcSGuennadi Liakhovetski 9483b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9493b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 950e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 9513b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9523b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9533b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9543b0beafcSGuennadi Liakhovetski return; 9553b0beafcSGuennadi Liakhovetski } 9563b0beafcSGuennadi Liakhovetski 9573b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9583b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 959fdc50a94SYusuke Goda 960fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 961fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 9627541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 9637541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 9647541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 9657541ca98SLaurent Pinchart break; 966fdc50a94SYusuke Goda case MMC_APP_CMD: 96792ff0c5bSTeppei Kamijou case SD_IO_RW_DIRECT: 9683b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 969fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 970fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 971fdc50a94SYusuke Goda return; 972fdc50a94SYusuke Goda default: 973fdc50a94SYusuke Goda break; 974fdc50a94SYusuke Goda } 975fdc50a94SYusuke Goda 976f985da17SGuennadi Liakhovetski host->mrq = mrq; 977f985da17SGuennadi Liakhovetski 978f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 979fdc50a94SYusuke Goda } 980fdc50a94SYusuke Goda 981a6609267SGuennadi Liakhovetski static int sh_mmcif_clk_update(struct sh_mmcif_host *host) 982a6609267SGuennadi Liakhovetski { 983ac0a2e98SUlf Hansson int ret = clk_prepare_enable(host->hclk); 984a6609267SGuennadi Liakhovetski 985a6609267SGuennadi Liakhovetski if (!ret) { 986a6609267SGuennadi Liakhovetski host->clk = clk_get_rate(host->hclk); 987a6609267SGuennadi Liakhovetski host->mmc->f_max = host->clk / 2; 988a6609267SGuennadi Liakhovetski host->mmc->f_min = host->clk / 512; 989a6609267SGuennadi Liakhovetski } 990a6609267SGuennadi Liakhovetski 991a6609267SGuennadi Liakhovetski return ret; 992a6609267SGuennadi Liakhovetski } 993a6609267SGuennadi Liakhovetski 9947d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 9957d17baa0SGuennadi Liakhovetski { 9967d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 9977d17baa0SGuennadi Liakhovetski 9987d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 9997d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 10007d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 10017d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 10027d17baa0SGuennadi Liakhovetski } 10037d17baa0SGuennadi Liakhovetski 1004fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1005fdc50a94SYusuke Goda { 1006fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 10073b0beafcSGuennadi Liakhovetski unsigned long flags; 10083b0beafcSGuennadi Liakhovetski 10093b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 10103b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 1011e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s() rejected, state %u\n", __func__, host->state); 10123b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 10133b0beafcSGuennadi Liakhovetski return; 10143b0beafcSGuennadi Liakhovetski } 10153b0beafcSGuennadi Liakhovetski 10163b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 10173b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 1018fdc50a94SYusuke Goda 1019f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 1020c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 1021faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 1022faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 1023c9b0cef2SGuennadi Liakhovetski host->card_present = true; 1024faca6648SGuennadi Liakhovetski } 10257d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1026f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 1027f5e0cec4SGuennadi Liakhovetski /* clock stop */ 1028f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 1029faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 1030c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 1031c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 1032c9b0cef2SGuennadi Liakhovetski host->card_present = false; 1033c9b0cef2SGuennadi Liakhovetski } 1034c9b0cef2SGuennadi Liakhovetski } 1035faca6648SGuennadi Liakhovetski if (host->power) { 1036f8a8ced7STeppei Kamijou pm_runtime_put_sync(&host->pd->dev); 1037ac0a2e98SUlf Hansson clk_disable_unprepare(host->hclk); 1038faca6648SGuennadi Liakhovetski host->power = false; 10397d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 10407d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1041faca6648SGuennadi Liakhovetski } 10423b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1043f5e0cec4SGuennadi Liakhovetski return; 1044fdc50a94SYusuke Goda } 1045fdc50a94SYusuke Goda 1046c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 1047c9b0cef2SGuennadi Liakhovetski if (!host->power) { 1048a6609267SGuennadi Liakhovetski sh_mmcif_clk_update(host); 1049c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 1050c9b0cef2SGuennadi Liakhovetski host->power = true; 1051c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 1052c9b0cef2SGuennadi Liakhovetski } 1053fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 1054c9b0cef2SGuennadi Liakhovetski } 1055fdc50a94SYusuke Goda 1056555061f9STeppei Kamijou host->timing = ios->timing; 1057fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10583b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1059fdc50a94SYusuke Goda } 1060fdc50a94SYusuke Goda 1061777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1062777271d0SArnd Hannemann { 1063777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1064777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 1065e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1066e480606aSGuennadi Liakhovetski 1067e480606aSGuennadi Liakhovetski if (ret >= 0) 1068e480606aSGuennadi Liakhovetski return ret; 1069777271d0SArnd Hannemann 1070bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1071777271d0SArnd Hannemann return -ENOSYS; 1072777271d0SArnd Hannemann else 1073777271d0SArnd Hannemann return p->get_cd(host->pd); 1074777271d0SArnd Hannemann } 1075777271d0SArnd Hannemann 1076fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1077fdc50a94SYusuke Goda .request = sh_mmcif_request, 1078fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1079777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1080fdc50a94SYusuke Goda }; 1081fdc50a94SYusuke Goda 1082f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1083f985da17SGuennadi Liakhovetski { 1084f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 108569983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1086f985da17SGuennadi Liakhovetski long time; 1087f985da17SGuennadi Liakhovetski 1088f985da17SGuennadi Liakhovetski if (host->sd_error) { 1089f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1090f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1091f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1092f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1093f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1094f985da17SGuennadi Liakhovetski break; 1095f985da17SGuennadi Liakhovetski default: 1096f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1097f985da17SGuennadi Liakhovetski break; 1098f985da17SGuennadi Liakhovetski } 1099e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "CMD%d error %d\n", 1100e475b270STeppei Kamijou cmd->opcode, cmd->error); 1101aba9d646SGuennadi Liakhovetski host->sd_error = false; 1102f985da17SGuennadi Liakhovetski return false; 1103f985da17SGuennadi Liakhovetski } 1104f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1105f985da17SGuennadi Liakhovetski cmd->error = 0; 1106f985da17SGuennadi Liakhovetski return false; 1107f985da17SGuennadi Liakhovetski } 1108f985da17SGuennadi Liakhovetski 1109f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1110f985da17SGuennadi Liakhovetski 111169983404SGuennadi Liakhovetski if (!data) 1112f985da17SGuennadi Liakhovetski return false; 1113f985da17SGuennadi Liakhovetski 111490f1cb43SGuennadi Liakhovetski /* 111590f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to 111690f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active 111790f1cb43SGuennadi Liakhovetski */ 111890f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete); 111990f1cb43SGuennadi Liakhovetski 112069983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1121f985da17SGuennadi Liakhovetski if (host->chan_rx) 1122f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1123f985da17SGuennadi Liakhovetski } else { 1124f985da17SGuennadi Liakhovetski if (host->chan_tx) 1125f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1126f985da17SGuennadi Liakhovetski } 1127f985da17SGuennadi Liakhovetski 1128f985da17SGuennadi Liakhovetski if (!host->dma_active) { 112969983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 113099eb9d8dSGuennadi Liakhovetski return !data->error; 1131f985da17SGuennadi Liakhovetski } 1132f985da17SGuennadi Liakhovetski 1133f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1134f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1135f985da17SGuennadi Liakhovetski host->timeout); 1136eae30983STeppei Kamijou 1137eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1138eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1139eae30983STeppei Kamijou data->sg, data->sg_len, 1140eae30983STeppei Kamijou DMA_FROM_DEVICE); 1141eae30983STeppei Kamijou else 1142eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1143eae30983STeppei Kamijou data->sg, data->sg_len, 1144eae30983STeppei Kamijou DMA_TO_DEVICE); 1145eae30983STeppei Kamijou 1146f985da17SGuennadi Liakhovetski if (host->sd_error) { 1147f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1148f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1149f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 115069983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1151f985da17SGuennadi Liakhovetski } else if (!time) { 1152e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n"); 115369983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1154f985da17SGuennadi Liakhovetski } else if (time < 0) { 1155e475b270STeppei Kamijou dev_err(host->mmc->parent, 1156e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time); 115769983404SGuennadi Liakhovetski data->error = time; 1158f985da17SGuennadi Liakhovetski } 1159f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1160f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1161f985da17SGuennadi Liakhovetski host->dma_active = false; 1162f985da17SGuennadi Liakhovetski 1163eae30983STeppei Kamijou if (data->error) { 116469983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1165eae30983STeppei Kamijou /* Abort DMA */ 1166eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1167eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1168eae30983STeppei Kamijou else 1169eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1170eae30983STeppei Kamijou } 1171f985da17SGuennadi Liakhovetski 1172f985da17SGuennadi Liakhovetski return false; 1173f985da17SGuennadi Liakhovetski } 1174f985da17SGuennadi Liakhovetski 1175f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1176f985da17SGuennadi Liakhovetski { 1177f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 11788047310eSGuennadi Liakhovetski struct mmc_request *mrq; 11795df460b1SGuennadi Liakhovetski bool wait = false; 1180dbb42d96SKouichi Tomita unsigned long flags; 1181dbb42d96SKouichi Tomita int wait_work; 1182dbb42d96SKouichi Tomita 1183dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 1184dbb42d96SKouichi Tomita wait_work = host->wait_for; 1185dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 1186f985da17SGuennadi Liakhovetski 1187f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1188f985da17SGuennadi Liakhovetski 11898047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 11908047310eSGuennadi Liakhovetski 11918047310eSGuennadi Liakhovetski mrq = host->mrq; 11928047310eSGuennadi Liakhovetski if (!mrq) { 11938047310eSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 11948047310eSGuennadi Liakhovetski host->state, host->wait_for); 11958047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 11968047310eSGuennadi Liakhovetski return IRQ_HANDLED; 11978047310eSGuennadi Liakhovetski } 11988047310eSGuennadi Liakhovetski 1199f985da17SGuennadi Liakhovetski /* 1200f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1201f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1202f985da17SGuennadi Liakhovetski */ 1203dbb42d96SKouichi Tomita switch (wait_work) { 1204f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1205f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 12068047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1207f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1208f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 12095df460b1SGuennadi Liakhovetski /* Wait for data? */ 12105df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1211f985da17SGuennadi Liakhovetski break; 1212f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 12135df460b1SGuennadi Liakhovetski /* Wait for more data? */ 12145df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1215f985da17SGuennadi Liakhovetski break; 1216f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 12175df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12185df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1219f985da17SGuennadi Liakhovetski break; 1220f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 12215df460b1SGuennadi Liakhovetski /* Wait data to write? */ 12225df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1223f985da17SGuennadi Liakhovetski break; 1224f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 12255df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12265df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1227f985da17SGuennadi Liakhovetski break; 1228f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1229f985da17SGuennadi Liakhovetski if (host->sd_error) { 1230f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1231e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->stop->error); 1232f985da17SGuennadi Liakhovetski break; 1233f985da17SGuennadi Liakhovetski } 1234f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1235f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1236f985da17SGuennadi Liakhovetski break; 1237f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1238f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1239e475b270STeppei Kamijou if (host->sd_error) { 124091ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1241e475b270STeppei Kamijou dev_dbg(&host->pd->dev, "%s(): %d\n", __func__, mrq->data->error); 1242e475b270STeppei Kamijou } 1243f985da17SGuennadi Liakhovetski break; 1244f985da17SGuennadi Liakhovetski default: 1245f985da17SGuennadi Liakhovetski BUG(); 1246f985da17SGuennadi Liakhovetski } 1247f985da17SGuennadi Liakhovetski 12485df460b1SGuennadi Liakhovetski if (wait) { 12495df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12505df460b1SGuennadi Liakhovetski /* Wait for more data */ 12518047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12525df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 12535df460b1SGuennadi Liakhovetski } 12545df460b1SGuennadi Liakhovetski 1255f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 125691ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 125769983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 125869983404SGuennadi Liakhovetski data->bytes_xfered = 125969983404SGuennadi Liakhovetski data->blocks * data->blksz; 1260f985da17SGuennadi Liakhovetski 126169983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1262f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 12635df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 12645df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12658047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1266f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1267f985da17SGuennadi Liakhovetski } 1268f985da17SGuennadi Liakhovetski } 12695df460b1SGuennadi Liakhovetski } 1270f985da17SGuennadi Liakhovetski 1271f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1272f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 127369983404SGuennadi Liakhovetski host->mrq = NULL; 1274f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1275f985da17SGuennadi Liakhovetski 12768047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12778047310eSGuennadi Liakhovetski 1278f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1279f985da17SGuennadi Liakhovetski } 1280f985da17SGuennadi Liakhovetski 1281fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1282fdc50a94SYusuke Goda { 1283fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1284967bcb77SGuennadi Liakhovetski u32 state, mask; 1285fdc50a94SYusuke Goda 1286487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1287967bcb77SGuennadi Liakhovetski mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1288967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 1289967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1290967bcb77SGuennadi Liakhovetski else 1291967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 12928af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1293fdc50a94SYusuke Goda 12948af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN) 12958af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "IRQ state = 0x%08x incompletely cleared\n", 12968af50750SGuennadi Liakhovetski state); 12978af50750SGuennadi Liakhovetski 12988af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) { 1299aa0787a9SGuennadi Liakhovetski host->sd_error = true; 13008af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = 0x%08x\n", state); 1301fdc50a94SYusuke Goda } 1302f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 13038af50750SGuennadi Liakhovetski if (!host->mrq) 13048af50750SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "NULL IRQ state = 0x%08x\n", state); 1305f985da17SGuennadi Liakhovetski if (!host->dma_active) 1306f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1307f985da17SGuennadi Liakhovetski else if (host->sd_error) 1308f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1309f985da17SGuennadi Liakhovetski } else { 1310aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1311f985da17SGuennadi Liakhovetski } 1312fdc50a94SYusuke Goda 1313fdc50a94SYusuke Goda return IRQ_HANDLED; 1314fdc50a94SYusuke Goda } 1315fdc50a94SYusuke Goda 1316f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1317f985da17SGuennadi Liakhovetski { 1318f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1319f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1320f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 13218047310eSGuennadi Liakhovetski unsigned long flags; 1322f985da17SGuennadi Liakhovetski 1323f985da17SGuennadi Liakhovetski if (host->dying) 1324f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1325f985da17SGuennadi Liakhovetski return; 1326f985da17SGuennadi Liakhovetski 13278047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 13288047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 13298047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13308047310eSGuennadi Liakhovetski return; 13318047310eSGuennadi Liakhovetski } 13328047310eSGuennadi Liakhovetski 13334cbd5224SKouichi Tomita dev_err(&host->pd->dev, "Timeout waiting for %u on CMD%u\n", 13344cbd5224SKouichi Tomita host->wait_for, mrq->cmd->opcode); 13354cbd5224SKouichi Tomita 13368047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 13378047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13388047310eSGuennadi Liakhovetski 1339f985da17SGuennadi Liakhovetski /* 1340f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1341f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1342f985da17SGuennadi Liakhovetski */ 1343f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1344f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1345f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1346f985da17SGuennadi Liakhovetski break; 1347f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1348f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1349f985da17SGuennadi Liakhovetski break; 1350f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1351f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1352f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1353f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1354f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1355f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 135669983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1357f985da17SGuennadi Liakhovetski break; 1358f985da17SGuennadi Liakhovetski default: 1359f985da17SGuennadi Liakhovetski BUG(); 1360f985da17SGuennadi Liakhovetski } 1361f985da17SGuennadi Liakhovetski 1362f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1363f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1364f985da17SGuennadi Liakhovetski host->mrq = NULL; 1365f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1366f985da17SGuennadi Liakhovetski } 1367f985da17SGuennadi Liakhovetski 13687d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 13697d17baa0SGuennadi Liakhovetski { 13707d17baa0SGuennadi Liakhovetski struct sh_mmcif_plat_data *pd = host->pd->dev.platform_data; 13717d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 13727d17baa0SGuennadi Liakhovetski 13737d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 13747d17baa0SGuennadi Liakhovetski 1375bf68a812SGuennadi Liakhovetski if (!pd) 1376bf68a812SGuennadi Liakhovetski return; 1377bf68a812SGuennadi Liakhovetski 13787d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 13797d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 13807d17baa0SGuennadi Liakhovetski else if (pd->ocr) 13817d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 13827d17baa0SGuennadi Liakhovetski } 13837d17baa0SGuennadi Liakhovetski 1384c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1385fdc50a94SYusuke Goda { 1386fdc50a94SYusuke Goda int ret = 0, irq[2]; 1387fdc50a94SYusuke Goda struct mmc_host *mmc; 1388e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 138960985c39SKuninori Morimoto struct device *dev = &pdev->dev; 139060985c39SKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 1391fdc50a94SYusuke Goda struct resource *res; 1392fdc50a94SYusuke Goda void __iomem *reg; 13932cd5b3e0SShinya Kuribayashi const char *name; 1394fdc50a94SYusuke Goda 1395fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1396fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 13972cd5b3e0SShinya Kuribayashi if (irq[0] < 0) { 139860985c39SKuninori Morimoto dev_err(dev, "Get irq error\n"); 1399fdc50a94SYusuke Goda return -ENXIO; 1400fdc50a94SYusuke Goda } 140118f55fccSBen Dooks 1402fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 140360985c39SKuninori Morimoto reg = devm_ioremap_resource(dev, res); 140418f55fccSBen Dooks if (IS_ERR(reg)) 140518f55fccSBen Dooks return PTR_ERR(reg); 1406e1aae2ebSGuennadi Liakhovetski 140760985c39SKuninori Morimoto mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 140818f55fccSBen Dooks if (!mmc) 140918f55fccSBen Dooks return -ENOMEM; 14102c9054dcSSimon Baatz 14112c9054dcSSimon Baatz ret = mmc_of_parse(mmc); 14122c9054dcSSimon Baatz if (ret < 0) 141346991005SBen Dooks goto err_host; 14142c9054dcSSimon Baatz 1415fdc50a94SYusuke Goda host = mmc_priv(mmc); 1416fdc50a94SYusuke Goda host->mmc = mmc; 1417fdc50a94SYusuke Goda host->addr = reg; 1418bad4371dSTakeshi Kihara host->timeout = msecs_to_jiffies(10000); 1419967bcb77SGuennadi Liakhovetski host->ccs_enable = !pd || !pd->ccs_unsupported; 14206d6fd367SGuennadi Liakhovetski host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; 1421fdc50a94SYusuke Goda 1422fdc50a94SYusuke Goda host->pd = pdev; 1423fdc50a94SYusuke Goda 14243b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1425fdc50a94SYusuke Goda 1426fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 14277d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 14287d17baa0SGuennadi Liakhovetski 1429eca889f6SGuennadi Liakhovetski mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1430bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1431fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1432a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1433fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1434a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1435a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1436fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1437fdc50a94SYusuke Goda 1438fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1439a782d688SGuennadi Liakhovetski 144060985c39SKuninori Morimoto pm_runtime_enable(dev); 1441faca6648SGuennadi Liakhovetski host->power = false; 1442faca6648SGuennadi Liakhovetski 144360985c39SKuninori Morimoto host->hclk = devm_clk_get(dev, NULL); 1444b289174fSGuennadi Liakhovetski if (IS_ERR(host->hclk)) { 1445b289174fSGuennadi Liakhovetski ret = PTR_ERR(host->hclk); 144660985c39SKuninori Morimoto dev_err(dev, "cannot get clock: %d\n", ret); 144746991005SBen Dooks goto err_pm; 1448b289174fSGuennadi Liakhovetski } 1449a6609267SGuennadi Liakhovetski ret = sh_mmcif_clk_update(host); 1450a6609267SGuennadi Liakhovetski if (ret < 0) 145146991005SBen Dooks goto err_pm; 1452b289174fSGuennadi Liakhovetski 145360985c39SKuninori Morimoto ret = pm_runtime_resume(dev); 1454faca6648SGuennadi Liakhovetski if (ret < 0) 145546991005SBen Dooks goto err_clk; 1456a782d688SGuennadi Liakhovetski 14575ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1458fdc50a94SYusuke Goda 1459b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 14603b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14613b0beafcSGuennadi Liakhovetski 146260985c39SKuninori Morimoto name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; 146360985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, 14646f4789e6SBen Dooks sh_mmcif_irqt, 0, name, host); 1465fdc50a94SYusuke Goda if (ret) { 146660985c39SKuninori Morimoto dev_err(dev, "request_irq error (%s)\n", name); 146711a80852SBen Dooks goto err_clk; 1468fdc50a94SYusuke Goda } 14692cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 147060985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[1], 14716f4789e6SBen Dooks sh_mmcif_intr, sh_mmcif_irqt, 14722cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1473fdc50a94SYusuke Goda if (ret) { 147460985c39SKuninori Morimoto dev_err(dev, "request_irq error (sh_mmc:int)\n"); 147511a80852SBen Dooks goto err_clk; 1476fdc50a94SYusuke Goda } 14772cd5b3e0SShinya Kuribayashi } 1478fdc50a94SYusuke Goda 1479e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1480214fc309SLaurent Pinchart ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); 1481e480606aSGuennadi Liakhovetski if (ret < 0) 14827f67f3a2SBen Dooks goto err_clk; 1483e480606aSGuennadi Liakhovetski } 1484e480606aSGuennadi Liakhovetski 14858047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 14868047310eSGuennadi Liakhovetski 14875ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 14885ba85d95SGuennadi Liakhovetski if (ret < 0) 14897f67f3a2SBen Dooks goto err_clk; 1490fdc50a94SYusuke Goda 149160985c39SKuninori Morimoto dev_pm_qos_expose_latency_limit(dev, 100); 1492efe6a8adSRafael J. Wysocki 149360985c39SKuninori Morimoto dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", 1494ce7eb688SBen Dooks sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 1495ce7eb688SBen Dooks clk_get_rate(host->hclk) / 1000000UL); 1496ce7eb688SBen Dooks 1497ce7eb688SBen Dooks clk_disable_unprepare(host->hclk); 1498fdc50a94SYusuke Goda return ret; 1499fdc50a94SYusuke Goda 150046991005SBen Dooks err_clk: 1501ac0a2e98SUlf Hansson clk_disable_unprepare(host->hclk); 150246991005SBen Dooks err_pm: 150360985c39SKuninori Morimoto pm_runtime_disable(dev); 150446991005SBen Dooks err_host: 1505fdc50a94SYusuke Goda mmc_free_host(mmc); 1506fdc50a94SYusuke Goda return ret; 1507fdc50a94SYusuke Goda } 1508fdc50a94SYusuke Goda 15096e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1510fdc50a94SYusuke Goda { 1511fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1512fdc50a94SYusuke Goda 1513f985da17SGuennadi Liakhovetski host->dying = true; 1514ac0a2e98SUlf Hansson clk_prepare_enable(host->hclk); 1515faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1516aa0787a9SGuennadi Liakhovetski 1517efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1518efe6a8adSRafael J. Wysocki 1519faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 15203b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15213b0beafcSGuennadi Liakhovetski 1522f985da17SGuennadi Liakhovetski /* 1523f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1524f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1525f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1526f985da17SGuennadi Liakhovetski */ 1527f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1528f985da17SGuennadi Liakhovetski 1529ac0a2e98SUlf Hansson clk_disable_unprepare(host->hclk); 1530fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1531faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1532faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1533fdc50a94SYusuke Goda 1534fdc50a94SYusuke Goda return 0; 1535fdc50a94SYusuke Goda } 1536fdc50a94SYusuke Goda 153751129f31SUlf Hansson #ifdef CONFIG_PM_SLEEP 1538faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1539faca6648SGuennadi Liakhovetski { 1540b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1541faca6648SGuennadi Liakhovetski 1542faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1543faca6648SGuennadi Liakhovetski 1544cb3ca1aeSUlf Hansson return 0; 1545faca6648SGuennadi Liakhovetski } 1546faca6648SGuennadi Liakhovetski 1547faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1548faca6648SGuennadi Liakhovetski { 1549cb3ca1aeSUlf Hansson return 0; 1550faca6648SGuennadi Liakhovetski } 155151129f31SUlf Hansson #endif 1552faca6648SGuennadi Liakhovetski 1553faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 155451129f31SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1555faca6648SGuennadi Liakhovetski }; 1556faca6648SGuennadi Liakhovetski 1557fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1558fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1559fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1560fdc50a94SYusuke Goda .driver = { 1561fdc50a94SYusuke Goda .name = DRIVER_NAME, 1562faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1563bf68a812SGuennadi Liakhovetski .of_match_table = mmcif_of_match, 1564fdc50a94SYusuke Goda }, 1565fdc50a94SYusuke Goda }; 1566fdc50a94SYusuke Goda 1567d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1568fdc50a94SYusuke Goda 1569fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1570fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1571aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1572fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1573