1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 58e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 59faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 603b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6188b47679SPaul Gortmaker #include <linux/module.h> 62fdc50a94SYusuke Goda 63fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 64fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 65fdc50a94SYusuke Goda 66fdc50a94SYusuke Goda /* CE_CMD_SET */ 67fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 68fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 69fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 70fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 71fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 72fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 73fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 74fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 75fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 76fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 77fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 78fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 79fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 80fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 81fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 82fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 83fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 84fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 85fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 86fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 87fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 88fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 89fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 90fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 91fdc50a94SYusuke Goda 92fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 93fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 94fdc50a94SYusuke Goda 95fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 96fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 97fdc50a94SYusuke Goda 98fdc50a94SYusuke Goda /* CE_INT */ 99fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 100fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 101fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 102fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 103fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 104fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 105fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 106fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 107fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 108fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 109fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 110fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 111fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 112fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 113fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 114fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 115fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 116fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 117fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 118fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 119fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 120fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 121fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 122fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 123fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 124fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 125fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 126fdc50a94SYusuke Goda 127fdc50a94SYusuke Goda /* CE_INT_MASK */ 128fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 129fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 130fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 131fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 132fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 133fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 134fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 135fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 136fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 137fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 138fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 139fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 140fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 141fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 142fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 143fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 144fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 145fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 146fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 147fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 148fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 149fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 150fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 151fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 152fdc50a94SYusuke Goda 153ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 154ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 155ee4b8887SGuennadi Liakhovetski MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | \ 156ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 157ee4b8887SGuennadi Liakhovetski 158fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 159fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 160fdc50a94SYusuke Goda 161fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 162fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 163fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 164fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 165fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 166fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 167fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 168fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 169fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 170fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 171fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 172fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 173fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 174fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 175fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 176fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 177fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 178fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 179fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 180fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 181fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 182fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 183fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 184fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 185fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 186fdc50a94SYusuke Goda 187fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 188fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 189fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 190fdc50a94SYusuke Goda 1913b0beafcSGuennadi Liakhovetski enum mmcif_state { 1923b0beafcSGuennadi Liakhovetski STATE_IDLE, 1933b0beafcSGuennadi Liakhovetski STATE_REQUEST, 1943b0beafcSGuennadi Liakhovetski STATE_IOS, 1953b0beafcSGuennadi Liakhovetski }; 1963b0beafcSGuennadi Liakhovetski 197f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 198f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 199f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 200f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 201f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 202f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 203f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 204f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 205f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 206f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 207f985da17SGuennadi Liakhovetski }; 208f985da17SGuennadi Liakhovetski 209fdc50a94SYusuke Goda struct sh_mmcif_host { 210fdc50a94SYusuke Goda struct mmc_host *mmc; 211f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 212fdc50a94SYusuke Goda struct platform_device *pd; 213714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave dma_slave_tx; 214714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave dma_slave_rx; 215fdc50a94SYusuke Goda struct clk *hclk; 216fdc50a94SYusuke Goda unsigned int clk; 217fdc50a94SYusuke Goda int bus_width; 218aa0787a9SGuennadi Liakhovetski bool sd_error; 219f985da17SGuennadi Liakhovetski bool dying; 220fdc50a94SYusuke Goda long timeout; 221fdc50a94SYusuke Goda void __iomem *addr; 222f985da17SGuennadi Liakhovetski u32 *pio_ptr; 223ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2243b0beafcSGuennadi Liakhovetski enum mmcif_state state; 225f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 226f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 227f985da17SGuennadi Liakhovetski size_t blocksize; 228f985da17SGuennadi Liakhovetski int sg_idx; 229f985da17SGuennadi Liakhovetski int sg_blkidx; 230faca6648SGuennadi Liakhovetski bool power; 231c9b0cef2SGuennadi Liakhovetski bool card_present; 232fdc50a94SYusuke Goda 233a782d688SGuennadi Liakhovetski /* DMA support */ 234a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 235a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 236a782d688SGuennadi Liakhovetski struct completion dma_complete; 237f38f94c6SLinus Walleij bool dma_active; 238a782d688SGuennadi Liakhovetski }; 239fdc50a94SYusuke Goda 240fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 241fdc50a94SYusuke Goda unsigned int reg, u32 val) 242fdc50a94SYusuke Goda { 243487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 244fdc50a94SYusuke Goda } 245fdc50a94SYusuke Goda 246fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 247fdc50a94SYusuke Goda unsigned int reg, u32 val) 248fdc50a94SYusuke Goda { 249487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 250fdc50a94SYusuke Goda } 251fdc50a94SYusuke Goda 252a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 253a782d688SGuennadi Liakhovetski { 254a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 25569983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 25669983404SGuennadi Liakhovetski 257a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 258a782d688SGuennadi Liakhovetski 25969983404SGuennadi Liakhovetski if (WARN(!data, "%s: NULL data in DMA completion!\n", 260a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 261a782d688SGuennadi Liakhovetski return; 262a782d688SGuennadi Liakhovetski 26369983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) 2641ed828dbSLinus Walleij dma_unmap_sg(host->chan_rx->device->dev, 26569983404SGuennadi Liakhovetski data->sg, data->sg_len, 266a782d688SGuennadi Liakhovetski DMA_FROM_DEVICE); 267a782d688SGuennadi Liakhovetski else 2681ed828dbSLinus Walleij dma_unmap_sg(host->chan_tx->device->dev, 26969983404SGuennadi Liakhovetski data->sg, data->sg_len, 270a782d688SGuennadi Liakhovetski DMA_TO_DEVICE); 271a782d688SGuennadi Liakhovetski 272a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 273a782d688SGuennadi Liakhovetski } 274a782d688SGuennadi Liakhovetski 275a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 276a782d688SGuennadi Liakhovetski { 27769983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 27869983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 279a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 280a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 281a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 282a782d688SGuennadi Liakhovetski int ret; 283a782d688SGuennadi Liakhovetski 28469983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 2851ed828dbSLinus Walleij DMA_FROM_DEVICE); 286a782d688SGuennadi Liakhovetski if (ret > 0) { 287f38f94c6SLinus Walleij host->dma_active = true; 288a782d688SGuennadi Liakhovetski desc = chan->device->device_prep_slave_sg(chan, sg, ret, 28905f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 290a782d688SGuennadi Liakhovetski } 291a782d688SGuennadi Liakhovetski 292a782d688SGuennadi Liakhovetski if (desc) { 293a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 294a782d688SGuennadi Liakhovetski desc->callback_param = host; 295a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 296a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 297a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 298a782d688SGuennadi Liakhovetski } 299a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 30069983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 301a782d688SGuennadi Liakhovetski 302a782d688SGuennadi Liakhovetski if (!desc) { 303a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 304a782d688SGuennadi Liakhovetski if (ret >= 0) 305a782d688SGuennadi Liakhovetski ret = -EIO; 306a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 307f38f94c6SLinus Walleij host->dma_active = false; 308a782d688SGuennadi Liakhovetski dma_release_channel(chan); 309a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 310a782d688SGuennadi Liakhovetski chan = host->chan_tx; 311a782d688SGuennadi Liakhovetski if (chan) { 312a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 313a782d688SGuennadi Liakhovetski dma_release_channel(chan); 314a782d688SGuennadi Liakhovetski } 315a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 316a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 317a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 318a782d688SGuennadi Liakhovetski } 319a782d688SGuennadi Liakhovetski 320a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 32169983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 322a782d688SGuennadi Liakhovetski } 323a782d688SGuennadi Liakhovetski 324a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 325a782d688SGuennadi Liakhovetski { 32669983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 32769983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 328a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 329a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 330a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 331a782d688SGuennadi Liakhovetski int ret; 332a782d688SGuennadi Liakhovetski 33369983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3341ed828dbSLinus Walleij DMA_TO_DEVICE); 335a782d688SGuennadi Liakhovetski if (ret > 0) { 336f38f94c6SLinus Walleij host->dma_active = true; 337a782d688SGuennadi Liakhovetski desc = chan->device->device_prep_slave_sg(chan, sg, ret, 33805f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 339a782d688SGuennadi Liakhovetski } 340a782d688SGuennadi Liakhovetski 341a782d688SGuennadi Liakhovetski if (desc) { 342a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 343a782d688SGuennadi Liakhovetski desc->callback_param = host; 344a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 345a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 346a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 347a782d688SGuennadi Liakhovetski } 348a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 34969983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 350a782d688SGuennadi Liakhovetski 351a782d688SGuennadi Liakhovetski if (!desc) { 352a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 353a782d688SGuennadi Liakhovetski if (ret >= 0) 354a782d688SGuennadi Liakhovetski ret = -EIO; 355a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 356f38f94c6SLinus Walleij host->dma_active = false; 357a782d688SGuennadi Liakhovetski dma_release_channel(chan); 358a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 359a782d688SGuennadi Liakhovetski chan = host->chan_rx; 360a782d688SGuennadi Liakhovetski if (chan) { 361a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 362a782d688SGuennadi Liakhovetski dma_release_channel(chan); 363a782d688SGuennadi Liakhovetski } 364a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 365a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 366a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 367a782d688SGuennadi Liakhovetski } 368a782d688SGuennadi Liakhovetski 369a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 370a782d688SGuennadi Liakhovetski desc, cookie); 371a782d688SGuennadi Liakhovetski } 372a782d688SGuennadi Liakhovetski 373a782d688SGuennadi Liakhovetski static bool sh_mmcif_filter(struct dma_chan *chan, void *arg) 374a782d688SGuennadi Liakhovetski { 375a782d688SGuennadi Liakhovetski dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); 376a782d688SGuennadi Liakhovetski chan->private = arg; 377a782d688SGuennadi Liakhovetski return true; 378a782d688SGuennadi Liakhovetski } 379a782d688SGuennadi Liakhovetski 380a782d688SGuennadi Liakhovetski static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 381a782d688SGuennadi Liakhovetski struct sh_mmcif_plat_data *pdata) 382a782d688SGuennadi Liakhovetski { 383714c4a6eSGuennadi Liakhovetski struct sh_dmae_slave *tx, *rx; 384f38f94c6SLinus Walleij host->dma_active = false; 385a782d688SGuennadi Liakhovetski 386a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 387a782d688SGuennadi Liakhovetski if (pdata->dma) { 388714c4a6eSGuennadi Liakhovetski dev_warn(&host->pd->dev, 389714c4a6eSGuennadi Liakhovetski "Update your platform to use embedded DMA slave IDs\n"); 390714c4a6eSGuennadi Liakhovetski tx = &pdata->dma->chan_priv_tx; 391714c4a6eSGuennadi Liakhovetski rx = &pdata->dma->chan_priv_rx; 392714c4a6eSGuennadi Liakhovetski } else { 393714c4a6eSGuennadi Liakhovetski tx = &host->dma_slave_tx; 394714c4a6eSGuennadi Liakhovetski tx->slave_id = pdata->slave_id_tx; 395714c4a6eSGuennadi Liakhovetski rx = &host->dma_slave_rx; 396714c4a6eSGuennadi Liakhovetski rx->slave_id = pdata->slave_id_rx; 397714c4a6eSGuennadi Liakhovetski } 398714c4a6eSGuennadi Liakhovetski if (tx->slave_id > 0 && rx->slave_id > 0) { 399a782d688SGuennadi Liakhovetski dma_cap_mask_t mask; 400a782d688SGuennadi Liakhovetski 401a782d688SGuennadi Liakhovetski dma_cap_zero(mask); 402a782d688SGuennadi Liakhovetski dma_cap_set(DMA_SLAVE, mask); 403a782d688SGuennadi Liakhovetski 404714c4a6eSGuennadi Liakhovetski host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, tx); 405a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 406a782d688SGuennadi Liakhovetski host->chan_tx); 407a782d688SGuennadi Liakhovetski 408a782d688SGuennadi Liakhovetski if (!host->chan_tx) 409a782d688SGuennadi Liakhovetski return; 410a782d688SGuennadi Liakhovetski 411714c4a6eSGuennadi Liakhovetski host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, rx); 412a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 413a782d688SGuennadi Liakhovetski host->chan_rx); 414a782d688SGuennadi Liakhovetski 415a782d688SGuennadi Liakhovetski if (!host->chan_rx) { 416a782d688SGuennadi Liakhovetski dma_release_channel(host->chan_tx); 417a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 418a782d688SGuennadi Liakhovetski return; 419a782d688SGuennadi Liakhovetski } 420a782d688SGuennadi Liakhovetski 421a782d688SGuennadi Liakhovetski init_completion(&host->dma_complete); 422a782d688SGuennadi Liakhovetski } 423a782d688SGuennadi Liakhovetski } 424a782d688SGuennadi Liakhovetski 425a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 426a782d688SGuennadi Liakhovetski { 427a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 428a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 429a782d688SGuennadi Liakhovetski if (host->chan_tx) { 430a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 431a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 432a782d688SGuennadi Liakhovetski dma_release_channel(chan); 433a782d688SGuennadi Liakhovetski } 434a782d688SGuennadi Liakhovetski if (host->chan_rx) { 435a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 436a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 437a782d688SGuennadi Liakhovetski dma_release_channel(chan); 438a782d688SGuennadi Liakhovetski } 439a782d688SGuennadi Liakhovetski 440f38f94c6SLinus Walleij host->dma_active = false; 441a782d688SGuennadi Liakhovetski } 442fdc50a94SYusuke Goda 443fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 444fdc50a94SYusuke Goda { 445fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 446fdc50a94SYusuke Goda 447fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 448fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 449fdc50a94SYusuke Goda 450fdc50a94SYusuke Goda if (!clk) 451fdc50a94SYusuke Goda return; 452fdc50a94SYusuke Goda if (p->sup_pclk && clk == host->clk) 453fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 454fdc50a94SYusuke Goda else 455fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 45686df1745SGuennadi Liakhovetski ((fls(host->clk / clk) - 1) << 16)); 457fdc50a94SYusuke Goda 458fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 459fdc50a94SYusuke Goda } 460fdc50a94SYusuke Goda 461fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 462fdc50a94SYusuke Goda { 463fdc50a94SYusuke Goda u32 tmp; 464fdc50a94SYusuke Goda 465487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 466fdc50a94SYusuke Goda 467487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 468487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 469fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 470fdc50a94SYusuke Goda SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 471fdc50a94SYusuke Goda /* byte swap on */ 472fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 473fdc50a94SYusuke Goda } 474fdc50a94SYusuke Goda 475fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 476fdc50a94SYusuke Goda { 477fdc50a94SYusuke Goda u32 state1, state2; 478ee4b8887SGuennadi Liakhovetski int ret, timeout; 479fdc50a94SYusuke Goda 480aa0787a9SGuennadi Liakhovetski host->sd_error = false; 481fdc50a94SYusuke Goda 482487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 483487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 484e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 485e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 486fdc50a94SYusuke Goda 487fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 488fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 489fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 490ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 491487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 492fdc50a94SYusuke Goda & STS1_CMDSEQ)) 493fdc50a94SYusuke Goda break; 494fdc50a94SYusuke Goda mdelay(1); 495fdc50a94SYusuke Goda } 496ee4b8887SGuennadi Liakhovetski if (!timeout) { 497ee4b8887SGuennadi Liakhovetski dev_err(&host->pd->dev, 498ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 499ee4b8887SGuennadi Liakhovetski return -EIO; 500ee4b8887SGuennadi Liakhovetski } 501fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 502e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 503fdc50a94SYusuke Goda return -EIO; 504fdc50a94SYusuke Goda } 505fdc50a94SYusuke Goda 506fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 507ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": CRC error\n"); 508fdc50a94SYusuke Goda ret = -EIO; 509fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 510ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Timeout\n"); 511fdc50a94SYusuke Goda ret = -ETIMEDOUT; 512fdc50a94SYusuke Goda } else { 513ee4b8887SGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": End/Index error\n"); 514fdc50a94SYusuke Goda ret = -EIO; 515fdc50a94SYusuke Goda } 516fdc50a94SYusuke Goda return ret; 517fdc50a94SYusuke Goda } 518fdc50a94SYusuke Goda 519f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 520f985da17SGuennadi Liakhovetski { 521f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 522f985da17SGuennadi Liakhovetski 523f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 524f985da17SGuennadi Liakhovetski 525f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 526f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 527f985da17SGuennadi Liakhovetski 528f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 529f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 530f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 531f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 532f985da17SGuennadi Liakhovetski } else { 533f985da17SGuennadi Liakhovetski host->pio_ptr = p; 534f985da17SGuennadi Liakhovetski } 535f985da17SGuennadi Liakhovetski 536f985da17SGuennadi Liakhovetski if (host->sg_idx == data->sg_len) 537f985da17SGuennadi Liakhovetski return false; 538f985da17SGuennadi Liakhovetski 539f985da17SGuennadi Liakhovetski return true; 540f985da17SGuennadi Liakhovetski } 541f985da17SGuennadi Liakhovetski 542f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 543fdc50a94SYusuke Goda struct mmc_request *mrq) 544fdc50a94SYusuke Goda { 545f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 546f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 547f985da17SGuennadi Liakhovetski 548f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 549f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 550fdc50a94SYusuke Goda 551fdc50a94SYusuke Goda /* buf read enable */ 552fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 553f985da17SGuennadi Liakhovetski } 554fdc50a94SYusuke Goda 555f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 556f985da17SGuennadi Liakhovetski { 557f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 558f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 559f985da17SGuennadi Liakhovetski int i; 560f985da17SGuennadi Liakhovetski 561f985da17SGuennadi Liakhovetski if (host->sd_error) { 562f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 563f985da17SGuennadi Liakhovetski return false; 564f985da17SGuennadi Liakhovetski } 565f985da17SGuennadi Liakhovetski 566f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 567487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 568fdc50a94SYusuke Goda 569fdc50a94SYusuke Goda /* buffer read end */ 570fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 571f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 572fdc50a94SYusuke Goda 573f985da17SGuennadi Liakhovetski return true; 574fdc50a94SYusuke Goda } 575fdc50a94SYusuke Goda 576f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 577fdc50a94SYusuke Goda struct mmc_request *mrq) 578fdc50a94SYusuke Goda { 579fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 580fdc50a94SYusuke Goda 581f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 582f985da17SGuennadi Liakhovetski return; 583f985da17SGuennadi Liakhovetski 584f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 585f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 586f985da17SGuennadi Liakhovetski 587f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 588f985da17SGuennadi Liakhovetski host->sg_idx = 0; 589f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 590f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 591f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 592fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 593fdc50a94SYusuke Goda } 594fdc50a94SYusuke Goda 595f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 596f985da17SGuennadi Liakhovetski { 597f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 598f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 599f985da17SGuennadi Liakhovetski int i; 600f985da17SGuennadi Liakhovetski 601f985da17SGuennadi Liakhovetski if (host->sd_error) { 602f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 603f985da17SGuennadi Liakhovetski return false; 604f985da17SGuennadi Liakhovetski } 605f985da17SGuennadi Liakhovetski 606f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 607f985da17SGuennadi Liakhovetski 608f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 609f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 610f985da17SGuennadi Liakhovetski 611f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 612f985da17SGuennadi Liakhovetski return false; 613f985da17SGuennadi Liakhovetski 614f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 615f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 616f985da17SGuennadi Liakhovetski 617f985da17SGuennadi Liakhovetski return true; 618f985da17SGuennadi Liakhovetski } 619f985da17SGuennadi Liakhovetski 620f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 621fdc50a94SYusuke Goda struct mmc_request *mrq) 622fdc50a94SYusuke Goda { 623f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 624f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 625fdc50a94SYusuke Goda 626f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 627f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 628fdc50a94SYusuke Goda 629fdc50a94SYusuke Goda /* buf write enable */ 630f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 631f985da17SGuennadi Liakhovetski } 632fdc50a94SYusuke Goda 633f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 634f985da17SGuennadi Liakhovetski { 635f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 636f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 637f985da17SGuennadi Liakhovetski int i; 638f985da17SGuennadi Liakhovetski 639f985da17SGuennadi Liakhovetski if (host->sd_error) { 640f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 641f985da17SGuennadi Liakhovetski return false; 642f985da17SGuennadi Liakhovetski } 643f985da17SGuennadi Liakhovetski 644f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 645487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 646fdc50a94SYusuke Goda 647fdc50a94SYusuke Goda /* buffer write end */ 648fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 649f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 650fdc50a94SYusuke Goda 651f985da17SGuennadi Liakhovetski return true; 652fdc50a94SYusuke Goda } 653fdc50a94SYusuke Goda 654f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 655fdc50a94SYusuke Goda struct mmc_request *mrq) 656fdc50a94SYusuke Goda { 657fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 658fdc50a94SYusuke Goda 659f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 660f985da17SGuennadi Liakhovetski return; 661fdc50a94SYusuke Goda 662f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 663f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 664f985da17SGuennadi Liakhovetski 665f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 666f985da17SGuennadi Liakhovetski host->sg_idx = 0; 667f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 668f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 669f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 670fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 671fdc50a94SYusuke Goda } 672f985da17SGuennadi Liakhovetski 673f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 674f985da17SGuennadi Liakhovetski { 675f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 676f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 677f985da17SGuennadi Liakhovetski int i; 678f985da17SGuennadi Liakhovetski 679f985da17SGuennadi Liakhovetski if (host->sd_error) { 680f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 681f985da17SGuennadi Liakhovetski return false; 682fdc50a94SYusuke Goda } 683f985da17SGuennadi Liakhovetski 684f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 685f985da17SGuennadi Liakhovetski 686f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 687f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 688f985da17SGuennadi Liakhovetski 689f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 690f985da17SGuennadi Liakhovetski return false; 691f985da17SGuennadi Liakhovetski 692f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 693f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 694f985da17SGuennadi Liakhovetski 695f985da17SGuennadi Liakhovetski return true; 696fdc50a94SYusuke Goda } 697fdc50a94SYusuke Goda 698fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 699fdc50a94SYusuke Goda struct mmc_command *cmd) 700fdc50a94SYusuke Goda { 701fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 702487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 703487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 704487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 705487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 706fdc50a94SYusuke Goda } else 707487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 708fdc50a94SYusuke Goda } 709fdc50a94SYusuke Goda 710fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 711fdc50a94SYusuke Goda struct mmc_command *cmd) 712fdc50a94SYusuke Goda { 713487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 714fdc50a94SYusuke Goda } 715fdc50a94SYusuke Goda 716fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 71769983404SGuennadi Liakhovetski struct mmc_request *mrq) 718fdc50a94SYusuke Goda { 71969983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 72069983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 72169983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 722fdc50a94SYusuke Goda u32 tmp = 0; 723fdc50a94SYusuke Goda 724fdc50a94SYusuke Goda /* Response Type check */ 725fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 726fdc50a94SYusuke Goda case MMC_RSP_NONE: 727fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 728fdc50a94SYusuke Goda break; 729fdc50a94SYusuke Goda case MMC_RSP_R1: 730fdc50a94SYusuke Goda case MMC_RSP_R1B: 731fdc50a94SYusuke Goda case MMC_RSP_R3: 732fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 733fdc50a94SYusuke Goda break; 734fdc50a94SYusuke Goda case MMC_RSP_R2: 735fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 736fdc50a94SYusuke Goda break; 737fdc50a94SYusuke Goda default: 738e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 739fdc50a94SYusuke Goda break; 740fdc50a94SYusuke Goda } 741fdc50a94SYusuke Goda switch (opc) { 742fdc50a94SYusuke Goda /* RBSY */ 743fdc50a94SYusuke Goda case MMC_SWITCH: 744fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 745fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 746fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 747fdc50a94SYusuke Goda case MMC_ERASE: 748fdc50a94SYusuke Goda case MMC_GEN_CMD: 749fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 750fdc50a94SYusuke Goda break; 751fdc50a94SYusuke Goda } 752fdc50a94SYusuke Goda /* WDAT / DATW */ 75369983404SGuennadi Liakhovetski if (data) { 754fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 755fdc50a94SYusuke Goda switch (host->bus_width) { 756fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 757fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 758fdc50a94SYusuke Goda break; 759fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 760fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 761fdc50a94SYusuke Goda break; 762fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 763fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 764fdc50a94SYusuke Goda break; 765fdc50a94SYusuke Goda default: 766e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 767fdc50a94SYusuke Goda break; 768fdc50a94SYusuke Goda } 769fdc50a94SYusuke Goda } 770fdc50a94SYusuke Goda /* DWEN */ 771fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 772fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 773fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 774fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 775fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 776fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 77769983404SGuennadi Liakhovetski data->blocks << 16); 778fdc50a94SYusuke Goda } 779fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 780fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 781fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 782fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 783fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 784fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 785fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 786fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 787fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 788fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 789fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 790fdc50a94SYusuke Goda 79169983404SGuennadi Liakhovetski return (opc << 24) | tmp; 792fdc50a94SYusuke Goda } 793fdc50a94SYusuke Goda 794e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 795fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 796fdc50a94SYusuke Goda { 797fdc50a94SYusuke Goda switch (opc) { 798fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 799f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 800f985da17SGuennadi Liakhovetski return 0; 801fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 802f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 803f985da17SGuennadi Liakhovetski return 0; 804fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 805f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 806f985da17SGuennadi Liakhovetski return 0; 807fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 808fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 809f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 810f985da17SGuennadi Liakhovetski return 0; 811fdc50a94SYusuke Goda default: 812e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 813ee4b8887SGuennadi Liakhovetski return -EINVAL; 814fdc50a94SYusuke Goda } 815fdc50a94SYusuke Goda } 816fdc50a94SYusuke Goda 817fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 818ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 819fdc50a94SYusuke Goda { 820ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 821f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 822f985da17SGuennadi Liakhovetski u32 mask; 823fdc50a94SYusuke Goda 824fdc50a94SYusuke Goda switch (opc) { 825ee4b8887SGuennadi Liakhovetski /* response busy check */ 826fdc50a94SYusuke Goda case MMC_SWITCH: 827fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 828fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 829fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 830fdc50a94SYusuke Goda case MMC_ERASE: 831fdc50a94SYusuke Goda case MMC_GEN_CMD: 832ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 833fdc50a94SYusuke Goda break; 834fdc50a94SYusuke Goda default: 835ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 836fdc50a94SYusuke Goda break; 837fdc50a94SYusuke Goda } 838fdc50a94SYusuke Goda 83969983404SGuennadi Liakhovetski if (mrq->data) { 840487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 841487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 842487d9fc5SMagnus Damm mrq->data->blksz); 843fdc50a94SYusuke Goda } 84469983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 845fdc50a94SYusuke Goda 846487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 847487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 848fdc50a94SYusuke Goda /* set arg */ 849487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 850fdc50a94SYusuke Goda /* set cmd */ 851487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 852fdc50a94SYusuke Goda 853f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 854f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 855fdc50a94SYusuke Goda } 856fdc50a94SYusuke Goda 857fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 858ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 859fdc50a94SYusuke Goda { 86069983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 86169983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 862fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 86369983404SGuennadi Liakhovetski break; 86469983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 865fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 86669983404SGuennadi Liakhovetski break; 86769983404SGuennadi Liakhovetski default: 868e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 86969983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 870fdc50a94SYusuke Goda return; 871fdc50a94SYusuke Goda } 872fdc50a94SYusuke Goda 873f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 874f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 875fdc50a94SYusuke Goda } 876fdc50a94SYusuke Goda 877fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 878fdc50a94SYusuke Goda { 879fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 8803b0beafcSGuennadi Liakhovetski unsigned long flags; 8813b0beafcSGuennadi Liakhovetski 8823b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8833b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8843b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 8853b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 8863b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 8873b0beafcSGuennadi Liakhovetski return; 8883b0beafcSGuennadi Liakhovetski } 8893b0beafcSGuennadi Liakhovetski 8903b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 8913b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 892fdc50a94SYusuke Goda 893fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 894fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 895fdc50a94SYusuke Goda case SD_IO_SEND_OP_COND: 896fdc50a94SYusuke Goda case MMC_APP_CMD: 8973b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 898fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 899fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 900fdc50a94SYusuke Goda return; 901fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 902fdc50a94SYusuke Goda if (!mrq->data) { 903fdc50a94SYusuke Goda /* send_if_cond cmd (not support) */ 9043b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 905fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 906fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 907fdc50a94SYusuke Goda return; 908fdc50a94SYusuke Goda } 909fdc50a94SYusuke Goda break; 910fdc50a94SYusuke Goda default: 911fdc50a94SYusuke Goda break; 912fdc50a94SYusuke Goda } 913fdc50a94SYusuke Goda 914f985da17SGuennadi Liakhovetski host->mrq = mrq; 915f985da17SGuennadi Liakhovetski 916f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 917fdc50a94SYusuke Goda } 918fdc50a94SYusuke Goda 919fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 920fdc50a94SYusuke Goda { 921fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 922fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 9233b0beafcSGuennadi Liakhovetski unsigned long flags; 9243b0beafcSGuennadi Liakhovetski 9253b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9263b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 9273b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9283b0beafcSGuennadi Liakhovetski return; 9293b0beafcSGuennadi Liakhovetski } 9303b0beafcSGuennadi Liakhovetski 9313b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 9323b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 933fdc50a94SYusuke Goda 934f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 935c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 936faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 937faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 938c9b0cef2SGuennadi Liakhovetski host->card_present = true; 939faca6648SGuennadi Liakhovetski } 940f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 941f5e0cec4SGuennadi Liakhovetski /* clock stop */ 942f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 943faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 944c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 945c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 946c9b0cef2SGuennadi Liakhovetski host->card_present = false; 947c9b0cef2SGuennadi Liakhovetski } 948c9b0cef2SGuennadi Liakhovetski } 949faca6648SGuennadi Liakhovetski if (host->power) { 950faca6648SGuennadi Liakhovetski pm_runtime_put(&host->pd->dev); 951faca6648SGuennadi Liakhovetski host->power = false; 952f6bc41fbSGuennadi Liakhovetski if (p->down_pwr && ios->power_mode == MMC_POWER_OFF) 953f5e0cec4SGuennadi Liakhovetski p->down_pwr(host->pd); 954faca6648SGuennadi Liakhovetski } 9553b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 956f5e0cec4SGuennadi Liakhovetski return; 957fdc50a94SYusuke Goda } 958fdc50a94SYusuke Goda 959c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 960c9b0cef2SGuennadi Liakhovetski if (!host->power) { 961c9b0cef2SGuennadi Liakhovetski if (p->set_pwr) 962c9b0cef2SGuennadi Liakhovetski p->set_pwr(host->pd, ios->power_mode); 963c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 964c9b0cef2SGuennadi Liakhovetski host->power = true; 965c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 966c9b0cef2SGuennadi Liakhovetski } 967fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 968c9b0cef2SGuennadi Liakhovetski } 969fdc50a94SYusuke Goda 970fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 9713b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 972fdc50a94SYusuke Goda } 973fdc50a94SYusuke Goda 974777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 975777271d0SArnd Hannemann { 976777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 977777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 978777271d0SArnd Hannemann 979777271d0SArnd Hannemann if (!p->get_cd) 980777271d0SArnd Hannemann return -ENOSYS; 981777271d0SArnd Hannemann else 982777271d0SArnd Hannemann return p->get_cd(host->pd); 983777271d0SArnd Hannemann } 984777271d0SArnd Hannemann 985fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 986fdc50a94SYusuke Goda .request = sh_mmcif_request, 987fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 988777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 989fdc50a94SYusuke Goda }; 990fdc50a94SYusuke Goda 991f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 992f985da17SGuennadi Liakhovetski { 993f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 99469983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 995f985da17SGuennadi Liakhovetski long time; 996f985da17SGuennadi Liakhovetski 997f985da17SGuennadi Liakhovetski if (host->sd_error) { 998f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 999f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1000f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1001f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1002f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1003f985da17SGuennadi Liakhovetski host->sd_error = false; 1004f985da17SGuennadi Liakhovetski break; 1005f985da17SGuennadi Liakhovetski default: 1006f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1007f985da17SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Cmd(d'%d) error %d\n", 1008f985da17SGuennadi Liakhovetski cmd->opcode, cmd->error); 1009f985da17SGuennadi Liakhovetski break; 1010f985da17SGuennadi Liakhovetski } 1011f985da17SGuennadi Liakhovetski return false; 1012f985da17SGuennadi Liakhovetski } 1013f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1014f985da17SGuennadi Liakhovetski cmd->error = 0; 1015f985da17SGuennadi Liakhovetski return false; 1016f985da17SGuennadi Liakhovetski } 1017f985da17SGuennadi Liakhovetski 1018f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1019f985da17SGuennadi Liakhovetski 102069983404SGuennadi Liakhovetski if (!data) 1021f985da17SGuennadi Liakhovetski return false; 1022f985da17SGuennadi Liakhovetski 102369983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1024f985da17SGuennadi Liakhovetski if (host->chan_rx) 1025f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1026f985da17SGuennadi Liakhovetski } else { 1027f985da17SGuennadi Liakhovetski if (host->chan_tx) 1028f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1029f985da17SGuennadi Liakhovetski } 1030f985da17SGuennadi Liakhovetski 1031f985da17SGuennadi Liakhovetski if (!host->dma_active) { 103269983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 103369983404SGuennadi Liakhovetski if (!data->error) 1034f985da17SGuennadi Liakhovetski return true; 1035f985da17SGuennadi Liakhovetski return false; 1036f985da17SGuennadi Liakhovetski } 1037f985da17SGuennadi Liakhovetski 1038f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1039f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1040f985da17SGuennadi Liakhovetski host->timeout); 1041f985da17SGuennadi Liakhovetski if (host->sd_error) { 1042f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1043f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1044f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 104569983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) 1046f985da17SGuennadi Liakhovetski dmaengine_terminate_all(host->chan_rx); 1047f985da17SGuennadi Liakhovetski else 1048f985da17SGuennadi Liakhovetski dmaengine_terminate_all(host->chan_tx); 104969983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1050f985da17SGuennadi Liakhovetski } else if (!time) { 105169983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1052f985da17SGuennadi Liakhovetski } else if (time < 0) { 105369983404SGuennadi Liakhovetski data->error = time; 1054f985da17SGuennadi Liakhovetski } 1055f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1056f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1057f985da17SGuennadi Liakhovetski host->dma_active = false; 1058f985da17SGuennadi Liakhovetski 105969983404SGuennadi Liakhovetski if (data->error) 106069983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1061f985da17SGuennadi Liakhovetski 1062f985da17SGuennadi Liakhovetski return false; 1063f985da17SGuennadi Liakhovetski } 1064f985da17SGuennadi Liakhovetski 1065f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1066f985da17SGuennadi Liakhovetski { 1067f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 1068f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 106969983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 1070f985da17SGuennadi Liakhovetski 1071f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1072f985da17SGuennadi Liakhovetski 1073f985da17SGuennadi Liakhovetski /* 1074f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1075f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1076f985da17SGuennadi Liakhovetski */ 1077f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1078f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1079f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 1080f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1081f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1082f985da17SGuennadi Liakhovetski if (sh_mmcif_end_cmd(host)) 1083f985da17SGuennadi Liakhovetski /* Wait for data */ 1084f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1085f985da17SGuennadi Liakhovetski break; 1086f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1087f985da17SGuennadi Liakhovetski if (sh_mmcif_mread_block(host)) 1088f985da17SGuennadi Liakhovetski /* Wait for more data */ 1089f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1090f985da17SGuennadi Liakhovetski break; 1091f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1092f985da17SGuennadi Liakhovetski if (sh_mmcif_read_block(host)) 1093f985da17SGuennadi Liakhovetski /* Wait for data end */ 1094f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1095f985da17SGuennadi Liakhovetski break; 1096f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1097f985da17SGuennadi Liakhovetski if (sh_mmcif_mwrite_block(host)) 1098f985da17SGuennadi Liakhovetski /* Wait data to write */ 1099f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1100f985da17SGuennadi Liakhovetski break; 1101f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1102f985da17SGuennadi Liakhovetski if (sh_mmcif_write_block(host)) 1103f985da17SGuennadi Liakhovetski /* Wait for data end */ 1104f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1105f985da17SGuennadi Liakhovetski break; 1106f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1107f985da17SGuennadi Liakhovetski if (host->sd_error) { 1108f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1109f985da17SGuennadi Liakhovetski break; 1110f985da17SGuennadi Liakhovetski } 1111f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1112f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1113f985da17SGuennadi Liakhovetski break; 1114f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1115f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1116f985da17SGuennadi Liakhovetski if (host->sd_error) 111769983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1118f985da17SGuennadi Liakhovetski break; 1119f985da17SGuennadi Liakhovetski default: 1120f985da17SGuennadi Liakhovetski BUG(); 1121f985da17SGuennadi Liakhovetski } 1122f985da17SGuennadi Liakhovetski 1123f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 112469983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 112569983404SGuennadi Liakhovetski data->bytes_xfered = 112669983404SGuennadi Liakhovetski data->blocks * data->blksz; 1127f985da17SGuennadi Liakhovetski 112869983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1129f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 1130f985da17SGuennadi Liakhovetski if (!mrq->stop->error) 1131f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1132f985da17SGuennadi Liakhovetski } 1133f985da17SGuennadi Liakhovetski } 1134f985da17SGuennadi Liakhovetski 1135f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1136f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 113769983404SGuennadi Liakhovetski host->mrq = NULL; 1138f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1139f985da17SGuennadi Liakhovetski 1140f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1141f985da17SGuennadi Liakhovetski } 1142f985da17SGuennadi Liakhovetski 1143fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1144fdc50a94SYusuke Goda { 1145fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1146aa0787a9SGuennadi Liakhovetski u32 state; 1147fdc50a94SYusuke Goda int err = 0; 1148fdc50a94SYusuke Goda 1149487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1150fdc50a94SYusuke Goda 11518a8284a9SGuennadi Liakhovetski if (state & INT_ERR_STS) { 11528a8284a9SGuennadi Liakhovetski /* error interrupts - process first */ 11538a8284a9SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 11548a8284a9SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 11558a8284a9SGuennadi Liakhovetski err = 1; 11568a8284a9SGuennadi Liakhovetski } else if (state & INT_RBSYE) { 1157487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1158487d9fc5SMagnus Damm ~(INT_RBSYE | INT_CRSPE)); 1159fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 1160fdc50a94SYusuke Goda } else if (state & INT_CRSPE) { 1161487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 1162fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 1163fdc50a94SYusuke Goda } else if (state & INT_BUFREN) { 1164487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 1165fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 1166fdc50a94SYusuke Goda } else if (state & INT_BUFWEN) { 1167487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 1168fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 1169fdc50a94SYusuke Goda } else if (state & INT_CMD12DRE) { 1170487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1171fdc50a94SYusuke Goda ~(INT_CMD12DRE | INT_CMD12RBE | 1172fdc50a94SYusuke Goda INT_CMD12CRE | INT_BUFRE)); 1173fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 1174fdc50a94SYusuke Goda } else if (state & INT_BUFRE) { 1175487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 1176fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 1177fdc50a94SYusuke Goda } else if (state & INT_DTRANE) { 1178487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); 1179fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 1180fdc50a94SYusuke Goda } else if (state & INT_CMD12RBE) { 1181487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 1182fdc50a94SYusuke Goda ~(INT_CMD12RBE | INT_CMD12CRE)); 1183fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 1184fdc50a94SYusuke Goda } else { 1185faca6648SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 1186487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 1187fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 1188fdc50a94SYusuke Goda err = 1; 1189fdc50a94SYusuke Goda } 1190fdc50a94SYusuke Goda if (err) { 1191aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1192e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 1193fdc50a94SYusuke Goda } 1194f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 1195f985da17SGuennadi Liakhovetski if (!host->dma_active) 1196f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1197f985da17SGuennadi Liakhovetski else if (host->sd_error) 1198f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1199f985da17SGuennadi Liakhovetski } else { 1200aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 1201f985da17SGuennadi Liakhovetski } 1202fdc50a94SYusuke Goda 1203fdc50a94SYusuke Goda return IRQ_HANDLED; 1204fdc50a94SYusuke Goda } 1205fdc50a94SYusuke Goda 1206f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1207f985da17SGuennadi Liakhovetski { 1208f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1209f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1210f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 1211f985da17SGuennadi Liakhovetski 1212f985da17SGuennadi Liakhovetski if (host->dying) 1213f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1214f985da17SGuennadi Liakhovetski return; 1215f985da17SGuennadi Liakhovetski 1216f985da17SGuennadi Liakhovetski /* 1217f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1218f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1219f985da17SGuennadi Liakhovetski */ 1220f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1221f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1222f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1223f985da17SGuennadi Liakhovetski break; 1224f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1225f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1226f985da17SGuennadi Liakhovetski break; 1227f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1228f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1229f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1230f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1231f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1232f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 123369983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1234f985da17SGuennadi Liakhovetski break; 1235f985da17SGuennadi Liakhovetski default: 1236f985da17SGuennadi Liakhovetski BUG(); 1237f985da17SGuennadi Liakhovetski } 1238f985da17SGuennadi Liakhovetski 1239f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1240f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1241f985da17SGuennadi Liakhovetski host->mrq = NULL; 1242f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1243f985da17SGuennadi Liakhovetski } 1244f985da17SGuennadi Liakhovetski 1245fdc50a94SYusuke Goda static int __devinit sh_mmcif_probe(struct platform_device *pdev) 1246fdc50a94SYusuke Goda { 1247fdc50a94SYusuke Goda int ret = 0, irq[2]; 1248fdc50a94SYusuke Goda struct mmc_host *mmc; 1249e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1250e47bf32aSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd; 1251fdc50a94SYusuke Goda struct resource *res; 1252fdc50a94SYusuke Goda void __iomem *reg; 1253fdc50a94SYusuke Goda char clk_name[8]; 1254fdc50a94SYusuke Goda 1255fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1256fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1257fdc50a94SYusuke Goda if (irq[0] < 0 || irq[1] < 0) { 1258e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1259fdc50a94SYusuke Goda return -ENXIO; 1260fdc50a94SYusuke Goda } 1261fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1262fdc50a94SYusuke Goda if (!res) { 1263fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1264fdc50a94SYusuke Goda return -ENXIO; 1265fdc50a94SYusuke Goda } 1266fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1267fdc50a94SYusuke Goda if (!reg) { 1268fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1269fdc50a94SYusuke Goda return -ENOMEM; 1270fdc50a94SYusuke Goda } 1271e47bf32aSGuennadi Liakhovetski pd = pdev->dev.platform_data; 1272fdc50a94SYusuke Goda if (!pd) { 1273fdc50a94SYusuke Goda dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); 1274fdc50a94SYusuke Goda ret = -ENXIO; 1275fdc50a94SYusuke Goda goto clean_up; 1276fdc50a94SYusuke Goda } 1277fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1278fdc50a94SYusuke Goda if (!mmc) { 1279fdc50a94SYusuke Goda ret = -ENOMEM; 1280fdc50a94SYusuke Goda goto clean_up; 1281fdc50a94SYusuke Goda } 1282fdc50a94SYusuke Goda host = mmc_priv(mmc); 1283fdc50a94SYusuke Goda host->mmc = mmc; 1284fdc50a94SYusuke Goda host->addr = reg; 1285fdc50a94SYusuke Goda host->timeout = 1000; 1286fdc50a94SYusuke Goda 1287fdc50a94SYusuke Goda snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 1288fdc50a94SYusuke Goda host->hclk = clk_get(&pdev->dev, clk_name); 1289fdc50a94SYusuke Goda if (IS_ERR(host->hclk)) { 1290fdc50a94SYusuke Goda dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 1291fdc50a94SYusuke Goda ret = PTR_ERR(host->hclk); 1292fdc50a94SYusuke Goda goto clean_up1; 1293fdc50a94SYusuke Goda } 1294fdc50a94SYusuke Goda clk_enable(host->hclk); 1295fdc50a94SYusuke Goda host->clk = clk_get_rate(host->hclk); 1296fdc50a94SYusuke Goda host->pd = pdev; 1297fdc50a94SYusuke Goda 12983b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1299fdc50a94SYusuke Goda 1300fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 1301fdc50a94SYusuke Goda mmc->f_max = host->clk; 1302fdc50a94SYusuke Goda /* close to 400KHz */ 1303fdc50a94SYusuke Goda if (mmc->f_max < 51200000) 1304fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 128; 1305fdc50a94SYusuke Goda else if (mmc->f_max < 102400000) 1306fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 256; 1307fdc50a94SYusuke Goda else 1308fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 512; 1309fdc50a94SYusuke Goda if (pd->ocr) 1310fdc50a94SYusuke Goda mmc->ocr_avail = pd->ocr; 1311fdc50a94SYusuke Goda mmc->caps = MMC_CAP_MMC_HIGHSPEED; 1312fdc50a94SYusuke Goda if (pd->caps) 1313fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1314a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1315fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1316a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1317a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1318fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1319fdc50a94SYusuke Goda 1320fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 1321fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1322a782d688SGuennadi Liakhovetski 1323faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1324faca6648SGuennadi Liakhovetski host->power = false; 1325faca6648SGuennadi Liakhovetski 1326faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1327faca6648SGuennadi Liakhovetski if (ret < 0) 1328faca6648SGuennadi Liakhovetski goto clean_up2; 1329a782d688SGuennadi Liakhovetski 13305ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1331fdc50a94SYusuke Goda 13323b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 13333b0beafcSGuennadi Liakhovetski 1334f985da17SGuennadi Liakhovetski ret = request_threaded_irq(irq[0], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:error", host); 1335fdc50a94SYusuke Goda if (ret) { 1336e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); 1337faca6648SGuennadi Liakhovetski goto clean_up3; 1338fdc50a94SYusuke Goda } 1339f985da17SGuennadi Liakhovetski ret = request_threaded_irq(irq[1], sh_mmcif_intr, sh_mmcif_irqt, 0, "sh_mmc:int", host); 1340fdc50a94SYusuke Goda if (ret) { 1341e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 13425ba85d95SGuennadi Liakhovetski goto clean_up4; 1343fdc50a94SYusuke Goda } 1344fdc50a94SYusuke Goda 13455ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 13465ba85d95SGuennadi Liakhovetski if (ret < 0) 13475ba85d95SGuennadi Liakhovetski goto clean_up5; 1348fdc50a94SYusuke Goda 1349e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1350e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1351487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1352fdc50a94SYusuke Goda return ret; 1353fdc50a94SYusuke Goda 13545ba85d95SGuennadi Liakhovetski clean_up5: 13555ba85d95SGuennadi Liakhovetski free_irq(irq[1], host); 13565ba85d95SGuennadi Liakhovetski clean_up4: 13575ba85d95SGuennadi Liakhovetski free_irq(irq[0], host); 1358faca6648SGuennadi Liakhovetski clean_up3: 1359faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1360fdc50a94SYusuke Goda clean_up2: 1361faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1362fdc50a94SYusuke Goda clk_disable(host->hclk); 1363fdc50a94SYusuke Goda clean_up1: 1364fdc50a94SYusuke Goda mmc_free_host(mmc); 1365fdc50a94SYusuke Goda clean_up: 1366fdc50a94SYusuke Goda if (reg) 1367fdc50a94SYusuke Goda iounmap(reg); 1368fdc50a94SYusuke Goda return ret; 1369fdc50a94SYusuke Goda } 1370fdc50a94SYusuke Goda 1371fdc50a94SYusuke Goda static int __devexit sh_mmcif_remove(struct platform_device *pdev) 1372fdc50a94SYusuke Goda { 1373fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1374fdc50a94SYusuke Goda int irq[2]; 1375fdc50a94SYusuke Goda 1376f985da17SGuennadi Liakhovetski host->dying = true; 1377faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1378aa0787a9SGuennadi Liakhovetski 1379faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 13803b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 13813b0beafcSGuennadi Liakhovetski 1382f985da17SGuennadi Liakhovetski /* 1383f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1384f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1385f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1386f985da17SGuennadi Liakhovetski */ 1387f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1388f985da17SGuennadi Liakhovetski 1389aa0787a9SGuennadi Liakhovetski if (host->addr) 1390aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1391aa0787a9SGuennadi Liakhovetski 1392fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1393fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1394fdc50a94SYusuke Goda 1395fdc50a94SYusuke Goda free_irq(irq[0], host); 1396fdc50a94SYusuke Goda free_irq(irq[1], host); 1397fdc50a94SYusuke Goda 1398aa0787a9SGuennadi Liakhovetski platform_set_drvdata(pdev, NULL); 1399aa0787a9SGuennadi Liakhovetski 1400fdc50a94SYusuke Goda clk_disable(host->hclk); 1401fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1402faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1403faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1404fdc50a94SYusuke Goda 1405fdc50a94SYusuke Goda return 0; 1406fdc50a94SYusuke Goda } 1407fdc50a94SYusuke Goda 1408faca6648SGuennadi Liakhovetski #ifdef CONFIG_PM 1409faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1410faca6648SGuennadi Liakhovetski { 1411faca6648SGuennadi Liakhovetski struct platform_device *pdev = to_platform_device(dev); 1412faca6648SGuennadi Liakhovetski struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1413faca6648SGuennadi Liakhovetski int ret = mmc_suspend_host(host->mmc); 1414faca6648SGuennadi Liakhovetski 1415faca6648SGuennadi Liakhovetski if (!ret) { 1416faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1417faca6648SGuennadi Liakhovetski clk_disable(host->hclk); 1418faca6648SGuennadi Liakhovetski } 1419faca6648SGuennadi Liakhovetski 1420faca6648SGuennadi Liakhovetski return ret; 1421faca6648SGuennadi Liakhovetski } 1422faca6648SGuennadi Liakhovetski 1423faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1424faca6648SGuennadi Liakhovetski { 1425faca6648SGuennadi Liakhovetski struct platform_device *pdev = to_platform_device(dev); 1426faca6648SGuennadi Liakhovetski struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1427faca6648SGuennadi Liakhovetski 1428faca6648SGuennadi Liakhovetski clk_enable(host->hclk); 1429faca6648SGuennadi Liakhovetski 1430faca6648SGuennadi Liakhovetski return mmc_resume_host(host->mmc); 1431faca6648SGuennadi Liakhovetski } 1432faca6648SGuennadi Liakhovetski #else 1433faca6648SGuennadi Liakhovetski #define sh_mmcif_suspend NULL 1434faca6648SGuennadi Liakhovetski #define sh_mmcif_resume NULL 1435faca6648SGuennadi Liakhovetski #endif /* CONFIG_PM */ 1436faca6648SGuennadi Liakhovetski 1437faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1438faca6648SGuennadi Liakhovetski .suspend = sh_mmcif_suspend, 1439faca6648SGuennadi Liakhovetski .resume = sh_mmcif_resume, 1440faca6648SGuennadi Liakhovetski }; 1441faca6648SGuennadi Liakhovetski 1442fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1443fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1444fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1445fdc50a94SYusuke Goda .driver = { 1446fdc50a94SYusuke Goda .name = DRIVER_NAME, 1447faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1448fdc50a94SYusuke Goda }, 1449fdc50a94SYusuke Goda }; 1450fdc50a94SYusuke Goda 1451d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1452fdc50a94SYusuke Goda 1453fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1454fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1455aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1456fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1457