1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 598047310eSGuennadi Liakhovetski #include <linux/mutex.h> 6089d49a70SKuninori Morimoto #include <linux/of_device.h> 61a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 62e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 63efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 64faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 65d00cadacSGuennadi Liakhovetski #include <linux/sh_dma.h> 663b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6788b47679SPaul Gortmaker #include <linux/module.h> 68fdc50a94SYusuke Goda 69fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 70fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 71fdc50a94SYusuke Goda 72fdc50a94SYusuke Goda /* CE_CMD_SET */ 73fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 74fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 75fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 76fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 77fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 78fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 79fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 80fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 81fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 82fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 83fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 84fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 85fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 86fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 88fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 89fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 90fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 91fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 92fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 93fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 94555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 95fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 96fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 97fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 98fdc50a94SYusuke Goda 99fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 100fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 101fdc50a94SYusuke Goda 102fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 103fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 104fdc50a94SYusuke Goda 105fdc50a94SYusuke Goda /* CE_INT */ 106fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 107fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 108fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 109fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 110fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 111fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 112fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 113fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 114fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 115fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 116fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 117fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 118fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 119fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 120fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 121fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 122fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 123fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 124fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 125fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 126fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 127fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 128fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 129fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 130fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 131fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 132fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 133fdc50a94SYusuke Goda 1348af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 1358af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 1368af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 1378af50750SGuennadi Liakhovetski 138967bcb77SGuennadi Liakhovetski #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 139967bcb77SGuennadi Liakhovetski 140fdc50a94SYusuke Goda /* CE_INT_MASK */ 141fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 142fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 143fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 144fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 145fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 146fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 147fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 148fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 149fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 150fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 151fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 152fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 153fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 154fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 155fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 156fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 157fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 158fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 159fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 160fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 161fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 162fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 163fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 164fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 165fdc50a94SYusuke Goda 166ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 167ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 168967bcb77SGuennadi Liakhovetski MASK_MCRCSTO | MASK_MWDATTO | \ 169ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 170ee4b8887SGuennadi Liakhovetski 1718af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 1728af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \ 1738af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 1748af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE) 1758af50750SGuennadi Liakhovetski 176fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 177fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 178fdc50a94SYusuke Goda 179fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 180fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 181fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 182fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 183fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 184fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 185fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 186fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 187fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 188fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 189fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 190fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 191fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 192fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 193fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 194fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 195fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 196fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 197fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 198fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 199fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 200fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 201fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 202fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 203fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 204fdc50a94SYusuke Goda 205fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 206fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 207fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 208fdc50a94SYusuke Goda 2091b1a694dSKuninori Morimoto enum sh_mmcif_state { 2103b0beafcSGuennadi Liakhovetski STATE_IDLE, 2113b0beafcSGuennadi Liakhovetski STATE_REQUEST, 2123b0beafcSGuennadi Liakhovetski STATE_IOS, 2138047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2143b0beafcSGuennadi Liakhovetski }; 2153b0beafcSGuennadi Liakhovetski 2161b1a694dSKuninori Morimoto enum sh_mmcif_wait_for { 217f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 218f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 219f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 220f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 221f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 222f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 223f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 224f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 225f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 226f985da17SGuennadi Liakhovetski }; 227f985da17SGuennadi Liakhovetski 22889d49a70SKuninori Morimoto /* 22989d49a70SKuninori Morimoto * difference for each SoC 23089d49a70SKuninori Morimoto */ 231fdc50a94SYusuke Goda struct sh_mmcif_host { 232fdc50a94SYusuke Goda struct mmc_host *mmc; 233f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 234fdc50a94SYusuke Goda struct platform_device *pd; 2356aed678bSKuninori Morimoto struct clk *clk; 236fdc50a94SYusuke Goda int bus_width; 237555061f9STeppei Kamijou unsigned char timing; 238aa0787a9SGuennadi Liakhovetski bool sd_error; 239f985da17SGuennadi Liakhovetski bool dying; 240fdc50a94SYusuke Goda long timeout; 241fdc50a94SYusuke Goda void __iomem *addr; 242f985da17SGuennadi Liakhovetski u32 *pio_ptr; 243ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2441b1a694dSKuninori Morimoto enum sh_mmcif_state state; 2451b1a694dSKuninori Morimoto enum sh_mmcif_wait_for wait_for; 246f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 247f985da17SGuennadi Liakhovetski size_t blocksize; 248f985da17SGuennadi Liakhovetski int sg_idx; 249f985da17SGuennadi Liakhovetski int sg_blkidx; 250faca6648SGuennadi Liakhovetski bool power; 251967bcb77SGuennadi Liakhovetski bool ccs_enable; /* Command Completion Signal support */ 2526d6fd367SGuennadi Liakhovetski bool clk_ctrl2_enable; 2538047310eSGuennadi Liakhovetski struct mutex thread_lock; 25489d49a70SKuninori Morimoto u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ 255fdc50a94SYusuke Goda 256a782d688SGuennadi Liakhovetski /* DMA support */ 257a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 258a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 259a782d688SGuennadi Liakhovetski struct completion dma_complete; 260f38f94c6SLinus Walleij bool dma_active; 261a782d688SGuennadi Liakhovetski }; 262fdc50a94SYusuke Goda 2631b1a694dSKuninori Morimoto static const struct of_device_id sh_mmcif_of_match[] = { 26470830b41SKuninori Morimoto { .compatible = "renesas,sh-mmcif" }, 26570830b41SKuninori Morimoto { } 26670830b41SKuninori Morimoto }; 2671b1a694dSKuninori Morimoto MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); 26870830b41SKuninori Morimoto 269585c3a5aSKuninori Morimoto #define sh_mmcif_host_to_dev(host) (&host->pd->dev) 270585c3a5aSKuninori Morimoto 271fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 272fdc50a94SYusuke Goda unsigned int reg, u32 val) 273fdc50a94SYusuke Goda { 274487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 275fdc50a94SYusuke Goda } 276fdc50a94SYusuke Goda 277fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 278fdc50a94SYusuke Goda unsigned int reg, u32 val) 279fdc50a94SYusuke Goda { 280487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 281fdc50a94SYusuke Goda } 282fdc50a94SYusuke Goda 2831b1a694dSKuninori Morimoto static void sh_mmcif_dma_complete(void *arg) 284a782d688SGuennadi Liakhovetski { 285a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2868047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 287585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 28869983404SGuennadi Liakhovetski 289585c3a5aSKuninori Morimoto dev_dbg(dev, "Command completed\n"); 290a782d688SGuennadi Liakhovetski 2918047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 292585c3a5aSKuninori Morimoto dev_name(dev))) 293a782d688SGuennadi Liakhovetski return; 294a782d688SGuennadi Liakhovetski 295a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 296a782d688SGuennadi Liakhovetski } 297a782d688SGuennadi Liakhovetski 298a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 299a782d688SGuennadi Liakhovetski { 30069983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 30169983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 302a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 303a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 304585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 305a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 306a782d688SGuennadi Liakhovetski int ret; 307a782d688SGuennadi Liakhovetski 30869983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3091ed828dbSLinus Walleij DMA_FROM_DEVICE); 310a782d688SGuennadi Liakhovetski if (ret > 0) { 311f38f94c6SLinus Walleij host->dma_active = true; 31216052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 31305f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 314a782d688SGuennadi Liakhovetski } 315a782d688SGuennadi Liakhovetski 316a782d688SGuennadi Liakhovetski if (desc) { 3171b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete; 318a782d688SGuennadi Liakhovetski desc->callback_param = host; 319a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 320a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 321a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 322a782d688SGuennadi Liakhovetski } 323585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 32469983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 325a782d688SGuennadi Liakhovetski 326a782d688SGuennadi Liakhovetski if (!desc) { 327a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 328a782d688SGuennadi Liakhovetski if (ret >= 0) 329a782d688SGuennadi Liakhovetski ret = -EIO; 330a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 331f38f94c6SLinus Walleij host->dma_active = false; 332a782d688SGuennadi Liakhovetski dma_release_channel(chan); 333a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 334a782d688SGuennadi Liakhovetski chan = host->chan_tx; 335a782d688SGuennadi Liakhovetski if (chan) { 336a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 337a782d688SGuennadi Liakhovetski dma_release_channel(chan); 338a782d688SGuennadi Liakhovetski } 339585c3a5aSKuninori Morimoto dev_warn(dev, 340a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 341a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 342a782d688SGuennadi Liakhovetski } 343a782d688SGuennadi Liakhovetski 344585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 34569983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 346a782d688SGuennadi Liakhovetski } 347a782d688SGuennadi Liakhovetski 348a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 349a782d688SGuennadi Liakhovetski { 35069983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 35169983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 352a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 353a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 354585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 355a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 356a782d688SGuennadi Liakhovetski int ret; 357a782d688SGuennadi Liakhovetski 35869983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3591ed828dbSLinus Walleij DMA_TO_DEVICE); 360a782d688SGuennadi Liakhovetski if (ret > 0) { 361f38f94c6SLinus Walleij host->dma_active = true; 36216052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 36305f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 364a782d688SGuennadi Liakhovetski } 365a782d688SGuennadi Liakhovetski 366a782d688SGuennadi Liakhovetski if (desc) { 3671b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete; 368a782d688SGuennadi Liakhovetski desc->callback_param = host; 369a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 370a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 371a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 372a782d688SGuennadi Liakhovetski } 373585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 37469983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 375a782d688SGuennadi Liakhovetski 376a782d688SGuennadi Liakhovetski if (!desc) { 377a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 378a782d688SGuennadi Liakhovetski if (ret >= 0) 379a782d688SGuennadi Liakhovetski ret = -EIO; 380a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 381f38f94c6SLinus Walleij host->dma_active = false; 382a782d688SGuennadi Liakhovetski dma_release_channel(chan); 383a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 384a782d688SGuennadi Liakhovetski chan = host->chan_rx; 385a782d688SGuennadi Liakhovetski if (chan) { 386a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 387a782d688SGuennadi Liakhovetski dma_release_channel(chan); 388a782d688SGuennadi Liakhovetski } 389585c3a5aSKuninori Morimoto dev_warn(dev, 390a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 391a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 392a782d688SGuennadi Liakhovetski } 393a782d688SGuennadi Liakhovetski 394585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, 395a782d688SGuennadi Liakhovetski desc, cookie); 396a782d688SGuennadi Liakhovetski } 397a782d688SGuennadi Liakhovetski 398e5a233cbSLaurent Pinchart static struct dma_chan * 39927cbd7e8SArnd Bergmann sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) 400a782d688SGuennadi Liakhovetski { 4010e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 4020e79f9aeSGuennadi Liakhovetski 403e5a233cbSLaurent Pinchart dma_cap_zero(mask); 404e5a233cbSLaurent Pinchart dma_cap_set(DMA_SLAVE, mask); 40527cbd7e8SArnd Bergmann if (slave_id <= 0) 406e5a233cbSLaurent Pinchart return NULL; 407e5a233cbSLaurent Pinchart 40827cbd7e8SArnd Bergmann return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id); 40927cbd7e8SArnd Bergmann } 410e5a233cbSLaurent Pinchart 41127cbd7e8SArnd Bergmann static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, 41227cbd7e8SArnd Bergmann struct dma_chan *chan, 41327cbd7e8SArnd Bergmann enum dma_transfer_direction direction) 41427cbd7e8SArnd Bergmann { 41527cbd7e8SArnd Bergmann struct resource *res; 41627cbd7e8SArnd Bergmann struct dma_slave_config cfg = { 0, }; 41727cbd7e8SArnd Bergmann 41827cbd7e8SArnd Bergmann res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 419e5a233cbSLaurent Pinchart cfg.direction = direction; 420d25006e7SLaurent Pinchart 421e36152aaSLaurent Pinchart if (direction == DMA_DEV_TO_MEM) { 422d25006e7SLaurent Pinchart cfg.src_addr = res->start + MMCIF_CE_DATA; 423e36152aaSLaurent Pinchart cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 424e36152aaSLaurent Pinchart } else { 425e5a233cbSLaurent Pinchart cfg.dst_addr = res->start + MMCIF_CE_DATA; 426e36152aaSLaurent Pinchart cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 427e36152aaSLaurent Pinchart } 428d25006e7SLaurent Pinchart 42927cbd7e8SArnd Bergmann return dmaengine_slave_config(chan, &cfg); 430e5a233cbSLaurent Pinchart } 431e5a233cbSLaurent Pinchart 43227cbd7e8SArnd Bergmann static void sh_mmcif_request_dma(struct sh_mmcif_host *host) 433e5a233cbSLaurent Pinchart { 434585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 435f38f94c6SLinus Walleij host->dma_active = false; 436a782d688SGuennadi Liakhovetski 437a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 43827cbd7e8SArnd Bergmann if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) { 43927cbd7e8SArnd Bergmann struct sh_mmcif_plat_data *pdata = dev->platform_data; 44027cbd7e8SArnd Bergmann 44127cbd7e8SArnd Bergmann host->chan_tx = sh_mmcif_request_dma_pdata(host, 44227cbd7e8SArnd Bergmann pdata->slave_id_tx); 44327cbd7e8SArnd Bergmann host->chan_rx = sh_mmcif_request_dma_pdata(host, 44427cbd7e8SArnd Bergmann pdata->slave_id_rx); 44527cbd7e8SArnd Bergmann } else { 44627cbd7e8SArnd Bergmann host->chan_tx = dma_request_slave_channel(dev, "tx"); 447a32ef81cSChris Paterson host->chan_rx = dma_request_slave_channel(dev, "rx"); 44827cbd7e8SArnd Bergmann } 44927cbd7e8SArnd Bergmann dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, 45027cbd7e8SArnd Bergmann host->chan_rx); 45127cbd7e8SArnd Bergmann 45227cbd7e8SArnd Bergmann if (!host->chan_tx || !host->chan_rx || 45327cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || 45427cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) 45527cbd7e8SArnd Bergmann goto error; 45627cbd7e8SArnd Bergmann 457a782d688SGuennadi Liakhovetski return; 458a782d688SGuennadi Liakhovetski 45927cbd7e8SArnd Bergmann error: 46027cbd7e8SArnd Bergmann if (host->chan_tx) 4610e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 46227cbd7e8SArnd Bergmann if (host->chan_rx) 46327cbd7e8SArnd Bergmann dma_release_channel(host->chan_rx); 46427cbd7e8SArnd Bergmann host->chan_tx = host->chan_rx = NULL; 465e5a233cbSLaurent Pinchart } 466a782d688SGuennadi Liakhovetski 467a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 468a782d688SGuennadi Liakhovetski { 469a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 470a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 471a782d688SGuennadi Liakhovetski if (host->chan_tx) { 472a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 473a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 474a782d688SGuennadi Liakhovetski dma_release_channel(chan); 475a782d688SGuennadi Liakhovetski } 476a782d688SGuennadi Liakhovetski if (host->chan_rx) { 477a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 478a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 479a782d688SGuennadi Liakhovetski dma_release_channel(chan); 480a782d688SGuennadi Liakhovetski } 481a782d688SGuennadi Liakhovetski 482f38f94c6SLinus Walleij host->dma_active = false; 483a782d688SGuennadi Liakhovetski } 484fdc50a94SYusuke Goda 485fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 486fdc50a94SYusuke Goda { 487585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 488585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *p = dev->platform_data; 489bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 4906aed678bSKuninori Morimoto unsigned int current_clk = clk_get_rate(host->clk); 49189d49a70SKuninori Morimoto unsigned int clkdiv; 492fdc50a94SYusuke Goda 493fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 494fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 495fdc50a94SYusuke Goda 496fdc50a94SYusuke Goda if (!clk) 497fdc50a94SYusuke Goda return; 498fdc50a94SYusuke Goda 49989d49a70SKuninori Morimoto if (host->clkdiv_map) { 50089d49a70SKuninori Morimoto unsigned int freq, best_freq, myclk, div, diff_min, diff; 50189d49a70SKuninori Morimoto int i; 50289d49a70SKuninori Morimoto 50389d49a70SKuninori Morimoto clkdiv = 0; 50489d49a70SKuninori Morimoto diff_min = ~0; 50589d49a70SKuninori Morimoto best_freq = 0; 50689d49a70SKuninori Morimoto for (i = 31; i >= 0; i--) { 50789d49a70SKuninori Morimoto if (!((1 << i) & host->clkdiv_map)) 50889d49a70SKuninori Morimoto continue; 50989d49a70SKuninori Morimoto 51089d49a70SKuninori Morimoto /* 51189d49a70SKuninori Morimoto * clk = parent_freq / div 51289d49a70SKuninori Morimoto * -> parent_freq = clk x div 51389d49a70SKuninori Morimoto */ 51489d49a70SKuninori Morimoto 51589d49a70SKuninori Morimoto div = 1 << (i + 1); 51689d49a70SKuninori Morimoto freq = clk_round_rate(host->clk, clk * div); 51789d49a70SKuninori Morimoto myclk = freq / div; 51889d49a70SKuninori Morimoto diff = (myclk > clk) ? myclk - clk : clk - myclk; 51989d49a70SKuninori Morimoto 52089d49a70SKuninori Morimoto if (diff <= diff_min) { 52189d49a70SKuninori Morimoto best_freq = freq; 52289d49a70SKuninori Morimoto clkdiv = i; 52389d49a70SKuninori Morimoto diff_min = diff; 52489d49a70SKuninori Morimoto } 52589d49a70SKuninori Morimoto } 52689d49a70SKuninori Morimoto 52789d49a70SKuninori Morimoto dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", 52889d49a70SKuninori Morimoto (best_freq / (1 << (clkdiv + 1))), clk, 52989d49a70SKuninori Morimoto best_freq, clkdiv); 53089d49a70SKuninori Morimoto 53189d49a70SKuninori Morimoto clk_set_rate(host->clk, best_freq); 53289d49a70SKuninori Morimoto clkdiv = clkdiv << 16; 53389d49a70SKuninori Morimoto } else if (sup_pclk && clk == current_clk) { 53489d49a70SKuninori Morimoto clkdiv = CLK_SUP_PCLK; 53589d49a70SKuninori Morimoto } else { 53689d49a70SKuninori Morimoto clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; 53789d49a70SKuninori Morimoto } 53889d49a70SKuninori Morimoto 53989d49a70SKuninori Morimoto sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); 540fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 541fdc50a94SYusuke Goda } 542fdc50a94SYusuke Goda 543fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 544fdc50a94SYusuke Goda { 545fdc50a94SYusuke Goda u32 tmp; 546fdc50a94SYusuke Goda 547487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 548fdc50a94SYusuke Goda 549487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 550487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 551967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 552967bcb77SGuennadi Liakhovetski tmp |= SCCSTO_29; 5536d6fd367SGuennadi Liakhovetski if (host->clk_ctrl2_enable) 5546d6fd367SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 555fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 556967bcb77SGuennadi Liakhovetski SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 557fdc50a94SYusuke Goda /* byte swap on */ 558fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 559fdc50a94SYusuke Goda } 560fdc50a94SYusuke Goda 561fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 562fdc50a94SYusuke Goda { 563585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 564fdc50a94SYusuke Goda u32 state1, state2; 565ee4b8887SGuennadi Liakhovetski int ret, timeout; 566fdc50a94SYusuke Goda 567aa0787a9SGuennadi Liakhovetski host->sd_error = false; 568fdc50a94SYusuke Goda 569487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 570487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 571585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); 572585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); 573fdc50a94SYusuke Goda 574fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 575fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 576fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 57752e00b84SUlf Hansson for (timeout = 10000; timeout; timeout--) { 578487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 579fdc50a94SYusuke Goda & STS1_CMDSEQ)) 580fdc50a94SYusuke Goda break; 581fdc50a94SYusuke Goda mdelay(1); 582fdc50a94SYusuke Goda } 583ee4b8887SGuennadi Liakhovetski if (!timeout) { 584585c3a5aSKuninori Morimoto dev_err(dev, 585ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 586ee4b8887SGuennadi Liakhovetski return -EIO; 587ee4b8887SGuennadi Liakhovetski } 588fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 589585c3a5aSKuninori Morimoto dev_dbg(dev, "Forced end of command sequence\n"); 590fdc50a94SYusuke Goda return -EIO; 591fdc50a94SYusuke Goda } 592fdc50a94SYusuke Goda 593fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 594585c3a5aSKuninori Morimoto dev_err(dev, " CRC error: state %u, wait %u\n", 595e475b270STeppei Kamijou host->state, host->wait_for); 596fdc50a94SYusuke Goda ret = -EIO; 597fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 598585c3a5aSKuninori Morimoto dev_err(dev, " Timeout: state %u, wait %u\n", 599e475b270STeppei Kamijou host->state, host->wait_for); 600fdc50a94SYusuke Goda ret = -ETIMEDOUT; 601fdc50a94SYusuke Goda } else { 602585c3a5aSKuninori Morimoto dev_dbg(dev, " End/Index error: state %u, wait %u\n", 603e475b270STeppei Kamijou host->state, host->wait_for); 604fdc50a94SYusuke Goda ret = -EIO; 605fdc50a94SYusuke Goda } 606fdc50a94SYusuke Goda return ret; 607fdc50a94SYusuke Goda } 608fdc50a94SYusuke Goda 609f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 610f985da17SGuennadi Liakhovetski { 611f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 612f985da17SGuennadi Liakhovetski 613f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 614f985da17SGuennadi Liakhovetski 615f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 616f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 617f985da17SGuennadi Liakhovetski 618f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 619f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 620f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 621f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 622f985da17SGuennadi Liakhovetski } else { 623f985da17SGuennadi Liakhovetski host->pio_ptr = p; 624f985da17SGuennadi Liakhovetski } 625f985da17SGuennadi Liakhovetski 62699eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 627f985da17SGuennadi Liakhovetski } 628f985da17SGuennadi Liakhovetski 629f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 630fdc50a94SYusuke Goda struct mmc_request *mrq) 631fdc50a94SYusuke Goda { 632f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 633f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 634f985da17SGuennadi Liakhovetski 635f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 636fdc50a94SYusuke Goda 637fdc50a94SYusuke Goda /* buf read enable */ 638fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 639f985da17SGuennadi Liakhovetski } 640fdc50a94SYusuke Goda 641f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 642f985da17SGuennadi Liakhovetski { 643585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 644f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 645f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 646f985da17SGuennadi Liakhovetski int i; 647f985da17SGuennadi Liakhovetski 648f985da17SGuennadi Liakhovetski if (host->sd_error) { 649f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 650585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 651f985da17SGuennadi Liakhovetski return false; 652f985da17SGuennadi Liakhovetski } 653f985da17SGuennadi Liakhovetski 654f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 655487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 656fdc50a94SYusuke Goda 657fdc50a94SYusuke Goda /* buffer read end */ 658fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 659f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 660fdc50a94SYusuke Goda 661f985da17SGuennadi Liakhovetski return true; 662fdc50a94SYusuke Goda } 663fdc50a94SYusuke Goda 664f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 665fdc50a94SYusuke Goda struct mmc_request *mrq) 666fdc50a94SYusuke Goda { 667fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 668fdc50a94SYusuke Goda 669f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 670f985da17SGuennadi Liakhovetski return; 671f985da17SGuennadi Liakhovetski 672f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 673f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 674f985da17SGuennadi Liakhovetski 675f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 676f985da17SGuennadi Liakhovetski host->sg_idx = 0; 677f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 678f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6795df460b1SGuennadi Liakhovetski 680fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 681fdc50a94SYusuke Goda } 682fdc50a94SYusuke Goda 683f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 684f985da17SGuennadi Liakhovetski { 685585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 686f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 687f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 688f985da17SGuennadi Liakhovetski int i; 689f985da17SGuennadi Liakhovetski 690f985da17SGuennadi Liakhovetski if (host->sd_error) { 691f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 692585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 693f985da17SGuennadi Liakhovetski return false; 694f985da17SGuennadi Liakhovetski } 695f985da17SGuennadi Liakhovetski 696f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 697f985da17SGuennadi Liakhovetski 698f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 699f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 700f985da17SGuennadi Liakhovetski 701f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 702f985da17SGuennadi Liakhovetski return false; 703f985da17SGuennadi Liakhovetski 704f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 705f985da17SGuennadi Liakhovetski 706f985da17SGuennadi Liakhovetski return true; 707f985da17SGuennadi Liakhovetski } 708f985da17SGuennadi Liakhovetski 709f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 710fdc50a94SYusuke Goda struct mmc_request *mrq) 711fdc50a94SYusuke Goda { 712f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 713f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 714fdc50a94SYusuke Goda 715f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 716fdc50a94SYusuke Goda 717fdc50a94SYusuke Goda /* buf write enable */ 718f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 719f985da17SGuennadi Liakhovetski } 720fdc50a94SYusuke Goda 721f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 722f985da17SGuennadi Liakhovetski { 723585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 724f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 725f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 726f985da17SGuennadi Liakhovetski int i; 727f985da17SGuennadi Liakhovetski 728f985da17SGuennadi Liakhovetski if (host->sd_error) { 729f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 730585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 731f985da17SGuennadi Liakhovetski return false; 732f985da17SGuennadi Liakhovetski } 733f985da17SGuennadi Liakhovetski 734f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 735487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 736fdc50a94SYusuke Goda 737fdc50a94SYusuke Goda /* buffer write end */ 738fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 739f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 740fdc50a94SYusuke Goda 741f985da17SGuennadi Liakhovetski return true; 742fdc50a94SYusuke Goda } 743fdc50a94SYusuke Goda 744f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 745fdc50a94SYusuke Goda struct mmc_request *mrq) 746fdc50a94SYusuke Goda { 747fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 748fdc50a94SYusuke Goda 749f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 750f985da17SGuennadi Liakhovetski return; 751fdc50a94SYusuke Goda 752f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 753f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 754f985da17SGuennadi Liakhovetski 755f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 756f985da17SGuennadi Liakhovetski host->sg_idx = 0; 757f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 758f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 7595df460b1SGuennadi Liakhovetski 760fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 761fdc50a94SYusuke Goda } 762f985da17SGuennadi Liakhovetski 763f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 764f985da17SGuennadi Liakhovetski { 765585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 766f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 767f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 768f985da17SGuennadi Liakhovetski int i; 769f985da17SGuennadi Liakhovetski 770f985da17SGuennadi Liakhovetski if (host->sd_error) { 771f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 772585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 773f985da17SGuennadi Liakhovetski return false; 774fdc50a94SYusuke Goda } 775f985da17SGuennadi Liakhovetski 776f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 777f985da17SGuennadi Liakhovetski 778f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 779f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 780f985da17SGuennadi Liakhovetski 781f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 782f985da17SGuennadi Liakhovetski return false; 783f985da17SGuennadi Liakhovetski 784f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 785f985da17SGuennadi Liakhovetski 786f985da17SGuennadi Liakhovetski return true; 787fdc50a94SYusuke Goda } 788fdc50a94SYusuke Goda 789fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 790fdc50a94SYusuke Goda struct mmc_command *cmd) 791fdc50a94SYusuke Goda { 792fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 793487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 794487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 795487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 796487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 797fdc50a94SYusuke Goda } else 798487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 799fdc50a94SYusuke Goda } 800fdc50a94SYusuke Goda 801fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 802fdc50a94SYusuke Goda struct mmc_command *cmd) 803fdc50a94SYusuke Goda { 804487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 805fdc50a94SYusuke Goda } 806fdc50a94SYusuke Goda 807fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 80869983404SGuennadi Liakhovetski struct mmc_request *mrq) 809fdc50a94SYusuke Goda { 810585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 81169983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 81269983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 81369983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 814fdc50a94SYusuke Goda u32 tmp = 0; 815fdc50a94SYusuke Goda 816fdc50a94SYusuke Goda /* Response Type check */ 817fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 818fdc50a94SYusuke Goda case MMC_RSP_NONE: 819fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 820fdc50a94SYusuke Goda break; 821fdc50a94SYusuke Goda case MMC_RSP_R1: 822fdc50a94SYusuke Goda case MMC_RSP_R3: 823fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 824fdc50a94SYusuke Goda break; 8255b1c29bcSUlf Hansson case MMC_RSP_R1B: 8265b1c29bcSUlf Hansson tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B; 8275b1c29bcSUlf Hansson break; 828fdc50a94SYusuke Goda case MMC_RSP_R2: 829fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 830fdc50a94SYusuke Goda break; 831fdc50a94SYusuke Goda default: 832585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported response type.\n"); 833fdc50a94SYusuke Goda break; 834fdc50a94SYusuke Goda } 8355b1c29bcSUlf Hansson 836fdc50a94SYusuke Goda /* WDAT / DATW */ 83769983404SGuennadi Liakhovetski if (data) { 838fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 839fdc50a94SYusuke Goda switch (host->bus_width) { 840fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 841fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 842fdc50a94SYusuke Goda break; 843fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 844fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 845fdc50a94SYusuke Goda break; 846fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 847fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 848fdc50a94SYusuke Goda break; 849fdc50a94SYusuke Goda default: 850585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported bus width.\n"); 851fdc50a94SYusuke Goda break; 852fdc50a94SYusuke Goda } 853555061f9STeppei Kamijou switch (host->timing) { 8544039ff47SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 855555061f9STeppei Kamijou /* 856555061f9STeppei Kamijou * MMC core will only set this timing, if the host 8574039ff47SSeungwon Jeon * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 8584039ff47SSeungwon Jeon * capability. MMCIF implementations with this 8594039ff47SSeungwon Jeon * capability, e.g. sh73a0, will have to set it 8604039ff47SSeungwon Jeon * in their platform data. 861555061f9STeppei Kamijou */ 862555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 863555061f9STeppei Kamijou break; 864555061f9STeppei Kamijou } 865fdc50a94SYusuke Goda } 866fdc50a94SYusuke Goda /* DWEN */ 867fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 868fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 869fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 870fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 871fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 872fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 87369983404SGuennadi Liakhovetski data->blocks << 16); 874fdc50a94SYusuke Goda } 875fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 876fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 877fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 878fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 879fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 880fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 881fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 882fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 883fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 884fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 885fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 886fdc50a94SYusuke Goda 88769983404SGuennadi Liakhovetski return (opc << 24) | tmp; 888fdc50a94SYusuke Goda } 889fdc50a94SYusuke Goda 890e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 891fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 892fdc50a94SYusuke Goda { 893585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 894585c3a5aSKuninori Morimoto 895fdc50a94SYusuke Goda switch (opc) { 896fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 897f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 898f985da17SGuennadi Liakhovetski return 0; 899fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 900f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 901f985da17SGuennadi Liakhovetski return 0; 902fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 903f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 904f985da17SGuennadi Liakhovetski return 0; 905fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 906fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 907f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 908f985da17SGuennadi Liakhovetski return 0; 909fdc50a94SYusuke Goda default: 910585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported CMD%d\n", opc); 911ee4b8887SGuennadi Liakhovetski return -EINVAL; 912fdc50a94SYusuke Goda } 913fdc50a94SYusuke Goda } 914fdc50a94SYusuke Goda 915fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 916ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 917fdc50a94SYusuke Goda { 918ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 919f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 9205b1c29bcSUlf Hansson u32 mask = 0; 921dbb42d96SKouichi Tomita unsigned long flags; 922fdc50a94SYusuke Goda 9235b1c29bcSUlf Hansson if (cmd->flags & MMC_RSP_BUSY) 924ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 9255b1c29bcSUlf Hansson else 926ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 927fdc50a94SYusuke Goda 928967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 929967bcb77SGuennadi Liakhovetski mask |= MASK_MCCSTO; 930967bcb77SGuennadi Liakhovetski 93169983404SGuennadi Liakhovetski if (mrq->data) { 932487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 933487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 934487d9fc5SMagnus Damm mrq->data->blksz); 935fdc50a94SYusuke Goda } 93669983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 937fdc50a94SYusuke Goda 938967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 939487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 940967bcb77SGuennadi Liakhovetski else 941967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 942487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 943fdc50a94SYusuke Goda /* set arg */ 944487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 945fdc50a94SYusuke Goda /* set cmd */ 946dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 947487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 948fdc50a94SYusuke Goda 949f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 950f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 951dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 952fdc50a94SYusuke Goda } 953fdc50a94SYusuke Goda 954fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 955ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 956fdc50a94SYusuke Goda { 957585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 958585c3a5aSKuninori Morimoto 95969983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 96069983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 961fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 96269983404SGuennadi Liakhovetski break; 96369983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 964fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 96569983404SGuennadi Liakhovetski break; 96669983404SGuennadi Liakhovetski default: 967585c3a5aSKuninori Morimoto dev_err(dev, "unsupported stop cmd\n"); 96869983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 969fdc50a94SYusuke Goda return; 970fdc50a94SYusuke Goda } 971fdc50a94SYusuke Goda 972f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 973fdc50a94SYusuke Goda } 974fdc50a94SYusuke Goda 975fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 976fdc50a94SYusuke Goda { 977fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 978585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 9793b0beafcSGuennadi Liakhovetski unsigned long flags; 9803b0beafcSGuennadi Liakhovetski 9813b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9823b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 983585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 984585c3a5aSKuninori Morimoto __func__, host->state); 9853b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9863b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9873b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9883b0beafcSGuennadi Liakhovetski return; 9893b0beafcSGuennadi Liakhovetski } 9903b0beafcSGuennadi Liakhovetski 9913b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9923b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 993fdc50a94SYusuke Goda 994f985da17SGuennadi Liakhovetski host->mrq = mrq; 995f985da17SGuennadi Liakhovetski 996f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 997fdc50a94SYusuke Goda } 998fdc50a94SYusuke Goda 9999bb09a30SKuninori Morimoto static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) 1000a6609267SGuennadi Liakhovetski { 100189d49a70SKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 100289d49a70SKuninori Morimoto 100389d49a70SKuninori Morimoto if (host->mmc->f_max) { 100489d49a70SKuninori Morimoto unsigned int f_max, f_min = 0, f_min_old; 100589d49a70SKuninori Morimoto 100689d49a70SKuninori Morimoto f_max = host->mmc->f_max; 100789d49a70SKuninori Morimoto for (f_min_old = f_max; f_min_old > 2;) { 100889d49a70SKuninori Morimoto f_min = clk_round_rate(host->clk, f_min_old / 2); 100989d49a70SKuninori Morimoto if (f_min == f_min_old) 101089d49a70SKuninori Morimoto break; 101189d49a70SKuninori Morimoto f_min_old = f_min; 101289d49a70SKuninori Morimoto } 101389d49a70SKuninori Morimoto 101489d49a70SKuninori Morimoto /* 101589d49a70SKuninori Morimoto * This driver assumes this SoC is R-Car Gen2 or later 101689d49a70SKuninori Morimoto */ 101789d49a70SKuninori Morimoto host->clkdiv_map = 0x3ff; 101889d49a70SKuninori Morimoto 101989d49a70SKuninori Morimoto host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); 102089d49a70SKuninori Morimoto host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); 102189d49a70SKuninori Morimoto } else { 10226aed678bSKuninori Morimoto unsigned int clk = clk_get_rate(host->clk); 10236aed678bSKuninori Morimoto 10246aed678bSKuninori Morimoto host->mmc->f_max = clk / 2; 10256aed678bSKuninori Morimoto host->mmc->f_min = clk / 512; 1026a6609267SGuennadi Liakhovetski } 1027a6609267SGuennadi Liakhovetski 102889d49a70SKuninori Morimoto dev_dbg(dev, "clk max/min = %d/%d\n", 102989d49a70SKuninori Morimoto host->mmc->f_max, host->mmc->f_min); 103089d49a70SKuninori Morimoto } 103189d49a70SKuninori Morimoto 1032fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1033fdc50a94SYusuke Goda { 1034fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 1035585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 10363b0beafcSGuennadi Liakhovetski unsigned long flags; 10373b0beafcSGuennadi Liakhovetski 10383b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 10393b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 1040585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 1041585c3a5aSKuninori Morimoto __func__, host->state); 10423b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 10433b0beafcSGuennadi Liakhovetski return; 10443b0beafcSGuennadi Liakhovetski } 10453b0beafcSGuennadi Liakhovetski 10463b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 10473b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 1048fdc50a94SYusuke Goda 10494caf653aSUlf Hansson switch (ios->power_mode) { 10504caf653aSUlf Hansson case MMC_POWER_UP: 105133a31ceaSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 105233a31ceaSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd); 1053c9b0cef2SGuennadi Liakhovetski if (!host->power) { 10549bb09a30SKuninori Morimoto clk_prepare_enable(host->clk); 1055585c3a5aSKuninori Morimoto pm_runtime_get_sync(dev); 1056c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 10574caf653aSUlf Hansson sh_mmcif_request_dma(host); 10584caf653aSUlf Hansson host->power = true; 1059c9b0cef2SGuennadi Liakhovetski } 10604caf653aSUlf Hansson break; 10614caf653aSUlf Hansson case MMC_POWER_OFF: 106233a31ceaSUlf Hansson if (!IS_ERR(mmc->supply.vmmc)) 106333a31ceaSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0); 10644caf653aSUlf Hansson if (host->power) { 10654caf653aSUlf Hansson sh_mmcif_clock_control(host, 0); 10664caf653aSUlf Hansson sh_mmcif_release_dma(host); 10674caf653aSUlf Hansson pm_runtime_put(dev); 10684caf653aSUlf Hansson clk_disable_unprepare(host->clk); 10694caf653aSUlf Hansson host->power = false; 10704caf653aSUlf Hansson } 10714caf653aSUlf Hansson break; 10724caf653aSUlf Hansson case MMC_POWER_ON: 1073fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 10744caf653aSUlf Hansson break; 1075c9b0cef2SGuennadi Liakhovetski } 1076fdc50a94SYusuke Goda 1077555061f9STeppei Kamijou host->timing = ios->timing; 1078fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10793b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1080fdc50a94SYusuke Goda } 1081fdc50a94SYusuke Goda 1082fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1083fdc50a94SYusuke Goda .request = sh_mmcif_request, 1084fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 10855957eebaSUlf Hansson .get_cd = mmc_gpio_get_cd, 1086fdc50a94SYusuke Goda }; 1087fdc50a94SYusuke Goda 1088f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1089f985da17SGuennadi Liakhovetski { 1090f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 109169983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1092585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1093f985da17SGuennadi Liakhovetski long time; 1094f985da17SGuennadi Liakhovetski 1095f985da17SGuennadi Liakhovetski if (host->sd_error) { 1096f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1097f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1098f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1099f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1100f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1101f985da17SGuennadi Liakhovetski break; 1102f985da17SGuennadi Liakhovetski default: 1103f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1104f985da17SGuennadi Liakhovetski break; 1105f985da17SGuennadi Liakhovetski } 1106585c3a5aSKuninori Morimoto dev_dbg(dev, "CMD%d error %d\n", 1107e475b270STeppei Kamijou cmd->opcode, cmd->error); 1108aba9d646SGuennadi Liakhovetski host->sd_error = false; 1109f985da17SGuennadi Liakhovetski return false; 1110f985da17SGuennadi Liakhovetski } 1111f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1112f985da17SGuennadi Liakhovetski cmd->error = 0; 1113f985da17SGuennadi Liakhovetski return false; 1114f985da17SGuennadi Liakhovetski } 1115f985da17SGuennadi Liakhovetski 1116f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1117f985da17SGuennadi Liakhovetski 111869983404SGuennadi Liakhovetski if (!data) 1119f985da17SGuennadi Liakhovetski return false; 1120f985da17SGuennadi Liakhovetski 112190f1cb43SGuennadi Liakhovetski /* 112290f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to 112390f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active 112490f1cb43SGuennadi Liakhovetski */ 112590f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete); 112690f1cb43SGuennadi Liakhovetski 112769983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1128f985da17SGuennadi Liakhovetski if (host->chan_rx) 1129f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1130f985da17SGuennadi Liakhovetski } else { 1131f985da17SGuennadi Liakhovetski if (host->chan_tx) 1132f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1133f985da17SGuennadi Liakhovetski } 1134f985da17SGuennadi Liakhovetski 1135f985da17SGuennadi Liakhovetski if (!host->dma_active) { 113669983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 113799eb9d8dSGuennadi Liakhovetski return !data->error; 1138f985da17SGuennadi Liakhovetski } 1139f985da17SGuennadi Liakhovetski 1140f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1141f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1142f985da17SGuennadi Liakhovetski host->timeout); 1143eae30983STeppei Kamijou 1144eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1145eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1146eae30983STeppei Kamijou data->sg, data->sg_len, 1147eae30983STeppei Kamijou DMA_FROM_DEVICE); 1148eae30983STeppei Kamijou else 1149eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1150eae30983STeppei Kamijou data->sg, data->sg_len, 1151eae30983STeppei Kamijou DMA_TO_DEVICE); 1152eae30983STeppei Kamijou 1153f985da17SGuennadi Liakhovetski if (host->sd_error) { 1154f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1155f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1156f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 115769983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1158f985da17SGuennadi Liakhovetski } else if (!time) { 1159e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n"); 116069983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1161f985da17SGuennadi Liakhovetski } else if (time < 0) { 1162e475b270STeppei Kamijou dev_err(host->mmc->parent, 1163e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time); 116469983404SGuennadi Liakhovetski data->error = time; 1165f985da17SGuennadi Liakhovetski } 1166f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1167f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1168f985da17SGuennadi Liakhovetski host->dma_active = false; 1169f985da17SGuennadi Liakhovetski 1170eae30983STeppei Kamijou if (data->error) { 117169983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1172eae30983STeppei Kamijou /* Abort DMA */ 1173eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1174eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1175eae30983STeppei Kamijou else 1176eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1177eae30983STeppei Kamijou } 1178f985da17SGuennadi Liakhovetski 1179f985da17SGuennadi Liakhovetski return false; 1180f985da17SGuennadi Liakhovetski } 1181f985da17SGuennadi Liakhovetski 1182f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1183f985da17SGuennadi Liakhovetski { 1184f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 11858047310eSGuennadi Liakhovetski struct mmc_request *mrq; 1186585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 11875df460b1SGuennadi Liakhovetski bool wait = false; 1188dbb42d96SKouichi Tomita unsigned long flags; 1189dbb42d96SKouichi Tomita int wait_work; 1190dbb42d96SKouichi Tomita 1191dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 1192dbb42d96SKouichi Tomita wait_work = host->wait_for; 1193dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 1194f985da17SGuennadi Liakhovetski 1195f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1196f985da17SGuennadi Liakhovetski 11978047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 11988047310eSGuennadi Liakhovetski 11998047310eSGuennadi Liakhovetski mrq = host->mrq; 12008047310eSGuennadi Liakhovetski if (!mrq) { 1201585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 12028047310eSGuennadi Liakhovetski host->state, host->wait_for); 12038047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12048047310eSGuennadi Liakhovetski return IRQ_HANDLED; 12058047310eSGuennadi Liakhovetski } 12068047310eSGuennadi Liakhovetski 1207f985da17SGuennadi Liakhovetski /* 1208f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1209f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1210f985da17SGuennadi Liakhovetski */ 1211dbb42d96SKouichi Tomita switch (wait_work) { 1212f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1213f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 12148047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1215f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1216f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 12175df460b1SGuennadi Liakhovetski /* Wait for data? */ 12185df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1219f985da17SGuennadi Liakhovetski break; 1220f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 12215df460b1SGuennadi Liakhovetski /* Wait for more data? */ 12225df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1223f985da17SGuennadi Liakhovetski break; 1224f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 12255df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12265df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1227f985da17SGuennadi Liakhovetski break; 1228f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 12295df460b1SGuennadi Liakhovetski /* Wait data to write? */ 12305df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1231f985da17SGuennadi Liakhovetski break; 1232f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 12335df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12345df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1235f985da17SGuennadi Liakhovetski break; 1236f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1237f985da17SGuennadi Liakhovetski if (host->sd_error) { 1238f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1239585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); 1240f985da17SGuennadi Liakhovetski break; 1241f985da17SGuennadi Liakhovetski } 1242f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1243f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1244f985da17SGuennadi Liakhovetski break; 1245f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1246f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1247e475b270STeppei Kamijou if (host->sd_error) { 124891ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1249585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); 1250e475b270STeppei Kamijou } 1251f985da17SGuennadi Liakhovetski break; 1252f985da17SGuennadi Liakhovetski default: 1253f985da17SGuennadi Liakhovetski BUG(); 1254f985da17SGuennadi Liakhovetski } 1255f985da17SGuennadi Liakhovetski 12565df460b1SGuennadi Liakhovetski if (wait) { 12575df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12585df460b1SGuennadi Liakhovetski /* Wait for more data */ 12598047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12605df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 12615df460b1SGuennadi Liakhovetski } 12625df460b1SGuennadi Liakhovetski 1263f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 126491ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 126569983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 126669983404SGuennadi Liakhovetski data->bytes_xfered = 126769983404SGuennadi Liakhovetski data->blocks * data->blksz; 1268f985da17SGuennadi Liakhovetski 126969983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1270f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 12715df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 12725df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12738047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1274f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1275f985da17SGuennadi Liakhovetski } 1276f985da17SGuennadi Liakhovetski } 12775df460b1SGuennadi Liakhovetski } 1278f985da17SGuennadi Liakhovetski 1279f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1280f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 128169983404SGuennadi Liakhovetski host->mrq = NULL; 1282f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1283f985da17SGuennadi Liakhovetski 12848047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12858047310eSGuennadi Liakhovetski 1286f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1287f985da17SGuennadi Liakhovetski } 1288f985da17SGuennadi Liakhovetski 1289fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1290fdc50a94SYusuke Goda { 1291fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1292585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1293967bcb77SGuennadi Liakhovetski u32 state, mask; 1294fdc50a94SYusuke Goda 1295487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1296967bcb77SGuennadi Liakhovetski mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1297967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 1298967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1299967bcb77SGuennadi Liakhovetski else 1300967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 13018af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1302fdc50a94SYusuke Goda 13038af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN) 1304585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", 13058af50750SGuennadi Liakhovetski state); 13068af50750SGuennadi Liakhovetski 13078af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) { 1308aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1309585c3a5aSKuninori Morimoto dev_dbg(dev, "int err state = 0x%08x\n", state); 1310fdc50a94SYusuke Goda } 1311f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 13128af50750SGuennadi Liakhovetski if (!host->mrq) 1313585c3a5aSKuninori Morimoto dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); 1314f985da17SGuennadi Liakhovetski if (!host->dma_active) 1315f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1316f985da17SGuennadi Liakhovetski else if (host->sd_error) 13171b1a694dSKuninori Morimoto sh_mmcif_dma_complete(host); 1318f985da17SGuennadi Liakhovetski } else { 1319585c3a5aSKuninori Morimoto dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); 1320f985da17SGuennadi Liakhovetski } 1321fdc50a94SYusuke Goda 1322fdc50a94SYusuke Goda return IRQ_HANDLED; 1323fdc50a94SYusuke Goda } 1324fdc50a94SYusuke Goda 13251b1a694dSKuninori Morimoto static void sh_mmcif_timeout_work(struct work_struct *work) 1326f985da17SGuennadi Liakhovetski { 13271046a811SGeliang Tang struct delayed_work *d = to_delayed_work(work); 1328f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1329f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 1330585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 13318047310eSGuennadi Liakhovetski unsigned long flags; 1332f985da17SGuennadi Liakhovetski 1333f985da17SGuennadi Liakhovetski if (host->dying) 1334f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1335f985da17SGuennadi Liakhovetski return; 1336f985da17SGuennadi Liakhovetski 13378047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 13388047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 13398047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13408047310eSGuennadi Liakhovetski return; 13418047310eSGuennadi Liakhovetski } 13428047310eSGuennadi Liakhovetski 1343585c3a5aSKuninori Morimoto dev_err(dev, "Timeout waiting for %u on CMD%u\n", 13444cbd5224SKouichi Tomita host->wait_for, mrq->cmd->opcode); 13454cbd5224SKouichi Tomita 13468047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 13478047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13488047310eSGuennadi Liakhovetski 1349f985da17SGuennadi Liakhovetski /* 1350f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1351f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1352f985da17SGuennadi Liakhovetski */ 1353f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1354f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1355f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1356f985da17SGuennadi Liakhovetski break; 1357f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1358f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1359f985da17SGuennadi Liakhovetski break; 1360f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1361f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1362f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1363f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1364f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1365f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 136669983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1367f985da17SGuennadi Liakhovetski break; 1368f985da17SGuennadi Liakhovetski default: 1369f985da17SGuennadi Liakhovetski BUG(); 1370f985da17SGuennadi Liakhovetski } 1371f985da17SGuennadi Liakhovetski 1372f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1373f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1374f985da17SGuennadi Liakhovetski host->mrq = NULL; 1375f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1376f985da17SGuennadi Liakhovetski } 1377f985da17SGuennadi Liakhovetski 13787d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 13797d17baa0SGuennadi Liakhovetski { 1380585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1381585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 13827d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 13837d17baa0SGuennadi Liakhovetski 13847d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 13857d17baa0SGuennadi Liakhovetski 1386bf68a812SGuennadi Liakhovetski if (!pd) 1387bf68a812SGuennadi Liakhovetski return; 1388bf68a812SGuennadi Liakhovetski 13897d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 13907d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 13917d17baa0SGuennadi Liakhovetski else if (pd->ocr) 13927d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 13937d17baa0SGuennadi Liakhovetski } 13947d17baa0SGuennadi Liakhovetski 1395c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1396fdc50a94SYusuke Goda { 1397fdc50a94SYusuke Goda int ret = 0, irq[2]; 1398fdc50a94SYusuke Goda struct mmc_host *mmc; 1399e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 140060985c39SKuninori Morimoto struct device *dev = &pdev->dev; 140160985c39SKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 1402fdc50a94SYusuke Goda struct resource *res; 1403fdc50a94SYusuke Goda void __iomem *reg; 14042cd5b3e0SShinya Kuribayashi const char *name; 1405fdc50a94SYusuke Goda 1406fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1407fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 14082cd5b3e0SShinya Kuribayashi if (irq[0] < 0) { 140960985c39SKuninori Morimoto dev_err(dev, "Get irq error\n"); 1410fdc50a94SYusuke Goda return -ENXIO; 1411fdc50a94SYusuke Goda } 141218f55fccSBen Dooks 1413fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 141460985c39SKuninori Morimoto reg = devm_ioremap_resource(dev, res); 141518f55fccSBen Dooks if (IS_ERR(reg)) 141618f55fccSBen Dooks return PTR_ERR(reg); 1417e1aae2ebSGuennadi Liakhovetski 141860985c39SKuninori Morimoto mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 141918f55fccSBen Dooks if (!mmc) 142018f55fccSBen Dooks return -ENOMEM; 14212c9054dcSSimon Baatz 14222c9054dcSSimon Baatz ret = mmc_of_parse(mmc); 14232c9054dcSSimon Baatz if (ret < 0) 142446991005SBen Dooks goto err_host; 14252c9054dcSSimon Baatz 1426fdc50a94SYusuke Goda host = mmc_priv(mmc); 1427fdc50a94SYusuke Goda host->mmc = mmc; 1428fdc50a94SYusuke Goda host->addr = reg; 1429bad4371dSTakeshi Kihara host->timeout = msecs_to_jiffies(10000); 1430967bcb77SGuennadi Liakhovetski host->ccs_enable = !pd || !pd->ccs_unsupported; 14316d6fd367SGuennadi Liakhovetski host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; 1432fdc50a94SYusuke Goda 1433fdc50a94SYusuke Goda host->pd = pdev; 1434fdc50a94SYusuke Goda 14353b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1436fdc50a94SYusuke Goda 1437fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 14387d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 14397d17baa0SGuennadi Liakhovetski 1440eca889f6SGuennadi Liakhovetski mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1441dab3a28bSUlf Hansson mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO; 1442549646a9SUlf Hansson mmc->max_busy_timeout = 10000; 1443dab3a28bSUlf Hansson 1444bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1445fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1446a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1447fdc50a94SYusuke Goda mmc->max_blk_size = 512; 144809cbfeafSKirill A. Shutemov mmc->max_req_size = PAGE_SIZE * mmc->max_segs; 1449a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1450fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1451fdc50a94SYusuke Goda 1452fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1453a782d688SGuennadi Liakhovetski 14546aed678bSKuninori Morimoto host->clk = devm_clk_get(dev, NULL); 14556aed678bSKuninori Morimoto if (IS_ERR(host->clk)) { 14566aed678bSKuninori Morimoto ret = PTR_ERR(host->clk); 145760985c39SKuninori Morimoto dev_err(dev, "cannot get clock: %d\n", ret); 145888ac2a2cSUlf Hansson goto err_host; 1459b289174fSGuennadi Liakhovetski } 14609bb09a30SKuninori Morimoto 14619bb09a30SKuninori Morimoto ret = clk_prepare_enable(host->clk); 1462a6609267SGuennadi Liakhovetski if (ret < 0) 146388ac2a2cSUlf Hansson goto err_host; 1464b289174fSGuennadi Liakhovetski 14659bb09a30SKuninori Morimoto sh_mmcif_clk_setup(host); 14669bb09a30SKuninori Morimoto 146788ac2a2cSUlf Hansson pm_runtime_enable(dev); 146888ac2a2cSUlf Hansson host->power = false; 146988ac2a2cSUlf Hansson 147088ac2a2cSUlf Hansson ret = pm_runtime_get_sync(dev); 1471faca6648SGuennadi Liakhovetski if (ret < 0) 147246991005SBen Dooks goto err_clk; 1473a782d688SGuennadi Liakhovetski 14741b1a694dSKuninori Morimoto INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); 1475fdc50a94SYusuke Goda 1476b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 14773b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14783b0beafcSGuennadi Liakhovetski 147960985c39SKuninori Morimoto name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; 148060985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, 14816f4789e6SBen Dooks sh_mmcif_irqt, 0, name, host); 1482fdc50a94SYusuke Goda if (ret) { 148360985c39SKuninori Morimoto dev_err(dev, "request_irq error (%s)\n", name); 148411a80852SBen Dooks goto err_clk; 1485fdc50a94SYusuke Goda } 14862cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 148760985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[1], 14886f4789e6SBen Dooks sh_mmcif_intr, sh_mmcif_irqt, 14892cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1490fdc50a94SYusuke Goda if (ret) { 149160985c39SKuninori Morimoto dev_err(dev, "request_irq error (sh_mmc:int)\n"); 149211a80852SBen Dooks goto err_clk; 1493fdc50a94SYusuke Goda } 14942cd5b3e0SShinya Kuribayashi } 1495fdc50a94SYusuke Goda 14968047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 14978047310eSGuennadi Liakhovetski 14985ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 14995ba85d95SGuennadi Liakhovetski if (ret < 0) 15007f67f3a2SBen Dooks goto err_clk; 1501fdc50a94SYusuke Goda 150260985c39SKuninori Morimoto dev_pm_qos_expose_latency_limit(dev, 100); 1503efe6a8adSRafael J. Wysocki 150460985c39SKuninori Morimoto dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", 1505ce7eb688SBen Dooks sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 15066aed678bSKuninori Morimoto clk_get_rate(host->clk) / 1000000UL); 1507ce7eb688SBen Dooks 150888ac2a2cSUlf Hansson pm_runtime_put(dev); 15096aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1510fdc50a94SYusuke Goda return ret; 1511fdc50a94SYusuke Goda 151246991005SBen Dooks err_clk: 15136aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 151488ac2a2cSUlf Hansson pm_runtime_put_sync(dev); 151560985c39SKuninori Morimoto pm_runtime_disable(dev); 151646991005SBen Dooks err_host: 1517fdc50a94SYusuke Goda mmc_free_host(mmc); 1518fdc50a94SYusuke Goda return ret; 1519fdc50a94SYusuke Goda } 1520fdc50a94SYusuke Goda 15216e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1522fdc50a94SYusuke Goda { 1523fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1524fdc50a94SYusuke Goda 1525f985da17SGuennadi Liakhovetski host->dying = true; 15266aed678bSKuninori Morimoto clk_prepare_enable(host->clk); 1527faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1528aa0787a9SGuennadi Liakhovetski 1529efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1530efe6a8adSRafael J. Wysocki 1531faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 15323b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15333b0beafcSGuennadi Liakhovetski 1534f985da17SGuennadi Liakhovetski /* 1535f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1536f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1537f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1538f985da17SGuennadi Liakhovetski */ 1539f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1540f985da17SGuennadi Liakhovetski 15416aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1542fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1543faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1544faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1545fdc50a94SYusuke Goda 1546fdc50a94SYusuke Goda return 0; 1547fdc50a94SYusuke Goda } 1548fdc50a94SYusuke Goda 154951129f31SUlf Hansson #ifdef CONFIG_PM_SLEEP 1550faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1551faca6648SGuennadi Liakhovetski { 1552b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1553faca6648SGuennadi Liakhovetski 15545afc30fcSKoji Matsuoka pm_runtime_get_sync(dev); 1555faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15565afc30fcSKoji Matsuoka pm_runtime_put(dev); 1557faca6648SGuennadi Liakhovetski 1558cb3ca1aeSUlf Hansson return 0; 1559faca6648SGuennadi Liakhovetski } 1560faca6648SGuennadi Liakhovetski 1561faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1562faca6648SGuennadi Liakhovetski { 1563cb3ca1aeSUlf Hansson return 0; 1564faca6648SGuennadi Liakhovetski } 156551129f31SUlf Hansson #endif 1566faca6648SGuennadi Liakhovetski 1567faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 156851129f31SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1569faca6648SGuennadi Liakhovetski }; 1570faca6648SGuennadi Liakhovetski 1571fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1572fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1573fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1574fdc50a94SYusuke Goda .driver = { 1575fdc50a94SYusuke Goda .name = DRIVER_NAME, 1576faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 15771b1a694dSKuninori Morimoto .of_match_table = sh_mmcif_of_match, 1578fdc50a94SYusuke Goda }, 1579fdc50a94SYusuke Goda }; 1580fdc50a94SYusuke Goda 1581d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1582fdc50a94SYusuke Goda 1583fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1584fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1585aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1586fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1587