1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 598047310eSGuennadi Liakhovetski #include <linux/mutex.h> 60a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 61e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 62efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 63faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 64d00cadacSGuennadi Liakhovetski #include <linux/sh_dma.h> 653b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6688b47679SPaul Gortmaker #include <linux/module.h> 67fdc50a94SYusuke Goda 68fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 69fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 70fdc50a94SYusuke Goda 71fdc50a94SYusuke Goda /* CE_CMD_SET */ 72fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 73fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 74fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 75fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 76fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 77fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 78fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 79fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 80fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 81fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 82fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 83fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 84fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 85fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 86fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 88fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 89fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 90fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 91fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 92fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 93555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 94fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 95fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 96fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 97fdc50a94SYusuke Goda 98fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 99fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 100fdc50a94SYusuke Goda 101fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 102fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 103fdc50a94SYusuke Goda 104fdc50a94SYusuke Goda /* CE_INT */ 105fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 106fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 107fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 108fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 109fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 110fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 111fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 112fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 113fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 114fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 115fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 116fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 117fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 118fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 119fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 120fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 121fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 122fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 123fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 124fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 125fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 126fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 127fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 128fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 129fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 130fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 131fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 132fdc50a94SYusuke Goda 1338af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 1348af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 1358af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 1368af50750SGuennadi Liakhovetski 137967bcb77SGuennadi Liakhovetski #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 138967bcb77SGuennadi Liakhovetski 139fdc50a94SYusuke Goda /* CE_INT_MASK */ 140fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 141fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 142fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 143fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 144fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 145fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 146fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 147fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 148fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 149fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 150fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 151fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 152fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 153fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 154fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 155fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 156fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 157fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 158fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 159fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 160fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 161fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 162fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 163fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 164fdc50a94SYusuke Goda 165ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 166ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 167967bcb77SGuennadi Liakhovetski MASK_MCRCSTO | MASK_MWDATTO | \ 168ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 169ee4b8887SGuennadi Liakhovetski 1708af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 1718af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \ 1728af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 1738af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE) 1748af50750SGuennadi Liakhovetski 175fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 176fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 177fdc50a94SYusuke Goda 178fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 179fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 180fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 181fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 182fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 183fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 184fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 185fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 186fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 187fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 188fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 189fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 190fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 191fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 192fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 193fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 194fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 195fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 196fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 197fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 198fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 199fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 200fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 201fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 202fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 203fdc50a94SYusuke Goda 204fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 205fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 206fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 207fdc50a94SYusuke Goda 2083b0beafcSGuennadi Liakhovetski enum mmcif_state { 2093b0beafcSGuennadi Liakhovetski STATE_IDLE, 2103b0beafcSGuennadi Liakhovetski STATE_REQUEST, 2113b0beafcSGuennadi Liakhovetski STATE_IOS, 2128047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2133b0beafcSGuennadi Liakhovetski }; 2143b0beafcSGuennadi Liakhovetski 215f985da17SGuennadi Liakhovetski enum mmcif_wait_for { 216f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 217f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 218f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 219f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 220f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 221f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 222f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 223f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 224f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 225f985da17SGuennadi Liakhovetski }; 226f985da17SGuennadi Liakhovetski 227fdc50a94SYusuke Goda struct sh_mmcif_host { 228fdc50a94SYusuke Goda struct mmc_host *mmc; 229f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 230fdc50a94SYusuke Goda struct platform_device *pd; 2316aed678bSKuninori Morimoto struct clk *clk; 232fdc50a94SYusuke Goda int bus_width; 233555061f9STeppei Kamijou unsigned char timing; 234aa0787a9SGuennadi Liakhovetski bool sd_error; 235f985da17SGuennadi Liakhovetski bool dying; 236fdc50a94SYusuke Goda long timeout; 237fdc50a94SYusuke Goda void __iomem *addr; 238f985da17SGuennadi Liakhovetski u32 *pio_ptr; 239ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2403b0beafcSGuennadi Liakhovetski enum mmcif_state state; 241f985da17SGuennadi Liakhovetski enum mmcif_wait_for wait_for; 242f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 243f985da17SGuennadi Liakhovetski size_t blocksize; 244f985da17SGuennadi Liakhovetski int sg_idx; 245f985da17SGuennadi Liakhovetski int sg_blkidx; 246faca6648SGuennadi Liakhovetski bool power; 247c9b0cef2SGuennadi Liakhovetski bool card_present; 248967bcb77SGuennadi Liakhovetski bool ccs_enable; /* Command Completion Signal support */ 2496d6fd367SGuennadi Liakhovetski bool clk_ctrl2_enable; 2508047310eSGuennadi Liakhovetski struct mutex thread_lock; 251fdc50a94SYusuke Goda 252a782d688SGuennadi Liakhovetski /* DMA support */ 253a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 254a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 255a782d688SGuennadi Liakhovetski struct completion dma_complete; 256f38f94c6SLinus Walleij bool dma_active; 257a782d688SGuennadi Liakhovetski }; 258fdc50a94SYusuke Goda 25970830b41SKuninori Morimoto static const struct of_device_id mmcif_of_match[] = { 26070830b41SKuninori Morimoto { .compatible = "renesas,sh-mmcif" }, 26170830b41SKuninori Morimoto { } 26270830b41SKuninori Morimoto }; 26370830b41SKuninori Morimoto MODULE_DEVICE_TABLE(of, mmcif_of_match); 26470830b41SKuninori Morimoto 265585c3a5aSKuninori Morimoto #define sh_mmcif_host_to_dev(host) (&host->pd->dev) 266585c3a5aSKuninori Morimoto 267fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 268fdc50a94SYusuke Goda unsigned int reg, u32 val) 269fdc50a94SYusuke Goda { 270487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 271fdc50a94SYusuke Goda } 272fdc50a94SYusuke Goda 273fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 274fdc50a94SYusuke Goda unsigned int reg, u32 val) 275fdc50a94SYusuke Goda { 276487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 277fdc50a94SYusuke Goda } 278fdc50a94SYusuke Goda 279a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 280a782d688SGuennadi Liakhovetski { 281a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2828047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 283585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 28469983404SGuennadi Liakhovetski 285585c3a5aSKuninori Morimoto dev_dbg(dev, "Command completed\n"); 286a782d688SGuennadi Liakhovetski 2878047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 288585c3a5aSKuninori Morimoto dev_name(dev))) 289a782d688SGuennadi Liakhovetski return; 290a782d688SGuennadi Liakhovetski 291a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 292a782d688SGuennadi Liakhovetski } 293a782d688SGuennadi Liakhovetski 294a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 295a782d688SGuennadi Liakhovetski { 29669983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 29769983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 298a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 299a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 300585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 301a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 302a782d688SGuennadi Liakhovetski int ret; 303a782d688SGuennadi Liakhovetski 30469983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3051ed828dbSLinus Walleij DMA_FROM_DEVICE); 306a782d688SGuennadi Liakhovetski if (ret > 0) { 307f38f94c6SLinus Walleij host->dma_active = true; 30816052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 30905f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 310a782d688SGuennadi Liakhovetski } 311a782d688SGuennadi Liakhovetski 312a782d688SGuennadi Liakhovetski if (desc) { 313a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 314a782d688SGuennadi Liakhovetski desc->callback_param = host; 315a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 316a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 317a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 318a782d688SGuennadi Liakhovetski } 319585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 32069983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 321a782d688SGuennadi Liakhovetski 322a782d688SGuennadi Liakhovetski if (!desc) { 323a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 324a782d688SGuennadi Liakhovetski if (ret >= 0) 325a782d688SGuennadi Liakhovetski ret = -EIO; 326a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 327f38f94c6SLinus Walleij host->dma_active = false; 328a782d688SGuennadi Liakhovetski dma_release_channel(chan); 329a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 330a782d688SGuennadi Liakhovetski chan = host->chan_tx; 331a782d688SGuennadi Liakhovetski if (chan) { 332a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 333a782d688SGuennadi Liakhovetski dma_release_channel(chan); 334a782d688SGuennadi Liakhovetski } 335585c3a5aSKuninori Morimoto dev_warn(dev, 336a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 337a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 338a782d688SGuennadi Liakhovetski } 339a782d688SGuennadi Liakhovetski 340585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 34169983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 342a782d688SGuennadi Liakhovetski } 343a782d688SGuennadi Liakhovetski 344a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 345a782d688SGuennadi Liakhovetski { 34669983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 34769983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 348a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 349a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 350585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 351a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 352a782d688SGuennadi Liakhovetski int ret; 353a782d688SGuennadi Liakhovetski 35469983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3551ed828dbSLinus Walleij DMA_TO_DEVICE); 356a782d688SGuennadi Liakhovetski if (ret > 0) { 357f38f94c6SLinus Walleij host->dma_active = true; 35816052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 35905f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 360a782d688SGuennadi Liakhovetski } 361a782d688SGuennadi Liakhovetski 362a782d688SGuennadi Liakhovetski if (desc) { 363a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 364a782d688SGuennadi Liakhovetski desc->callback_param = host; 365a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 366a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 367a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 368a782d688SGuennadi Liakhovetski } 369585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 37069983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 371a782d688SGuennadi Liakhovetski 372a782d688SGuennadi Liakhovetski if (!desc) { 373a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 374a782d688SGuennadi Liakhovetski if (ret >= 0) 375a782d688SGuennadi Liakhovetski ret = -EIO; 376a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 377f38f94c6SLinus Walleij host->dma_active = false; 378a782d688SGuennadi Liakhovetski dma_release_channel(chan); 379a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 380a782d688SGuennadi Liakhovetski chan = host->chan_rx; 381a782d688SGuennadi Liakhovetski if (chan) { 382a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 383a782d688SGuennadi Liakhovetski dma_release_channel(chan); 384a782d688SGuennadi Liakhovetski } 385585c3a5aSKuninori Morimoto dev_warn(dev, 386a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 387a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 388a782d688SGuennadi Liakhovetski } 389a782d688SGuennadi Liakhovetski 390585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, 391a782d688SGuennadi Liakhovetski desc, cookie); 392a782d688SGuennadi Liakhovetski } 393a782d688SGuennadi Liakhovetski 394e5a233cbSLaurent Pinchart static struct dma_chan * 395e5a233cbSLaurent Pinchart sh_mmcif_request_dma_one(struct sh_mmcif_host *host, 396e5a233cbSLaurent Pinchart struct sh_mmcif_plat_data *pdata, 397e5a233cbSLaurent Pinchart enum dma_transfer_direction direction) 398a782d688SGuennadi Liakhovetski { 399d25006e7SLaurent Pinchart struct dma_slave_config cfg = { 0, }; 400e5a233cbSLaurent Pinchart struct dma_chan *chan; 4015f48dd06SKuninori Morimoto void *slave_data = NULL; 402e5a233cbSLaurent Pinchart struct resource *res; 403585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 4040e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 4050e79f9aeSGuennadi Liakhovetski int ret; 4060e79f9aeSGuennadi Liakhovetski 407e5a233cbSLaurent Pinchart dma_cap_zero(mask); 408e5a233cbSLaurent Pinchart dma_cap_set(DMA_SLAVE, mask); 409e5a233cbSLaurent Pinchart 410e5a233cbSLaurent Pinchart if (pdata) 4115f48dd06SKuninori Morimoto slave_data = direction == DMA_MEM_TO_DEV ? 4125f48dd06SKuninori Morimoto (void *)pdata->slave_id_tx : 4135f48dd06SKuninori Morimoto (void *)pdata->slave_id_rx; 414e5a233cbSLaurent Pinchart 415e5a233cbSLaurent Pinchart chan = dma_request_slave_channel_compat(mask, shdma_chan_filter, 416585c3a5aSKuninori Morimoto slave_data, dev, 417e5a233cbSLaurent Pinchart direction == DMA_MEM_TO_DEV ? "tx" : "rx"); 418e5a233cbSLaurent Pinchart 419585c3a5aSKuninori Morimoto dev_dbg(dev, "%s: %s: got channel %p\n", __func__, 420e5a233cbSLaurent Pinchart direction == DMA_MEM_TO_DEV ? "TX" : "RX", chan); 421e5a233cbSLaurent Pinchart 422e5a233cbSLaurent Pinchart if (!chan) 423e5a233cbSLaurent Pinchart return NULL; 424e5a233cbSLaurent Pinchart 425e5a233cbSLaurent Pinchart res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 426e5a233cbSLaurent Pinchart 427e5a233cbSLaurent Pinchart cfg.direction = direction; 428d25006e7SLaurent Pinchart 429e36152aaSLaurent Pinchart if (direction == DMA_DEV_TO_MEM) { 430d25006e7SLaurent Pinchart cfg.src_addr = res->start + MMCIF_CE_DATA; 431e36152aaSLaurent Pinchart cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 432e36152aaSLaurent Pinchart } else { 433e5a233cbSLaurent Pinchart cfg.dst_addr = res->start + MMCIF_CE_DATA; 434e36152aaSLaurent Pinchart cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 435e36152aaSLaurent Pinchart } 436d25006e7SLaurent Pinchart 437e5a233cbSLaurent Pinchart ret = dmaengine_slave_config(chan, &cfg); 438e5a233cbSLaurent Pinchart if (ret < 0) { 439e5a233cbSLaurent Pinchart dma_release_channel(chan); 440e5a233cbSLaurent Pinchart return NULL; 441e5a233cbSLaurent Pinchart } 442e5a233cbSLaurent Pinchart 443e5a233cbSLaurent Pinchart return chan; 444e5a233cbSLaurent Pinchart } 445e5a233cbSLaurent Pinchart 446e5a233cbSLaurent Pinchart static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 447e5a233cbSLaurent Pinchart struct sh_mmcif_plat_data *pdata) 448e5a233cbSLaurent Pinchart { 449585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 450f38f94c6SLinus Walleij host->dma_active = false; 451a782d688SGuennadi Liakhovetski 452acd6d772SGuennadi Liakhovetski if (pdata) { 4530e79f9aeSGuennadi Liakhovetski if (pdata->slave_id_tx <= 0 || pdata->slave_id_rx <= 0) 4540e79f9aeSGuennadi Liakhovetski return; 455585c3a5aSKuninori Morimoto } else if (!dev->of_node) { 456acd6d772SGuennadi Liakhovetski return; 457acd6d772SGuennadi Liakhovetski } 458a782d688SGuennadi Liakhovetski 459a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 460e5a233cbSLaurent Pinchart host->chan_tx = sh_mmcif_request_dma_one(host, pdata, DMA_MEM_TO_DEV); 461a782d688SGuennadi Liakhovetski if (!host->chan_tx) 462a782d688SGuennadi Liakhovetski return; 463a782d688SGuennadi Liakhovetski 464e5a233cbSLaurent Pinchart host->chan_rx = sh_mmcif_request_dma_one(host, pdata, DMA_DEV_TO_MEM); 465e5a233cbSLaurent Pinchart if (!host->chan_rx) { 4660e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 4670e79f9aeSGuennadi Liakhovetski host->chan_tx = NULL; 468a782d688SGuennadi Liakhovetski } 469e5a233cbSLaurent Pinchart } 470a782d688SGuennadi Liakhovetski 471a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 472a782d688SGuennadi Liakhovetski { 473a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 474a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 475a782d688SGuennadi Liakhovetski if (host->chan_tx) { 476a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 477a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 478a782d688SGuennadi Liakhovetski dma_release_channel(chan); 479a782d688SGuennadi Liakhovetski } 480a782d688SGuennadi Liakhovetski if (host->chan_rx) { 481a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 482a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 483a782d688SGuennadi Liakhovetski dma_release_channel(chan); 484a782d688SGuennadi Liakhovetski } 485a782d688SGuennadi Liakhovetski 486f38f94c6SLinus Walleij host->dma_active = false; 487a782d688SGuennadi Liakhovetski } 488fdc50a94SYusuke Goda 489fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 490fdc50a94SYusuke Goda { 491585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 492585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *p = dev->platform_data; 493bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 4946aed678bSKuninori Morimoto unsigned int current_clk = clk_get_rate(host->clk); 495fdc50a94SYusuke Goda 496fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 497fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 498fdc50a94SYusuke Goda 499fdc50a94SYusuke Goda if (!clk) 500fdc50a94SYusuke Goda return; 5016aed678bSKuninori Morimoto if (sup_pclk && clk == current_clk) 502fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 503fdc50a94SYusuke Goda else 504fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 5056aed678bSKuninori Morimoto ((fls(DIV_ROUND_UP(current_clk, 506f9388257SSimon Horman clk) - 1) - 1) << 16)); 507fdc50a94SYusuke Goda 508fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 509fdc50a94SYusuke Goda } 510fdc50a94SYusuke Goda 511fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 512fdc50a94SYusuke Goda { 513fdc50a94SYusuke Goda u32 tmp; 514fdc50a94SYusuke Goda 515487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 516fdc50a94SYusuke Goda 517487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 518487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 519967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 520967bcb77SGuennadi Liakhovetski tmp |= SCCSTO_29; 5216d6fd367SGuennadi Liakhovetski if (host->clk_ctrl2_enable) 5226d6fd367SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 523fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 524967bcb77SGuennadi Liakhovetski SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 525fdc50a94SYusuke Goda /* byte swap on */ 526fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 527fdc50a94SYusuke Goda } 528fdc50a94SYusuke Goda 529fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 530fdc50a94SYusuke Goda { 531585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 532fdc50a94SYusuke Goda u32 state1, state2; 533ee4b8887SGuennadi Liakhovetski int ret, timeout; 534fdc50a94SYusuke Goda 535aa0787a9SGuennadi Liakhovetski host->sd_error = false; 536fdc50a94SYusuke Goda 537487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 538487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 539585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); 540585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); 541fdc50a94SYusuke Goda 542fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 543fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 544fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 545ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 546487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 547fdc50a94SYusuke Goda & STS1_CMDSEQ)) 548fdc50a94SYusuke Goda break; 549fdc50a94SYusuke Goda mdelay(1); 550fdc50a94SYusuke Goda } 551ee4b8887SGuennadi Liakhovetski if (!timeout) { 552585c3a5aSKuninori Morimoto dev_err(dev, 553ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 554ee4b8887SGuennadi Liakhovetski return -EIO; 555ee4b8887SGuennadi Liakhovetski } 556fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 557585c3a5aSKuninori Morimoto dev_dbg(dev, "Forced end of command sequence\n"); 558fdc50a94SYusuke Goda return -EIO; 559fdc50a94SYusuke Goda } 560fdc50a94SYusuke Goda 561fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 562585c3a5aSKuninori Morimoto dev_err(dev, " CRC error: state %u, wait %u\n", 563e475b270STeppei Kamijou host->state, host->wait_for); 564fdc50a94SYusuke Goda ret = -EIO; 565fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 566585c3a5aSKuninori Morimoto dev_err(dev, " Timeout: state %u, wait %u\n", 567e475b270STeppei Kamijou host->state, host->wait_for); 568fdc50a94SYusuke Goda ret = -ETIMEDOUT; 569fdc50a94SYusuke Goda } else { 570585c3a5aSKuninori Morimoto dev_dbg(dev, " End/Index error: state %u, wait %u\n", 571e475b270STeppei Kamijou host->state, host->wait_for); 572fdc50a94SYusuke Goda ret = -EIO; 573fdc50a94SYusuke Goda } 574fdc50a94SYusuke Goda return ret; 575fdc50a94SYusuke Goda } 576fdc50a94SYusuke Goda 577f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 578f985da17SGuennadi Liakhovetski { 579f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 580f985da17SGuennadi Liakhovetski 581f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 582f985da17SGuennadi Liakhovetski 583f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 584f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 585f985da17SGuennadi Liakhovetski 586f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 587f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 588f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 589f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 590f985da17SGuennadi Liakhovetski } else { 591f985da17SGuennadi Liakhovetski host->pio_ptr = p; 592f985da17SGuennadi Liakhovetski } 593f985da17SGuennadi Liakhovetski 59499eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 595f985da17SGuennadi Liakhovetski } 596f985da17SGuennadi Liakhovetski 597f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 598fdc50a94SYusuke Goda struct mmc_request *mrq) 599fdc50a94SYusuke Goda { 600f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 601f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 602f985da17SGuennadi Liakhovetski 603f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 604fdc50a94SYusuke Goda 605fdc50a94SYusuke Goda /* buf read enable */ 606fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 607f985da17SGuennadi Liakhovetski } 608fdc50a94SYusuke Goda 609f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 610f985da17SGuennadi Liakhovetski { 611585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 612f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 613f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 614f985da17SGuennadi Liakhovetski int i; 615f985da17SGuennadi Liakhovetski 616f985da17SGuennadi Liakhovetski if (host->sd_error) { 617f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 618585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 619f985da17SGuennadi Liakhovetski return false; 620f985da17SGuennadi Liakhovetski } 621f985da17SGuennadi Liakhovetski 622f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 623487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 624fdc50a94SYusuke Goda 625fdc50a94SYusuke Goda /* buffer read end */ 626fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 627f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 628fdc50a94SYusuke Goda 629f985da17SGuennadi Liakhovetski return true; 630fdc50a94SYusuke Goda } 631fdc50a94SYusuke Goda 632f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 633fdc50a94SYusuke Goda struct mmc_request *mrq) 634fdc50a94SYusuke Goda { 635fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 636fdc50a94SYusuke Goda 637f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 638f985da17SGuennadi Liakhovetski return; 639f985da17SGuennadi Liakhovetski 640f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 641f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 642f985da17SGuennadi Liakhovetski 643f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 644f985da17SGuennadi Liakhovetski host->sg_idx = 0; 645f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 646f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6475df460b1SGuennadi Liakhovetski 648fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 649fdc50a94SYusuke Goda } 650fdc50a94SYusuke Goda 651f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 652f985da17SGuennadi Liakhovetski { 653585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 654f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 655f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 656f985da17SGuennadi Liakhovetski int i; 657f985da17SGuennadi Liakhovetski 658f985da17SGuennadi Liakhovetski if (host->sd_error) { 659f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 660585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 661f985da17SGuennadi Liakhovetski return false; 662f985da17SGuennadi Liakhovetski } 663f985da17SGuennadi Liakhovetski 664f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 665f985da17SGuennadi Liakhovetski 666f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 667f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 668f985da17SGuennadi Liakhovetski 669f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 670f985da17SGuennadi Liakhovetski return false; 671f985da17SGuennadi Liakhovetski 672f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 673f985da17SGuennadi Liakhovetski 674f985da17SGuennadi Liakhovetski return true; 675f985da17SGuennadi Liakhovetski } 676f985da17SGuennadi Liakhovetski 677f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 678fdc50a94SYusuke Goda struct mmc_request *mrq) 679fdc50a94SYusuke Goda { 680f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 681f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 682fdc50a94SYusuke Goda 683f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 684fdc50a94SYusuke Goda 685fdc50a94SYusuke Goda /* buf write enable */ 686f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 687f985da17SGuennadi Liakhovetski } 688fdc50a94SYusuke Goda 689f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 690f985da17SGuennadi Liakhovetski { 691585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 692f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 693f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 694f985da17SGuennadi Liakhovetski int i; 695f985da17SGuennadi Liakhovetski 696f985da17SGuennadi Liakhovetski if (host->sd_error) { 697f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 698585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 699f985da17SGuennadi Liakhovetski return false; 700f985da17SGuennadi Liakhovetski } 701f985da17SGuennadi Liakhovetski 702f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 703487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 704fdc50a94SYusuke Goda 705fdc50a94SYusuke Goda /* buffer write end */ 706fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 707f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 708fdc50a94SYusuke Goda 709f985da17SGuennadi Liakhovetski return true; 710fdc50a94SYusuke Goda } 711fdc50a94SYusuke Goda 712f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 713fdc50a94SYusuke Goda struct mmc_request *mrq) 714fdc50a94SYusuke Goda { 715fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 716fdc50a94SYusuke Goda 717f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 718f985da17SGuennadi Liakhovetski return; 719fdc50a94SYusuke Goda 720f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 721f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 722f985da17SGuennadi Liakhovetski 723f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 724f985da17SGuennadi Liakhovetski host->sg_idx = 0; 725f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 726f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 7275df460b1SGuennadi Liakhovetski 728fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 729fdc50a94SYusuke Goda } 730f985da17SGuennadi Liakhovetski 731f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 732f985da17SGuennadi Liakhovetski { 733585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 734f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 735f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 736f985da17SGuennadi Liakhovetski int i; 737f985da17SGuennadi Liakhovetski 738f985da17SGuennadi Liakhovetski if (host->sd_error) { 739f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 740585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 741f985da17SGuennadi Liakhovetski return false; 742fdc50a94SYusuke Goda } 743f985da17SGuennadi Liakhovetski 744f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 745f985da17SGuennadi Liakhovetski 746f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 747f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 748f985da17SGuennadi Liakhovetski 749f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 750f985da17SGuennadi Liakhovetski return false; 751f985da17SGuennadi Liakhovetski 752f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 753f985da17SGuennadi Liakhovetski 754f985da17SGuennadi Liakhovetski return true; 755fdc50a94SYusuke Goda } 756fdc50a94SYusuke Goda 757fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 758fdc50a94SYusuke Goda struct mmc_command *cmd) 759fdc50a94SYusuke Goda { 760fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 761487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 762487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 763487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 764487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 765fdc50a94SYusuke Goda } else 766487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 767fdc50a94SYusuke Goda } 768fdc50a94SYusuke Goda 769fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 770fdc50a94SYusuke Goda struct mmc_command *cmd) 771fdc50a94SYusuke Goda { 772487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 773fdc50a94SYusuke Goda } 774fdc50a94SYusuke Goda 775fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 77669983404SGuennadi Liakhovetski struct mmc_request *mrq) 777fdc50a94SYusuke Goda { 778585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 77969983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 78069983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 78169983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 782fdc50a94SYusuke Goda u32 tmp = 0; 783fdc50a94SYusuke Goda 784fdc50a94SYusuke Goda /* Response Type check */ 785fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 786fdc50a94SYusuke Goda case MMC_RSP_NONE: 787fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 788fdc50a94SYusuke Goda break; 789fdc50a94SYusuke Goda case MMC_RSP_R1: 790fdc50a94SYusuke Goda case MMC_RSP_R1B: 791fdc50a94SYusuke Goda case MMC_RSP_R3: 792fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 793fdc50a94SYusuke Goda break; 794fdc50a94SYusuke Goda case MMC_RSP_R2: 795fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 796fdc50a94SYusuke Goda break; 797fdc50a94SYusuke Goda default: 798585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported response type.\n"); 799fdc50a94SYusuke Goda break; 800fdc50a94SYusuke Goda } 801fdc50a94SYusuke Goda switch (opc) { 802fdc50a94SYusuke Goda /* RBSY */ 803a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 804fdc50a94SYusuke Goda case MMC_SWITCH: 805fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 806fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 807fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 808fdc50a94SYusuke Goda case MMC_ERASE: 809fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 810fdc50a94SYusuke Goda break; 811fdc50a94SYusuke Goda } 812fdc50a94SYusuke Goda /* WDAT / DATW */ 81369983404SGuennadi Liakhovetski if (data) { 814fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 815fdc50a94SYusuke Goda switch (host->bus_width) { 816fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 817fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 818fdc50a94SYusuke Goda break; 819fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 820fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 821fdc50a94SYusuke Goda break; 822fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 823fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 824fdc50a94SYusuke Goda break; 825fdc50a94SYusuke Goda default: 826585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported bus width.\n"); 827fdc50a94SYusuke Goda break; 828fdc50a94SYusuke Goda } 829555061f9STeppei Kamijou switch (host->timing) { 8304039ff47SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 831555061f9STeppei Kamijou /* 832555061f9STeppei Kamijou * MMC core will only set this timing, if the host 8334039ff47SSeungwon Jeon * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 8344039ff47SSeungwon Jeon * capability. MMCIF implementations with this 8354039ff47SSeungwon Jeon * capability, e.g. sh73a0, will have to set it 8364039ff47SSeungwon Jeon * in their platform data. 837555061f9STeppei Kamijou */ 838555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 839555061f9STeppei Kamijou break; 840555061f9STeppei Kamijou } 841fdc50a94SYusuke Goda } 842fdc50a94SYusuke Goda /* DWEN */ 843fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 844fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 845fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 846fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 847fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 848fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 84969983404SGuennadi Liakhovetski data->blocks << 16); 850fdc50a94SYusuke Goda } 851fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 852fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 853fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 854fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 855fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 856fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 857fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 858fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 859fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 860fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 861fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 862fdc50a94SYusuke Goda 86369983404SGuennadi Liakhovetski return (opc << 24) | tmp; 864fdc50a94SYusuke Goda } 865fdc50a94SYusuke Goda 866e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 867fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 868fdc50a94SYusuke Goda { 869585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 870585c3a5aSKuninori Morimoto 871fdc50a94SYusuke Goda switch (opc) { 872fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 873f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 874f985da17SGuennadi Liakhovetski return 0; 875fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 876f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 877f985da17SGuennadi Liakhovetski return 0; 878fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 879f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 880f985da17SGuennadi Liakhovetski return 0; 881fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 882fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 883f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 884f985da17SGuennadi Liakhovetski return 0; 885fdc50a94SYusuke Goda default: 886585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported CMD%d\n", opc); 887ee4b8887SGuennadi Liakhovetski return -EINVAL; 888fdc50a94SYusuke Goda } 889fdc50a94SYusuke Goda } 890fdc50a94SYusuke Goda 891fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 892ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 893fdc50a94SYusuke Goda { 894ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 895f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 896f985da17SGuennadi Liakhovetski u32 mask; 897dbb42d96SKouichi Tomita unsigned long flags; 898fdc50a94SYusuke Goda 899fdc50a94SYusuke Goda switch (opc) { 900ee4b8887SGuennadi Liakhovetski /* response busy check */ 901a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 902fdc50a94SYusuke Goda case MMC_SWITCH: 903fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 904fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 905fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 906fdc50a94SYusuke Goda case MMC_ERASE: 907ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 908fdc50a94SYusuke Goda break; 909fdc50a94SYusuke Goda default: 910ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 911fdc50a94SYusuke Goda break; 912fdc50a94SYusuke Goda } 913fdc50a94SYusuke Goda 914967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 915967bcb77SGuennadi Liakhovetski mask |= MASK_MCCSTO; 916967bcb77SGuennadi Liakhovetski 91769983404SGuennadi Liakhovetski if (mrq->data) { 918487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 919487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 920487d9fc5SMagnus Damm mrq->data->blksz); 921fdc50a94SYusuke Goda } 92269983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 923fdc50a94SYusuke Goda 924967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 925487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 926967bcb77SGuennadi Liakhovetski else 927967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 928487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 929fdc50a94SYusuke Goda /* set arg */ 930487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 931fdc50a94SYusuke Goda /* set cmd */ 932dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 933487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 934fdc50a94SYusuke Goda 935f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 936f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 937dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 938fdc50a94SYusuke Goda } 939fdc50a94SYusuke Goda 940fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 941ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 942fdc50a94SYusuke Goda { 943585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 944585c3a5aSKuninori Morimoto 94569983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 94669983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 947fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 94869983404SGuennadi Liakhovetski break; 94969983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 950fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 95169983404SGuennadi Liakhovetski break; 95269983404SGuennadi Liakhovetski default: 953585c3a5aSKuninori Morimoto dev_err(dev, "unsupported stop cmd\n"); 95469983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 955fdc50a94SYusuke Goda return; 956fdc50a94SYusuke Goda } 957fdc50a94SYusuke Goda 958f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 959fdc50a94SYusuke Goda } 960fdc50a94SYusuke Goda 961fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 962fdc50a94SYusuke Goda { 963fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 964585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 9653b0beafcSGuennadi Liakhovetski unsigned long flags; 9663b0beafcSGuennadi Liakhovetski 9673b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 9683b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 969585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 970585c3a5aSKuninori Morimoto __func__, host->state); 9713b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 9723b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 9733b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 9743b0beafcSGuennadi Liakhovetski return; 9753b0beafcSGuennadi Liakhovetski } 9763b0beafcSGuennadi Liakhovetski 9773b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 9783b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 979fdc50a94SYusuke Goda 980fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 981fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 9827541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 9837541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 9847541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 9857541ca98SLaurent Pinchart break; 986fdc50a94SYusuke Goda case MMC_APP_CMD: 98792ff0c5bSTeppei Kamijou case SD_IO_RW_DIRECT: 9883b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 989fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 990fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 991fdc50a94SYusuke Goda return; 992fdc50a94SYusuke Goda default: 993fdc50a94SYusuke Goda break; 994fdc50a94SYusuke Goda } 995fdc50a94SYusuke Goda 996f985da17SGuennadi Liakhovetski host->mrq = mrq; 997f985da17SGuennadi Liakhovetski 998f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 999fdc50a94SYusuke Goda } 1000fdc50a94SYusuke Goda 10019bb09a30SKuninori Morimoto static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) 1002a6609267SGuennadi Liakhovetski { 10036aed678bSKuninori Morimoto unsigned int clk = clk_get_rate(host->clk); 10046aed678bSKuninori Morimoto 10056aed678bSKuninori Morimoto host->mmc->f_max = clk / 2; 10066aed678bSKuninori Morimoto host->mmc->f_min = clk / 512; 1007a6609267SGuennadi Liakhovetski } 1008a6609267SGuennadi Liakhovetski 10097d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 10107d17baa0SGuennadi Liakhovetski { 10117d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 10127d17baa0SGuennadi Liakhovetski 10137d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 10147d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 10157d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 10167d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 10177d17baa0SGuennadi Liakhovetski } 10187d17baa0SGuennadi Liakhovetski 1019fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1020fdc50a94SYusuke Goda { 1021fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 1022585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 10233b0beafcSGuennadi Liakhovetski unsigned long flags; 10243b0beafcSGuennadi Liakhovetski 10253b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 10263b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 1027585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 1028585c3a5aSKuninori Morimoto __func__, host->state); 10293b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 10303b0beafcSGuennadi Liakhovetski return; 10313b0beafcSGuennadi Liakhovetski } 10323b0beafcSGuennadi Liakhovetski 10333b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 10343b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 1035fdc50a94SYusuke Goda 1036f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 1037c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 1038faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 1039585c3a5aSKuninori Morimoto sh_mmcif_request_dma(host, dev->platform_data); 1040c9b0cef2SGuennadi Liakhovetski host->card_present = true; 1041faca6648SGuennadi Liakhovetski } 10427d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1043f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 1044f5e0cec4SGuennadi Liakhovetski /* clock stop */ 1045f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 1046faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 1047c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 1048c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 1049c9b0cef2SGuennadi Liakhovetski host->card_present = false; 1050c9b0cef2SGuennadi Liakhovetski } 1051c9b0cef2SGuennadi Liakhovetski } 1052faca6648SGuennadi Liakhovetski if (host->power) { 1053585c3a5aSKuninori Morimoto pm_runtime_put_sync(dev); 10546aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1055faca6648SGuennadi Liakhovetski host->power = false; 10567d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 10577d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1058faca6648SGuennadi Liakhovetski } 10593b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1060f5e0cec4SGuennadi Liakhovetski return; 1061fdc50a94SYusuke Goda } 1062fdc50a94SYusuke Goda 1063c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 1064c9b0cef2SGuennadi Liakhovetski if (!host->power) { 10659bb09a30SKuninori Morimoto clk_prepare_enable(host->clk); 10669bb09a30SKuninori Morimoto 1067585c3a5aSKuninori Morimoto pm_runtime_get_sync(dev); 1068c9b0cef2SGuennadi Liakhovetski host->power = true; 1069c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 1070c9b0cef2SGuennadi Liakhovetski } 1071fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 1072c9b0cef2SGuennadi Liakhovetski } 1073fdc50a94SYusuke Goda 1074555061f9STeppei Kamijou host->timing = ios->timing; 1075fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 10763b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1077fdc50a94SYusuke Goda } 1078fdc50a94SYusuke Goda 1079777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1080777271d0SArnd Hannemann { 1081777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1082585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1083585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *p = dev->platform_data; 1084e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1085e480606aSGuennadi Liakhovetski 1086e480606aSGuennadi Liakhovetski if (ret >= 0) 1087e480606aSGuennadi Liakhovetski return ret; 1088777271d0SArnd Hannemann 1089bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1090777271d0SArnd Hannemann return -ENOSYS; 1091777271d0SArnd Hannemann else 1092777271d0SArnd Hannemann return p->get_cd(host->pd); 1093777271d0SArnd Hannemann } 1094777271d0SArnd Hannemann 1095fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1096fdc50a94SYusuke Goda .request = sh_mmcif_request, 1097fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1098777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1099fdc50a94SYusuke Goda }; 1100fdc50a94SYusuke Goda 1101f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1102f985da17SGuennadi Liakhovetski { 1103f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 110469983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1105585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1106f985da17SGuennadi Liakhovetski long time; 1107f985da17SGuennadi Liakhovetski 1108f985da17SGuennadi Liakhovetski if (host->sd_error) { 1109f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1110f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1111f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1112f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1113f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1114f985da17SGuennadi Liakhovetski break; 1115f985da17SGuennadi Liakhovetski default: 1116f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1117f985da17SGuennadi Liakhovetski break; 1118f985da17SGuennadi Liakhovetski } 1119585c3a5aSKuninori Morimoto dev_dbg(dev, "CMD%d error %d\n", 1120e475b270STeppei Kamijou cmd->opcode, cmd->error); 1121aba9d646SGuennadi Liakhovetski host->sd_error = false; 1122f985da17SGuennadi Liakhovetski return false; 1123f985da17SGuennadi Liakhovetski } 1124f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1125f985da17SGuennadi Liakhovetski cmd->error = 0; 1126f985da17SGuennadi Liakhovetski return false; 1127f985da17SGuennadi Liakhovetski } 1128f985da17SGuennadi Liakhovetski 1129f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1130f985da17SGuennadi Liakhovetski 113169983404SGuennadi Liakhovetski if (!data) 1132f985da17SGuennadi Liakhovetski return false; 1133f985da17SGuennadi Liakhovetski 113490f1cb43SGuennadi Liakhovetski /* 113590f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to 113690f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active 113790f1cb43SGuennadi Liakhovetski */ 113890f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete); 113990f1cb43SGuennadi Liakhovetski 114069983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1141f985da17SGuennadi Liakhovetski if (host->chan_rx) 1142f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1143f985da17SGuennadi Liakhovetski } else { 1144f985da17SGuennadi Liakhovetski if (host->chan_tx) 1145f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1146f985da17SGuennadi Liakhovetski } 1147f985da17SGuennadi Liakhovetski 1148f985da17SGuennadi Liakhovetski if (!host->dma_active) { 114969983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 115099eb9d8dSGuennadi Liakhovetski return !data->error; 1151f985da17SGuennadi Liakhovetski } 1152f985da17SGuennadi Liakhovetski 1153f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1154f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1155f985da17SGuennadi Liakhovetski host->timeout); 1156eae30983STeppei Kamijou 1157eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1158eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1159eae30983STeppei Kamijou data->sg, data->sg_len, 1160eae30983STeppei Kamijou DMA_FROM_DEVICE); 1161eae30983STeppei Kamijou else 1162eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1163eae30983STeppei Kamijou data->sg, data->sg_len, 1164eae30983STeppei Kamijou DMA_TO_DEVICE); 1165eae30983STeppei Kamijou 1166f985da17SGuennadi Liakhovetski if (host->sd_error) { 1167f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1168f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1169f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 117069983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1171f985da17SGuennadi Liakhovetski } else if (!time) { 1172e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n"); 117369983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1174f985da17SGuennadi Liakhovetski } else if (time < 0) { 1175e475b270STeppei Kamijou dev_err(host->mmc->parent, 1176e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time); 117769983404SGuennadi Liakhovetski data->error = time; 1178f985da17SGuennadi Liakhovetski } 1179f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1180f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1181f985da17SGuennadi Liakhovetski host->dma_active = false; 1182f985da17SGuennadi Liakhovetski 1183eae30983STeppei Kamijou if (data->error) { 118469983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1185eae30983STeppei Kamijou /* Abort DMA */ 1186eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1187eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1188eae30983STeppei Kamijou else 1189eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1190eae30983STeppei Kamijou } 1191f985da17SGuennadi Liakhovetski 1192f985da17SGuennadi Liakhovetski return false; 1193f985da17SGuennadi Liakhovetski } 1194f985da17SGuennadi Liakhovetski 1195f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1196f985da17SGuennadi Liakhovetski { 1197f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 11988047310eSGuennadi Liakhovetski struct mmc_request *mrq; 1199585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 12005df460b1SGuennadi Liakhovetski bool wait = false; 1201dbb42d96SKouichi Tomita unsigned long flags; 1202dbb42d96SKouichi Tomita int wait_work; 1203dbb42d96SKouichi Tomita 1204dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 1205dbb42d96SKouichi Tomita wait_work = host->wait_for; 1206dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 1207f985da17SGuennadi Liakhovetski 1208f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1209f985da17SGuennadi Liakhovetski 12108047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 12118047310eSGuennadi Liakhovetski 12128047310eSGuennadi Liakhovetski mrq = host->mrq; 12138047310eSGuennadi Liakhovetski if (!mrq) { 1214585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 12158047310eSGuennadi Liakhovetski host->state, host->wait_for); 12168047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12178047310eSGuennadi Liakhovetski return IRQ_HANDLED; 12188047310eSGuennadi Liakhovetski } 12198047310eSGuennadi Liakhovetski 1220f985da17SGuennadi Liakhovetski /* 1221f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1222f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1223f985da17SGuennadi Liakhovetski */ 1224dbb42d96SKouichi Tomita switch (wait_work) { 1225f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1226f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 12278047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1228f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1229f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 12305df460b1SGuennadi Liakhovetski /* Wait for data? */ 12315df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1232f985da17SGuennadi Liakhovetski break; 1233f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 12345df460b1SGuennadi Liakhovetski /* Wait for more data? */ 12355df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1236f985da17SGuennadi Liakhovetski break; 1237f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 12385df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12395df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1240f985da17SGuennadi Liakhovetski break; 1241f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 12425df460b1SGuennadi Liakhovetski /* Wait data to write? */ 12435df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1244f985da17SGuennadi Liakhovetski break; 1245f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 12465df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12475df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1248f985da17SGuennadi Liakhovetski break; 1249f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1250f985da17SGuennadi Liakhovetski if (host->sd_error) { 1251f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1252585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); 1253f985da17SGuennadi Liakhovetski break; 1254f985da17SGuennadi Liakhovetski } 1255f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1256f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1257f985da17SGuennadi Liakhovetski break; 1258f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1259f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1260e475b270STeppei Kamijou if (host->sd_error) { 126191ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1262585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); 1263e475b270STeppei Kamijou } 1264f985da17SGuennadi Liakhovetski break; 1265f985da17SGuennadi Liakhovetski default: 1266f985da17SGuennadi Liakhovetski BUG(); 1267f985da17SGuennadi Liakhovetski } 1268f985da17SGuennadi Liakhovetski 12695df460b1SGuennadi Liakhovetski if (wait) { 12705df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12715df460b1SGuennadi Liakhovetski /* Wait for more data */ 12728047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12735df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 12745df460b1SGuennadi Liakhovetski } 12755df460b1SGuennadi Liakhovetski 1276f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 127791ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 127869983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 127969983404SGuennadi Liakhovetski data->bytes_xfered = 128069983404SGuennadi Liakhovetski data->blocks * data->blksz; 1281f985da17SGuennadi Liakhovetski 128269983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1283f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 12845df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 12855df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 12868047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1287f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1288f985da17SGuennadi Liakhovetski } 1289f985da17SGuennadi Liakhovetski } 12905df460b1SGuennadi Liakhovetski } 1291f985da17SGuennadi Liakhovetski 1292f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1293f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 129469983404SGuennadi Liakhovetski host->mrq = NULL; 1295f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1296f985da17SGuennadi Liakhovetski 12978047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12988047310eSGuennadi Liakhovetski 1299f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1300f985da17SGuennadi Liakhovetski } 1301f985da17SGuennadi Liakhovetski 1302fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1303fdc50a94SYusuke Goda { 1304fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1305585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1306967bcb77SGuennadi Liakhovetski u32 state, mask; 1307fdc50a94SYusuke Goda 1308487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1309967bcb77SGuennadi Liakhovetski mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1310967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 1311967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1312967bcb77SGuennadi Liakhovetski else 1313967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 13148af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1315fdc50a94SYusuke Goda 13168af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN) 1317585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", 13188af50750SGuennadi Liakhovetski state); 13198af50750SGuennadi Liakhovetski 13208af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) { 1321aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1322585c3a5aSKuninori Morimoto dev_dbg(dev, "int err state = 0x%08x\n", state); 1323fdc50a94SYusuke Goda } 1324f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 13258af50750SGuennadi Liakhovetski if (!host->mrq) 1326585c3a5aSKuninori Morimoto dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); 1327f985da17SGuennadi Liakhovetski if (!host->dma_active) 1328f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1329f985da17SGuennadi Liakhovetski else if (host->sd_error) 1330f985da17SGuennadi Liakhovetski mmcif_dma_complete(host); 1331f985da17SGuennadi Liakhovetski } else { 1332585c3a5aSKuninori Morimoto dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); 1333f985da17SGuennadi Liakhovetski } 1334fdc50a94SYusuke Goda 1335fdc50a94SYusuke Goda return IRQ_HANDLED; 1336fdc50a94SYusuke Goda } 1337fdc50a94SYusuke Goda 1338f985da17SGuennadi Liakhovetski static void mmcif_timeout_work(struct work_struct *work) 1339f985da17SGuennadi Liakhovetski { 1340f985da17SGuennadi Liakhovetski struct delayed_work *d = container_of(work, struct delayed_work, work); 1341f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1342f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 1343585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 13448047310eSGuennadi Liakhovetski unsigned long flags; 1345f985da17SGuennadi Liakhovetski 1346f985da17SGuennadi Liakhovetski if (host->dying) 1347f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1348f985da17SGuennadi Liakhovetski return; 1349f985da17SGuennadi Liakhovetski 13508047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 13518047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 13528047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13538047310eSGuennadi Liakhovetski return; 13548047310eSGuennadi Liakhovetski } 13558047310eSGuennadi Liakhovetski 1356585c3a5aSKuninori Morimoto dev_err(dev, "Timeout waiting for %u on CMD%u\n", 13574cbd5224SKouichi Tomita host->wait_for, mrq->cmd->opcode); 13584cbd5224SKouichi Tomita 13598047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 13608047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 13618047310eSGuennadi Liakhovetski 1362f985da17SGuennadi Liakhovetski /* 1363f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1364f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1365f985da17SGuennadi Liakhovetski */ 1366f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1367f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1368f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1369f985da17SGuennadi Liakhovetski break; 1370f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1371f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1372f985da17SGuennadi Liakhovetski break; 1373f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1374f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1375f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1376f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1377f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1378f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 137969983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1380f985da17SGuennadi Liakhovetski break; 1381f985da17SGuennadi Liakhovetski default: 1382f985da17SGuennadi Liakhovetski BUG(); 1383f985da17SGuennadi Liakhovetski } 1384f985da17SGuennadi Liakhovetski 1385f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1386f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1387f985da17SGuennadi Liakhovetski host->mrq = NULL; 1388f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1389f985da17SGuennadi Liakhovetski } 1390f985da17SGuennadi Liakhovetski 13917d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 13927d17baa0SGuennadi Liakhovetski { 1393585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1394585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 13957d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 13967d17baa0SGuennadi Liakhovetski 13977d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 13987d17baa0SGuennadi Liakhovetski 1399bf68a812SGuennadi Liakhovetski if (!pd) 1400bf68a812SGuennadi Liakhovetski return; 1401bf68a812SGuennadi Liakhovetski 14027d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 14037d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 14047d17baa0SGuennadi Liakhovetski else if (pd->ocr) 14057d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 14067d17baa0SGuennadi Liakhovetski } 14077d17baa0SGuennadi Liakhovetski 1408c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1409fdc50a94SYusuke Goda { 1410fdc50a94SYusuke Goda int ret = 0, irq[2]; 1411fdc50a94SYusuke Goda struct mmc_host *mmc; 1412e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 141360985c39SKuninori Morimoto struct device *dev = &pdev->dev; 141460985c39SKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 1415fdc50a94SYusuke Goda struct resource *res; 1416fdc50a94SYusuke Goda void __iomem *reg; 14172cd5b3e0SShinya Kuribayashi const char *name; 1418fdc50a94SYusuke Goda 1419fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1420fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 14212cd5b3e0SShinya Kuribayashi if (irq[0] < 0) { 142260985c39SKuninori Morimoto dev_err(dev, "Get irq error\n"); 1423fdc50a94SYusuke Goda return -ENXIO; 1424fdc50a94SYusuke Goda } 142518f55fccSBen Dooks 1426fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 142760985c39SKuninori Morimoto reg = devm_ioremap_resource(dev, res); 142818f55fccSBen Dooks if (IS_ERR(reg)) 142918f55fccSBen Dooks return PTR_ERR(reg); 1430e1aae2ebSGuennadi Liakhovetski 143160985c39SKuninori Morimoto mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 143218f55fccSBen Dooks if (!mmc) 143318f55fccSBen Dooks return -ENOMEM; 14342c9054dcSSimon Baatz 14352c9054dcSSimon Baatz ret = mmc_of_parse(mmc); 14362c9054dcSSimon Baatz if (ret < 0) 143746991005SBen Dooks goto err_host; 14382c9054dcSSimon Baatz 1439fdc50a94SYusuke Goda host = mmc_priv(mmc); 1440fdc50a94SYusuke Goda host->mmc = mmc; 1441fdc50a94SYusuke Goda host->addr = reg; 1442bad4371dSTakeshi Kihara host->timeout = msecs_to_jiffies(10000); 1443967bcb77SGuennadi Liakhovetski host->ccs_enable = !pd || !pd->ccs_unsupported; 14446d6fd367SGuennadi Liakhovetski host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; 1445fdc50a94SYusuke Goda 1446fdc50a94SYusuke Goda host->pd = pdev; 1447fdc50a94SYusuke Goda 14483b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1449fdc50a94SYusuke Goda 1450fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 14517d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 14527d17baa0SGuennadi Liakhovetski 1453eca889f6SGuennadi Liakhovetski mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1454bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1455fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1456a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1457fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1458a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1459a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1460fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1461fdc50a94SYusuke Goda 1462fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1463a782d688SGuennadi Liakhovetski 146460985c39SKuninori Morimoto pm_runtime_enable(dev); 1465faca6648SGuennadi Liakhovetski host->power = false; 1466faca6648SGuennadi Liakhovetski 14676aed678bSKuninori Morimoto host->clk = devm_clk_get(dev, NULL); 14686aed678bSKuninori Morimoto if (IS_ERR(host->clk)) { 14696aed678bSKuninori Morimoto ret = PTR_ERR(host->clk); 147060985c39SKuninori Morimoto dev_err(dev, "cannot get clock: %d\n", ret); 147146991005SBen Dooks goto err_pm; 1472b289174fSGuennadi Liakhovetski } 14739bb09a30SKuninori Morimoto 14749bb09a30SKuninori Morimoto ret = clk_prepare_enable(host->clk); 1475a6609267SGuennadi Liakhovetski if (ret < 0) 147646991005SBen Dooks goto err_pm; 1477b289174fSGuennadi Liakhovetski 14789bb09a30SKuninori Morimoto sh_mmcif_clk_setup(host); 14799bb09a30SKuninori Morimoto 148060985c39SKuninori Morimoto ret = pm_runtime_resume(dev); 1481faca6648SGuennadi Liakhovetski if (ret < 0) 148246991005SBen Dooks goto err_clk; 1483a782d688SGuennadi Liakhovetski 14845ba85d95SGuennadi Liakhovetski INIT_DELAYED_WORK(&host->timeout_work, mmcif_timeout_work); 1485fdc50a94SYusuke Goda 1486b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 14873b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 14883b0beafcSGuennadi Liakhovetski 148960985c39SKuninori Morimoto name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; 149060985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, 14916f4789e6SBen Dooks sh_mmcif_irqt, 0, name, host); 1492fdc50a94SYusuke Goda if (ret) { 149360985c39SKuninori Morimoto dev_err(dev, "request_irq error (%s)\n", name); 149411a80852SBen Dooks goto err_clk; 1495fdc50a94SYusuke Goda } 14962cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 149760985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[1], 14986f4789e6SBen Dooks sh_mmcif_intr, sh_mmcif_irqt, 14992cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1500fdc50a94SYusuke Goda if (ret) { 150160985c39SKuninori Morimoto dev_err(dev, "request_irq error (sh_mmc:int)\n"); 150211a80852SBen Dooks goto err_clk; 1503fdc50a94SYusuke Goda } 15042cd5b3e0SShinya Kuribayashi } 1505fdc50a94SYusuke Goda 1506e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1507214fc309SLaurent Pinchart ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); 1508e480606aSGuennadi Liakhovetski if (ret < 0) 15097f67f3a2SBen Dooks goto err_clk; 1510e480606aSGuennadi Liakhovetski } 1511e480606aSGuennadi Liakhovetski 15128047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 15138047310eSGuennadi Liakhovetski 15145ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 15155ba85d95SGuennadi Liakhovetski if (ret < 0) 15167f67f3a2SBen Dooks goto err_clk; 1517fdc50a94SYusuke Goda 151860985c39SKuninori Morimoto dev_pm_qos_expose_latency_limit(dev, 100); 1519efe6a8adSRafael J. Wysocki 152060985c39SKuninori Morimoto dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", 1521ce7eb688SBen Dooks sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 15226aed678bSKuninori Morimoto clk_get_rate(host->clk) / 1000000UL); 1523ce7eb688SBen Dooks 15246aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1525fdc50a94SYusuke Goda return ret; 1526fdc50a94SYusuke Goda 152746991005SBen Dooks err_clk: 15286aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 152946991005SBen Dooks err_pm: 153060985c39SKuninori Morimoto pm_runtime_disable(dev); 153146991005SBen Dooks err_host: 1532fdc50a94SYusuke Goda mmc_free_host(mmc); 1533fdc50a94SYusuke Goda return ret; 1534fdc50a94SYusuke Goda } 1535fdc50a94SYusuke Goda 15366e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1537fdc50a94SYusuke Goda { 1538fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1539fdc50a94SYusuke Goda 1540f985da17SGuennadi Liakhovetski host->dying = true; 15416aed678bSKuninori Morimoto clk_prepare_enable(host->clk); 1542faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1543aa0787a9SGuennadi Liakhovetski 1544efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1545efe6a8adSRafael J. Wysocki 1546faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 15473b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15483b0beafcSGuennadi Liakhovetski 1549f985da17SGuennadi Liakhovetski /* 1550f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1551f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1552f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1553f985da17SGuennadi Liakhovetski */ 1554f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1555f985da17SGuennadi Liakhovetski 15566aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1557fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1558faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1559faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1560fdc50a94SYusuke Goda 1561fdc50a94SYusuke Goda return 0; 1562fdc50a94SYusuke Goda } 1563fdc50a94SYusuke Goda 156451129f31SUlf Hansson #ifdef CONFIG_PM_SLEEP 1565faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1566faca6648SGuennadi Liakhovetski { 1567b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1568faca6648SGuennadi Liakhovetski 1569faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1570faca6648SGuennadi Liakhovetski 1571cb3ca1aeSUlf Hansson return 0; 1572faca6648SGuennadi Liakhovetski } 1573faca6648SGuennadi Liakhovetski 1574faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1575faca6648SGuennadi Liakhovetski { 1576cb3ca1aeSUlf Hansson return 0; 1577faca6648SGuennadi Liakhovetski } 157851129f31SUlf Hansson #endif 1579faca6648SGuennadi Liakhovetski 1580faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 158151129f31SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1582faca6648SGuennadi Liakhovetski }; 1583faca6648SGuennadi Liakhovetski 1584fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1585fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1586fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1587fdc50a94SYusuke Goda .driver = { 1588fdc50a94SYusuke Goda .name = DRIVER_NAME, 1589faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1590bf68a812SGuennadi Liakhovetski .of_match_table = mmcif_of_match, 1591fdc50a94SYusuke Goda }, 1592fdc50a94SYusuke Goda }; 1593fdc50a94SYusuke Goda 1594d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1595fdc50a94SYusuke Goda 1596fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1597fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1598aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1599fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1600