1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19f985da17SGuennadi Liakhovetski /* 20f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according 21f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement. 22f985da17SGuennadi Liakhovetski * 23f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional 24f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these 25f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half 26f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion 27f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns 28f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously. 29f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves. 30f985da17SGuennadi Liakhovetski * 31f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler 32f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and 33f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods. 34f985da17SGuennadi Liakhovetski * 35f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback 36f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful 37f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is 38f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read 39f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next 40f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and 41f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the 42f985da17SGuennadi Liakhovetski * bottom half waiting state. 43f985da17SGuennadi Liakhovetski */ 44f985da17SGuennadi Liakhovetski 4586df1745SGuennadi Liakhovetski #include <linux/bitops.h> 46aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 47aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 48e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 49fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 50a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 51fdc50a94SYusuke Goda #include <linux/mmc/card.h> 52fdc50a94SYusuke Goda #include <linux/mmc/core.h> 53e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 54fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 55fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 56fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 57e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h> 58bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h> 598047310eSGuennadi Liakhovetski #include <linux/mutex.h> 6089d49a70SKuninori Morimoto #include <linux/of_device.h> 61a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 62e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 63efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h> 64faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 65d00cadacSGuennadi Liakhovetski #include <linux/sh_dma.h> 663b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 6788b47679SPaul Gortmaker #include <linux/module.h> 68fdc50a94SYusuke Goda 69fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 70fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 71fdc50a94SYusuke Goda 72fdc50a94SYusuke Goda /* CE_CMD_SET */ 73fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 74fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 75fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 76fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 77fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 78fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 79fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 80fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 81fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 82fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 83fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 84fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 85fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 86fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 87fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 88fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 89fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 90fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 91fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 92fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 93fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 94555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */ 95fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 96fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 97fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 98fdc50a94SYusuke Goda 99fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 100fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 101fdc50a94SYusuke Goda 102fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 103fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 104fdc50a94SYusuke Goda 105fdc50a94SYusuke Goda /* CE_INT */ 106fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 107fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 108fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 109fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 110fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 111fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 112fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 113fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 114fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 115fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 116fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 117fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 118fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 119fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 120fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 121fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 122fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 123fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 124fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 125fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 126fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 127fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 128fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 129fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 130fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 131fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 132fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 133fdc50a94SYusuke Goda 1348af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \ 1358af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \ 1368af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE) 1378af50750SGuennadi Liakhovetski 138967bcb77SGuennadi Liakhovetski #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE) 139967bcb77SGuennadi Liakhovetski 140fdc50a94SYusuke Goda /* CE_INT_MASK */ 141fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 142fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 143fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 144fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 145fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 146fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 147fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 148fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 149fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 150fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 151fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 152fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 153fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 154fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 155fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 156fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 157fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 158fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 159fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 160fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 161fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 162fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 163fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 164fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 165fdc50a94SYusuke Goda 166ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \ 167ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \ 168967bcb77SGuennadi Liakhovetski MASK_MCRCSTO | MASK_MWDATTO | \ 169ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO) 170ee4b8887SGuennadi Liakhovetski 1718af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \ 1728af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \ 1738af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \ 1748af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE) 1758af50750SGuennadi Liakhovetski 176fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 177fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 178fdc50a94SYusuke Goda 179fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 180fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 181fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 182fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 183fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 184fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 185fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 186fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 187fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 188fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 189fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 190fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 191fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 192fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 193fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 194fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 195fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 196fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 197fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 198fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 199fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 200fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 201fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 202fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 203fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 204fdc50a94SYusuke Goda 205fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 206fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 207fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 208fdc50a94SYusuke Goda 2091b1a694dSKuninori Morimoto enum sh_mmcif_state { 2103b0beafcSGuennadi Liakhovetski STATE_IDLE, 2113b0beafcSGuennadi Liakhovetski STATE_REQUEST, 2123b0beafcSGuennadi Liakhovetski STATE_IOS, 2138047310eSGuennadi Liakhovetski STATE_TIMEOUT, 2143b0beafcSGuennadi Liakhovetski }; 2153b0beafcSGuennadi Liakhovetski 2161b1a694dSKuninori Morimoto enum sh_mmcif_wait_for { 217f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST, 218f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD, 219f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD, 220f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE, 221f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ, 222f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE, 223f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END, 224f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END, 225f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP, 226f985da17SGuennadi Liakhovetski }; 227f985da17SGuennadi Liakhovetski 22889d49a70SKuninori Morimoto /* 22989d49a70SKuninori Morimoto * difference for each SoC 23089d49a70SKuninori Morimoto */ 231fdc50a94SYusuke Goda struct sh_mmcif_host { 232fdc50a94SYusuke Goda struct mmc_host *mmc; 233f985da17SGuennadi Liakhovetski struct mmc_request *mrq; 234fdc50a94SYusuke Goda struct platform_device *pd; 2356aed678bSKuninori Morimoto struct clk *clk; 236fdc50a94SYusuke Goda int bus_width; 237555061f9STeppei Kamijou unsigned char timing; 238aa0787a9SGuennadi Liakhovetski bool sd_error; 239f985da17SGuennadi Liakhovetski bool dying; 240fdc50a94SYusuke Goda long timeout; 241fdc50a94SYusuke Goda void __iomem *addr; 242f985da17SGuennadi Liakhovetski u32 *pio_ptr; 243ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */ 2441b1a694dSKuninori Morimoto enum sh_mmcif_state state; 2451b1a694dSKuninori Morimoto enum sh_mmcif_wait_for wait_for; 246f985da17SGuennadi Liakhovetski struct delayed_work timeout_work; 247f985da17SGuennadi Liakhovetski size_t blocksize; 248f985da17SGuennadi Liakhovetski int sg_idx; 249f985da17SGuennadi Liakhovetski int sg_blkidx; 250faca6648SGuennadi Liakhovetski bool power; 251c9b0cef2SGuennadi Liakhovetski bool card_present; 252967bcb77SGuennadi Liakhovetski bool ccs_enable; /* Command Completion Signal support */ 2536d6fd367SGuennadi Liakhovetski bool clk_ctrl2_enable; 2548047310eSGuennadi Liakhovetski struct mutex thread_lock; 25589d49a70SKuninori Morimoto u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */ 256fdc50a94SYusuke Goda 257a782d688SGuennadi Liakhovetski /* DMA support */ 258a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 259a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 260a782d688SGuennadi Liakhovetski struct completion dma_complete; 261f38f94c6SLinus Walleij bool dma_active; 262a782d688SGuennadi Liakhovetski }; 263fdc50a94SYusuke Goda 2641b1a694dSKuninori Morimoto static const struct of_device_id sh_mmcif_of_match[] = { 26570830b41SKuninori Morimoto { .compatible = "renesas,sh-mmcif" }, 26670830b41SKuninori Morimoto { } 26770830b41SKuninori Morimoto }; 2681b1a694dSKuninori Morimoto MODULE_DEVICE_TABLE(of, sh_mmcif_of_match); 26970830b41SKuninori Morimoto 270585c3a5aSKuninori Morimoto #define sh_mmcif_host_to_dev(host) (&host->pd->dev) 271585c3a5aSKuninori Morimoto 272fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 273fdc50a94SYusuke Goda unsigned int reg, u32 val) 274fdc50a94SYusuke Goda { 275487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 276fdc50a94SYusuke Goda } 277fdc50a94SYusuke Goda 278fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 279fdc50a94SYusuke Goda unsigned int reg, u32 val) 280fdc50a94SYusuke Goda { 281487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 282fdc50a94SYusuke Goda } 283fdc50a94SYusuke Goda 2841b1a694dSKuninori Morimoto static void sh_mmcif_dma_complete(void *arg) 285a782d688SGuennadi Liakhovetski { 286a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 2878047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 288585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 28969983404SGuennadi Liakhovetski 290585c3a5aSKuninori Morimoto dev_dbg(dev, "Command completed\n"); 291a782d688SGuennadi Liakhovetski 2928047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n", 293585c3a5aSKuninori Morimoto dev_name(dev))) 294a782d688SGuennadi Liakhovetski return; 295a782d688SGuennadi Liakhovetski 296a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 297a782d688SGuennadi Liakhovetski } 298a782d688SGuennadi Liakhovetski 299a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 300a782d688SGuennadi Liakhovetski { 30169983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 30269983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 303a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 304a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 305585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 306a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 307a782d688SGuennadi Liakhovetski int ret; 308a782d688SGuennadi Liakhovetski 30969983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3101ed828dbSLinus Walleij DMA_FROM_DEVICE); 311a782d688SGuennadi Liakhovetski if (ret > 0) { 312f38f94c6SLinus Walleij host->dma_active = true; 31316052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 31405f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 315a782d688SGuennadi Liakhovetski } 316a782d688SGuennadi Liakhovetski 317a782d688SGuennadi Liakhovetski if (desc) { 3181b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete; 319a782d688SGuennadi Liakhovetski desc->callback_param = host; 320a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 321a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 322a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 323a782d688SGuennadi Liakhovetski } 324585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 32569983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 326a782d688SGuennadi Liakhovetski 327a782d688SGuennadi Liakhovetski if (!desc) { 328a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 329a782d688SGuennadi Liakhovetski if (ret >= 0) 330a782d688SGuennadi Liakhovetski ret = -EIO; 331a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 332f38f94c6SLinus Walleij host->dma_active = false; 333a782d688SGuennadi Liakhovetski dma_release_channel(chan); 334a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 335a782d688SGuennadi Liakhovetski chan = host->chan_tx; 336a782d688SGuennadi Liakhovetski if (chan) { 337a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 338a782d688SGuennadi Liakhovetski dma_release_channel(chan); 339a782d688SGuennadi Liakhovetski } 340585c3a5aSKuninori Morimoto dev_warn(dev, 341a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 342a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 343a782d688SGuennadi Liakhovetski } 344a782d688SGuennadi Liakhovetski 345585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 34669983404SGuennadi Liakhovetski desc, cookie, data->sg_len); 347a782d688SGuennadi Liakhovetski } 348a782d688SGuennadi Liakhovetski 349a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 350a782d688SGuennadi Liakhovetski { 35169983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 35269983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg; 353a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 354a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 355585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 356a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 357a782d688SGuennadi Liakhovetski int ret; 358a782d688SGuennadi Liakhovetski 35969983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len, 3601ed828dbSLinus Walleij DMA_TO_DEVICE); 361a782d688SGuennadi Liakhovetski if (ret > 0) { 362f38f94c6SLinus Walleij host->dma_active = true; 36316052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret, 36405f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 365a782d688SGuennadi Liakhovetski } 366a782d688SGuennadi Liakhovetski 367a782d688SGuennadi Liakhovetski if (desc) { 3681b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete; 369a782d688SGuennadi Liakhovetski desc->callback_param = host; 370a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 371a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 372a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 373a782d688SGuennadi Liakhovetski } 374585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n", 37569983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie); 376a782d688SGuennadi Liakhovetski 377a782d688SGuennadi Liakhovetski if (!desc) { 378a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 379a782d688SGuennadi Liakhovetski if (ret >= 0) 380a782d688SGuennadi Liakhovetski ret = -EIO; 381a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 382f38f94c6SLinus Walleij host->dma_active = false; 383a782d688SGuennadi Liakhovetski dma_release_channel(chan); 384a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 385a782d688SGuennadi Liakhovetski chan = host->chan_rx; 386a782d688SGuennadi Liakhovetski if (chan) { 387a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 388a782d688SGuennadi Liakhovetski dma_release_channel(chan); 389a782d688SGuennadi Liakhovetski } 390585c3a5aSKuninori Morimoto dev_warn(dev, 391a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 392a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 393a782d688SGuennadi Liakhovetski } 394a782d688SGuennadi Liakhovetski 395585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__, 396a782d688SGuennadi Liakhovetski desc, cookie); 397a782d688SGuennadi Liakhovetski } 398a782d688SGuennadi Liakhovetski 399e5a233cbSLaurent Pinchart static struct dma_chan * 40027cbd7e8SArnd Bergmann sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id) 401a782d688SGuennadi Liakhovetski { 4020e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask; 4030e79f9aeSGuennadi Liakhovetski 404e5a233cbSLaurent Pinchart dma_cap_zero(mask); 405e5a233cbSLaurent Pinchart dma_cap_set(DMA_SLAVE, mask); 40627cbd7e8SArnd Bergmann if (slave_id <= 0) 407e5a233cbSLaurent Pinchart return NULL; 408e5a233cbSLaurent Pinchart 40927cbd7e8SArnd Bergmann return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id); 41027cbd7e8SArnd Bergmann } 411e5a233cbSLaurent Pinchart 41227cbd7e8SArnd Bergmann static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host, 41327cbd7e8SArnd Bergmann struct dma_chan *chan, 41427cbd7e8SArnd Bergmann enum dma_transfer_direction direction) 41527cbd7e8SArnd Bergmann { 41627cbd7e8SArnd Bergmann struct resource *res; 41727cbd7e8SArnd Bergmann struct dma_slave_config cfg = { 0, }; 41827cbd7e8SArnd Bergmann 41927cbd7e8SArnd Bergmann res = platform_get_resource(host->pd, IORESOURCE_MEM, 0); 420e5a233cbSLaurent Pinchart cfg.direction = direction; 421d25006e7SLaurent Pinchart 422e36152aaSLaurent Pinchart if (direction == DMA_DEV_TO_MEM) { 423d25006e7SLaurent Pinchart cfg.src_addr = res->start + MMCIF_CE_DATA; 424e36152aaSLaurent Pinchart cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 425e36152aaSLaurent Pinchart } else { 426e5a233cbSLaurent Pinchart cfg.dst_addr = res->start + MMCIF_CE_DATA; 427e36152aaSLaurent Pinchart cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES; 428e36152aaSLaurent Pinchart } 429d25006e7SLaurent Pinchart 43027cbd7e8SArnd Bergmann return dmaengine_slave_config(chan, &cfg); 431e5a233cbSLaurent Pinchart } 432e5a233cbSLaurent Pinchart 43327cbd7e8SArnd Bergmann static void sh_mmcif_request_dma(struct sh_mmcif_host *host) 434e5a233cbSLaurent Pinchart { 435585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 436f38f94c6SLinus Walleij host->dma_active = false; 437a782d688SGuennadi Liakhovetski 438a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 43927cbd7e8SArnd Bergmann if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) { 44027cbd7e8SArnd Bergmann struct sh_mmcif_plat_data *pdata = dev->platform_data; 44127cbd7e8SArnd Bergmann 44227cbd7e8SArnd Bergmann host->chan_tx = sh_mmcif_request_dma_pdata(host, 44327cbd7e8SArnd Bergmann pdata->slave_id_tx); 44427cbd7e8SArnd Bergmann host->chan_rx = sh_mmcif_request_dma_pdata(host, 44527cbd7e8SArnd Bergmann pdata->slave_id_rx); 44627cbd7e8SArnd Bergmann } else { 44727cbd7e8SArnd Bergmann host->chan_tx = dma_request_slave_channel(dev, "tx"); 448a32ef81cSChris Paterson host->chan_rx = dma_request_slave_channel(dev, "rx"); 44927cbd7e8SArnd Bergmann } 45027cbd7e8SArnd Bergmann dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx, 45127cbd7e8SArnd Bergmann host->chan_rx); 45227cbd7e8SArnd Bergmann 45327cbd7e8SArnd Bergmann if (!host->chan_tx || !host->chan_rx || 45427cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) || 45527cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM)) 45627cbd7e8SArnd Bergmann goto error; 45727cbd7e8SArnd Bergmann 458a782d688SGuennadi Liakhovetski return; 459a782d688SGuennadi Liakhovetski 46027cbd7e8SArnd Bergmann error: 46127cbd7e8SArnd Bergmann if (host->chan_tx) 4620e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx); 46327cbd7e8SArnd Bergmann if (host->chan_rx) 46427cbd7e8SArnd Bergmann dma_release_channel(host->chan_rx); 46527cbd7e8SArnd Bergmann host->chan_tx = host->chan_rx = NULL; 466e5a233cbSLaurent Pinchart } 467a782d688SGuennadi Liakhovetski 468a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 469a782d688SGuennadi Liakhovetski { 470a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 471a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 472a782d688SGuennadi Liakhovetski if (host->chan_tx) { 473a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 474a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 475a782d688SGuennadi Liakhovetski dma_release_channel(chan); 476a782d688SGuennadi Liakhovetski } 477a782d688SGuennadi Liakhovetski if (host->chan_rx) { 478a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 479a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 480a782d688SGuennadi Liakhovetski dma_release_channel(chan); 481a782d688SGuennadi Liakhovetski } 482a782d688SGuennadi Liakhovetski 483f38f94c6SLinus Walleij host->dma_active = false; 484a782d688SGuennadi Liakhovetski } 485fdc50a94SYusuke Goda 486fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 487fdc50a94SYusuke Goda { 488585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 489585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *p = dev->platform_data; 490bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false; 4916aed678bSKuninori Morimoto unsigned int current_clk = clk_get_rate(host->clk); 49289d49a70SKuninori Morimoto unsigned int clkdiv; 493fdc50a94SYusuke Goda 494fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 495fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 496fdc50a94SYusuke Goda 497fdc50a94SYusuke Goda if (!clk) 498fdc50a94SYusuke Goda return; 499fdc50a94SYusuke Goda 50089d49a70SKuninori Morimoto if (host->clkdiv_map) { 50189d49a70SKuninori Morimoto unsigned int freq, best_freq, myclk, div, diff_min, diff; 50289d49a70SKuninori Morimoto int i; 50389d49a70SKuninori Morimoto 50489d49a70SKuninori Morimoto clkdiv = 0; 50589d49a70SKuninori Morimoto diff_min = ~0; 50689d49a70SKuninori Morimoto best_freq = 0; 50789d49a70SKuninori Morimoto for (i = 31; i >= 0; i--) { 50889d49a70SKuninori Morimoto if (!((1 << i) & host->clkdiv_map)) 50989d49a70SKuninori Morimoto continue; 51089d49a70SKuninori Morimoto 51189d49a70SKuninori Morimoto /* 51289d49a70SKuninori Morimoto * clk = parent_freq / div 51389d49a70SKuninori Morimoto * -> parent_freq = clk x div 51489d49a70SKuninori Morimoto */ 51589d49a70SKuninori Morimoto 51689d49a70SKuninori Morimoto div = 1 << (i + 1); 51789d49a70SKuninori Morimoto freq = clk_round_rate(host->clk, clk * div); 51889d49a70SKuninori Morimoto myclk = freq / div; 51989d49a70SKuninori Morimoto diff = (myclk > clk) ? myclk - clk : clk - myclk; 52089d49a70SKuninori Morimoto 52189d49a70SKuninori Morimoto if (diff <= diff_min) { 52289d49a70SKuninori Morimoto best_freq = freq; 52389d49a70SKuninori Morimoto clkdiv = i; 52489d49a70SKuninori Morimoto diff_min = diff; 52589d49a70SKuninori Morimoto } 52689d49a70SKuninori Morimoto } 52789d49a70SKuninori Morimoto 52889d49a70SKuninori Morimoto dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n", 52989d49a70SKuninori Morimoto (best_freq / (1 << (clkdiv + 1))), clk, 53089d49a70SKuninori Morimoto best_freq, clkdiv); 53189d49a70SKuninori Morimoto 53289d49a70SKuninori Morimoto clk_set_rate(host->clk, best_freq); 53389d49a70SKuninori Morimoto clkdiv = clkdiv << 16; 53489d49a70SKuninori Morimoto } else if (sup_pclk && clk == current_clk) { 53589d49a70SKuninori Morimoto clkdiv = CLK_SUP_PCLK; 53689d49a70SKuninori Morimoto } else { 53789d49a70SKuninori Morimoto clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16; 53889d49a70SKuninori Morimoto } 53989d49a70SKuninori Morimoto 54089d49a70SKuninori Morimoto sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv); 541fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 542fdc50a94SYusuke Goda } 543fdc50a94SYusuke Goda 544fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 545fdc50a94SYusuke Goda { 546fdc50a94SYusuke Goda u32 tmp; 547fdc50a94SYusuke Goda 548487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 549fdc50a94SYusuke Goda 550487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 551487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 552967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 553967bcb77SGuennadi Liakhovetski tmp |= SCCSTO_29; 5546d6fd367SGuennadi Liakhovetski if (host->clk_ctrl2_enable) 5556d6fd367SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000); 556fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 557967bcb77SGuennadi Liakhovetski SRSPTO_256 | SRBSYTO_29 | SRWDTO_29); 558fdc50a94SYusuke Goda /* byte swap on */ 559fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 560fdc50a94SYusuke Goda } 561fdc50a94SYusuke Goda 562fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 563fdc50a94SYusuke Goda { 564585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 565fdc50a94SYusuke Goda u32 state1, state2; 566ee4b8887SGuennadi Liakhovetski int ret, timeout; 567fdc50a94SYusuke Goda 568aa0787a9SGuennadi Liakhovetski host->sd_error = false; 569fdc50a94SYusuke Goda 570487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 571487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 572585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1); 573585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2); 574fdc50a94SYusuke Goda 575fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 576fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 577fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 578ee4b8887SGuennadi Liakhovetski for (timeout = 10000000; timeout; timeout--) { 579487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 580fdc50a94SYusuke Goda & STS1_CMDSEQ)) 581fdc50a94SYusuke Goda break; 582fdc50a94SYusuke Goda mdelay(1); 583fdc50a94SYusuke Goda } 584ee4b8887SGuennadi Liakhovetski if (!timeout) { 585585c3a5aSKuninori Morimoto dev_err(dev, 586ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n"); 587ee4b8887SGuennadi Liakhovetski return -EIO; 588ee4b8887SGuennadi Liakhovetski } 589fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 590585c3a5aSKuninori Morimoto dev_dbg(dev, "Forced end of command sequence\n"); 591fdc50a94SYusuke Goda return -EIO; 592fdc50a94SYusuke Goda } 593fdc50a94SYusuke Goda 594fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 595585c3a5aSKuninori Morimoto dev_err(dev, " CRC error: state %u, wait %u\n", 596e475b270STeppei Kamijou host->state, host->wait_for); 597fdc50a94SYusuke Goda ret = -EIO; 598fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 599585c3a5aSKuninori Morimoto dev_err(dev, " Timeout: state %u, wait %u\n", 600e475b270STeppei Kamijou host->state, host->wait_for); 601fdc50a94SYusuke Goda ret = -ETIMEDOUT; 602fdc50a94SYusuke Goda } else { 603585c3a5aSKuninori Morimoto dev_dbg(dev, " End/Index error: state %u, wait %u\n", 604e475b270STeppei Kamijou host->state, host->wait_for); 605fdc50a94SYusuke Goda ret = -EIO; 606fdc50a94SYusuke Goda } 607fdc50a94SYusuke Goda return ret; 608fdc50a94SYusuke Goda } 609fdc50a94SYusuke Goda 610f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p) 611f985da17SGuennadi Liakhovetski { 612f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 613f985da17SGuennadi Liakhovetski 614f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize; 615f985da17SGuennadi Liakhovetski 616f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */ 617f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length); 618f985da17SGuennadi Liakhovetski 619f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) { 620f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 621f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len) 622f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg); 623f985da17SGuennadi Liakhovetski } else { 624f985da17SGuennadi Liakhovetski host->pio_ptr = p; 625f985da17SGuennadi Liakhovetski } 626f985da17SGuennadi Liakhovetski 62799eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len; 628f985da17SGuennadi Liakhovetski } 629f985da17SGuennadi Liakhovetski 630f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host, 631fdc50a94SYusuke Goda struct mmc_request *mrq) 632fdc50a94SYusuke Goda { 633f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 634f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 635f985da17SGuennadi Liakhovetski 636f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ; 637fdc50a94SYusuke Goda 638fdc50a94SYusuke Goda /* buf read enable */ 639fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 640f985da17SGuennadi Liakhovetski } 641fdc50a94SYusuke Goda 642f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host) 643f985da17SGuennadi Liakhovetski { 644585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 645f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 646f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 647f985da17SGuennadi Liakhovetski int i; 648f985da17SGuennadi Liakhovetski 649f985da17SGuennadi Liakhovetski if (host->sd_error) { 650f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 651585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 652f985da17SGuennadi Liakhovetski return false; 653f985da17SGuennadi Liakhovetski } 654f985da17SGuennadi Liakhovetski 655f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 656487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 657fdc50a94SYusuke Goda 658fdc50a94SYusuke Goda /* buffer read end */ 659fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 660f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END; 661fdc50a94SYusuke Goda 662f985da17SGuennadi Liakhovetski return true; 663fdc50a94SYusuke Goda } 664fdc50a94SYusuke Goda 665f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host, 666fdc50a94SYusuke Goda struct mmc_request *mrq) 667fdc50a94SYusuke Goda { 668fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 669fdc50a94SYusuke Goda 670f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 671f985da17SGuennadi Liakhovetski return; 672f985da17SGuennadi Liakhovetski 673f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 674f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 675f985da17SGuennadi Liakhovetski 676f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD; 677f985da17SGuennadi Liakhovetski host->sg_idx = 0; 678f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 679f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 6805df460b1SGuennadi Liakhovetski 681fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 682fdc50a94SYusuke Goda } 683fdc50a94SYusuke Goda 684f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host) 685f985da17SGuennadi Liakhovetski { 686585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 687f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 688f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 689f985da17SGuennadi Liakhovetski int i; 690f985da17SGuennadi Liakhovetski 691f985da17SGuennadi Liakhovetski if (host->sd_error) { 692f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 693585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 694f985da17SGuennadi Liakhovetski return false; 695f985da17SGuennadi Liakhovetski } 696f985da17SGuennadi Liakhovetski 697f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 698f985da17SGuennadi Liakhovetski 699f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 700f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 701f985da17SGuennadi Liakhovetski 702f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 703f985da17SGuennadi Liakhovetski return false; 704f985da17SGuennadi Liakhovetski 705f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 706f985da17SGuennadi Liakhovetski 707f985da17SGuennadi Liakhovetski return true; 708f985da17SGuennadi Liakhovetski } 709f985da17SGuennadi Liakhovetski 710f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host, 711fdc50a94SYusuke Goda struct mmc_request *mrq) 712fdc50a94SYusuke Goda { 713f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 714f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3; 715fdc50a94SYusuke Goda 716f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE; 717fdc50a94SYusuke Goda 718fdc50a94SYusuke Goda /* buf write enable */ 719f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 720f985da17SGuennadi Liakhovetski } 721fdc50a94SYusuke Goda 722f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host) 723f985da17SGuennadi Liakhovetski { 724585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 725f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 726f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg); 727f985da17SGuennadi Liakhovetski int i; 728f985da17SGuennadi Liakhovetski 729f985da17SGuennadi Liakhovetski if (host->sd_error) { 730f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 731585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 732f985da17SGuennadi Liakhovetski return false; 733f985da17SGuennadi Liakhovetski } 734f985da17SGuennadi Liakhovetski 735f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 736487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 737fdc50a94SYusuke Goda 738fdc50a94SYusuke Goda /* buffer write end */ 739fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 740f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END; 741fdc50a94SYusuke Goda 742f985da17SGuennadi Liakhovetski return true; 743fdc50a94SYusuke Goda } 744fdc50a94SYusuke Goda 745f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host, 746fdc50a94SYusuke Goda struct mmc_request *mrq) 747fdc50a94SYusuke Goda { 748fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 749fdc50a94SYusuke Goda 750f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length) 751f985da17SGuennadi Liakhovetski return; 752fdc50a94SYusuke Goda 753f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) & 754f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK; 755f985da17SGuennadi Liakhovetski 756f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE; 757f985da17SGuennadi Liakhovetski host->sg_idx = 0; 758f985da17SGuennadi Liakhovetski host->sg_blkidx = 0; 759f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg); 7605df460b1SGuennadi Liakhovetski 761fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 762fdc50a94SYusuke Goda } 763f985da17SGuennadi Liakhovetski 764f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host) 765f985da17SGuennadi Liakhovetski { 766585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 767f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 768f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr; 769f985da17SGuennadi Liakhovetski int i; 770f985da17SGuennadi Liakhovetski 771f985da17SGuennadi Liakhovetski if (host->sd_error) { 772f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 773585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error); 774f985da17SGuennadi Liakhovetski return false; 775fdc50a94SYusuke Goda } 776f985da17SGuennadi Liakhovetski 777f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length); 778f985da17SGuennadi Liakhovetski 779f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++) 780f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 781f985da17SGuennadi Liakhovetski 782f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p)) 783f985da17SGuennadi Liakhovetski return false; 784f985da17SGuennadi Liakhovetski 785f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 786f985da17SGuennadi Liakhovetski 787f985da17SGuennadi Liakhovetski return true; 788fdc50a94SYusuke Goda } 789fdc50a94SYusuke Goda 790fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 791fdc50a94SYusuke Goda struct mmc_command *cmd) 792fdc50a94SYusuke Goda { 793fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 794487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 795487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 796487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 797487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 798fdc50a94SYusuke Goda } else 799487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 800fdc50a94SYusuke Goda } 801fdc50a94SYusuke Goda 802fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 803fdc50a94SYusuke Goda struct mmc_command *cmd) 804fdc50a94SYusuke Goda { 805487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 806fdc50a94SYusuke Goda } 807fdc50a94SYusuke Goda 808fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 80969983404SGuennadi Liakhovetski struct mmc_request *mrq) 810fdc50a94SYusuke Goda { 811585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 81269983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data; 81369983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 81469983404SGuennadi Liakhovetski u32 opc = cmd->opcode; 815fdc50a94SYusuke Goda u32 tmp = 0; 816fdc50a94SYusuke Goda 817fdc50a94SYusuke Goda /* Response Type check */ 818fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 819fdc50a94SYusuke Goda case MMC_RSP_NONE: 820fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 821fdc50a94SYusuke Goda break; 822fdc50a94SYusuke Goda case MMC_RSP_R1: 823fdc50a94SYusuke Goda case MMC_RSP_R1B: 824fdc50a94SYusuke Goda case MMC_RSP_R3: 825fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 826fdc50a94SYusuke Goda break; 827fdc50a94SYusuke Goda case MMC_RSP_R2: 828fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 829fdc50a94SYusuke Goda break; 830fdc50a94SYusuke Goda default: 831585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported response type.\n"); 832fdc50a94SYusuke Goda break; 833fdc50a94SYusuke Goda } 834fdc50a94SYusuke Goda switch (opc) { 835fdc50a94SYusuke Goda /* RBSY */ 836a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 837fdc50a94SYusuke Goda case MMC_SWITCH: 838fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 839fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 840fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 841fdc50a94SYusuke Goda case MMC_ERASE: 842fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 843fdc50a94SYusuke Goda break; 844fdc50a94SYusuke Goda } 845fdc50a94SYusuke Goda /* WDAT / DATW */ 84669983404SGuennadi Liakhovetski if (data) { 847fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 848fdc50a94SYusuke Goda switch (host->bus_width) { 849fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 850fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 851fdc50a94SYusuke Goda break; 852fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 853fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 854fdc50a94SYusuke Goda break; 855fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 856fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 857fdc50a94SYusuke Goda break; 858fdc50a94SYusuke Goda default: 859585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported bus width.\n"); 860fdc50a94SYusuke Goda break; 861fdc50a94SYusuke Goda } 862555061f9STeppei Kamijou switch (host->timing) { 8634039ff47SSeungwon Jeon case MMC_TIMING_MMC_DDR52: 864555061f9STeppei Kamijou /* 865555061f9STeppei Kamijou * MMC core will only set this timing, if the host 8664039ff47SSeungwon Jeon * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR 8674039ff47SSeungwon Jeon * capability. MMCIF implementations with this 8684039ff47SSeungwon Jeon * capability, e.g. sh73a0, will have to set it 8694039ff47SSeungwon Jeon * in their platform data. 870555061f9STeppei Kamijou */ 871555061f9STeppei Kamijou tmp |= CMD_SET_DARS; 872555061f9STeppei Kamijou break; 873555061f9STeppei Kamijou } 874fdc50a94SYusuke Goda } 875fdc50a94SYusuke Goda /* DWEN */ 876fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 877fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 878fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 879fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 880fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 881fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 88269983404SGuennadi Liakhovetski data->blocks << 16); 883fdc50a94SYusuke Goda } 884fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 885fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 886fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 887fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 888fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 889fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 890fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 891fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 892fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 893fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 894fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 895fdc50a94SYusuke Goda 89669983404SGuennadi Liakhovetski return (opc << 24) | tmp; 897fdc50a94SYusuke Goda } 898fdc50a94SYusuke Goda 899e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 900fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 901fdc50a94SYusuke Goda { 902585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 903585c3a5aSKuninori Morimoto 904fdc50a94SYusuke Goda switch (opc) { 905fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 906f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq); 907f985da17SGuennadi Liakhovetski return 0; 908fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 909f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq); 910f985da17SGuennadi Liakhovetski return 0; 911fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 912f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq); 913f985da17SGuennadi Liakhovetski return 0; 914fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 915fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 916f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq); 917f985da17SGuennadi Liakhovetski return 0; 918fdc50a94SYusuke Goda default: 919585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported CMD%d\n", opc); 920ee4b8887SGuennadi Liakhovetski return -EINVAL; 921fdc50a94SYusuke Goda } 922fdc50a94SYusuke Goda } 923fdc50a94SYusuke Goda 924fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 925ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 926fdc50a94SYusuke Goda { 927ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd; 928f985da17SGuennadi Liakhovetski u32 opc = cmd->opcode; 929f985da17SGuennadi Liakhovetski u32 mask; 930dbb42d96SKouichi Tomita unsigned long flags; 931fdc50a94SYusuke Goda 932fdc50a94SYusuke Goda switch (opc) { 933ee4b8887SGuennadi Liakhovetski /* response busy check */ 934a812ba0fSTeppei Kamijou case MMC_SLEEP_AWAKE: 935fdc50a94SYusuke Goda case MMC_SWITCH: 936fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 937fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 938fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 939fdc50a94SYusuke Goda case MMC_ERASE: 940ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE; 941fdc50a94SYusuke Goda break; 942fdc50a94SYusuke Goda default: 943ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE; 944fdc50a94SYusuke Goda break; 945fdc50a94SYusuke Goda } 946fdc50a94SYusuke Goda 947967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 948967bcb77SGuennadi Liakhovetski mask |= MASK_MCCSTO; 949967bcb77SGuennadi Liakhovetski 95069983404SGuennadi Liakhovetski if (mrq->data) { 951487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 952487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 953487d9fc5SMagnus Damm mrq->data->blksz); 954fdc50a94SYusuke Goda } 95569983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq); 956fdc50a94SYusuke Goda 957967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 958487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 959967bcb77SGuennadi Liakhovetski else 960967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS); 961487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 962fdc50a94SYusuke Goda /* set arg */ 963487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 964fdc50a94SYusuke Goda /* set cmd */ 965dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 966487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 967fdc50a94SYusuke Goda 968f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD; 969f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 970dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 971fdc50a94SYusuke Goda } 972fdc50a94SYusuke Goda 973fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 974ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq) 975fdc50a94SYusuke Goda { 976585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 977585c3a5aSKuninori Morimoto 97869983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) { 97969983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK: 980fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 98169983404SGuennadi Liakhovetski break; 98269983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK: 983fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 98469983404SGuennadi Liakhovetski break; 98569983404SGuennadi Liakhovetski default: 986585c3a5aSKuninori Morimoto dev_err(dev, "unsupported stop cmd\n"); 98769983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 988fdc50a94SYusuke Goda return; 989fdc50a94SYusuke Goda } 990fdc50a94SYusuke Goda 991f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP; 992fdc50a94SYusuke Goda } 993fdc50a94SYusuke Goda 994fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 995fdc50a94SYusuke Goda { 996fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 997585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 9983b0beafcSGuennadi Liakhovetski unsigned long flags; 9993b0beafcSGuennadi Liakhovetski 10003b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 10013b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 1002585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 1003585c3a5aSKuninori Morimoto __func__, host->state); 10043b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 10053b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 10063b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 10073b0beafcSGuennadi Liakhovetski return; 10083b0beafcSGuennadi Liakhovetski } 10093b0beafcSGuennadi Liakhovetski 10103b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 10113b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 1012fdc50a94SYusuke Goda 1013fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 1014fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 10157541ca98SLaurent Pinchart case MMC_SLEEP_AWAKE: /* = SD_IO_SEND_OP_COND (5) */ 10167541ca98SLaurent Pinchart case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 10177541ca98SLaurent Pinchart if ((mrq->cmd->flags & MMC_CMD_MASK) != MMC_CMD_BCR) 10187541ca98SLaurent Pinchart break; 1019fdc50a94SYusuke Goda case MMC_APP_CMD: 102092ff0c5bSTeppei Kamijou case SD_IO_RW_DIRECT: 10213b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1022fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 1023fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 1024fdc50a94SYusuke Goda return; 1025fdc50a94SYusuke Goda default: 1026fdc50a94SYusuke Goda break; 1027fdc50a94SYusuke Goda } 1028fdc50a94SYusuke Goda 1029f985da17SGuennadi Liakhovetski host->mrq = mrq; 1030f985da17SGuennadi Liakhovetski 1031f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq); 1032fdc50a94SYusuke Goda } 1033fdc50a94SYusuke Goda 10349bb09a30SKuninori Morimoto static void sh_mmcif_clk_setup(struct sh_mmcif_host *host) 1035a6609267SGuennadi Liakhovetski { 103689d49a70SKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 103789d49a70SKuninori Morimoto 103889d49a70SKuninori Morimoto if (host->mmc->f_max) { 103989d49a70SKuninori Morimoto unsigned int f_max, f_min = 0, f_min_old; 104089d49a70SKuninori Morimoto 104189d49a70SKuninori Morimoto f_max = host->mmc->f_max; 104289d49a70SKuninori Morimoto for (f_min_old = f_max; f_min_old > 2;) { 104389d49a70SKuninori Morimoto f_min = clk_round_rate(host->clk, f_min_old / 2); 104489d49a70SKuninori Morimoto if (f_min == f_min_old) 104589d49a70SKuninori Morimoto break; 104689d49a70SKuninori Morimoto f_min_old = f_min; 104789d49a70SKuninori Morimoto } 104889d49a70SKuninori Morimoto 104989d49a70SKuninori Morimoto /* 105089d49a70SKuninori Morimoto * This driver assumes this SoC is R-Car Gen2 or later 105189d49a70SKuninori Morimoto */ 105289d49a70SKuninori Morimoto host->clkdiv_map = 0x3ff; 105389d49a70SKuninori Morimoto 105489d49a70SKuninori Morimoto host->mmc->f_max = f_max / (1 << ffs(host->clkdiv_map)); 105589d49a70SKuninori Morimoto host->mmc->f_min = f_min / (1 << fls(host->clkdiv_map)); 105689d49a70SKuninori Morimoto } else { 10576aed678bSKuninori Morimoto unsigned int clk = clk_get_rate(host->clk); 10586aed678bSKuninori Morimoto 10596aed678bSKuninori Morimoto host->mmc->f_max = clk / 2; 10606aed678bSKuninori Morimoto host->mmc->f_min = clk / 512; 1061a6609267SGuennadi Liakhovetski } 1062a6609267SGuennadi Liakhovetski 106389d49a70SKuninori Morimoto dev_dbg(dev, "clk max/min = %d/%d\n", 106489d49a70SKuninori Morimoto host->mmc->f_max, host->mmc->f_min); 106589d49a70SKuninori Morimoto } 106689d49a70SKuninori Morimoto 10677d17baa0SGuennadi Liakhovetski static void sh_mmcif_set_power(struct sh_mmcif_host *host, struct mmc_ios *ios) 10687d17baa0SGuennadi Liakhovetski { 10697d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 10707d17baa0SGuennadi Liakhovetski 10717d17baa0SGuennadi Liakhovetski if (!IS_ERR(mmc->supply.vmmc)) 10727d17baa0SGuennadi Liakhovetski /* Errors ignored... */ 10737d17baa0SGuennadi Liakhovetski mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 10747d17baa0SGuennadi Liakhovetski ios->power_mode ? ios->vdd : 0); 10757d17baa0SGuennadi Liakhovetski } 10767d17baa0SGuennadi Liakhovetski 1077fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 1078fdc50a94SYusuke Goda { 1079fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 1080585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 10813b0beafcSGuennadi Liakhovetski unsigned long flags; 10823b0beafcSGuennadi Liakhovetski 10833b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 10843b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 1085585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n", 1086585c3a5aSKuninori Morimoto __func__, host->state); 10873b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 10883b0beafcSGuennadi Liakhovetski return; 10893b0beafcSGuennadi Liakhovetski } 10903b0beafcSGuennadi Liakhovetski 10913b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 10923b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 1093fdc50a94SYusuke Goda 1094f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 1095c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 1096faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 109727cbd7e8SArnd Bergmann sh_mmcif_request_dma(host); 1098c9b0cef2SGuennadi Liakhovetski host->card_present = true; 1099faca6648SGuennadi Liakhovetski } 11007d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1101f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 1102f5e0cec4SGuennadi Liakhovetski /* clock stop */ 1103f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 1104faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 1105c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 1106c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 1107c9b0cef2SGuennadi Liakhovetski host->card_present = false; 1108c9b0cef2SGuennadi Liakhovetski } 1109c9b0cef2SGuennadi Liakhovetski } 1110faca6648SGuennadi Liakhovetski if (host->power) { 1111585c3a5aSKuninori Morimoto pm_runtime_put_sync(dev); 11126aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1113faca6648SGuennadi Liakhovetski host->power = false; 11147d17baa0SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) 11157d17baa0SGuennadi Liakhovetski sh_mmcif_set_power(host, ios); 1116faca6648SGuennadi Liakhovetski } 11173b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1118f5e0cec4SGuennadi Liakhovetski return; 1119fdc50a94SYusuke Goda } 1120fdc50a94SYusuke Goda 1121c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 1122c9b0cef2SGuennadi Liakhovetski if (!host->power) { 11239bb09a30SKuninori Morimoto clk_prepare_enable(host->clk); 11249bb09a30SKuninori Morimoto 1125585c3a5aSKuninori Morimoto pm_runtime_get_sync(dev); 1126c9b0cef2SGuennadi Liakhovetski host->power = true; 1127c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 1128c9b0cef2SGuennadi Liakhovetski } 1129fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 1130c9b0cef2SGuennadi Liakhovetski } 1131fdc50a94SYusuke Goda 1132555061f9STeppei Kamijou host->timing = ios->timing; 1133fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 11343b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 1135fdc50a94SYusuke Goda } 1136fdc50a94SYusuke Goda 1137777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 1138777271d0SArnd Hannemann { 1139777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 1140585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1141585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *p = dev->platform_data; 1142e480606aSGuennadi Liakhovetski int ret = mmc_gpio_get_cd(mmc); 1143e480606aSGuennadi Liakhovetski 1144e480606aSGuennadi Liakhovetski if (ret >= 0) 1145e480606aSGuennadi Liakhovetski return ret; 1146777271d0SArnd Hannemann 1147bf68a812SGuennadi Liakhovetski if (!p || !p->get_cd) 1148777271d0SArnd Hannemann return -ENOSYS; 1149777271d0SArnd Hannemann else 1150777271d0SArnd Hannemann return p->get_cd(host->pd); 1151777271d0SArnd Hannemann } 1152777271d0SArnd Hannemann 1153fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 1154fdc50a94SYusuke Goda .request = sh_mmcif_request, 1155fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 1156777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 1157fdc50a94SYusuke Goda }; 1158fdc50a94SYusuke Goda 1159f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host) 1160f985da17SGuennadi Liakhovetski { 1161f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd; 116269983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data; 1163585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1164f985da17SGuennadi Liakhovetski long time; 1165f985da17SGuennadi Liakhovetski 1166f985da17SGuennadi Liakhovetski if (host->sd_error) { 1167f985da17SGuennadi Liakhovetski switch (cmd->opcode) { 1168f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID: 1169f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD: 1170f985da17SGuennadi Liakhovetski case MMC_APP_CMD: 1171f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT; 1172f985da17SGuennadi Liakhovetski break; 1173f985da17SGuennadi Liakhovetski default: 1174f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host); 1175f985da17SGuennadi Liakhovetski break; 1176f985da17SGuennadi Liakhovetski } 1177585c3a5aSKuninori Morimoto dev_dbg(dev, "CMD%d error %d\n", 1178e475b270STeppei Kamijou cmd->opcode, cmd->error); 1179aba9d646SGuennadi Liakhovetski host->sd_error = false; 1180f985da17SGuennadi Liakhovetski return false; 1181f985da17SGuennadi Liakhovetski } 1182f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) { 1183f985da17SGuennadi Liakhovetski cmd->error = 0; 1184f985da17SGuennadi Liakhovetski return false; 1185f985da17SGuennadi Liakhovetski } 1186f985da17SGuennadi Liakhovetski 1187f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd); 1188f985da17SGuennadi Liakhovetski 118969983404SGuennadi Liakhovetski if (!data) 1190f985da17SGuennadi Liakhovetski return false; 1191f985da17SGuennadi Liakhovetski 119290f1cb43SGuennadi Liakhovetski /* 119390f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to 119490f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active 119590f1cb43SGuennadi Liakhovetski */ 119690f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete); 119790f1cb43SGuennadi Liakhovetski 119869983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) { 1199f985da17SGuennadi Liakhovetski if (host->chan_rx) 1200f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 1201f985da17SGuennadi Liakhovetski } else { 1202f985da17SGuennadi Liakhovetski if (host->chan_tx) 1203f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 1204f985da17SGuennadi Liakhovetski } 1205f985da17SGuennadi Liakhovetski 1206f985da17SGuennadi Liakhovetski if (!host->dma_active) { 120769983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode); 120899eb9d8dSGuennadi Liakhovetski return !data->error; 1209f985da17SGuennadi Liakhovetski } 1210f985da17SGuennadi Liakhovetski 1211f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */ 1212f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete, 1213f985da17SGuennadi Liakhovetski host->timeout); 1214eae30983STeppei Kamijou 1215eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1216eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev, 1217eae30983STeppei Kamijou data->sg, data->sg_len, 1218eae30983STeppei Kamijou DMA_FROM_DEVICE); 1219eae30983STeppei Kamijou else 1220eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev, 1221eae30983STeppei Kamijou data->sg, data->sg_len, 1222eae30983STeppei Kamijou DMA_TO_DEVICE); 1223eae30983STeppei Kamijou 1224f985da17SGuennadi Liakhovetski if (host->sd_error) { 1225f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent, 1226f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n"); 1227f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */ 122869983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host); 1229f985da17SGuennadi Liakhovetski } else if (!time) { 1230e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n"); 123169983404SGuennadi Liakhovetski data->error = -ETIMEDOUT; 1232f985da17SGuennadi Liakhovetski } else if (time < 0) { 1233e475b270STeppei Kamijou dev_err(host->mmc->parent, 1234e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time); 123569983404SGuennadi Liakhovetski data->error = time; 1236f985da17SGuennadi Liakhovetski } 1237f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 1238f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 1239f985da17SGuennadi Liakhovetski host->dma_active = false; 1240f985da17SGuennadi Liakhovetski 1241eae30983STeppei Kamijou if (data->error) { 124269983404SGuennadi Liakhovetski data->bytes_xfered = 0; 1243eae30983STeppei Kamijou /* Abort DMA */ 1244eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ) 1245eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_rx); 1246eae30983STeppei Kamijou else 1247eae30983STeppei Kamijou dmaengine_terminate_all(host->chan_tx); 1248eae30983STeppei Kamijou } 1249f985da17SGuennadi Liakhovetski 1250f985da17SGuennadi Liakhovetski return false; 1251f985da17SGuennadi Liakhovetski } 1252f985da17SGuennadi Liakhovetski 1253f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id) 1254f985da17SGuennadi Liakhovetski { 1255f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id; 12568047310eSGuennadi Liakhovetski struct mmc_request *mrq; 1257585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 12585df460b1SGuennadi Liakhovetski bool wait = false; 1259dbb42d96SKouichi Tomita unsigned long flags; 1260dbb42d96SKouichi Tomita int wait_work; 1261dbb42d96SKouichi Tomita 1262dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags); 1263dbb42d96SKouichi Tomita wait_work = host->wait_for; 1264dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags); 1265f985da17SGuennadi Liakhovetski 1266f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1267f985da17SGuennadi Liakhovetski 12688047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock); 12698047310eSGuennadi Liakhovetski 12708047310eSGuennadi Liakhovetski mrq = host->mrq; 12718047310eSGuennadi Liakhovetski if (!mrq) { 1272585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n", 12738047310eSGuennadi Liakhovetski host->state, host->wait_for); 12748047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 12758047310eSGuennadi Liakhovetski return IRQ_HANDLED; 12768047310eSGuennadi Liakhovetski } 12778047310eSGuennadi Liakhovetski 1278f985da17SGuennadi Liakhovetski /* 1279f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the 1280f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not 1281f985da17SGuennadi Liakhovetski */ 1282dbb42d96SKouichi Tomita switch (wait_work) { 1283f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST: 1284f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */ 12858047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1286f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1287f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 12885df460b1SGuennadi Liakhovetski /* Wait for data? */ 12895df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host); 1290f985da17SGuennadi Liakhovetski break; 1291f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 12925df460b1SGuennadi Liakhovetski /* Wait for more data? */ 12935df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host); 1294f985da17SGuennadi Liakhovetski break; 1295f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 12965df460b1SGuennadi Liakhovetski /* Wait for data end? */ 12975df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host); 1298f985da17SGuennadi Liakhovetski break; 1299f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 13005df460b1SGuennadi Liakhovetski /* Wait data to write? */ 13015df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host); 1302f985da17SGuennadi Liakhovetski break; 1303f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 13045df460b1SGuennadi Liakhovetski /* Wait for data end? */ 13055df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host); 1306f985da17SGuennadi Liakhovetski break; 1307f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1308f985da17SGuennadi Liakhovetski if (host->sd_error) { 1309f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1310585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error); 1311f985da17SGuennadi Liakhovetski break; 1312f985da17SGuennadi Liakhovetski } 1313f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop); 1314f985da17SGuennadi Liakhovetski mrq->stop->error = 0; 1315f985da17SGuennadi Liakhovetski break; 1316f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1317f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 1318e475b270STeppei Kamijou if (host->sd_error) { 131991ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1320585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error); 1321e475b270STeppei Kamijou } 1322f985da17SGuennadi Liakhovetski break; 1323f985da17SGuennadi Liakhovetski default: 1324f985da17SGuennadi Liakhovetski BUG(); 1325f985da17SGuennadi Liakhovetski } 1326f985da17SGuennadi Liakhovetski 13275df460b1SGuennadi Liakhovetski if (wait) { 13285df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 13295df460b1SGuennadi Liakhovetski /* Wait for more data */ 13308047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 13315df460b1SGuennadi Liakhovetski return IRQ_HANDLED; 13325df460b1SGuennadi Liakhovetski } 13335df460b1SGuennadi Liakhovetski 1334f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) { 133591ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data; 133669983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error) 133769983404SGuennadi Liakhovetski data->bytes_xfered = 133869983404SGuennadi Liakhovetski data->blocks * data->blksz; 1339f985da17SGuennadi Liakhovetski 134069983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) { 1341f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq); 13425df460b1SGuennadi Liakhovetski if (!mrq->stop->error) { 13435df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout); 13448047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 1345f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1346f985da17SGuennadi Liakhovetski } 1347f985da17SGuennadi Liakhovetski } 13485df460b1SGuennadi Liakhovetski } 1349f985da17SGuennadi Liakhovetski 1350f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1351f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 135269983404SGuennadi Liakhovetski host->mrq = NULL; 1353f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1354f985da17SGuennadi Liakhovetski 13558047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock); 13568047310eSGuennadi Liakhovetski 1357f985da17SGuennadi Liakhovetski return IRQ_HANDLED; 1358f985da17SGuennadi Liakhovetski } 1359f985da17SGuennadi Liakhovetski 1360fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 1361fdc50a94SYusuke Goda { 1362fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 1363585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1364967bcb77SGuennadi Liakhovetski u32 state, mask; 1365fdc50a94SYusuke Goda 1366487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 1367967bcb77SGuennadi Liakhovetski mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK); 1368967bcb77SGuennadi Liakhovetski if (host->ccs_enable) 1369967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask)); 1370967bcb77SGuennadi Liakhovetski else 1371967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask)); 13728af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN); 1373fdc50a94SYusuke Goda 13748af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN) 1375585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n", 13768af50750SGuennadi Liakhovetski state); 13778af50750SGuennadi Liakhovetski 13788af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) { 1379aa0787a9SGuennadi Liakhovetski host->sd_error = true; 1380585c3a5aSKuninori Morimoto dev_dbg(dev, "int err state = 0x%08x\n", state); 1381fdc50a94SYusuke Goda } 1382f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) { 13838af50750SGuennadi Liakhovetski if (!host->mrq) 1384585c3a5aSKuninori Morimoto dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state); 1385f985da17SGuennadi Liakhovetski if (!host->dma_active) 1386f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD; 1387f985da17SGuennadi Liakhovetski else if (host->sd_error) 13881b1a694dSKuninori Morimoto sh_mmcif_dma_complete(host); 1389f985da17SGuennadi Liakhovetski } else { 1390585c3a5aSKuninori Morimoto dev_dbg(dev, "Unexpected IRQ 0x%x\n", state); 1391f985da17SGuennadi Liakhovetski } 1392fdc50a94SYusuke Goda 1393fdc50a94SYusuke Goda return IRQ_HANDLED; 1394fdc50a94SYusuke Goda } 1395fdc50a94SYusuke Goda 13961b1a694dSKuninori Morimoto static void sh_mmcif_timeout_work(struct work_struct *work) 1397f985da17SGuennadi Liakhovetski { 13981046a811SGeliang Tang struct delayed_work *d = to_delayed_work(work); 1399f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work); 1400f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq; 1401585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 14028047310eSGuennadi Liakhovetski unsigned long flags; 1403f985da17SGuennadi Liakhovetski 1404f985da17SGuennadi Liakhovetski if (host->dying) 1405f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */ 1406f985da17SGuennadi Liakhovetski return; 1407f985da17SGuennadi Liakhovetski 14088047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 14098047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) { 14108047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 14118047310eSGuennadi Liakhovetski return; 14128047310eSGuennadi Liakhovetski } 14138047310eSGuennadi Liakhovetski 1414585c3a5aSKuninori Morimoto dev_err(dev, "Timeout waiting for %u on CMD%u\n", 14154cbd5224SKouichi Tomita host->wait_for, mrq->cmd->opcode); 14164cbd5224SKouichi Tomita 14178047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT; 14188047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 14198047310eSGuennadi Liakhovetski 1420f985da17SGuennadi Liakhovetski /* 1421f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless 1422f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used 1423f985da17SGuennadi Liakhovetski */ 1424f985da17SGuennadi Liakhovetski switch (host->wait_for) { 1425f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD: 1426f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host); 1427f985da17SGuennadi Liakhovetski break; 1428f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP: 1429f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host); 1430f985da17SGuennadi Liakhovetski break; 1431f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD: 1432f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE: 1433f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ: 1434f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE: 1435f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END: 1436f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END: 143769983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host); 1438f985da17SGuennadi Liakhovetski break; 1439f985da17SGuennadi Liakhovetski default: 1440f985da17SGuennadi Liakhovetski BUG(); 1441f985da17SGuennadi Liakhovetski } 1442f985da17SGuennadi Liakhovetski 1443f985da17SGuennadi Liakhovetski host->state = STATE_IDLE; 1444f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST; 1445f985da17SGuennadi Liakhovetski host->mrq = NULL; 1446f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq); 1447f985da17SGuennadi Liakhovetski } 1448f985da17SGuennadi Liakhovetski 14497d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host) 14507d17baa0SGuennadi Liakhovetski { 1451585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host); 1452585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 14537d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc; 14547d17baa0SGuennadi Liakhovetski 14557d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc); 14567d17baa0SGuennadi Liakhovetski 1457bf68a812SGuennadi Liakhovetski if (!pd) 1458bf68a812SGuennadi Liakhovetski return; 1459bf68a812SGuennadi Liakhovetski 14607d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail) 14617d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr; 14627d17baa0SGuennadi Liakhovetski else if (pd->ocr) 14637d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n"); 14647d17baa0SGuennadi Liakhovetski } 14657d17baa0SGuennadi Liakhovetski 1466c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev) 1467fdc50a94SYusuke Goda { 1468fdc50a94SYusuke Goda int ret = 0, irq[2]; 1469fdc50a94SYusuke Goda struct mmc_host *mmc; 1470e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 147160985c39SKuninori Morimoto struct device *dev = &pdev->dev; 147260985c39SKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data; 1473fdc50a94SYusuke Goda struct resource *res; 1474fdc50a94SYusuke Goda void __iomem *reg; 14752cd5b3e0SShinya Kuribayashi const char *name; 1476fdc50a94SYusuke Goda 1477fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1478fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 14792cd5b3e0SShinya Kuribayashi if (irq[0] < 0) { 148060985c39SKuninori Morimoto dev_err(dev, "Get irq error\n"); 1481fdc50a94SYusuke Goda return -ENXIO; 1482fdc50a94SYusuke Goda } 148318f55fccSBen Dooks 1484fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 148560985c39SKuninori Morimoto reg = devm_ioremap_resource(dev, res); 148618f55fccSBen Dooks if (IS_ERR(reg)) 148718f55fccSBen Dooks return PTR_ERR(reg); 1488e1aae2ebSGuennadi Liakhovetski 148960985c39SKuninori Morimoto mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev); 149018f55fccSBen Dooks if (!mmc) 149118f55fccSBen Dooks return -ENOMEM; 14922c9054dcSSimon Baatz 14932c9054dcSSimon Baatz ret = mmc_of_parse(mmc); 14942c9054dcSSimon Baatz if (ret < 0) 149546991005SBen Dooks goto err_host; 14962c9054dcSSimon Baatz 1497fdc50a94SYusuke Goda host = mmc_priv(mmc); 1498fdc50a94SYusuke Goda host->mmc = mmc; 1499fdc50a94SYusuke Goda host->addr = reg; 1500bad4371dSTakeshi Kihara host->timeout = msecs_to_jiffies(10000); 1501967bcb77SGuennadi Liakhovetski host->ccs_enable = !pd || !pd->ccs_unsupported; 15026d6fd367SGuennadi Liakhovetski host->clk_ctrl2_enable = pd && pd->clk_ctrl2_present; 1503fdc50a94SYusuke Goda 1504fdc50a94SYusuke Goda host->pd = pdev; 1505fdc50a94SYusuke Goda 15063b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1507fdc50a94SYusuke Goda 1508fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 15097d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host); 15107d17baa0SGuennadi Liakhovetski 1511eca889f6SGuennadi Liakhovetski mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY; 1512bf68a812SGuennadi Liakhovetski if (pd && pd->caps) 1513fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1514a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1515fdc50a94SYusuke Goda mmc->max_blk_size = 512; 151609cbfeafSKirill A. Shutemov mmc->max_req_size = PAGE_SIZE * mmc->max_segs; 1517a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1518fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1519fdc50a94SYusuke Goda 1520fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1521a782d688SGuennadi Liakhovetski 152260985c39SKuninori Morimoto pm_runtime_enable(dev); 1523faca6648SGuennadi Liakhovetski host->power = false; 1524faca6648SGuennadi Liakhovetski 15256aed678bSKuninori Morimoto host->clk = devm_clk_get(dev, NULL); 15266aed678bSKuninori Morimoto if (IS_ERR(host->clk)) { 15276aed678bSKuninori Morimoto ret = PTR_ERR(host->clk); 152860985c39SKuninori Morimoto dev_err(dev, "cannot get clock: %d\n", ret); 152946991005SBen Dooks goto err_pm; 1530b289174fSGuennadi Liakhovetski } 15319bb09a30SKuninori Morimoto 15329bb09a30SKuninori Morimoto ret = clk_prepare_enable(host->clk); 1533a6609267SGuennadi Liakhovetski if (ret < 0) 153446991005SBen Dooks goto err_pm; 1535b289174fSGuennadi Liakhovetski 15369bb09a30SKuninori Morimoto sh_mmcif_clk_setup(host); 15379bb09a30SKuninori Morimoto 153860985c39SKuninori Morimoto ret = pm_runtime_resume(dev); 1539faca6648SGuennadi Liakhovetski if (ret < 0) 154046991005SBen Dooks goto err_clk; 1541a782d688SGuennadi Liakhovetski 15421b1a694dSKuninori Morimoto INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work); 1543fdc50a94SYusuke Goda 1544b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host); 15453b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 15463b0beafcSGuennadi Liakhovetski 154760985c39SKuninori Morimoto name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error"; 154860985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr, 15496f4789e6SBen Dooks sh_mmcif_irqt, 0, name, host); 1550fdc50a94SYusuke Goda if (ret) { 155160985c39SKuninori Morimoto dev_err(dev, "request_irq error (%s)\n", name); 155211a80852SBen Dooks goto err_clk; 1553fdc50a94SYusuke Goda } 15542cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) { 155560985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[1], 15566f4789e6SBen Dooks sh_mmcif_intr, sh_mmcif_irqt, 15572cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host); 1558fdc50a94SYusuke Goda if (ret) { 155960985c39SKuninori Morimoto dev_err(dev, "request_irq error (sh_mmc:int)\n"); 156011a80852SBen Dooks goto err_clk; 1561fdc50a94SYusuke Goda } 15622cd5b3e0SShinya Kuribayashi } 1563fdc50a94SYusuke Goda 1564e480606aSGuennadi Liakhovetski if (pd && pd->use_cd_gpio) { 1565214fc309SLaurent Pinchart ret = mmc_gpio_request_cd(mmc, pd->cd_gpio, 0); 1566e480606aSGuennadi Liakhovetski if (ret < 0) 15677f67f3a2SBen Dooks goto err_clk; 1568e480606aSGuennadi Liakhovetski } 1569e480606aSGuennadi Liakhovetski 15708047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock); 15718047310eSGuennadi Liakhovetski 15725ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc); 15735ba85d95SGuennadi Liakhovetski if (ret < 0) 15747f67f3a2SBen Dooks goto err_clk; 1575fdc50a94SYusuke Goda 157660985c39SKuninori Morimoto dev_pm_qos_expose_latency_limit(dev, 100); 1577efe6a8adSRafael J. Wysocki 157860985c39SKuninori Morimoto dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n", 1579ce7eb688SBen Dooks sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff, 15806aed678bSKuninori Morimoto clk_get_rate(host->clk) / 1000000UL); 1581ce7eb688SBen Dooks 15826aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1583fdc50a94SYusuke Goda return ret; 1584fdc50a94SYusuke Goda 158546991005SBen Dooks err_clk: 15866aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 158746991005SBen Dooks err_pm: 158860985c39SKuninori Morimoto pm_runtime_disable(dev); 158946991005SBen Dooks err_host: 1590fdc50a94SYusuke Goda mmc_free_host(mmc); 1591fdc50a94SYusuke Goda return ret; 1592fdc50a94SYusuke Goda } 1593fdc50a94SYusuke Goda 15946e0ee714SBill Pemberton static int sh_mmcif_remove(struct platform_device *pdev) 1595fdc50a94SYusuke Goda { 1596fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1597fdc50a94SYusuke Goda 1598f985da17SGuennadi Liakhovetski host->dying = true; 15996aed678bSKuninori Morimoto clk_prepare_enable(host->clk); 1600faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1601aa0787a9SGuennadi Liakhovetski 1602efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev); 1603efe6a8adSRafael J. Wysocki 1604faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 16053b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 16063b0beafcSGuennadi Liakhovetski 1607f985da17SGuennadi Liakhovetski /* 1608f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the 1609f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either 1610f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies). 1611f985da17SGuennadi Liakhovetski */ 1612f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work); 1613f985da17SGuennadi Liakhovetski 16146aed678bSKuninori Morimoto clk_disable_unprepare(host->clk); 1615fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1616faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1617faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1618fdc50a94SYusuke Goda 1619fdc50a94SYusuke Goda return 0; 1620fdc50a94SYusuke Goda } 1621fdc50a94SYusuke Goda 162251129f31SUlf Hansson #ifdef CONFIG_PM_SLEEP 1623faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1624faca6648SGuennadi Liakhovetski { 1625b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev); 1626faca6648SGuennadi Liakhovetski 16275afc30fcSKoji Matsuoka pm_runtime_get_sync(dev); 1628faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 16295afc30fcSKoji Matsuoka pm_runtime_put(dev); 1630faca6648SGuennadi Liakhovetski 1631cb3ca1aeSUlf Hansson return 0; 1632faca6648SGuennadi Liakhovetski } 1633faca6648SGuennadi Liakhovetski 1634faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1635faca6648SGuennadi Liakhovetski { 1636cb3ca1aeSUlf Hansson return 0; 1637faca6648SGuennadi Liakhovetski } 163851129f31SUlf Hansson #endif 1639faca6648SGuennadi Liakhovetski 1640faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 164151129f31SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume) 1642faca6648SGuennadi Liakhovetski }; 1643faca6648SGuennadi Liakhovetski 1644fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1645fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1646fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1647fdc50a94SYusuke Goda .driver = { 1648fdc50a94SYusuke Goda .name = DRIVER_NAME, 1649faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 16501b1a694dSKuninori Morimoto .of_match_table = sh_mmcif_of_match, 1651fdc50a94SYusuke Goda }, 1652fdc50a94SYusuke Goda }; 1653fdc50a94SYusuke Goda 1654d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver); 1655fdc50a94SYusuke Goda 1656fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1657fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1658aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1659fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1660