1fdc50a94SYusuke Goda /* 2fdc50a94SYusuke Goda * MMCIF eMMC driver. 3fdc50a94SYusuke Goda * 4fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp. 5fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com> 6fdc50a94SYusuke Goda * 7fdc50a94SYusuke Goda * This program is free software; you can redistribute it and/or modify 8fdc50a94SYusuke Goda * it under the terms of the GNU General Public License as published by 9fdc50a94SYusuke Goda * the Free Software Foundation; either version 2 of the License. 10fdc50a94SYusuke Goda * 11fdc50a94SYusuke Goda * 12fdc50a94SYusuke Goda * TODO 13fdc50a94SYusuke Goda * 1. DMA 14fdc50a94SYusuke Goda * 2. Power management 15fdc50a94SYusuke Goda * 3. Handle MMC errors better 16fdc50a94SYusuke Goda * 17fdc50a94SYusuke Goda */ 18fdc50a94SYusuke Goda 19aa0787a9SGuennadi Liakhovetski #include <linux/clk.h> 20aa0787a9SGuennadi Liakhovetski #include <linux/completion.h> 21e47bf32aSGuennadi Liakhovetski #include <linux/delay.h> 22fdc50a94SYusuke Goda #include <linux/dma-mapping.h> 23a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h> 24fdc50a94SYusuke Goda #include <linux/mmc/card.h> 25fdc50a94SYusuke Goda #include <linux/mmc/core.h> 26e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h> 27fdc50a94SYusuke Goda #include <linux/mmc/mmc.h> 28fdc50a94SYusuke Goda #include <linux/mmc/sdio.h> 29fdc50a94SYusuke Goda #include <linux/mmc/sh_mmcif.h> 30a782d688SGuennadi Liakhovetski #include <linux/pagemap.h> 31e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h> 32faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h> 333b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h> 34fdc50a94SYusuke Goda 35fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif" 36fdc50a94SYusuke Goda #define DRIVER_VERSION "2010-04-28" 37fdc50a94SYusuke Goda 38fdc50a94SYusuke Goda /* CE_CMD_SET */ 39fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000 40fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22)) 41fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */ 42fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */ 43fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */ 44fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20) 45fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */ 46fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */ 47fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */ 48fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */ 49fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */ 50fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */ 51fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */ 52fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/ 53fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/ 54fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/ 55fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/ 56fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */ 57fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */ 58fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */ 59fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5) 60fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */ 61fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */ 62fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */ 63fdc50a94SYusuke Goda 64fdc50a94SYusuke Goda /* CE_CMD_CTRL */ 65fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0) 66fdc50a94SYusuke Goda 67fdc50a94SYusuke Goda /* CE_BLOCK_SET */ 68fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff 69fdc50a94SYusuke Goda 70fdc50a94SYusuke Goda /* CE_INT */ 71fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29) 72fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26) 73fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25) 74fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24) 75fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23) 76fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22) 77fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21) 78fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20) 79fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19) 80fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17) 81fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16) 82fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15) 83fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14) 84fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11) 85fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10) 86fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9) 87fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8) 88fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5) 89fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4) 90fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3) 91fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2) 92fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1) 93fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0) 94fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \ 95fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \ 96fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \ 97fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO) 98fdc50a94SYusuke Goda 99fdc50a94SYusuke Goda /* CE_INT_MASK */ 100fdc50a94SYusuke Goda #define MASK_ALL 0x00000000 101fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29) 102fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26) 103fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25) 104fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24) 105fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23) 106fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22) 107fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21) 108fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20) 109fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19) 110fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17) 111fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16) 112fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15) 113fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14) 114fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11) 115fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10) 116fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9) 117fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8) 118fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5) 119fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4) 120fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3) 121fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2) 122fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1) 123fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0) 124fdc50a94SYusuke Goda 125fdc50a94SYusuke Goda /* CE_HOST_STS1 */ 126fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31) 127fdc50a94SYusuke Goda 128fdc50a94SYusuke Goda /* CE_HOST_STS2 */ 129fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31) 130fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30) 131fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29) 132fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28) 133fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27) 134fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26) 135fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25) 136fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24) 137fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23) 138fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22) 139fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15) 140fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14) 141fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13) 142fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12) 143fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11) 144fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10) 145fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9) 146fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8) 147fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \ 148fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE) 149fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \ 150fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \ 151fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \ 152fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO) 153fdc50a94SYusuke Goda 154fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52MHz */ 155fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20MHz */ 156fdc50a94SYusuke Goda #define CLKDEV_INIT 400000 /* 400 KHz */ 157fdc50a94SYusuke Goda 1583b0beafcSGuennadi Liakhovetski enum mmcif_state { 1593b0beafcSGuennadi Liakhovetski STATE_IDLE, 1603b0beafcSGuennadi Liakhovetski STATE_REQUEST, 1613b0beafcSGuennadi Liakhovetski STATE_IOS, 1623b0beafcSGuennadi Liakhovetski }; 1633b0beafcSGuennadi Liakhovetski 164fdc50a94SYusuke Goda struct sh_mmcif_host { 165fdc50a94SYusuke Goda struct mmc_host *mmc; 166fdc50a94SYusuke Goda struct mmc_data *data; 167fdc50a94SYusuke Goda struct platform_device *pd; 168fdc50a94SYusuke Goda struct clk *hclk; 169fdc50a94SYusuke Goda unsigned int clk; 170fdc50a94SYusuke Goda int bus_width; 171aa0787a9SGuennadi Liakhovetski bool sd_error; 172fdc50a94SYusuke Goda long timeout; 173fdc50a94SYusuke Goda void __iomem *addr; 174aa0787a9SGuennadi Liakhovetski struct completion intr_wait; 1753b0beafcSGuennadi Liakhovetski enum mmcif_state state; 1763b0beafcSGuennadi Liakhovetski spinlock_t lock; 177faca6648SGuennadi Liakhovetski bool power; 178c9b0cef2SGuennadi Liakhovetski bool card_present; 179fdc50a94SYusuke Goda 180a782d688SGuennadi Liakhovetski /* DMA support */ 181a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx; 182a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx; 183a782d688SGuennadi Liakhovetski struct completion dma_complete; 184f38f94c6SLinus Walleij bool dma_active; 185a782d688SGuennadi Liakhovetski }; 186fdc50a94SYusuke Goda 187fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host, 188fdc50a94SYusuke Goda unsigned int reg, u32 val) 189fdc50a94SYusuke Goda { 190487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg); 191fdc50a94SYusuke Goda } 192fdc50a94SYusuke Goda 193fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host, 194fdc50a94SYusuke Goda unsigned int reg, u32 val) 195fdc50a94SYusuke Goda { 196487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg); 197fdc50a94SYusuke Goda } 198fdc50a94SYusuke Goda 199a782d688SGuennadi Liakhovetski static void mmcif_dma_complete(void *arg) 200a782d688SGuennadi Liakhovetski { 201a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg; 202a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Command completed\n"); 203a782d688SGuennadi Liakhovetski 204a782d688SGuennadi Liakhovetski if (WARN(!host->data, "%s: NULL data in DMA completion!\n", 205a782d688SGuennadi Liakhovetski dev_name(&host->pd->dev))) 206a782d688SGuennadi Liakhovetski return; 207a782d688SGuennadi Liakhovetski 208a782d688SGuennadi Liakhovetski if (host->data->flags & MMC_DATA_READ) 2091ed828dbSLinus Walleij dma_unmap_sg(host->chan_rx->device->dev, 2109dc3fb5eSLinus Walleij host->data->sg, host->data->sg_len, 211a782d688SGuennadi Liakhovetski DMA_FROM_DEVICE); 212a782d688SGuennadi Liakhovetski else 2131ed828dbSLinus Walleij dma_unmap_sg(host->chan_tx->device->dev, 2149dc3fb5eSLinus Walleij host->data->sg, host->data->sg_len, 215a782d688SGuennadi Liakhovetski DMA_TO_DEVICE); 216a782d688SGuennadi Liakhovetski 217a782d688SGuennadi Liakhovetski complete(&host->dma_complete); 218a782d688SGuennadi Liakhovetski } 219a782d688SGuennadi Liakhovetski 220a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host) 221a782d688SGuennadi Liakhovetski { 222a782d688SGuennadi Liakhovetski struct scatterlist *sg = host->data->sg; 223a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 224a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 225a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 226a782d688SGuennadi Liakhovetski int ret; 227a782d688SGuennadi Liakhovetski 2281ed828dbSLinus Walleij ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len, 2291ed828dbSLinus Walleij DMA_FROM_DEVICE); 230a782d688SGuennadi Liakhovetski if (ret > 0) { 231f38f94c6SLinus Walleij host->dma_active = true; 232a782d688SGuennadi Liakhovetski desc = chan->device->device_prep_slave_sg(chan, sg, ret, 23305f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 234a782d688SGuennadi Liakhovetski } 235a782d688SGuennadi Liakhovetski 236a782d688SGuennadi Liakhovetski if (desc) { 237a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 238a782d688SGuennadi Liakhovetski desc->callback_param = host; 239a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 240a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN); 241a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 242a782d688SGuennadi Liakhovetski } 243a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 244a782d688SGuennadi Liakhovetski __func__, host->data->sg_len, ret, cookie); 245a782d688SGuennadi Liakhovetski 246a782d688SGuennadi Liakhovetski if (!desc) { 247a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 248a782d688SGuennadi Liakhovetski if (ret >= 0) 249a782d688SGuennadi Liakhovetski ret = -EIO; 250a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 251f38f94c6SLinus Walleij host->dma_active = false; 252a782d688SGuennadi Liakhovetski dma_release_channel(chan); 253a782d688SGuennadi Liakhovetski /* Free the Tx channel too */ 254a782d688SGuennadi Liakhovetski chan = host->chan_tx; 255a782d688SGuennadi Liakhovetski if (chan) { 256a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 257a782d688SGuennadi Liakhovetski dma_release_channel(chan); 258a782d688SGuennadi Liakhovetski } 259a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 260a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 261a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 262a782d688SGuennadi Liakhovetski } 263a782d688SGuennadi Liakhovetski 264a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__, 265a782d688SGuennadi Liakhovetski desc, cookie, host->data->sg_len); 266a782d688SGuennadi Liakhovetski } 267a782d688SGuennadi Liakhovetski 268a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host) 269a782d688SGuennadi Liakhovetski { 270a782d688SGuennadi Liakhovetski struct scatterlist *sg = host->data->sg; 271a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL; 272a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 273a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL; 274a782d688SGuennadi Liakhovetski int ret; 275a782d688SGuennadi Liakhovetski 2761ed828dbSLinus Walleij ret = dma_map_sg(chan->device->dev, sg, host->data->sg_len, 2771ed828dbSLinus Walleij DMA_TO_DEVICE); 278a782d688SGuennadi Liakhovetski if (ret > 0) { 279f38f94c6SLinus Walleij host->dma_active = true; 280a782d688SGuennadi Liakhovetski desc = chan->device->device_prep_slave_sg(chan, sg, ret, 28105f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK); 282a782d688SGuennadi Liakhovetski } 283a782d688SGuennadi Liakhovetski 284a782d688SGuennadi Liakhovetski if (desc) { 285a782d688SGuennadi Liakhovetski desc->callback = mmcif_dma_complete; 286a782d688SGuennadi Liakhovetski desc->callback_param = host; 287a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc); 288a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN); 289a5ece7d2SLinus Walleij dma_async_issue_pending(chan); 290a782d688SGuennadi Liakhovetski } 291a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): mapped %d -> %d, cookie %d\n", 292a782d688SGuennadi Liakhovetski __func__, host->data->sg_len, ret, cookie); 293a782d688SGuennadi Liakhovetski 294a782d688SGuennadi Liakhovetski if (!desc) { 295a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */ 296a782d688SGuennadi Liakhovetski if (ret >= 0) 297a782d688SGuennadi Liakhovetski ret = -EIO; 298a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 299f38f94c6SLinus Walleij host->dma_active = false; 300a782d688SGuennadi Liakhovetski dma_release_channel(chan); 301a782d688SGuennadi Liakhovetski /* Free the Rx channel too */ 302a782d688SGuennadi Liakhovetski chan = host->chan_rx; 303a782d688SGuennadi Liakhovetski if (chan) { 304a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 305a782d688SGuennadi Liakhovetski dma_release_channel(chan); 306a782d688SGuennadi Liakhovetski } 307a782d688SGuennadi Liakhovetski dev_warn(&host->pd->dev, 308a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret); 309a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 310a782d688SGuennadi Liakhovetski } 311a782d688SGuennadi Liakhovetski 312a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s(): desc %p, cookie %d\n", __func__, 313a782d688SGuennadi Liakhovetski desc, cookie); 314a782d688SGuennadi Liakhovetski } 315a782d688SGuennadi Liakhovetski 316a782d688SGuennadi Liakhovetski static bool sh_mmcif_filter(struct dma_chan *chan, void *arg) 317a782d688SGuennadi Liakhovetski { 318a782d688SGuennadi Liakhovetski dev_dbg(chan->device->dev, "%s: slave data %p\n", __func__, arg); 319a782d688SGuennadi Liakhovetski chan->private = arg; 320a782d688SGuennadi Liakhovetski return true; 321a782d688SGuennadi Liakhovetski } 322a782d688SGuennadi Liakhovetski 323a782d688SGuennadi Liakhovetski static void sh_mmcif_request_dma(struct sh_mmcif_host *host, 324a782d688SGuennadi Liakhovetski struct sh_mmcif_plat_data *pdata) 325a782d688SGuennadi Liakhovetski { 326f38f94c6SLinus Walleij host->dma_active = false; 327a782d688SGuennadi Liakhovetski 328a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */ 329a782d688SGuennadi Liakhovetski if (pdata->dma) { 330a782d688SGuennadi Liakhovetski dma_cap_mask_t mask; 331a782d688SGuennadi Liakhovetski 332a782d688SGuennadi Liakhovetski dma_cap_zero(mask); 333a782d688SGuennadi Liakhovetski dma_cap_set(DMA_SLAVE, mask); 334a782d688SGuennadi Liakhovetski 335a782d688SGuennadi Liakhovetski host->chan_tx = dma_request_channel(mask, sh_mmcif_filter, 336a782d688SGuennadi Liakhovetski &pdata->dma->chan_priv_tx); 337a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: TX: got channel %p\n", __func__, 338a782d688SGuennadi Liakhovetski host->chan_tx); 339a782d688SGuennadi Liakhovetski 340a782d688SGuennadi Liakhovetski if (!host->chan_tx) 341a782d688SGuennadi Liakhovetski return; 342a782d688SGuennadi Liakhovetski 343a782d688SGuennadi Liakhovetski host->chan_rx = dma_request_channel(mask, sh_mmcif_filter, 344a782d688SGuennadi Liakhovetski &pdata->dma->chan_priv_rx); 345a782d688SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "%s: RX: got channel %p\n", __func__, 346a782d688SGuennadi Liakhovetski host->chan_rx); 347a782d688SGuennadi Liakhovetski 348a782d688SGuennadi Liakhovetski if (!host->chan_rx) { 349a782d688SGuennadi Liakhovetski dma_release_channel(host->chan_tx); 350a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 351a782d688SGuennadi Liakhovetski return; 352a782d688SGuennadi Liakhovetski } 353a782d688SGuennadi Liakhovetski 354a782d688SGuennadi Liakhovetski init_completion(&host->dma_complete); 355a782d688SGuennadi Liakhovetski } 356a782d688SGuennadi Liakhovetski } 357a782d688SGuennadi Liakhovetski 358a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host) 359a782d688SGuennadi Liakhovetski { 360a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 361a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */ 362a782d688SGuennadi Liakhovetski if (host->chan_tx) { 363a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx; 364a782d688SGuennadi Liakhovetski host->chan_tx = NULL; 365a782d688SGuennadi Liakhovetski dma_release_channel(chan); 366a782d688SGuennadi Liakhovetski } 367a782d688SGuennadi Liakhovetski if (host->chan_rx) { 368a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx; 369a782d688SGuennadi Liakhovetski host->chan_rx = NULL; 370a782d688SGuennadi Liakhovetski dma_release_channel(chan); 371a782d688SGuennadi Liakhovetski } 372a782d688SGuennadi Liakhovetski 373f38f94c6SLinus Walleij host->dma_active = false; 374a782d688SGuennadi Liakhovetski } 375fdc50a94SYusuke Goda 376fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk) 377fdc50a94SYusuke Goda { 378fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 379fdc50a94SYusuke Goda 380fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 381fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR); 382fdc50a94SYusuke Goda 383fdc50a94SYusuke Goda if (!clk) 384fdc50a94SYusuke Goda return; 385fdc50a94SYusuke Goda if (p->sup_pclk && clk == host->clk) 386fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_SUP_PCLK); 387fdc50a94SYusuke Goda else 388fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & 389fdc50a94SYusuke Goda (ilog2(__rounddown_pow_of_two(host->clk / clk)) << 16)); 390fdc50a94SYusuke Goda 391fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE); 392fdc50a94SYusuke Goda } 393fdc50a94SYusuke Goda 394fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host) 395fdc50a94SYusuke Goda { 396fdc50a94SYusuke Goda u32 tmp; 397fdc50a94SYusuke Goda 398487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL); 399fdc50a94SYusuke Goda 400487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON); 401487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF); 402fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp | 403fdc50a94SYusuke Goda SRSPTO_256 | SRBSYTO_29 | SRWDTO_29 | SCCSTO_29); 404fdc50a94SYusuke Goda /* byte swap on */ 405fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP); 406fdc50a94SYusuke Goda } 407fdc50a94SYusuke Goda 408fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host) 409fdc50a94SYusuke Goda { 410fdc50a94SYusuke Goda u32 state1, state2; 411fdc50a94SYusuke Goda int ret, timeout = 10000000; 412fdc50a94SYusuke Goda 413aa0787a9SGuennadi Liakhovetski host->sd_error = false; 414fdc50a94SYusuke Goda 415487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1); 416487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2); 417e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS1 = %08x\n", state1); 418e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "ERR HOST_STS2 = %08x\n", state2); 419fdc50a94SYusuke Goda 420fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) { 421fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK); 422fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK); 423fdc50a94SYusuke Goda while (1) { 424fdc50a94SYusuke Goda timeout--; 425fdc50a94SYusuke Goda if (timeout < 0) { 426e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, 427e47bf32aSGuennadi Liakhovetski "Forceed end of command sequence timeout err\n"); 428fdc50a94SYusuke Goda return -EIO; 429fdc50a94SYusuke Goda } 430487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1) 431fdc50a94SYusuke Goda & STS1_CMDSEQ)) 432fdc50a94SYusuke Goda break; 433fdc50a94SYusuke Goda mdelay(1); 434fdc50a94SYusuke Goda } 435fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 436e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Forced end of command sequence\n"); 437fdc50a94SYusuke Goda return -EIO; 438fdc50a94SYusuke Goda } 439fdc50a94SYusuke Goda 440fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) { 441e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Happened CRC error\n"); 442fdc50a94SYusuke Goda ret = -EIO; 443fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) { 444e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Happened Timeout error\n"); 445fdc50a94SYusuke Goda ret = -ETIMEDOUT; 446fdc50a94SYusuke Goda } else { 447e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, ": Happened End/Index error\n"); 448fdc50a94SYusuke Goda ret = -EIO; 449fdc50a94SYusuke Goda } 450fdc50a94SYusuke Goda return ret; 451fdc50a94SYusuke Goda } 452fdc50a94SYusuke Goda 453fdc50a94SYusuke Goda static int sh_mmcif_single_read(struct sh_mmcif_host *host, 454fdc50a94SYusuke Goda struct mmc_request *mrq) 455fdc50a94SYusuke Goda { 456fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 457fdc50a94SYusuke Goda long time; 458fdc50a94SYusuke Goda u32 blocksize, i, *p = sg_virt(data->sg); 459fdc50a94SYusuke Goda 460fdc50a94SYusuke Goda /* buf read enable */ 461fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 462aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 463aa0787a9SGuennadi Liakhovetski host->timeout); 464aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 465fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 466fdc50a94SYusuke Goda 467fdc50a94SYusuke Goda blocksize = (BLOCK_SIZE_MASK & 468487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; 469fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 470487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA); 471fdc50a94SYusuke Goda 472fdc50a94SYusuke Goda /* buffer read end */ 473fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 474aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 475aa0787a9SGuennadi Liakhovetski host->timeout); 476aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 477fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 478fdc50a94SYusuke Goda 479fdc50a94SYusuke Goda return 0; 480fdc50a94SYusuke Goda } 481fdc50a94SYusuke Goda 482fdc50a94SYusuke Goda static int sh_mmcif_multi_read(struct sh_mmcif_host *host, 483fdc50a94SYusuke Goda struct mmc_request *mrq) 484fdc50a94SYusuke Goda { 485fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 486fdc50a94SYusuke Goda long time; 487fdc50a94SYusuke Goda u32 blocksize, i, j, sec, *p; 488fdc50a94SYusuke Goda 489487d9fc5SMagnus Damm blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, 490487d9fc5SMagnus Damm MMCIF_CE_BLOCK_SET); 491fdc50a94SYusuke Goda for (j = 0; j < data->sg_len; j++) { 492fdc50a94SYusuke Goda p = sg_virt(data->sg); 493fdc50a94SYusuke Goda for (sec = 0; sec < data->sg->length / blocksize; sec++) { 494fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 495fdc50a94SYusuke Goda /* buf read enable */ 496aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 497aa0787a9SGuennadi Liakhovetski host->timeout); 498fdc50a94SYusuke Goda 499aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 500fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 501fdc50a94SYusuke Goda 502fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 503487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, 504487d9fc5SMagnus Damm MMCIF_CE_DATA); 505fdc50a94SYusuke Goda } 506fdc50a94SYusuke Goda if (j < data->sg_len - 1) 507fdc50a94SYusuke Goda data->sg++; 508fdc50a94SYusuke Goda } 509fdc50a94SYusuke Goda return 0; 510fdc50a94SYusuke Goda } 511fdc50a94SYusuke Goda 512fdc50a94SYusuke Goda static int sh_mmcif_single_write(struct sh_mmcif_host *host, 513fdc50a94SYusuke Goda struct mmc_request *mrq) 514fdc50a94SYusuke Goda { 515fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 516fdc50a94SYusuke Goda long time; 517fdc50a94SYusuke Goda u32 blocksize, i, *p = sg_virt(data->sg); 518fdc50a94SYusuke Goda 519fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 520fdc50a94SYusuke Goda 521fdc50a94SYusuke Goda /* buf write enable */ 522aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 523aa0787a9SGuennadi Liakhovetski host->timeout); 524aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 525fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 526fdc50a94SYusuke Goda 527fdc50a94SYusuke Goda blocksize = (BLOCK_SIZE_MASK & 528487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET)) + 3; 529fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 530487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++); 531fdc50a94SYusuke Goda 532fdc50a94SYusuke Goda /* buffer write end */ 533fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 534fdc50a94SYusuke Goda 535aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 536aa0787a9SGuennadi Liakhovetski host->timeout); 537aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 538fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 539fdc50a94SYusuke Goda 540fdc50a94SYusuke Goda return 0; 541fdc50a94SYusuke Goda } 542fdc50a94SYusuke Goda 543fdc50a94SYusuke Goda static int sh_mmcif_multi_write(struct sh_mmcif_host *host, 544fdc50a94SYusuke Goda struct mmc_request *mrq) 545fdc50a94SYusuke Goda { 546fdc50a94SYusuke Goda struct mmc_data *data = mrq->data; 547fdc50a94SYusuke Goda long time; 548fdc50a94SYusuke Goda u32 i, sec, j, blocksize, *p; 549fdc50a94SYusuke Goda 550487d9fc5SMagnus Damm blocksize = BLOCK_SIZE_MASK & sh_mmcif_readl(host->addr, 551487d9fc5SMagnus Damm MMCIF_CE_BLOCK_SET); 552fdc50a94SYusuke Goda 553fdc50a94SYusuke Goda for (j = 0; j < data->sg_len; j++) { 554fdc50a94SYusuke Goda p = sg_virt(data->sg); 555fdc50a94SYusuke Goda for (sec = 0; sec < data->sg->length / blocksize; sec++) { 556fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 557fdc50a94SYusuke Goda /* buf write enable*/ 558aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 559aa0787a9SGuennadi Liakhovetski host->timeout); 560fdc50a94SYusuke Goda 561aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) 562fdc50a94SYusuke Goda return sh_mmcif_error_manage(host); 563fdc50a94SYusuke Goda 564fdc50a94SYusuke Goda for (i = 0; i < blocksize / 4; i++) 565487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, 566487d9fc5SMagnus Damm MMCIF_CE_DATA, *p++); 567fdc50a94SYusuke Goda } 568fdc50a94SYusuke Goda if (j < data->sg_len - 1) 569fdc50a94SYusuke Goda data->sg++; 570fdc50a94SYusuke Goda } 571fdc50a94SYusuke Goda return 0; 572fdc50a94SYusuke Goda } 573fdc50a94SYusuke Goda 574fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host, 575fdc50a94SYusuke Goda struct mmc_command *cmd) 576fdc50a94SYusuke Goda { 577fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) { 578487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3); 579487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2); 580487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1); 581487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 582fdc50a94SYusuke Goda } else 583487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0); 584fdc50a94SYusuke Goda } 585fdc50a94SYusuke Goda 586fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host, 587fdc50a94SYusuke Goda struct mmc_command *cmd) 588fdc50a94SYusuke Goda { 589487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12); 590fdc50a94SYusuke Goda } 591fdc50a94SYusuke Goda 592fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host, 593fdc50a94SYusuke Goda struct mmc_request *mrq, struct mmc_command *cmd, u32 opc) 594fdc50a94SYusuke Goda { 595fdc50a94SYusuke Goda u32 tmp = 0; 596fdc50a94SYusuke Goda 597fdc50a94SYusuke Goda /* Response Type check */ 598fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) { 599fdc50a94SYusuke Goda case MMC_RSP_NONE: 600fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO; 601fdc50a94SYusuke Goda break; 602fdc50a94SYusuke Goda case MMC_RSP_R1: 603fdc50a94SYusuke Goda case MMC_RSP_R1B: 604fdc50a94SYusuke Goda case MMC_RSP_R3: 605fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B; 606fdc50a94SYusuke Goda break; 607fdc50a94SYusuke Goda case MMC_RSP_R2: 608fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B; 609fdc50a94SYusuke Goda break; 610fdc50a94SYusuke Goda default: 611e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported response type.\n"); 612fdc50a94SYusuke Goda break; 613fdc50a94SYusuke Goda } 614fdc50a94SYusuke Goda switch (opc) { 615fdc50a94SYusuke Goda /* RBSY */ 616fdc50a94SYusuke Goda case MMC_SWITCH: 617fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 618fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 619fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 620fdc50a94SYusuke Goda case MMC_ERASE: 621fdc50a94SYusuke Goda case MMC_GEN_CMD: 622fdc50a94SYusuke Goda tmp |= CMD_SET_RBSY; 623fdc50a94SYusuke Goda break; 624fdc50a94SYusuke Goda } 625fdc50a94SYusuke Goda /* WDAT / DATW */ 626fdc50a94SYusuke Goda if (host->data) { 627fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT; 628fdc50a94SYusuke Goda switch (host->bus_width) { 629fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1: 630fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1; 631fdc50a94SYusuke Goda break; 632fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4: 633fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4; 634fdc50a94SYusuke Goda break; 635fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8: 636fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8; 637fdc50a94SYusuke Goda break; 638fdc50a94SYusuke Goda default: 639e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "Unsupported bus width.\n"); 640fdc50a94SYusuke Goda break; 641fdc50a94SYusuke Goda } 642fdc50a94SYusuke Goda } 643fdc50a94SYusuke Goda /* DWEN */ 644fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) 645fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN; 646fdc50a94SYusuke Goda /* CMLTE/CMD12EN */ 647fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) { 648fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN; 649fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET, 650fdc50a94SYusuke Goda mrq->data->blocks << 16); 651fdc50a94SYusuke Goda } 652fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */ 653fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID || 654fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 655fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS; 656fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */ 657fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND) 658fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS; 659fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */ 660fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID || 661fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID) 662fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL; 663fdc50a94SYusuke Goda 664fdc50a94SYusuke Goda return opc = ((opc << 24) | tmp); 665fdc50a94SYusuke Goda } 666fdc50a94SYusuke Goda 667e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host, 668fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc) 669fdc50a94SYusuke Goda { 670e47bf32aSGuennadi Liakhovetski int ret; 671fdc50a94SYusuke Goda 672fdc50a94SYusuke Goda switch (opc) { 673fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK: 674fdc50a94SYusuke Goda ret = sh_mmcif_multi_read(host, mrq); 675fdc50a94SYusuke Goda break; 676fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK: 677fdc50a94SYusuke Goda ret = sh_mmcif_multi_write(host, mrq); 678fdc50a94SYusuke Goda break; 679fdc50a94SYusuke Goda case MMC_WRITE_BLOCK: 680fdc50a94SYusuke Goda ret = sh_mmcif_single_write(host, mrq); 681fdc50a94SYusuke Goda break; 682fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK: 683fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: 684fdc50a94SYusuke Goda ret = sh_mmcif_single_read(host, mrq); 685fdc50a94SYusuke Goda break; 686fdc50a94SYusuke Goda default: 687e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "UNSUPPORTED CMD = d'%08d\n", opc); 688fdc50a94SYusuke Goda ret = -EINVAL; 689fdc50a94SYusuke Goda break; 690fdc50a94SYusuke Goda } 691fdc50a94SYusuke Goda return ret; 692fdc50a94SYusuke Goda } 693fdc50a94SYusuke Goda 694fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host, 695fdc50a94SYusuke Goda struct mmc_request *mrq, struct mmc_command *cmd) 696fdc50a94SYusuke Goda { 697fdc50a94SYusuke Goda long time; 698fdc50a94SYusuke Goda int ret = 0, mask = 0; 699fdc50a94SYusuke Goda u32 opc = cmd->opcode; 700fdc50a94SYusuke Goda 701fdc50a94SYusuke Goda switch (opc) { 702fdc50a94SYusuke Goda /* respons busy check */ 703fdc50a94SYusuke Goda case MMC_SWITCH: 704fdc50a94SYusuke Goda case MMC_STOP_TRANSMISSION: 705fdc50a94SYusuke Goda case MMC_SET_WRITE_PROT: 706fdc50a94SYusuke Goda case MMC_CLR_WRITE_PROT: 707fdc50a94SYusuke Goda case MMC_ERASE: 708fdc50a94SYusuke Goda case MMC_GEN_CMD: 709fdc50a94SYusuke Goda mask = MASK_MRBSYE; 710fdc50a94SYusuke Goda break; 711fdc50a94SYusuke Goda default: 712fdc50a94SYusuke Goda mask = MASK_MCRSPE; 713fdc50a94SYusuke Goda break; 714fdc50a94SYusuke Goda } 715fdc50a94SYusuke Goda mask |= MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | 716fdc50a94SYusuke Goda MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | 717fdc50a94SYusuke Goda MASK_MCCSTO | MASK_MCRCSTO | MASK_MWDATTO | 718fdc50a94SYusuke Goda MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO; 719fdc50a94SYusuke Goda 720fdc50a94SYusuke Goda if (host->data) { 721487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0); 722487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 723487d9fc5SMagnus Damm mrq->data->blksz); 724fdc50a94SYusuke Goda } 725fdc50a94SYusuke Goda opc = sh_mmcif_set_cmd(host, mrq, cmd, opc); 726fdc50a94SYusuke Goda 727487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0); 728487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask); 729fdc50a94SYusuke Goda /* set arg */ 730487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg); 731fdc50a94SYusuke Goda /* set cmd */ 732487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc); 733fdc50a94SYusuke Goda 734aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 735aa0787a9SGuennadi Liakhovetski host->timeout); 736aa0787a9SGuennadi Liakhovetski if (time <= 0) { 737fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 738fdc50a94SYusuke Goda return; 739fdc50a94SYusuke Goda } 740fdc50a94SYusuke Goda if (host->sd_error) { 741fdc50a94SYusuke Goda switch (cmd->opcode) { 742fdc50a94SYusuke Goda case MMC_ALL_SEND_CID: 743fdc50a94SYusuke Goda case MMC_SELECT_CARD: 744fdc50a94SYusuke Goda case MMC_APP_CMD: 745fdc50a94SYusuke Goda cmd->error = -ETIMEDOUT; 746fdc50a94SYusuke Goda break; 747fdc50a94SYusuke Goda default: 748e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Cmd(d'%d) err\n", 749e47bf32aSGuennadi Liakhovetski cmd->opcode); 750fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 751fdc50a94SYusuke Goda break; 752fdc50a94SYusuke Goda } 753aa0787a9SGuennadi Liakhovetski host->sd_error = false; 754fdc50a94SYusuke Goda return; 755fdc50a94SYusuke Goda } 756fdc50a94SYusuke Goda if (!(cmd->flags & MMC_RSP_PRESENT)) { 757e47bf32aSGuennadi Liakhovetski cmd->error = 0; 758fdc50a94SYusuke Goda return; 759fdc50a94SYusuke Goda } 760fdc50a94SYusuke Goda sh_mmcif_get_response(host, cmd); 761fdc50a94SYusuke Goda if (host->data) { 762f38f94c6SLinus Walleij if (!host->dma_active) { 763fdc50a94SYusuke Goda ret = sh_mmcif_data_trans(host, mrq, cmd->opcode); 764a782d688SGuennadi Liakhovetski } else { 765a782d688SGuennadi Liakhovetski long time = 766a782d688SGuennadi Liakhovetski wait_for_completion_interruptible_timeout(&host->dma_complete, 767a782d688SGuennadi Liakhovetski host->timeout); 768a782d688SGuennadi Liakhovetski if (!time) 769a782d688SGuennadi Liakhovetski ret = -ETIMEDOUT; 770a782d688SGuennadi Liakhovetski else if (time < 0) 771a782d688SGuennadi Liakhovetski ret = time; 772a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, 773a782d688SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN); 774f38f94c6SLinus Walleij host->dma_active = false; 775a782d688SGuennadi Liakhovetski } 776fdc50a94SYusuke Goda if (ret < 0) 777fdc50a94SYusuke Goda mrq->data->bytes_xfered = 0; 778fdc50a94SYusuke Goda else 779fdc50a94SYusuke Goda mrq->data->bytes_xfered = 780fdc50a94SYusuke Goda mrq->data->blocks * mrq->data->blksz; 781fdc50a94SYusuke Goda } 782fdc50a94SYusuke Goda cmd->error = ret; 783fdc50a94SYusuke Goda } 784fdc50a94SYusuke Goda 785fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host, 786fdc50a94SYusuke Goda struct mmc_request *mrq, struct mmc_command *cmd) 787fdc50a94SYusuke Goda { 788fdc50a94SYusuke Goda long time; 789fdc50a94SYusuke Goda 790fdc50a94SYusuke Goda if (mrq->cmd->opcode == MMC_READ_MULTIPLE_BLOCK) 791fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 792fdc50a94SYusuke Goda else if (mrq->cmd->opcode == MMC_WRITE_MULTIPLE_BLOCK) 793fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 794fdc50a94SYusuke Goda else { 795e47bf32aSGuennadi Liakhovetski dev_err(&host->pd->dev, "unsupported stop cmd\n"); 796fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 797fdc50a94SYusuke Goda return; 798fdc50a94SYusuke Goda } 799fdc50a94SYusuke Goda 800aa0787a9SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->intr_wait, 801aa0787a9SGuennadi Liakhovetski host->timeout); 802aa0787a9SGuennadi Liakhovetski if (time <= 0 || host->sd_error) { 803fdc50a94SYusuke Goda cmd->error = sh_mmcif_error_manage(host); 804fdc50a94SYusuke Goda return; 805fdc50a94SYusuke Goda } 806fdc50a94SYusuke Goda sh_mmcif_get_cmd12response(host, cmd); 807fdc50a94SYusuke Goda cmd->error = 0; 808fdc50a94SYusuke Goda } 809fdc50a94SYusuke Goda 810fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq) 811fdc50a94SYusuke Goda { 812fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 8133b0beafcSGuennadi Liakhovetski unsigned long flags; 8143b0beafcSGuennadi Liakhovetski 8153b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8163b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8173b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 8183b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN; 8193b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq); 8203b0beafcSGuennadi Liakhovetski return; 8213b0beafcSGuennadi Liakhovetski } 8223b0beafcSGuennadi Liakhovetski 8233b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST; 8243b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 825fdc50a94SYusuke Goda 826fdc50a94SYusuke Goda switch (mrq->cmd->opcode) { 827fdc50a94SYusuke Goda /* MMCIF does not support SD/SDIO command */ 828fdc50a94SYusuke Goda case SD_IO_SEND_OP_COND: 829fdc50a94SYusuke Goda case MMC_APP_CMD: 8303b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 831fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 832fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 833fdc50a94SYusuke Goda return; 834fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD: /* = SD_SEND_IF_COND (8) */ 835fdc50a94SYusuke Goda if (!mrq->data) { 836fdc50a94SYusuke Goda /* send_if_cond cmd (not support) */ 8373b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 838fdc50a94SYusuke Goda mrq->cmd->error = -ETIMEDOUT; 839fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 840fdc50a94SYusuke Goda return; 841fdc50a94SYusuke Goda } 842fdc50a94SYusuke Goda break; 843fdc50a94SYusuke Goda default: 844fdc50a94SYusuke Goda break; 845fdc50a94SYusuke Goda } 846fdc50a94SYusuke Goda host->data = mrq->data; 847a782d688SGuennadi Liakhovetski if (mrq->data) { 848a782d688SGuennadi Liakhovetski if (mrq->data->flags & MMC_DATA_READ) { 849a782d688SGuennadi Liakhovetski if (host->chan_rx) 850a782d688SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host); 851a782d688SGuennadi Liakhovetski } else { 852a782d688SGuennadi Liakhovetski if (host->chan_tx) 853a782d688SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host); 854a782d688SGuennadi Liakhovetski } 855a782d688SGuennadi Liakhovetski } 856fdc50a94SYusuke Goda sh_mmcif_start_cmd(host, mrq, mrq->cmd); 857fdc50a94SYusuke Goda host->data = NULL; 858fdc50a94SYusuke Goda 8593b0beafcSGuennadi Liakhovetski if (!mrq->cmd->error && mrq->stop) 860fdc50a94SYusuke Goda sh_mmcif_stop_cmd(host, mrq, mrq->stop); 8613b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 862fdc50a94SYusuke Goda mmc_request_done(mmc, mrq); 863fdc50a94SYusuke Goda } 864fdc50a94SYusuke Goda 865fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios) 866fdc50a94SYusuke Goda { 867fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc); 868fdc50a94SYusuke Goda struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 8693b0beafcSGuennadi Liakhovetski unsigned long flags; 8703b0beafcSGuennadi Liakhovetski 8713b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags); 8723b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) { 8733b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 8743b0beafcSGuennadi Liakhovetski return; 8753b0beafcSGuennadi Liakhovetski } 8763b0beafcSGuennadi Liakhovetski 8773b0beafcSGuennadi Liakhovetski host->state = STATE_IOS; 8783b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags); 879fdc50a94SYusuke Goda 880f5e0cec4SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_UP) { 881c9b0cef2SGuennadi Liakhovetski if (!host->card_present) { 882faca6648SGuennadi Liakhovetski /* See if we also get DMA */ 883faca6648SGuennadi Liakhovetski sh_mmcif_request_dma(host, host->pd->dev.platform_data); 884c9b0cef2SGuennadi Liakhovetski host->card_present = true; 885faca6648SGuennadi Liakhovetski } 886f5e0cec4SGuennadi Liakhovetski } else if (ios->power_mode == MMC_POWER_OFF || !ios->clock) { 887f5e0cec4SGuennadi Liakhovetski /* clock stop */ 888f5e0cec4SGuennadi Liakhovetski sh_mmcif_clock_control(host, 0); 889faca6648SGuennadi Liakhovetski if (ios->power_mode == MMC_POWER_OFF) { 890c9b0cef2SGuennadi Liakhovetski if (host->card_present) { 891c9b0cef2SGuennadi Liakhovetski sh_mmcif_release_dma(host); 892c9b0cef2SGuennadi Liakhovetski host->card_present = false; 893c9b0cef2SGuennadi Liakhovetski } 894c9b0cef2SGuennadi Liakhovetski } 895faca6648SGuennadi Liakhovetski if (host->power) { 896faca6648SGuennadi Liakhovetski pm_runtime_put(&host->pd->dev); 897faca6648SGuennadi Liakhovetski host->power = false; 898faca6648SGuennadi Liakhovetski if (p->down_pwr) 899f5e0cec4SGuennadi Liakhovetski p->down_pwr(host->pd); 900faca6648SGuennadi Liakhovetski } 9013b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 902f5e0cec4SGuennadi Liakhovetski return; 903fdc50a94SYusuke Goda } 904fdc50a94SYusuke Goda 905c9b0cef2SGuennadi Liakhovetski if (ios->clock) { 906c9b0cef2SGuennadi Liakhovetski if (!host->power) { 907c9b0cef2SGuennadi Liakhovetski if (p->set_pwr) 908c9b0cef2SGuennadi Liakhovetski p->set_pwr(host->pd, ios->power_mode); 909c9b0cef2SGuennadi Liakhovetski pm_runtime_get_sync(&host->pd->dev); 910c9b0cef2SGuennadi Liakhovetski host->power = true; 911c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host); 912c9b0cef2SGuennadi Liakhovetski } 913fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock); 914c9b0cef2SGuennadi Liakhovetski } 915fdc50a94SYusuke Goda 916fdc50a94SYusuke Goda host->bus_width = ios->bus_width; 9173b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE; 918fdc50a94SYusuke Goda } 919fdc50a94SYusuke Goda 920777271d0SArnd Hannemann static int sh_mmcif_get_cd(struct mmc_host *mmc) 921777271d0SArnd Hannemann { 922777271d0SArnd Hannemann struct sh_mmcif_host *host = mmc_priv(mmc); 923777271d0SArnd Hannemann struct sh_mmcif_plat_data *p = host->pd->dev.platform_data; 924777271d0SArnd Hannemann 925777271d0SArnd Hannemann if (!p->get_cd) 926777271d0SArnd Hannemann return -ENOSYS; 927777271d0SArnd Hannemann else 928777271d0SArnd Hannemann return p->get_cd(host->pd); 929777271d0SArnd Hannemann } 930777271d0SArnd Hannemann 931fdc50a94SYusuke Goda static struct mmc_host_ops sh_mmcif_ops = { 932fdc50a94SYusuke Goda .request = sh_mmcif_request, 933fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios, 934777271d0SArnd Hannemann .get_cd = sh_mmcif_get_cd, 935fdc50a94SYusuke Goda }; 936fdc50a94SYusuke Goda 937fdc50a94SYusuke Goda static void sh_mmcif_detect(struct mmc_host *mmc) 938fdc50a94SYusuke Goda { 939fdc50a94SYusuke Goda mmc_detect_change(mmc, 0); 940fdc50a94SYusuke Goda } 941fdc50a94SYusuke Goda 942fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id) 943fdc50a94SYusuke Goda { 944fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id; 945aa0787a9SGuennadi Liakhovetski u32 state; 946fdc50a94SYusuke Goda int err = 0; 947fdc50a94SYusuke Goda 948487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT); 949fdc50a94SYusuke Goda 950fdc50a94SYusuke Goda if (state & INT_RBSYE) { 951487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 952487d9fc5SMagnus Damm ~(INT_RBSYE | INT_CRSPE)); 953fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MRBSYE); 954fdc50a94SYusuke Goda } else if (state & INT_CRSPE) { 955487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_CRSPE); 956fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCRSPE); 957fdc50a94SYusuke Goda } else if (state & INT_BUFREN) { 958487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFREN); 959fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFREN); 960fdc50a94SYusuke Goda } else if (state & INT_BUFWEN) { 961487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFWEN); 962fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN); 963fdc50a94SYusuke Goda } else if (state & INT_CMD12DRE) { 964487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 965fdc50a94SYusuke Goda ~(INT_CMD12DRE | INT_CMD12RBE | 966fdc50a94SYusuke Goda INT_CMD12CRE | INT_BUFRE)); 967fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE); 968fdc50a94SYusuke Goda } else if (state & INT_BUFRE) { 969487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_BUFRE); 970fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MBUFRE); 971fdc50a94SYusuke Goda } else if (state & INT_DTRANE) { 972487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~INT_DTRANE); 973fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MDTRANE); 974fdc50a94SYusuke Goda } else if (state & INT_CMD12RBE) { 975487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 976fdc50a94SYusuke Goda ~(INT_CMD12RBE | INT_CMD12CRE)); 977fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE); 978fdc50a94SYusuke Goda } else if (state & INT_ERR_STS) { 979fdc50a94SYusuke Goda /* err interrupts */ 980487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 981fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 982fdc50a94SYusuke Goda err = 1; 983fdc50a94SYusuke Goda } else { 984faca6648SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unsupported interrupt: 0x%x\n", state); 985487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~state); 986fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state); 987fdc50a94SYusuke Goda err = 1; 988fdc50a94SYusuke Goda } 989fdc50a94SYusuke Goda if (err) { 990aa0787a9SGuennadi Liakhovetski host->sd_error = true; 991e47bf32aSGuennadi Liakhovetski dev_dbg(&host->pd->dev, "int err state = %08x\n", state); 992fdc50a94SYusuke Goda } 993aa0787a9SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) 994aa0787a9SGuennadi Liakhovetski complete(&host->intr_wait); 995aa0787a9SGuennadi Liakhovetski else 996aa0787a9SGuennadi Liakhovetski dev_dbg(&host->pd->dev, "Unexpected IRQ 0x%x\n", state); 997fdc50a94SYusuke Goda 998fdc50a94SYusuke Goda return IRQ_HANDLED; 999fdc50a94SYusuke Goda } 1000fdc50a94SYusuke Goda 1001fdc50a94SYusuke Goda static int __devinit sh_mmcif_probe(struct platform_device *pdev) 1002fdc50a94SYusuke Goda { 1003fdc50a94SYusuke Goda int ret = 0, irq[2]; 1004fdc50a94SYusuke Goda struct mmc_host *mmc; 1005e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host; 1006e47bf32aSGuennadi Liakhovetski struct sh_mmcif_plat_data *pd; 1007fdc50a94SYusuke Goda struct resource *res; 1008fdc50a94SYusuke Goda void __iomem *reg; 1009fdc50a94SYusuke Goda char clk_name[8]; 1010fdc50a94SYusuke Goda 1011fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1012fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1013fdc50a94SYusuke Goda if (irq[0] < 0 || irq[1] < 0) { 1014e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "Get irq error\n"); 1015fdc50a94SYusuke Goda return -ENXIO; 1016fdc50a94SYusuke Goda } 1017fdc50a94SYusuke Goda res = platform_get_resource(pdev, IORESOURCE_MEM, 0); 1018fdc50a94SYusuke Goda if (!res) { 1019fdc50a94SYusuke Goda dev_err(&pdev->dev, "platform_get_resource error.\n"); 1020fdc50a94SYusuke Goda return -ENXIO; 1021fdc50a94SYusuke Goda } 1022fdc50a94SYusuke Goda reg = ioremap(res->start, resource_size(res)); 1023fdc50a94SYusuke Goda if (!reg) { 1024fdc50a94SYusuke Goda dev_err(&pdev->dev, "ioremap error.\n"); 1025fdc50a94SYusuke Goda return -ENOMEM; 1026fdc50a94SYusuke Goda } 1027e47bf32aSGuennadi Liakhovetski pd = pdev->dev.platform_data; 1028fdc50a94SYusuke Goda if (!pd) { 1029fdc50a94SYusuke Goda dev_err(&pdev->dev, "sh_mmcif plat data error.\n"); 1030fdc50a94SYusuke Goda ret = -ENXIO; 1031fdc50a94SYusuke Goda goto clean_up; 1032fdc50a94SYusuke Goda } 1033fdc50a94SYusuke Goda mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), &pdev->dev); 1034fdc50a94SYusuke Goda if (!mmc) { 1035fdc50a94SYusuke Goda ret = -ENOMEM; 1036fdc50a94SYusuke Goda goto clean_up; 1037fdc50a94SYusuke Goda } 1038fdc50a94SYusuke Goda host = mmc_priv(mmc); 1039fdc50a94SYusuke Goda host->mmc = mmc; 1040fdc50a94SYusuke Goda host->addr = reg; 1041fdc50a94SYusuke Goda host->timeout = 1000; 1042fdc50a94SYusuke Goda 1043fdc50a94SYusuke Goda snprintf(clk_name, sizeof(clk_name), "mmc%d", pdev->id); 1044fdc50a94SYusuke Goda host->hclk = clk_get(&pdev->dev, clk_name); 1045fdc50a94SYusuke Goda if (IS_ERR(host->hclk)) { 1046fdc50a94SYusuke Goda dev_err(&pdev->dev, "cannot get clock \"%s\"\n", clk_name); 1047fdc50a94SYusuke Goda ret = PTR_ERR(host->hclk); 1048fdc50a94SYusuke Goda goto clean_up1; 1049fdc50a94SYusuke Goda } 1050fdc50a94SYusuke Goda clk_enable(host->hclk); 1051fdc50a94SYusuke Goda host->clk = clk_get_rate(host->hclk); 1052fdc50a94SYusuke Goda host->pd = pdev; 1053fdc50a94SYusuke Goda 1054aa0787a9SGuennadi Liakhovetski init_completion(&host->intr_wait); 10553b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock); 1056fdc50a94SYusuke Goda 1057fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops; 1058fdc50a94SYusuke Goda mmc->f_max = host->clk; 1059fdc50a94SYusuke Goda /* close to 400KHz */ 1060fdc50a94SYusuke Goda if (mmc->f_max < 51200000) 1061fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 128; 1062fdc50a94SYusuke Goda else if (mmc->f_max < 102400000) 1063fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 256; 1064fdc50a94SYusuke Goda else 1065fdc50a94SYusuke Goda mmc->f_min = mmc->f_max / 512; 1066fdc50a94SYusuke Goda if (pd->ocr) 1067fdc50a94SYusuke Goda mmc->ocr_avail = pd->ocr; 1068fdc50a94SYusuke Goda mmc->caps = MMC_CAP_MMC_HIGHSPEED; 1069fdc50a94SYusuke Goda if (pd->caps) 1070fdc50a94SYusuke Goda mmc->caps |= pd->caps; 1071a782d688SGuennadi Liakhovetski mmc->max_segs = 32; 1072fdc50a94SYusuke Goda mmc->max_blk_size = 512; 1073a782d688SGuennadi Liakhovetski mmc->max_req_size = PAGE_CACHE_SIZE * mmc->max_segs; 1074a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size; 1075fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size; 1076fdc50a94SYusuke Goda 1077fdc50a94SYusuke Goda sh_mmcif_sync_reset(host); 1078fdc50a94SYusuke Goda platform_set_drvdata(pdev, host); 1079a782d688SGuennadi Liakhovetski 1080faca6648SGuennadi Liakhovetski pm_runtime_enable(&pdev->dev); 1081faca6648SGuennadi Liakhovetski host->power = false; 1082faca6648SGuennadi Liakhovetski 1083faca6648SGuennadi Liakhovetski ret = pm_runtime_resume(&pdev->dev); 1084faca6648SGuennadi Liakhovetski if (ret < 0) 1085faca6648SGuennadi Liakhovetski goto clean_up2; 1086a782d688SGuennadi Liakhovetski 1087fdc50a94SYusuke Goda mmc_add_host(mmc); 1088fdc50a94SYusuke Goda 10893b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 10903b0beafcSGuennadi Liakhovetski 1091fdc50a94SYusuke Goda ret = request_irq(irq[0], sh_mmcif_intr, 0, "sh_mmc:error", host); 1092fdc50a94SYusuke Goda if (ret) { 1093e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:error)\n"); 1094faca6648SGuennadi Liakhovetski goto clean_up3; 1095fdc50a94SYusuke Goda } 1096fdc50a94SYusuke Goda ret = request_irq(irq[1], sh_mmcif_intr, 0, "sh_mmc:int", host); 1097fdc50a94SYusuke Goda if (ret) { 1098fdc50a94SYusuke Goda free_irq(irq[0], host); 1099e47bf32aSGuennadi Liakhovetski dev_err(&pdev->dev, "request_irq error (sh_mmc:int)\n"); 1100faca6648SGuennadi Liakhovetski goto clean_up3; 1101fdc50a94SYusuke Goda } 1102fdc50a94SYusuke Goda 1103fdc50a94SYusuke Goda sh_mmcif_detect(host->mmc); 1104fdc50a94SYusuke Goda 1105e47bf32aSGuennadi Liakhovetski dev_info(&pdev->dev, "driver version %s\n", DRIVER_VERSION); 1106e47bf32aSGuennadi Liakhovetski dev_dbg(&pdev->dev, "chip ver H'%04x\n", 1107487d9fc5SMagnus Damm sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0x0000ffff); 1108fdc50a94SYusuke Goda return ret; 1109fdc50a94SYusuke Goda 1110faca6648SGuennadi Liakhovetski clean_up3: 1111faca6648SGuennadi Liakhovetski mmc_remove_host(mmc); 1112faca6648SGuennadi Liakhovetski pm_runtime_suspend(&pdev->dev); 1113fdc50a94SYusuke Goda clean_up2: 1114faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1115fdc50a94SYusuke Goda clk_disable(host->hclk); 1116fdc50a94SYusuke Goda clean_up1: 1117fdc50a94SYusuke Goda mmc_free_host(mmc); 1118fdc50a94SYusuke Goda clean_up: 1119fdc50a94SYusuke Goda if (reg) 1120fdc50a94SYusuke Goda iounmap(reg); 1121fdc50a94SYusuke Goda return ret; 1122fdc50a94SYusuke Goda } 1123fdc50a94SYusuke Goda 1124fdc50a94SYusuke Goda static int __devexit sh_mmcif_remove(struct platform_device *pdev) 1125fdc50a94SYusuke Goda { 1126fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1127fdc50a94SYusuke Goda int irq[2]; 1128fdc50a94SYusuke Goda 1129faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev); 1130aa0787a9SGuennadi Liakhovetski 1131faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc); 11323b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 11333b0beafcSGuennadi Liakhovetski 1134aa0787a9SGuennadi Liakhovetski if (host->addr) 1135aa0787a9SGuennadi Liakhovetski iounmap(host->addr); 1136aa0787a9SGuennadi Liakhovetski 1137fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0); 1138fdc50a94SYusuke Goda irq[1] = platform_get_irq(pdev, 1); 1139fdc50a94SYusuke Goda 1140fdc50a94SYusuke Goda free_irq(irq[0], host); 1141fdc50a94SYusuke Goda free_irq(irq[1], host); 1142fdc50a94SYusuke Goda 1143aa0787a9SGuennadi Liakhovetski platform_set_drvdata(pdev, NULL); 1144aa0787a9SGuennadi Liakhovetski 1145fdc50a94SYusuke Goda clk_disable(host->hclk); 1146fdc50a94SYusuke Goda mmc_free_host(host->mmc); 1147faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev); 1148faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev); 1149fdc50a94SYusuke Goda 1150fdc50a94SYusuke Goda return 0; 1151fdc50a94SYusuke Goda } 1152fdc50a94SYusuke Goda 1153faca6648SGuennadi Liakhovetski #ifdef CONFIG_PM 1154faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev) 1155faca6648SGuennadi Liakhovetski { 1156faca6648SGuennadi Liakhovetski struct platform_device *pdev = to_platform_device(dev); 1157faca6648SGuennadi Liakhovetski struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1158faca6648SGuennadi Liakhovetski int ret = mmc_suspend_host(host->mmc); 1159faca6648SGuennadi Liakhovetski 1160faca6648SGuennadi Liakhovetski if (!ret) { 1161faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL); 1162faca6648SGuennadi Liakhovetski clk_disable(host->hclk); 1163faca6648SGuennadi Liakhovetski } 1164faca6648SGuennadi Liakhovetski 1165faca6648SGuennadi Liakhovetski return ret; 1166faca6648SGuennadi Liakhovetski } 1167faca6648SGuennadi Liakhovetski 1168faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev) 1169faca6648SGuennadi Liakhovetski { 1170faca6648SGuennadi Liakhovetski struct platform_device *pdev = to_platform_device(dev); 1171faca6648SGuennadi Liakhovetski struct sh_mmcif_host *host = platform_get_drvdata(pdev); 1172faca6648SGuennadi Liakhovetski 1173faca6648SGuennadi Liakhovetski clk_enable(host->hclk); 1174faca6648SGuennadi Liakhovetski 1175faca6648SGuennadi Liakhovetski return mmc_resume_host(host->mmc); 1176faca6648SGuennadi Liakhovetski } 1177faca6648SGuennadi Liakhovetski #else 1178faca6648SGuennadi Liakhovetski #define sh_mmcif_suspend NULL 1179faca6648SGuennadi Liakhovetski #define sh_mmcif_resume NULL 1180faca6648SGuennadi Liakhovetski #endif /* CONFIG_PM */ 1181faca6648SGuennadi Liakhovetski 1182faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = { 1183faca6648SGuennadi Liakhovetski .suspend = sh_mmcif_suspend, 1184faca6648SGuennadi Liakhovetski .resume = sh_mmcif_resume, 1185faca6648SGuennadi Liakhovetski }; 1186faca6648SGuennadi Liakhovetski 1187fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = { 1188fdc50a94SYusuke Goda .probe = sh_mmcif_probe, 1189fdc50a94SYusuke Goda .remove = sh_mmcif_remove, 1190fdc50a94SYusuke Goda .driver = { 1191fdc50a94SYusuke Goda .name = DRIVER_NAME, 1192faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops, 1193fdc50a94SYusuke Goda }, 1194fdc50a94SYusuke Goda }; 1195fdc50a94SYusuke Goda 1196fdc50a94SYusuke Goda static int __init sh_mmcif_init(void) 1197fdc50a94SYusuke Goda { 1198fdc50a94SYusuke Goda return platform_driver_register(&sh_mmcif_driver); 1199fdc50a94SYusuke Goda } 1200fdc50a94SYusuke Goda 1201fdc50a94SYusuke Goda static void __exit sh_mmcif_exit(void) 1202fdc50a94SYusuke Goda { 1203fdc50a94SYusuke Goda platform_driver_unregister(&sh_mmcif_driver); 1204fdc50a94SYusuke Goda } 1205fdc50a94SYusuke Goda 1206fdc50a94SYusuke Goda module_init(sh_mmcif_init); 1207fdc50a94SYusuke Goda module_exit(sh_mmcif_exit); 1208fdc50a94SYusuke Goda 1209fdc50a94SYusuke Goda 1210fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver"); 1211fdc50a94SYusuke Goda MODULE_LICENSE("GPL"); 1212aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME); 1213fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>"); 1214