1f707079dSWolfram Sang // SPDX-License-Identifier: GPL-2.0
2fdc50a94SYusuke Goda /*
3fdc50a94SYusuke Goda * MMCIF eMMC driver.
4fdc50a94SYusuke Goda *
5fdc50a94SYusuke Goda * Copyright (C) 2010 Renesas Solutions Corp.
6fdc50a94SYusuke Goda * Yusuke Goda <yusuke.goda.sx@renesas.com>
7fdc50a94SYusuke Goda */
8fdc50a94SYusuke Goda
9f985da17SGuennadi Liakhovetski /*
10f985da17SGuennadi Liakhovetski * The MMCIF driver is now processing MMC requests asynchronously, according
11f985da17SGuennadi Liakhovetski * to the Linux MMC API requirement.
12f985da17SGuennadi Liakhovetski *
13f985da17SGuennadi Liakhovetski * The MMCIF driver processes MMC requests in up to 3 stages: command, optional
14f985da17SGuennadi Liakhovetski * data, and optional stop. To achieve asynchronous processing each of these
15f985da17SGuennadi Liakhovetski * stages is split into two halves: a top and a bottom half. The top half
16f985da17SGuennadi Liakhovetski * initialises the hardware, installs a timeout handler to handle completion
17f985da17SGuennadi Liakhovetski * timeouts, and returns. In case of the command stage this immediately returns
18f985da17SGuennadi Liakhovetski * control to the caller, leaving all further processing to run asynchronously.
19f985da17SGuennadi Liakhovetski * All further request processing is performed by the bottom halves.
20f985da17SGuennadi Liakhovetski *
21f985da17SGuennadi Liakhovetski * The bottom half further consists of a "hard" IRQ handler, an IRQ handler
22f985da17SGuennadi Liakhovetski * thread, a DMA completion callback, if DMA is used, a timeout work, and
23f985da17SGuennadi Liakhovetski * request- and stage-specific handler methods.
24f985da17SGuennadi Liakhovetski *
25f985da17SGuennadi Liakhovetski * Each bottom half run begins with either a hardware interrupt, a DMA callback
26f985da17SGuennadi Liakhovetski * invocation, or a timeout work run. In case of an error or a successful
27f985da17SGuennadi Liakhovetski * processing completion, the MMC core is informed and the request processing is
28f985da17SGuennadi Liakhovetski * finished. In case processing has to continue, i.e., if data has to be read
29f985da17SGuennadi Liakhovetski * from or written to the card, or if a stop command has to be sent, the next
30f985da17SGuennadi Liakhovetski * top half is called, which performs the necessary hardware handling and
31f985da17SGuennadi Liakhovetski * reschedules the timeout work. This returns the driver state machine into the
32f985da17SGuennadi Liakhovetski * bottom half waiting state.
33f985da17SGuennadi Liakhovetski */
34f985da17SGuennadi Liakhovetski
3586df1745SGuennadi Liakhovetski #include <linux/bitops.h>
36aa0787a9SGuennadi Liakhovetski #include <linux/clk.h>
37aa0787a9SGuennadi Liakhovetski #include <linux/completion.h>
38e47bf32aSGuennadi Liakhovetski #include <linux/delay.h>
39fdc50a94SYusuke Goda #include <linux/dma-mapping.h>
40a782d688SGuennadi Liakhovetski #include <linux/dmaengine.h>
41fdc50a94SYusuke Goda #include <linux/mmc/card.h>
42fdc50a94SYusuke Goda #include <linux/mmc/core.h>
43e47bf32aSGuennadi Liakhovetski #include <linux/mmc/host.h>
44fdc50a94SYusuke Goda #include <linux/mmc/mmc.h>
45fdc50a94SYusuke Goda #include <linux/mmc/sdio.h>
46e480606aSGuennadi Liakhovetski #include <linux/mmc/slot-gpio.h>
47bf68a812SGuennadi Liakhovetski #include <linux/mod_devicetable.h>
488047310eSGuennadi Liakhovetski #include <linux/mutex.h>
49a782d688SGuennadi Liakhovetski #include <linux/pagemap.h>
5013acb62cSWolfram Sang #include <linux/platform_data/sh_mmcif.h>
51e47bf32aSGuennadi Liakhovetski #include <linux/platform_device.h>
52efe6a8adSRafael J. Wysocki #include <linux/pm_qos.h>
53faca6648SGuennadi Liakhovetski #include <linux/pm_runtime.h>
54d00cadacSGuennadi Liakhovetski #include <linux/sh_dma.h>
553b0beafcSGuennadi Liakhovetski #include <linux/spinlock.h>
5688b47679SPaul Gortmaker #include <linux/module.h>
57fdc50a94SYusuke Goda
58fdc50a94SYusuke Goda #define DRIVER_NAME "sh_mmcif"
59fdc50a94SYusuke Goda
60fdc50a94SYusuke Goda /* CE_CMD_SET */
61fdc50a94SYusuke Goda #define CMD_MASK 0x3f000000
62fdc50a94SYusuke Goda #define CMD_SET_RTYP_NO ((0 << 23) | (0 << 22))
63fdc50a94SYusuke Goda #define CMD_SET_RTYP_6B ((0 << 23) | (1 << 22)) /* R1/R1b/R3/R4/R5 */
64fdc50a94SYusuke Goda #define CMD_SET_RTYP_17B ((1 << 23) | (0 << 22)) /* R2 */
65fdc50a94SYusuke Goda #define CMD_SET_RBSY (1 << 21) /* R1b */
66fdc50a94SYusuke Goda #define CMD_SET_CCSEN (1 << 20)
67fdc50a94SYusuke Goda #define CMD_SET_WDAT (1 << 19) /* 1: on data, 0: no data */
68fdc50a94SYusuke Goda #define CMD_SET_DWEN (1 << 18) /* 1: write, 0: read */
69fdc50a94SYusuke Goda #define CMD_SET_CMLTE (1 << 17) /* 1: multi block trans, 0: single */
70fdc50a94SYusuke Goda #define CMD_SET_CMD12EN (1 << 16) /* 1: CMD12 auto issue */
71fdc50a94SYusuke Goda #define CMD_SET_RIDXC_INDEX ((0 << 15) | (0 << 14)) /* index check */
72fdc50a94SYusuke Goda #define CMD_SET_RIDXC_BITS ((0 << 15) | (1 << 14)) /* check bits check */
73fdc50a94SYusuke Goda #define CMD_SET_RIDXC_NO ((1 << 15) | (0 << 14)) /* no check */
74fdc50a94SYusuke Goda #define CMD_SET_CRC7C ((0 << 13) | (0 << 12)) /* CRC7 check*/
75fdc50a94SYusuke Goda #define CMD_SET_CRC7C_BITS ((0 << 13) | (1 << 12)) /* check bits check*/
76fdc50a94SYusuke Goda #define CMD_SET_CRC7C_INTERNAL ((1 << 13) | (0 << 12)) /* internal CRC7 check*/
77fdc50a94SYusuke Goda #define CMD_SET_CRC16C (1 << 10) /* 0: CRC16 check*/
78fdc50a94SYusuke Goda #define CMD_SET_CRCSTE (1 << 8) /* 1: not receive CRC status */
79fdc50a94SYusuke Goda #define CMD_SET_TBIT (1 << 7) /* 1: tran mission bit "Low" */
80fdc50a94SYusuke Goda #define CMD_SET_OPDM (1 << 6) /* 1: open/drain */
81fdc50a94SYusuke Goda #define CMD_SET_CCSH (1 << 5)
82555061f9STeppei Kamijou #define CMD_SET_DARS (1 << 2) /* Dual Data Rate */
83fdc50a94SYusuke Goda #define CMD_SET_DATW_1 ((0 << 1) | (0 << 0)) /* 1bit */
84fdc50a94SYusuke Goda #define CMD_SET_DATW_4 ((0 << 1) | (1 << 0)) /* 4bit */
85fdc50a94SYusuke Goda #define CMD_SET_DATW_8 ((1 << 1) | (0 << 0)) /* 8bit */
86fdc50a94SYusuke Goda
87fdc50a94SYusuke Goda /* CE_CMD_CTRL */
88fdc50a94SYusuke Goda #define CMD_CTRL_BREAK (1 << 0)
89fdc50a94SYusuke Goda
90fdc50a94SYusuke Goda /* CE_BLOCK_SET */
91fdc50a94SYusuke Goda #define BLOCK_SIZE_MASK 0x0000ffff
92fdc50a94SYusuke Goda
93fdc50a94SYusuke Goda /* CE_INT */
94fdc50a94SYusuke Goda #define INT_CCSDE (1 << 29)
95fdc50a94SYusuke Goda #define INT_CMD12DRE (1 << 26)
96fdc50a94SYusuke Goda #define INT_CMD12RBE (1 << 25)
97fdc50a94SYusuke Goda #define INT_CMD12CRE (1 << 24)
98fdc50a94SYusuke Goda #define INT_DTRANE (1 << 23)
99fdc50a94SYusuke Goda #define INT_BUFRE (1 << 22)
100fdc50a94SYusuke Goda #define INT_BUFWEN (1 << 21)
101fdc50a94SYusuke Goda #define INT_BUFREN (1 << 20)
102fdc50a94SYusuke Goda #define INT_CCSRCV (1 << 19)
103fdc50a94SYusuke Goda #define INT_RBSYE (1 << 17)
104fdc50a94SYusuke Goda #define INT_CRSPE (1 << 16)
105fdc50a94SYusuke Goda #define INT_CMDVIO (1 << 15)
106fdc50a94SYusuke Goda #define INT_BUFVIO (1 << 14)
107fdc50a94SYusuke Goda #define INT_WDATERR (1 << 11)
108fdc50a94SYusuke Goda #define INT_RDATERR (1 << 10)
109fdc50a94SYusuke Goda #define INT_RIDXERR (1 << 9)
110fdc50a94SYusuke Goda #define INT_RSPERR (1 << 8)
111fdc50a94SYusuke Goda #define INT_CCSTO (1 << 5)
112fdc50a94SYusuke Goda #define INT_CRCSTO (1 << 4)
113fdc50a94SYusuke Goda #define INT_WDATTO (1 << 3)
114fdc50a94SYusuke Goda #define INT_RDATTO (1 << 2)
115fdc50a94SYusuke Goda #define INT_RBSYTO (1 << 1)
116fdc50a94SYusuke Goda #define INT_RSPTO (1 << 0)
117fdc50a94SYusuke Goda #define INT_ERR_STS (INT_CMDVIO | INT_BUFVIO | INT_WDATERR | \
118fdc50a94SYusuke Goda INT_RDATERR | INT_RIDXERR | INT_RSPERR | \
119fdc50a94SYusuke Goda INT_CCSTO | INT_CRCSTO | INT_WDATTO | \
120fdc50a94SYusuke Goda INT_RDATTO | INT_RBSYTO | INT_RSPTO)
121fdc50a94SYusuke Goda
1228af50750SGuennadi Liakhovetski #define INT_ALL (INT_RBSYE | INT_CRSPE | INT_BUFREN | \
1238af50750SGuennadi Liakhovetski INT_BUFWEN | INT_CMD12DRE | INT_BUFRE | \
1248af50750SGuennadi Liakhovetski INT_DTRANE | INT_CMD12RBE | INT_CMD12CRE)
1258af50750SGuennadi Liakhovetski
126967bcb77SGuennadi Liakhovetski #define INT_CCS (INT_CCSTO | INT_CCSRCV | INT_CCSDE)
127967bcb77SGuennadi Liakhovetski
128fdc50a94SYusuke Goda /* CE_INT_MASK */
129fdc50a94SYusuke Goda #define MASK_ALL 0x00000000
130fdc50a94SYusuke Goda #define MASK_MCCSDE (1 << 29)
131fdc50a94SYusuke Goda #define MASK_MCMD12DRE (1 << 26)
132fdc50a94SYusuke Goda #define MASK_MCMD12RBE (1 << 25)
133fdc50a94SYusuke Goda #define MASK_MCMD12CRE (1 << 24)
134fdc50a94SYusuke Goda #define MASK_MDTRANE (1 << 23)
135fdc50a94SYusuke Goda #define MASK_MBUFRE (1 << 22)
136fdc50a94SYusuke Goda #define MASK_MBUFWEN (1 << 21)
137fdc50a94SYusuke Goda #define MASK_MBUFREN (1 << 20)
138fdc50a94SYusuke Goda #define MASK_MCCSRCV (1 << 19)
139fdc50a94SYusuke Goda #define MASK_MRBSYE (1 << 17)
140fdc50a94SYusuke Goda #define MASK_MCRSPE (1 << 16)
141fdc50a94SYusuke Goda #define MASK_MCMDVIO (1 << 15)
142fdc50a94SYusuke Goda #define MASK_MBUFVIO (1 << 14)
143fdc50a94SYusuke Goda #define MASK_MWDATERR (1 << 11)
144fdc50a94SYusuke Goda #define MASK_MRDATERR (1 << 10)
145fdc50a94SYusuke Goda #define MASK_MRIDXERR (1 << 9)
146fdc50a94SYusuke Goda #define MASK_MRSPERR (1 << 8)
147fdc50a94SYusuke Goda #define MASK_MCCSTO (1 << 5)
148fdc50a94SYusuke Goda #define MASK_MCRCSTO (1 << 4)
149fdc50a94SYusuke Goda #define MASK_MWDATTO (1 << 3)
150fdc50a94SYusuke Goda #define MASK_MRDATTO (1 << 2)
151fdc50a94SYusuke Goda #define MASK_MRBSYTO (1 << 1)
152fdc50a94SYusuke Goda #define MASK_MRSPTO (1 << 0)
153fdc50a94SYusuke Goda
154ee4b8887SGuennadi Liakhovetski #define MASK_START_CMD (MASK_MCMDVIO | MASK_MBUFVIO | MASK_MWDATERR | \
155ee4b8887SGuennadi Liakhovetski MASK_MRDATERR | MASK_MRIDXERR | MASK_MRSPERR | \
156967bcb77SGuennadi Liakhovetski MASK_MCRCSTO | MASK_MWDATTO | \
157ee4b8887SGuennadi Liakhovetski MASK_MRDATTO | MASK_MRBSYTO | MASK_MRSPTO)
158ee4b8887SGuennadi Liakhovetski
1598af50750SGuennadi Liakhovetski #define MASK_CLEAN (INT_ERR_STS | MASK_MRBSYE | MASK_MCRSPE | \
1608af50750SGuennadi Liakhovetski MASK_MBUFREN | MASK_MBUFWEN | \
1618af50750SGuennadi Liakhovetski MASK_MCMD12DRE | MASK_MBUFRE | MASK_MDTRANE | \
1628af50750SGuennadi Liakhovetski MASK_MCMD12RBE | MASK_MCMD12CRE)
1638af50750SGuennadi Liakhovetski
164fdc50a94SYusuke Goda /* CE_HOST_STS1 */
165fdc50a94SYusuke Goda #define STS1_CMDSEQ (1 << 31)
166fdc50a94SYusuke Goda
167fdc50a94SYusuke Goda /* CE_HOST_STS2 */
168fdc50a94SYusuke Goda #define STS2_CRCSTE (1 << 31)
169fdc50a94SYusuke Goda #define STS2_CRC16E (1 << 30)
170fdc50a94SYusuke Goda #define STS2_AC12CRCE (1 << 29)
171fdc50a94SYusuke Goda #define STS2_RSPCRC7E (1 << 28)
172fdc50a94SYusuke Goda #define STS2_CRCSTEBE (1 << 27)
173fdc50a94SYusuke Goda #define STS2_RDATEBE (1 << 26)
174fdc50a94SYusuke Goda #define STS2_AC12REBE (1 << 25)
175fdc50a94SYusuke Goda #define STS2_RSPEBE (1 << 24)
176fdc50a94SYusuke Goda #define STS2_AC12IDXE (1 << 23)
177fdc50a94SYusuke Goda #define STS2_RSPIDXE (1 << 22)
178fdc50a94SYusuke Goda #define STS2_CCSTO (1 << 15)
179fdc50a94SYusuke Goda #define STS2_RDATTO (1 << 14)
180fdc50a94SYusuke Goda #define STS2_DATBSYTO (1 << 13)
181fdc50a94SYusuke Goda #define STS2_CRCSTTO (1 << 12)
182fdc50a94SYusuke Goda #define STS2_AC12BSYTO (1 << 11)
183fdc50a94SYusuke Goda #define STS2_RSPBSYTO (1 << 10)
184fdc50a94SYusuke Goda #define STS2_AC12RSPTO (1 << 9)
185fdc50a94SYusuke Goda #define STS2_RSPTO (1 << 8)
186fdc50a94SYusuke Goda #define STS2_CRC_ERR (STS2_CRCSTE | STS2_CRC16E | \
187fdc50a94SYusuke Goda STS2_AC12CRCE | STS2_RSPCRC7E | STS2_CRCSTEBE)
188fdc50a94SYusuke Goda #define STS2_TIMEOUT_ERR (STS2_CCSTO | STS2_RDATTO | \
189fdc50a94SYusuke Goda STS2_DATBSYTO | STS2_CRCSTTO | \
190fdc50a94SYusuke Goda STS2_AC12BSYTO | STS2_RSPBSYTO | \
191fdc50a94SYusuke Goda STS2_AC12RSPTO | STS2_RSPTO)
192fdc50a94SYusuke Goda
193fdc50a94SYusuke Goda #define CLKDEV_EMMC_DATA 52000000 /* 52 MHz */
194fdc50a94SYusuke Goda #define CLKDEV_MMC_DATA 20000000 /* 20 MHz */
195b9a349fdSGeert Uytterhoeven #define CLKDEV_INIT 400000 /* 400 kHz */
196fdc50a94SYusuke Goda
1971b1a694dSKuninori Morimoto enum sh_mmcif_state {
1983b0beafcSGuennadi Liakhovetski STATE_IDLE,
1993b0beafcSGuennadi Liakhovetski STATE_REQUEST,
2003b0beafcSGuennadi Liakhovetski STATE_IOS,
2018047310eSGuennadi Liakhovetski STATE_TIMEOUT,
2023b0beafcSGuennadi Liakhovetski };
2033b0beafcSGuennadi Liakhovetski
2041b1a694dSKuninori Morimoto enum sh_mmcif_wait_for {
205f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_REQUEST,
206f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_CMD,
207f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MREAD,
208f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_MWRITE,
209f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ,
210f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE,
211f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_READ_END,
212f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_WRITE_END,
213f985da17SGuennadi Liakhovetski MMCIF_WAIT_FOR_STOP,
214f985da17SGuennadi Liakhovetski };
215f985da17SGuennadi Liakhovetski
21689d49a70SKuninori Morimoto /*
21789d49a70SKuninori Morimoto * difference for each SoC
21889d49a70SKuninori Morimoto */
219fdc50a94SYusuke Goda struct sh_mmcif_host {
220fdc50a94SYusuke Goda struct mmc_host *mmc;
221f985da17SGuennadi Liakhovetski struct mmc_request *mrq;
222fdc50a94SYusuke Goda struct platform_device *pd;
2236aed678bSKuninori Morimoto struct clk *clk;
224fdc50a94SYusuke Goda int bus_width;
225555061f9STeppei Kamijou unsigned char timing;
226aa0787a9SGuennadi Liakhovetski bool sd_error;
227f985da17SGuennadi Liakhovetski bool dying;
228fdc50a94SYusuke Goda long timeout;
229fdc50a94SYusuke Goda void __iomem *addr;
230f985da17SGuennadi Liakhovetski u32 *pio_ptr;
231ee4b8887SGuennadi Liakhovetski spinlock_t lock; /* protect sh_mmcif_host::state */
2321b1a694dSKuninori Morimoto enum sh_mmcif_state state;
2331b1a694dSKuninori Morimoto enum sh_mmcif_wait_for wait_for;
234f985da17SGuennadi Liakhovetski struct delayed_work timeout_work;
235f985da17SGuennadi Liakhovetski size_t blocksize;
236f985da17SGuennadi Liakhovetski int sg_idx;
237f985da17SGuennadi Liakhovetski int sg_blkidx;
238faca6648SGuennadi Liakhovetski bool power;
239967bcb77SGuennadi Liakhovetski bool ccs_enable; /* Command Completion Signal support */
2406d6fd367SGuennadi Liakhovetski bool clk_ctrl2_enable;
2418047310eSGuennadi Liakhovetski struct mutex thread_lock;
24289d49a70SKuninori Morimoto u32 clkdiv_map; /* see CE_CLK_CTRL::CLKDIV */
243fdc50a94SYusuke Goda
244a782d688SGuennadi Liakhovetski /* DMA support */
245a782d688SGuennadi Liakhovetski struct dma_chan *chan_rx;
246a782d688SGuennadi Liakhovetski struct dma_chan *chan_tx;
247a782d688SGuennadi Liakhovetski struct completion dma_complete;
248f38f94c6SLinus Walleij bool dma_active;
249a782d688SGuennadi Liakhovetski };
250fdc50a94SYusuke Goda
2511b1a694dSKuninori Morimoto static const struct of_device_id sh_mmcif_of_match[] = {
25270830b41SKuninori Morimoto { .compatible = "renesas,sh-mmcif" },
25370830b41SKuninori Morimoto { }
25470830b41SKuninori Morimoto };
2551b1a694dSKuninori Morimoto MODULE_DEVICE_TABLE(of, sh_mmcif_of_match);
25670830b41SKuninori Morimoto
257585c3a5aSKuninori Morimoto #define sh_mmcif_host_to_dev(host) (&host->pd->dev)
258585c3a5aSKuninori Morimoto
sh_mmcif_bitset(struct sh_mmcif_host * host,unsigned int reg,u32 val)259fdc50a94SYusuke Goda static inline void sh_mmcif_bitset(struct sh_mmcif_host *host,
260fdc50a94SYusuke Goda unsigned int reg, u32 val)
261fdc50a94SYusuke Goda {
262487d9fc5SMagnus Damm writel(val | readl(host->addr + reg), host->addr + reg);
263fdc50a94SYusuke Goda }
264fdc50a94SYusuke Goda
sh_mmcif_bitclr(struct sh_mmcif_host * host,unsigned int reg,u32 val)265fdc50a94SYusuke Goda static inline void sh_mmcif_bitclr(struct sh_mmcif_host *host,
266fdc50a94SYusuke Goda unsigned int reg, u32 val)
267fdc50a94SYusuke Goda {
268487d9fc5SMagnus Damm writel(~val & readl(host->addr + reg), host->addr + reg);
269fdc50a94SYusuke Goda }
270fdc50a94SYusuke Goda
sh_mmcif_dma_complete(void * arg)2711b1a694dSKuninori Morimoto static void sh_mmcif_dma_complete(void *arg)
272a782d688SGuennadi Liakhovetski {
273a782d688SGuennadi Liakhovetski struct sh_mmcif_host *host = arg;
2748047310eSGuennadi Liakhovetski struct mmc_request *mrq = host->mrq;
275585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
27669983404SGuennadi Liakhovetski
277585c3a5aSKuninori Morimoto dev_dbg(dev, "Command completed\n");
278a782d688SGuennadi Liakhovetski
2798047310eSGuennadi Liakhovetski if (WARN(!mrq || !mrq->data, "%s: NULL data in DMA completion!\n",
280585c3a5aSKuninori Morimoto dev_name(dev)))
281a782d688SGuennadi Liakhovetski return;
282a782d688SGuennadi Liakhovetski
283a782d688SGuennadi Liakhovetski complete(&host->dma_complete);
284a782d688SGuennadi Liakhovetski }
285a782d688SGuennadi Liakhovetski
sh_mmcif_start_dma_rx(struct sh_mmcif_host * host)286a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_rx(struct sh_mmcif_host *host)
287a782d688SGuennadi Liakhovetski {
28869983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
28969983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg;
290a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL;
291a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx;
292585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
293a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL;
294a782d688SGuennadi Liakhovetski int ret;
295a782d688SGuennadi Liakhovetski
29669983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
2971ed828dbSLinus Walleij DMA_FROM_DEVICE);
298a782d688SGuennadi Liakhovetski if (ret > 0) {
299f38f94c6SLinus Walleij host->dma_active = true;
30016052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret,
30105f5799cSVinod Koul DMA_DEV_TO_MEM, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
302a782d688SGuennadi Liakhovetski }
303a782d688SGuennadi Liakhovetski
304a782d688SGuennadi Liakhovetski if (desc) {
3051b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete;
306a782d688SGuennadi Liakhovetski desc->callback_param = host;
307a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc);
308a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN);
309a5ece7d2SLinus Walleij dma_async_issue_pending(chan);
310a782d688SGuennadi Liakhovetski }
311585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",
31269983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie);
313a782d688SGuennadi Liakhovetski
314a782d688SGuennadi Liakhovetski if (!desc) {
315a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */
316a782d688SGuennadi Liakhovetski if (ret >= 0)
317a782d688SGuennadi Liakhovetski ret = -EIO;
318a782d688SGuennadi Liakhovetski host->chan_rx = NULL;
319f38f94c6SLinus Walleij host->dma_active = false;
320a782d688SGuennadi Liakhovetski dma_release_channel(chan);
321a782d688SGuennadi Liakhovetski /* Free the Tx channel too */
322a782d688SGuennadi Liakhovetski chan = host->chan_tx;
323a782d688SGuennadi Liakhovetski if (chan) {
324a782d688SGuennadi Liakhovetski host->chan_tx = NULL;
325a782d688SGuennadi Liakhovetski dma_release_channel(chan);
326a782d688SGuennadi Liakhovetski }
327585c3a5aSKuninori Morimoto dev_warn(dev,
328a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret);
329a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
330a782d688SGuennadi Liakhovetski }
331a782d688SGuennadi Liakhovetski
332585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d, sg[%d]\n", __func__,
33369983404SGuennadi Liakhovetski desc, cookie, data->sg_len);
334a782d688SGuennadi Liakhovetski }
335a782d688SGuennadi Liakhovetski
sh_mmcif_start_dma_tx(struct sh_mmcif_host * host)336a782d688SGuennadi Liakhovetski static void sh_mmcif_start_dma_tx(struct sh_mmcif_host *host)
337a782d688SGuennadi Liakhovetski {
33869983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
33969983404SGuennadi Liakhovetski struct scatterlist *sg = data->sg;
340a782d688SGuennadi Liakhovetski struct dma_async_tx_descriptor *desc = NULL;
341a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx;
342585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
343a782d688SGuennadi Liakhovetski dma_cookie_t cookie = -EINVAL;
344a782d688SGuennadi Liakhovetski int ret;
345a782d688SGuennadi Liakhovetski
34669983404SGuennadi Liakhovetski ret = dma_map_sg(chan->device->dev, sg, data->sg_len,
3471ed828dbSLinus Walleij DMA_TO_DEVICE);
348a782d688SGuennadi Liakhovetski if (ret > 0) {
349f38f94c6SLinus Walleij host->dma_active = true;
35016052827SAlexandre Bounine desc = dmaengine_prep_slave_sg(chan, sg, ret,
35105f5799cSVinod Koul DMA_MEM_TO_DEV, DMA_PREP_INTERRUPT | DMA_CTRL_ACK);
352a782d688SGuennadi Liakhovetski }
353a782d688SGuennadi Liakhovetski
354a782d688SGuennadi Liakhovetski if (desc) {
3551b1a694dSKuninori Morimoto desc->callback = sh_mmcif_dma_complete;
356a782d688SGuennadi Liakhovetski desc->callback_param = host;
357a5ece7d2SLinus Walleij cookie = dmaengine_submit(desc);
358a782d688SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAWEN);
359a5ece7d2SLinus Walleij dma_async_issue_pending(chan);
360a782d688SGuennadi Liakhovetski }
361585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): mapped %d -> %d, cookie %d\n",
36269983404SGuennadi Liakhovetski __func__, data->sg_len, ret, cookie);
363a782d688SGuennadi Liakhovetski
364a782d688SGuennadi Liakhovetski if (!desc) {
365a782d688SGuennadi Liakhovetski /* DMA failed, fall back to PIO */
366a782d688SGuennadi Liakhovetski if (ret >= 0)
367a782d688SGuennadi Liakhovetski ret = -EIO;
368a782d688SGuennadi Liakhovetski host->chan_tx = NULL;
369f38f94c6SLinus Walleij host->dma_active = false;
370a782d688SGuennadi Liakhovetski dma_release_channel(chan);
371a782d688SGuennadi Liakhovetski /* Free the Rx channel too */
372a782d688SGuennadi Liakhovetski chan = host->chan_rx;
373a782d688SGuennadi Liakhovetski if (chan) {
374a782d688SGuennadi Liakhovetski host->chan_rx = NULL;
375a782d688SGuennadi Liakhovetski dma_release_channel(chan);
376a782d688SGuennadi Liakhovetski }
377585c3a5aSKuninori Morimoto dev_warn(dev,
378a782d688SGuennadi Liakhovetski "DMA failed: %d, falling back to PIO\n", ret);
379a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
380a782d688SGuennadi Liakhovetski }
381a782d688SGuennadi Liakhovetski
382585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): desc %p, cookie %d\n", __func__,
383a782d688SGuennadi Liakhovetski desc, cookie);
384a782d688SGuennadi Liakhovetski }
385a782d688SGuennadi Liakhovetski
386e5a233cbSLaurent Pinchart static struct dma_chan *
sh_mmcif_request_dma_pdata(struct sh_mmcif_host * host,uintptr_t slave_id)38727cbd7e8SArnd Bergmann sh_mmcif_request_dma_pdata(struct sh_mmcif_host *host, uintptr_t slave_id)
388a782d688SGuennadi Liakhovetski {
3890e79f9aeSGuennadi Liakhovetski dma_cap_mask_t mask;
3900e79f9aeSGuennadi Liakhovetski
391e5a233cbSLaurent Pinchart dma_cap_zero(mask);
392e5a233cbSLaurent Pinchart dma_cap_set(DMA_SLAVE, mask);
39327cbd7e8SArnd Bergmann if (slave_id <= 0)
394e5a233cbSLaurent Pinchart return NULL;
395e5a233cbSLaurent Pinchart
39627cbd7e8SArnd Bergmann return dma_request_channel(mask, shdma_chan_filter, (void *)slave_id);
39727cbd7e8SArnd Bergmann }
398e5a233cbSLaurent Pinchart
sh_mmcif_dma_slave_config(struct sh_mmcif_host * host,struct dma_chan * chan,enum dma_transfer_direction direction)39927cbd7e8SArnd Bergmann static int sh_mmcif_dma_slave_config(struct sh_mmcif_host *host,
40027cbd7e8SArnd Bergmann struct dma_chan *chan,
40127cbd7e8SArnd Bergmann enum dma_transfer_direction direction)
40227cbd7e8SArnd Bergmann {
40327cbd7e8SArnd Bergmann struct resource *res;
40427cbd7e8SArnd Bergmann struct dma_slave_config cfg = { 0, };
40527cbd7e8SArnd Bergmann
40627cbd7e8SArnd Bergmann res = platform_get_resource(host->pd, IORESOURCE_MEM, 0);
4074d315357SJiasheng Jiang if (!res)
4084d315357SJiasheng Jiang return -EINVAL;
4094d315357SJiasheng Jiang
410e5a233cbSLaurent Pinchart cfg.direction = direction;
411d25006e7SLaurent Pinchart
412e36152aaSLaurent Pinchart if (direction == DMA_DEV_TO_MEM) {
413d25006e7SLaurent Pinchart cfg.src_addr = res->start + MMCIF_CE_DATA;
414e36152aaSLaurent Pinchart cfg.src_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
415e36152aaSLaurent Pinchart } else {
416e5a233cbSLaurent Pinchart cfg.dst_addr = res->start + MMCIF_CE_DATA;
417e36152aaSLaurent Pinchart cfg.dst_addr_width = DMA_SLAVE_BUSWIDTH_4_BYTES;
418e36152aaSLaurent Pinchart }
419d25006e7SLaurent Pinchart
42027cbd7e8SArnd Bergmann return dmaengine_slave_config(chan, &cfg);
421e5a233cbSLaurent Pinchart }
422e5a233cbSLaurent Pinchart
sh_mmcif_request_dma(struct sh_mmcif_host * host)42327cbd7e8SArnd Bergmann static void sh_mmcif_request_dma(struct sh_mmcif_host *host)
424e5a233cbSLaurent Pinchart {
425585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
426f38f94c6SLinus Walleij host->dma_active = false;
427a782d688SGuennadi Liakhovetski
428a782d688SGuennadi Liakhovetski /* We can only either use DMA for both Tx and Rx or not use it at all */
42927cbd7e8SArnd Bergmann if (IS_ENABLED(CONFIG_SUPERH) && dev->platform_data) {
43027cbd7e8SArnd Bergmann struct sh_mmcif_plat_data *pdata = dev->platform_data;
43127cbd7e8SArnd Bergmann
43227cbd7e8SArnd Bergmann host->chan_tx = sh_mmcif_request_dma_pdata(host,
43327cbd7e8SArnd Bergmann pdata->slave_id_tx);
43427cbd7e8SArnd Bergmann host->chan_rx = sh_mmcif_request_dma_pdata(host,
43527cbd7e8SArnd Bergmann pdata->slave_id_rx);
43627cbd7e8SArnd Bergmann } else {
437b67b4517SPeter Ujfalusi host->chan_tx = dma_request_chan(dev, "tx");
438b67b4517SPeter Ujfalusi if (IS_ERR(host->chan_tx))
439b67b4517SPeter Ujfalusi host->chan_tx = NULL;
440b67b4517SPeter Ujfalusi host->chan_rx = dma_request_chan(dev, "rx");
441b67b4517SPeter Ujfalusi if (IS_ERR(host->chan_rx))
442b67b4517SPeter Ujfalusi host->chan_rx = NULL;
44327cbd7e8SArnd Bergmann }
44427cbd7e8SArnd Bergmann dev_dbg(dev, "%s: got channel TX %p RX %p\n", __func__, host->chan_tx,
44527cbd7e8SArnd Bergmann host->chan_rx);
44627cbd7e8SArnd Bergmann
44727cbd7e8SArnd Bergmann if (!host->chan_tx || !host->chan_rx ||
44827cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_tx, DMA_MEM_TO_DEV) ||
44927cbd7e8SArnd Bergmann sh_mmcif_dma_slave_config(host, host->chan_rx, DMA_DEV_TO_MEM))
45027cbd7e8SArnd Bergmann goto error;
45127cbd7e8SArnd Bergmann
452a782d688SGuennadi Liakhovetski return;
453a782d688SGuennadi Liakhovetski
45427cbd7e8SArnd Bergmann error:
45527cbd7e8SArnd Bergmann if (host->chan_tx)
4560e79f9aeSGuennadi Liakhovetski dma_release_channel(host->chan_tx);
45727cbd7e8SArnd Bergmann if (host->chan_rx)
45827cbd7e8SArnd Bergmann dma_release_channel(host->chan_rx);
45927cbd7e8SArnd Bergmann host->chan_tx = host->chan_rx = NULL;
460e5a233cbSLaurent Pinchart }
461a782d688SGuennadi Liakhovetski
sh_mmcif_release_dma(struct sh_mmcif_host * host)462a782d688SGuennadi Liakhovetski static void sh_mmcif_release_dma(struct sh_mmcif_host *host)
463a782d688SGuennadi Liakhovetski {
464a782d688SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC, BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
465a782d688SGuennadi Liakhovetski /* Descriptors are freed automatically */
466a782d688SGuennadi Liakhovetski if (host->chan_tx) {
467a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_tx;
468a782d688SGuennadi Liakhovetski host->chan_tx = NULL;
469a782d688SGuennadi Liakhovetski dma_release_channel(chan);
470a782d688SGuennadi Liakhovetski }
471a782d688SGuennadi Liakhovetski if (host->chan_rx) {
472a782d688SGuennadi Liakhovetski struct dma_chan *chan = host->chan_rx;
473a782d688SGuennadi Liakhovetski host->chan_rx = NULL;
474a782d688SGuennadi Liakhovetski dma_release_channel(chan);
475a782d688SGuennadi Liakhovetski }
476a782d688SGuennadi Liakhovetski
477f38f94c6SLinus Walleij host->dma_active = false;
478a782d688SGuennadi Liakhovetski }
479fdc50a94SYusuke Goda
sh_mmcif_clock_control(struct sh_mmcif_host * host,unsigned int clk)480fdc50a94SYusuke Goda static void sh_mmcif_clock_control(struct sh_mmcif_host *host, unsigned int clk)
481fdc50a94SYusuke Goda {
482585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
483585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *p = dev->platform_data;
484bf68a812SGuennadi Liakhovetski bool sup_pclk = p ? p->sup_pclk : false;
4856aed678bSKuninori Morimoto unsigned int current_clk = clk_get_rate(host->clk);
48689d49a70SKuninori Morimoto unsigned int clkdiv;
487fdc50a94SYusuke Goda
488fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
489fdc50a94SYusuke Goda sh_mmcif_bitclr(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR);
490fdc50a94SYusuke Goda
491fdc50a94SYusuke Goda if (!clk)
492fdc50a94SYusuke Goda return;
493fdc50a94SYusuke Goda
49489d49a70SKuninori Morimoto if (host->clkdiv_map) {
49589d49a70SKuninori Morimoto unsigned int freq, best_freq, myclk, div, diff_min, diff;
49689d49a70SKuninori Morimoto int i;
49789d49a70SKuninori Morimoto
49889d49a70SKuninori Morimoto clkdiv = 0;
49989d49a70SKuninori Morimoto diff_min = ~0;
50089d49a70SKuninori Morimoto best_freq = 0;
50189d49a70SKuninori Morimoto for (i = 31; i >= 0; i--) {
50289d49a70SKuninori Morimoto if (!((1 << i) & host->clkdiv_map))
50389d49a70SKuninori Morimoto continue;
50489d49a70SKuninori Morimoto
50589d49a70SKuninori Morimoto /*
50689d49a70SKuninori Morimoto * clk = parent_freq / div
50789d49a70SKuninori Morimoto * -> parent_freq = clk x div
50889d49a70SKuninori Morimoto */
50989d49a70SKuninori Morimoto
51089d49a70SKuninori Morimoto div = 1 << (i + 1);
51189d49a70SKuninori Morimoto freq = clk_round_rate(host->clk, clk * div);
51289d49a70SKuninori Morimoto myclk = freq / div;
51389d49a70SKuninori Morimoto diff = (myclk > clk) ? myclk - clk : clk - myclk;
51489d49a70SKuninori Morimoto
51589d49a70SKuninori Morimoto if (diff <= diff_min) {
51689d49a70SKuninori Morimoto best_freq = freq;
51789d49a70SKuninori Morimoto clkdiv = i;
51889d49a70SKuninori Morimoto diff_min = diff;
51989d49a70SKuninori Morimoto }
52089d49a70SKuninori Morimoto }
52189d49a70SKuninori Morimoto
52289d49a70SKuninori Morimoto dev_dbg(dev, "clk %u/%u (%u, 0x%x)\n",
523bee15491SGeert Uytterhoeven (best_freq >> (clkdiv + 1)), clk, best_freq, clkdiv);
52489d49a70SKuninori Morimoto
52589d49a70SKuninori Morimoto clk_set_rate(host->clk, best_freq);
52689d49a70SKuninori Morimoto clkdiv = clkdiv << 16;
52789d49a70SKuninori Morimoto } else if (sup_pclk && clk == current_clk) {
52889d49a70SKuninori Morimoto clkdiv = CLK_SUP_PCLK;
52989d49a70SKuninori Morimoto } else {
53089d49a70SKuninori Morimoto clkdiv = (fls(DIV_ROUND_UP(current_clk, clk) - 1) - 1) << 16;
53189d49a70SKuninori Morimoto }
53289d49a70SKuninori Morimoto
53389d49a70SKuninori Morimoto sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_CLEAR & clkdiv);
534fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, CLK_ENABLE);
535fdc50a94SYusuke Goda }
536fdc50a94SYusuke Goda
sh_mmcif_sync_reset(struct sh_mmcif_host * host)537fdc50a94SYusuke Goda static void sh_mmcif_sync_reset(struct sh_mmcif_host *host)
538fdc50a94SYusuke Goda {
539fdc50a94SYusuke Goda u32 tmp;
540fdc50a94SYusuke Goda
541487d9fc5SMagnus Damm tmp = 0x010f0000 & sh_mmcif_readl(host->addr, MMCIF_CE_CLK_CTRL);
542fdc50a94SYusuke Goda
543487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_ON);
544487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_VERSION, SOFT_RST_OFF);
545967bcb77SGuennadi Liakhovetski if (host->ccs_enable)
546967bcb77SGuennadi Liakhovetski tmp |= SCCSTO_29;
5476d6fd367SGuennadi Liakhovetski if (host->clk_ctrl2_enable)
5486d6fd367SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_CLK_CTRL2, 0x0F0F0000);
549fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CLK_CTRL, tmp |
550967bcb77SGuennadi Liakhovetski SRSPTO_256 | SRBSYTO_29 | SRWDTO_29);
551fdc50a94SYusuke Goda /* byte swap on */
552fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BUF_ACC, BUF_ACC_ATYP);
553fdc50a94SYusuke Goda }
554fdc50a94SYusuke Goda
sh_mmcif_error_manage(struct sh_mmcif_host * host)555fdc50a94SYusuke Goda static int sh_mmcif_error_manage(struct sh_mmcif_host *host)
556fdc50a94SYusuke Goda {
557585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
558fdc50a94SYusuke Goda u32 state1, state2;
559ee4b8887SGuennadi Liakhovetski int ret, timeout;
560fdc50a94SYusuke Goda
561aa0787a9SGuennadi Liakhovetski host->sd_error = false;
562fdc50a94SYusuke Goda
563487d9fc5SMagnus Damm state1 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1);
564487d9fc5SMagnus Damm state2 = sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS2);
565585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS1 = %08x\n", state1);
566585c3a5aSKuninori Morimoto dev_dbg(dev, "ERR HOST_STS2 = %08x\n", state2);
567fdc50a94SYusuke Goda
568fdc50a94SYusuke Goda if (state1 & STS1_CMDSEQ) {
569fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, CMD_CTRL_BREAK);
570fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_CMD_CTRL, ~CMD_CTRL_BREAK);
57152e00b84SUlf Hansson for (timeout = 10000; timeout; timeout--) {
572487d9fc5SMagnus Damm if (!(sh_mmcif_readl(host->addr, MMCIF_CE_HOST_STS1)
573fdc50a94SYusuke Goda & STS1_CMDSEQ))
574fdc50a94SYusuke Goda break;
575fdc50a94SYusuke Goda mdelay(1);
576fdc50a94SYusuke Goda }
577ee4b8887SGuennadi Liakhovetski if (!timeout) {
578585c3a5aSKuninori Morimoto dev_err(dev,
579ee4b8887SGuennadi Liakhovetski "Forced end of command sequence timeout err\n");
580ee4b8887SGuennadi Liakhovetski return -EIO;
581ee4b8887SGuennadi Liakhovetski }
582fdc50a94SYusuke Goda sh_mmcif_sync_reset(host);
583585c3a5aSKuninori Morimoto dev_dbg(dev, "Forced end of command sequence\n");
584fdc50a94SYusuke Goda return -EIO;
585fdc50a94SYusuke Goda }
586fdc50a94SYusuke Goda
587fdc50a94SYusuke Goda if (state2 & STS2_CRC_ERR) {
588585c3a5aSKuninori Morimoto dev_err(dev, " CRC error: state %u, wait %u\n",
589e475b270STeppei Kamijou host->state, host->wait_for);
590fdc50a94SYusuke Goda ret = -EIO;
591fdc50a94SYusuke Goda } else if (state2 & STS2_TIMEOUT_ERR) {
592585c3a5aSKuninori Morimoto dev_err(dev, " Timeout: state %u, wait %u\n",
593e475b270STeppei Kamijou host->state, host->wait_for);
594fdc50a94SYusuke Goda ret = -ETIMEDOUT;
595fdc50a94SYusuke Goda } else {
596585c3a5aSKuninori Morimoto dev_dbg(dev, " End/Index error: state %u, wait %u\n",
597e475b270STeppei Kamijou host->state, host->wait_for);
598fdc50a94SYusuke Goda ret = -EIO;
599fdc50a94SYusuke Goda }
600fdc50a94SYusuke Goda return ret;
601fdc50a94SYusuke Goda }
602fdc50a94SYusuke Goda
sh_mmcif_next_block(struct sh_mmcif_host * host,u32 * p)603f985da17SGuennadi Liakhovetski static bool sh_mmcif_next_block(struct sh_mmcif_host *host, u32 *p)
604f985da17SGuennadi Liakhovetski {
605f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
606f985da17SGuennadi Liakhovetski
607f985da17SGuennadi Liakhovetski host->sg_blkidx += host->blocksize;
608f985da17SGuennadi Liakhovetski
609f985da17SGuennadi Liakhovetski /* data->sg->length must be a multiple of host->blocksize? */
610f985da17SGuennadi Liakhovetski BUG_ON(host->sg_blkidx > data->sg->length);
611f985da17SGuennadi Liakhovetski
612f985da17SGuennadi Liakhovetski if (host->sg_blkidx == data->sg->length) {
613f985da17SGuennadi Liakhovetski host->sg_blkidx = 0;
614f985da17SGuennadi Liakhovetski if (++host->sg_idx < data->sg_len)
615f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(++data->sg);
616f985da17SGuennadi Liakhovetski } else {
617f985da17SGuennadi Liakhovetski host->pio_ptr = p;
618f985da17SGuennadi Liakhovetski }
619f985da17SGuennadi Liakhovetski
62099eb9d8dSGuennadi Liakhovetski return host->sg_idx != data->sg_len;
621f985da17SGuennadi Liakhovetski }
622f985da17SGuennadi Liakhovetski
sh_mmcif_single_read(struct sh_mmcif_host * host,struct mmc_request * mrq)623f985da17SGuennadi Liakhovetski static void sh_mmcif_single_read(struct sh_mmcif_host *host,
624fdc50a94SYusuke Goda struct mmc_request *mrq)
625fdc50a94SYusuke Goda {
626f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
627f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3;
628f985da17SGuennadi Liakhovetski
629f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ;
630fdc50a94SYusuke Goda
631fdc50a94SYusuke Goda /* buf read enable */
632fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
633f985da17SGuennadi Liakhovetski }
634fdc50a94SYusuke Goda
sh_mmcif_read_block(struct sh_mmcif_host * host)635f985da17SGuennadi Liakhovetski static bool sh_mmcif_read_block(struct sh_mmcif_host *host)
636f985da17SGuennadi Liakhovetski {
637585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
638f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
639f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg);
640f985da17SGuennadi Liakhovetski int i;
641f985da17SGuennadi Liakhovetski
642f985da17SGuennadi Liakhovetski if (host->sd_error) {
643f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host);
644585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error);
645f985da17SGuennadi Liakhovetski return false;
646f985da17SGuennadi Liakhovetski }
647f985da17SGuennadi Liakhovetski
648f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++)
649487d9fc5SMagnus Damm *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
650fdc50a94SYusuke Goda
651fdc50a94SYusuke Goda /* buffer read end */
652fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFRE);
653f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_READ_END;
654fdc50a94SYusuke Goda
655f985da17SGuennadi Liakhovetski return true;
656fdc50a94SYusuke Goda }
657fdc50a94SYusuke Goda
sh_mmcif_multi_read(struct sh_mmcif_host * host,struct mmc_request * mrq)658f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_read(struct sh_mmcif_host *host,
659fdc50a94SYusuke Goda struct mmc_request *mrq)
660fdc50a94SYusuke Goda {
661fdc50a94SYusuke Goda struct mmc_data *data = mrq->data;
662fdc50a94SYusuke Goda
663f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length)
664f985da17SGuennadi Liakhovetski return;
665f985da17SGuennadi Liakhovetski
666f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
667f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK;
668f985da17SGuennadi Liakhovetski
669f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MREAD;
670f985da17SGuennadi Liakhovetski host->sg_idx = 0;
671f985da17SGuennadi Liakhovetski host->sg_blkidx = 0;
672f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg);
6735df460b1SGuennadi Liakhovetski
674fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
675fdc50a94SYusuke Goda }
676fdc50a94SYusuke Goda
sh_mmcif_mread_block(struct sh_mmcif_host * host)677f985da17SGuennadi Liakhovetski static bool sh_mmcif_mread_block(struct sh_mmcif_host *host)
678f985da17SGuennadi Liakhovetski {
679585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
680f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
681f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr;
682f985da17SGuennadi Liakhovetski int i;
683f985da17SGuennadi Liakhovetski
684f985da17SGuennadi Liakhovetski if (host->sd_error) {
685f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host);
686585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error);
687f985da17SGuennadi Liakhovetski return false;
688f985da17SGuennadi Liakhovetski }
689f985da17SGuennadi Liakhovetski
690f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length);
691f985da17SGuennadi Liakhovetski
692f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++)
693f985da17SGuennadi Liakhovetski *p++ = sh_mmcif_readl(host->addr, MMCIF_CE_DATA);
694f985da17SGuennadi Liakhovetski
695f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p))
696f985da17SGuennadi Liakhovetski return false;
697f985da17SGuennadi Liakhovetski
698f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFREN);
699f985da17SGuennadi Liakhovetski
700f985da17SGuennadi Liakhovetski return true;
701f985da17SGuennadi Liakhovetski }
702f985da17SGuennadi Liakhovetski
sh_mmcif_single_write(struct sh_mmcif_host * host,struct mmc_request * mrq)703f985da17SGuennadi Liakhovetski static void sh_mmcif_single_write(struct sh_mmcif_host *host,
704fdc50a94SYusuke Goda struct mmc_request *mrq)
705fdc50a94SYusuke Goda {
706f985da17SGuennadi Liakhovetski host->blocksize = (sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
707f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK) + 3;
708fdc50a94SYusuke Goda
709f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE;
710fdc50a94SYusuke Goda
711fdc50a94SYusuke Goda /* buf write enable */
712f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
713f985da17SGuennadi Liakhovetski }
714fdc50a94SYusuke Goda
sh_mmcif_write_block(struct sh_mmcif_host * host)715f985da17SGuennadi Liakhovetski static bool sh_mmcif_write_block(struct sh_mmcif_host *host)
716f985da17SGuennadi Liakhovetski {
717585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
718f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
719f985da17SGuennadi Liakhovetski u32 *p = sg_virt(data->sg);
720f985da17SGuennadi Liakhovetski int i;
721f985da17SGuennadi Liakhovetski
722f985da17SGuennadi Liakhovetski if (host->sd_error) {
723f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host);
724585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error);
725f985da17SGuennadi Liakhovetski return false;
726f985da17SGuennadi Liakhovetski }
727f985da17SGuennadi Liakhovetski
728f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++)
729487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
730fdc50a94SYusuke Goda
731fdc50a94SYusuke Goda /* buffer write end */
732fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MDTRANE);
733f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_WRITE_END;
734fdc50a94SYusuke Goda
735f985da17SGuennadi Liakhovetski return true;
736fdc50a94SYusuke Goda }
737fdc50a94SYusuke Goda
sh_mmcif_multi_write(struct sh_mmcif_host * host,struct mmc_request * mrq)738f985da17SGuennadi Liakhovetski static void sh_mmcif_multi_write(struct sh_mmcif_host *host,
739fdc50a94SYusuke Goda struct mmc_request *mrq)
740fdc50a94SYusuke Goda {
741fdc50a94SYusuke Goda struct mmc_data *data = mrq->data;
742fdc50a94SYusuke Goda
743f985da17SGuennadi Liakhovetski if (!data->sg_len || !data->sg->length)
744f985da17SGuennadi Liakhovetski return;
745fdc50a94SYusuke Goda
746f985da17SGuennadi Liakhovetski host->blocksize = sh_mmcif_readl(host->addr, MMCIF_CE_BLOCK_SET) &
747f985da17SGuennadi Liakhovetski BLOCK_SIZE_MASK;
748f985da17SGuennadi Liakhovetski
749f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_MWRITE;
750f985da17SGuennadi Liakhovetski host->sg_idx = 0;
751f985da17SGuennadi Liakhovetski host->sg_blkidx = 0;
752f985da17SGuennadi Liakhovetski host->pio_ptr = sg_virt(data->sg);
7535df460b1SGuennadi Liakhovetski
754fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
755fdc50a94SYusuke Goda }
756f985da17SGuennadi Liakhovetski
sh_mmcif_mwrite_block(struct sh_mmcif_host * host)757f985da17SGuennadi Liakhovetski static bool sh_mmcif_mwrite_block(struct sh_mmcif_host *host)
758f985da17SGuennadi Liakhovetski {
759585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
760f985da17SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
761f985da17SGuennadi Liakhovetski u32 *p = host->pio_ptr;
762f985da17SGuennadi Liakhovetski int i;
763f985da17SGuennadi Liakhovetski
764f985da17SGuennadi Liakhovetski if (host->sd_error) {
765f985da17SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host);
766585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, data->error);
767f985da17SGuennadi Liakhovetski return false;
768fdc50a94SYusuke Goda }
769f985da17SGuennadi Liakhovetski
770f985da17SGuennadi Liakhovetski BUG_ON(!data->sg->length);
771f985da17SGuennadi Liakhovetski
772f985da17SGuennadi Liakhovetski for (i = 0; i < host->blocksize / 4; i++)
773f985da17SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_DATA, *p++);
774f985da17SGuennadi Liakhovetski
775f985da17SGuennadi Liakhovetski if (!sh_mmcif_next_block(host, p))
776f985da17SGuennadi Liakhovetski return false;
777f985da17SGuennadi Liakhovetski
778f985da17SGuennadi Liakhovetski sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MBUFWEN);
779f985da17SGuennadi Liakhovetski
780f985da17SGuennadi Liakhovetski return true;
781fdc50a94SYusuke Goda }
782fdc50a94SYusuke Goda
sh_mmcif_get_response(struct sh_mmcif_host * host,struct mmc_command * cmd)783fdc50a94SYusuke Goda static void sh_mmcif_get_response(struct sh_mmcif_host *host,
784fdc50a94SYusuke Goda struct mmc_command *cmd)
785fdc50a94SYusuke Goda {
786fdc50a94SYusuke Goda if (cmd->flags & MMC_RSP_136) {
787487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP3);
788487d9fc5SMagnus Damm cmd->resp[1] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP2);
789487d9fc5SMagnus Damm cmd->resp[2] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP1);
790487d9fc5SMagnus Damm cmd->resp[3] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
791fdc50a94SYusuke Goda } else
792487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP0);
793fdc50a94SYusuke Goda }
794fdc50a94SYusuke Goda
sh_mmcif_get_cmd12response(struct sh_mmcif_host * host,struct mmc_command * cmd)795fdc50a94SYusuke Goda static void sh_mmcif_get_cmd12response(struct sh_mmcif_host *host,
796fdc50a94SYusuke Goda struct mmc_command *cmd)
797fdc50a94SYusuke Goda {
798487d9fc5SMagnus Damm cmd->resp[0] = sh_mmcif_readl(host->addr, MMCIF_CE_RESP_CMD12);
799fdc50a94SYusuke Goda }
800fdc50a94SYusuke Goda
sh_mmcif_set_cmd(struct sh_mmcif_host * host,struct mmc_request * mrq)801fdc50a94SYusuke Goda static u32 sh_mmcif_set_cmd(struct sh_mmcif_host *host,
80269983404SGuennadi Liakhovetski struct mmc_request *mrq)
803fdc50a94SYusuke Goda {
804585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
80569983404SGuennadi Liakhovetski struct mmc_data *data = mrq->data;
80669983404SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd;
80769983404SGuennadi Liakhovetski u32 opc = cmd->opcode;
808fdc50a94SYusuke Goda u32 tmp = 0;
809fdc50a94SYusuke Goda
810fdc50a94SYusuke Goda /* Response Type check */
811fdc50a94SYusuke Goda switch (mmc_resp_type(cmd)) {
812fdc50a94SYusuke Goda case MMC_RSP_NONE:
813fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_NO;
814fdc50a94SYusuke Goda break;
815fdc50a94SYusuke Goda case MMC_RSP_R1:
816fdc50a94SYusuke Goda case MMC_RSP_R3:
817fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_6B;
818fdc50a94SYusuke Goda break;
8195b1c29bcSUlf Hansson case MMC_RSP_R1B:
8205b1c29bcSUlf Hansson tmp |= CMD_SET_RBSY | CMD_SET_RTYP_6B;
8215b1c29bcSUlf Hansson break;
822fdc50a94SYusuke Goda case MMC_RSP_R2:
823fdc50a94SYusuke Goda tmp |= CMD_SET_RTYP_17B;
824fdc50a94SYusuke Goda break;
825fdc50a94SYusuke Goda default:
826585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported response type.\n");
827fdc50a94SYusuke Goda break;
828fdc50a94SYusuke Goda }
8295b1c29bcSUlf Hansson
830fdc50a94SYusuke Goda /* WDAT / DATW */
83169983404SGuennadi Liakhovetski if (data) {
832fdc50a94SYusuke Goda tmp |= CMD_SET_WDAT;
833fdc50a94SYusuke Goda switch (host->bus_width) {
834fdc50a94SYusuke Goda case MMC_BUS_WIDTH_1:
835fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_1;
836fdc50a94SYusuke Goda break;
837fdc50a94SYusuke Goda case MMC_BUS_WIDTH_4:
838fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_4;
839fdc50a94SYusuke Goda break;
840fdc50a94SYusuke Goda case MMC_BUS_WIDTH_8:
841fdc50a94SYusuke Goda tmp |= CMD_SET_DATW_8;
842fdc50a94SYusuke Goda break;
843fdc50a94SYusuke Goda default:
844585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported bus width.\n");
845fdc50a94SYusuke Goda break;
846fdc50a94SYusuke Goda }
847555061f9STeppei Kamijou switch (host->timing) {
8484039ff47SSeungwon Jeon case MMC_TIMING_MMC_DDR52:
849555061f9STeppei Kamijou /*
850555061f9STeppei Kamijou * MMC core will only set this timing, if the host
8514039ff47SSeungwon Jeon * advertises the MMC_CAP_1_8V_DDR/MMC_CAP_1_2V_DDR
8524039ff47SSeungwon Jeon * capability. MMCIF implementations with this
8534039ff47SSeungwon Jeon * capability, e.g. sh73a0, will have to set it
8544039ff47SSeungwon Jeon * in their platform data.
855555061f9STeppei Kamijou */
856555061f9STeppei Kamijou tmp |= CMD_SET_DARS;
857555061f9STeppei Kamijou break;
858555061f9STeppei Kamijou }
859fdc50a94SYusuke Goda }
860fdc50a94SYusuke Goda /* DWEN */
861fdc50a94SYusuke Goda if (opc == MMC_WRITE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK)
862fdc50a94SYusuke Goda tmp |= CMD_SET_DWEN;
863fdc50a94SYusuke Goda /* CMLTE/CMD12EN */
864fdc50a94SYusuke Goda if (opc == MMC_READ_MULTIPLE_BLOCK || opc == MMC_WRITE_MULTIPLE_BLOCK) {
865fdc50a94SYusuke Goda tmp |= CMD_SET_CMLTE | CMD_SET_CMD12EN;
866fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_BLOCK_SET,
86769983404SGuennadi Liakhovetski data->blocks << 16);
868fdc50a94SYusuke Goda }
869fdc50a94SYusuke Goda /* RIDXC[1:0] check bits */
870fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND || opc == MMC_ALL_SEND_CID ||
871fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
872fdc50a94SYusuke Goda tmp |= CMD_SET_RIDXC_BITS;
873fdc50a94SYusuke Goda /* RCRC7C[1:0] check bits */
874fdc50a94SYusuke Goda if (opc == MMC_SEND_OP_COND)
875fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_BITS;
876fdc50a94SYusuke Goda /* RCRC7C[1:0] internal CRC7 */
877fdc50a94SYusuke Goda if (opc == MMC_ALL_SEND_CID ||
878fdc50a94SYusuke Goda opc == MMC_SEND_CSD || opc == MMC_SEND_CID)
879fdc50a94SYusuke Goda tmp |= CMD_SET_CRC7C_INTERNAL;
880fdc50a94SYusuke Goda
88169983404SGuennadi Liakhovetski return (opc << 24) | tmp;
882fdc50a94SYusuke Goda }
883fdc50a94SYusuke Goda
sh_mmcif_data_trans(struct sh_mmcif_host * host,struct mmc_request * mrq,u32 opc)884e47bf32aSGuennadi Liakhovetski static int sh_mmcif_data_trans(struct sh_mmcif_host *host,
885fdc50a94SYusuke Goda struct mmc_request *mrq, u32 opc)
886fdc50a94SYusuke Goda {
887585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
888585c3a5aSKuninori Morimoto
889fdc50a94SYusuke Goda switch (opc) {
890fdc50a94SYusuke Goda case MMC_READ_MULTIPLE_BLOCK:
891f985da17SGuennadi Liakhovetski sh_mmcif_multi_read(host, mrq);
892f985da17SGuennadi Liakhovetski return 0;
893fdc50a94SYusuke Goda case MMC_WRITE_MULTIPLE_BLOCK:
894f985da17SGuennadi Liakhovetski sh_mmcif_multi_write(host, mrq);
895f985da17SGuennadi Liakhovetski return 0;
896fdc50a94SYusuke Goda case MMC_WRITE_BLOCK:
897f985da17SGuennadi Liakhovetski sh_mmcif_single_write(host, mrq);
898f985da17SGuennadi Liakhovetski return 0;
899fdc50a94SYusuke Goda case MMC_READ_SINGLE_BLOCK:
900fdc50a94SYusuke Goda case MMC_SEND_EXT_CSD:
901f985da17SGuennadi Liakhovetski sh_mmcif_single_read(host, mrq);
902f985da17SGuennadi Liakhovetski return 0;
903fdc50a94SYusuke Goda default:
904585c3a5aSKuninori Morimoto dev_err(dev, "Unsupported CMD%d\n", opc);
905ee4b8887SGuennadi Liakhovetski return -EINVAL;
906fdc50a94SYusuke Goda }
907fdc50a94SYusuke Goda }
908fdc50a94SYusuke Goda
sh_mmcif_start_cmd(struct sh_mmcif_host * host,struct mmc_request * mrq)909fdc50a94SYusuke Goda static void sh_mmcif_start_cmd(struct sh_mmcif_host *host,
910ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq)
911fdc50a94SYusuke Goda {
912ee4b8887SGuennadi Liakhovetski struct mmc_command *cmd = mrq->cmd;
913659032dcSColin Ian King u32 opc;
9145b1c29bcSUlf Hansson u32 mask = 0;
915dbb42d96SKouichi Tomita unsigned long flags;
916fdc50a94SYusuke Goda
9175b1c29bcSUlf Hansson if (cmd->flags & MMC_RSP_BUSY)
918ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MRBSYE;
9195b1c29bcSUlf Hansson else
920ee4b8887SGuennadi Liakhovetski mask = MASK_START_CMD | MASK_MCRSPE;
921fdc50a94SYusuke Goda
922967bcb77SGuennadi Liakhovetski if (host->ccs_enable)
923967bcb77SGuennadi Liakhovetski mask |= MASK_MCCSTO;
924967bcb77SGuennadi Liakhovetski
92569983404SGuennadi Liakhovetski if (mrq->data) {
926487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET, 0);
927487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_BLOCK_SET,
928487d9fc5SMagnus Damm mrq->data->blksz);
929fdc50a94SYusuke Goda }
93069983404SGuennadi Liakhovetski opc = sh_mmcif_set_cmd(host, mrq);
931fdc50a94SYusuke Goda
932967bcb77SGuennadi Liakhovetski if (host->ccs_enable)
933487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0);
934967bcb77SGuennadi Liakhovetski else
935967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, 0xD80430C0 | INT_CCS);
936487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, mask);
937fdc50a94SYusuke Goda /* set arg */
938487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_ARG, cmd->arg);
939fdc50a94SYusuke Goda /* set cmd */
940dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags);
941487d9fc5SMagnus Damm sh_mmcif_writel(host->addr, MMCIF_CE_CMD_SET, opc);
942fdc50a94SYusuke Goda
943f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_CMD;
944f985da17SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout);
945dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags);
946fdc50a94SYusuke Goda }
947fdc50a94SYusuke Goda
sh_mmcif_stop_cmd(struct sh_mmcif_host * host,struct mmc_request * mrq)948fdc50a94SYusuke Goda static void sh_mmcif_stop_cmd(struct sh_mmcif_host *host,
949ee4b8887SGuennadi Liakhovetski struct mmc_request *mrq)
950fdc50a94SYusuke Goda {
951585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
952585c3a5aSKuninori Morimoto
95369983404SGuennadi Liakhovetski switch (mrq->cmd->opcode) {
95469983404SGuennadi Liakhovetski case MMC_READ_MULTIPLE_BLOCK:
955fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12DRE);
95669983404SGuennadi Liakhovetski break;
95769983404SGuennadi Liakhovetski case MMC_WRITE_MULTIPLE_BLOCK:
958fdc50a94SYusuke Goda sh_mmcif_bitset(host, MMCIF_CE_INT_MASK, MASK_MCMD12RBE);
95969983404SGuennadi Liakhovetski break;
96069983404SGuennadi Liakhovetski default:
961585c3a5aSKuninori Morimoto dev_err(dev, "unsupported stop cmd\n");
96269983404SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host);
963fdc50a94SYusuke Goda return;
964fdc50a94SYusuke Goda }
965fdc50a94SYusuke Goda
966f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_STOP;
967fdc50a94SYusuke Goda }
968fdc50a94SYusuke Goda
sh_mmcif_request(struct mmc_host * mmc,struct mmc_request * mrq)969fdc50a94SYusuke Goda static void sh_mmcif_request(struct mmc_host *mmc, struct mmc_request *mrq)
970fdc50a94SYusuke Goda {
971fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc);
972585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
9733b0beafcSGuennadi Liakhovetski unsigned long flags;
9743b0beafcSGuennadi Liakhovetski
9753b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags);
9763b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) {
977585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n",
978585c3a5aSKuninori Morimoto __func__, host->state);
9793b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags);
9803b0beafcSGuennadi Liakhovetski mrq->cmd->error = -EAGAIN;
9813b0beafcSGuennadi Liakhovetski mmc_request_done(mmc, mrq);
9823b0beafcSGuennadi Liakhovetski return;
9833b0beafcSGuennadi Liakhovetski }
9843b0beafcSGuennadi Liakhovetski
9853b0beafcSGuennadi Liakhovetski host->state = STATE_REQUEST;
9863b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags);
987fdc50a94SYusuke Goda
988f985da17SGuennadi Liakhovetski host->mrq = mrq;
989f985da17SGuennadi Liakhovetski
990f985da17SGuennadi Liakhovetski sh_mmcif_start_cmd(host, mrq);
991fdc50a94SYusuke Goda }
992fdc50a94SYusuke Goda
sh_mmcif_clk_setup(struct sh_mmcif_host * host)9939bb09a30SKuninori Morimoto static void sh_mmcif_clk_setup(struct sh_mmcif_host *host)
994a6609267SGuennadi Liakhovetski {
99589d49a70SKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
99689d49a70SKuninori Morimoto
99789d49a70SKuninori Morimoto if (host->mmc->f_max) {
99889d49a70SKuninori Morimoto unsigned int f_max, f_min = 0, f_min_old;
99989d49a70SKuninori Morimoto
100089d49a70SKuninori Morimoto f_max = host->mmc->f_max;
100189d49a70SKuninori Morimoto for (f_min_old = f_max; f_min_old > 2;) {
100289d49a70SKuninori Morimoto f_min = clk_round_rate(host->clk, f_min_old / 2);
100389d49a70SKuninori Morimoto if (f_min == f_min_old)
100489d49a70SKuninori Morimoto break;
100589d49a70SKuninori Morimoto f_min_old = f_min;
100689d49a70SKuninori Morimoto }
100789d49a70SKuninori Morimoto
100889d49a70SKuninori Morimoto /*
100989d49a70SKuninori Morimoto * This driver assumes this SoC is R-Car Gen2 or later
101089d49a70SKuninori Morimoto */
101189d49a70SKuninori Morimoto host->clkdiv_map = 0x3ff;
101289d49a70SKuninori Morimoto
1013bee15491SGeert Uytterhoeven host->mmc->f_max = f_max >> ffs(host->clkdiv_map);
1014bee15491SGeert Uytterhoeven host->mmc->f_min = f_min >> fls(host->clkdiv_map);
101589d49a70SKuninori Morimoto } else {
10166aed678bSKuninori Morimoto unsigned int clk = clk_get_rate(host->clk);
10176aed678bSKuninori Morimoto
10186aed678bSKuninori Morimoto host->mmc->f_max = clk / 2;
10196aed678bSKuninori Morimoto host->mmc->f_min = clk / 512;
1020a6609267SGuennadi Liakhovetski }
1021a6609267SGuennadi Liakhovetski
102289d49a70SKuninori Morimoto dev_dbg(dev, "clk max/min = %d/%d\n",
102389d49a70SKuninori Morimoto host->mmc->f_max, host->mmc->f_min);
102489d49a70SKuninori Morimoto }
102589d49a70SKuninori Morimoto
sh_mmcif_set_ios(struct mmc_host * mmc,struct mmc_ios * ios)1026fdc50a94SYusuke Goda static void sh_mmcif_set_ios(struct mmc_host *mmc, struct mmc_ios *ios)
1027fdc50a94SYusuke Goda {
1028fdc50a94SYusuke Goda struct sh_mmcif_host *host = mmc_priv(mmc);
1029585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
10303b0beafcSGuennadi Liakhovetski unsigned long flags;
10313b0beafcSGuennadi Liakhovetski
10323b0beafcSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags);
10333b0beafcSGuennadi Liakhovetski if (host->state != STATE_IDLE) {
1034585c3a5aSKuninori Morimoto dev_dbg(dev, "%s() rejected, state %u\n",
1035585c3a5aSKuninori Morimoto __func__, host->state);
10363b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags);
10373b0beafcSGuennadi Liakhovetski return;
10383b0beafcSGuennadi Liakhovetski }
10393b0beafcSGuennadi Liakhovetski
10403b0beafcSGuennadi Liakhovetski host->state = STATE_IOS;
10413b0beafcSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags);
1042fdc50a94SYusuke Goda
10434caf653aSUlf Hansson switch (ios->power_mode) {
10444caf653aSUlf Hansson case MMC_POWER_UP:
104533a31ceaSUlf Hansson if (!IS_ERR(mmc->supply.vmmc))
104633a31ceaSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, ios->vdd);
1047c9b0cef2SGuennadi Liakhovetski if (!host->power) {
10489bb09a30SKuninori Morimoto clk_prepare_enable(host->clk);
1049585c3a5aSKuninori Morimoto pm_runtime_get_sync(dev);
1050c9b0cef2SGuennadi Liakhovetski sh_mmcif_sync_reset(host);
10514caf653aSUlf Hansson sh_mmcif_request_dma(host);
10524caf653aSUlf Hansson host->power = true;
1053c9b0cef2SGuennadi Liakhovetski }
10544caf653aSUlf Hansson break;
10554caf653aSUlf Hansson case MMC_POWER_OFF:
105633a31ceaSUlf Hansson if (!IS_ERR(mmc->supply.vmmc))
105733a31ceaSUlf Hansson mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, 0);
10584caf653aSUlf Hansson if (host->power) {
10594caf653aSUlf Hansson sh_mmcif_clock_control(host, 0);
10604caf653aSUlf Hansson sh_mmcif_release_dma(host);
10614caf653aSUlf Hansson pm_runtime_put(dev);
10624caf653aSUlf Hansson clk_disable_unprepare(host->clk);
10634caf653aSUlf Hansson host->power = false;
10644caf653aSUlf Hansson }
10654caf653aSUlf Hansson break;
10664caf653aSUlf Hansson case MMC_POWER_ON:
1067fdc50a94SYusuke Goda sh_mmcif_clock_control(host, ios->clock);
10684caf653aSUlf Hansson break;
1069c9b0cef2SGuennadi Liakhovetski }
1070fdc50a94SYusuke Goda
1071555061f9STeppei Kamijou host->timing = ios->timing;
1072fdc50a94SYusuke Goda host->bus_width = ios->bus_width;
10733b0beafcSGuennadi Liakhovetski host->state = STATE_IDLE;
1074fdc50a94SYusuke Goda }
1075fdc50a94SYusuke Goda
10761586cbb3SJulia Lawall static const struct mmc_host_ops sh_mmcif_ops = {
1077fdc50a94SYusuke Goda .request = sh_mmcif_request,
1078fdc50a94SYusuke Goda .set_ios = sh_mmcif_set_ios,
10795957eebaSUlf Hansson .get_cd = mmc_gpio_get_cd,
1080fdc50a94SYusuke Goda };
1081fdc50a94SYusuke Goda
sh_mmcif_end_cmd(struct sh_mmcif_host * host)1082f985da17SGuennadi Liakhovetski static bool sh_mmcif_end_cmd(struct sh_mmcif_host *host)
1083f985da17SGuennadi Liakhovetski {
1084f985da17SGuennadi Liakhovetski struct mmc_command *cmd = host->mrq->cmd;
108569983404SGuennadi Liakhovetski struct mmc_data *data = host->mrq->data;
1086585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
1087f985da17SGuennadi Liakhovetski long time;
1088f985da17SGuennadi Liakhovetski
1089f985da17SGuennadi Liakhovetski if (host->sd_error) {
1090f985da17SGuennadi Liakhovetski switch (cmd->opcode) {
1091f985da17SGuennadi Liakhovetski case MMC_ALL_SEND_CID:
1092f985da17SGuennadi Liakhovetski case MMC_SELECT_CARD:
1093f985da17SGuennadi Liakhovetski case MMC_APP_CMD:
1094f985da17SGuennadi Liakhovetski cmd->error = -ETIMEDOUT;
1095f985da17SGuennadi Liakhovetski break;
1096f985da17SGuennadi Liakhovetski default:
1097f985da17SGuennadi Liakhovetski cmd->error = sh_mmcif_error_manage(host);
1098f985da17SGuennadi Liakhovetski break;
1099f985da17SGuennadi Liakhovetski }
1100585c3a5aSKuninori Morimoto dev_dbg(dev, "CMD%d error %d\n",
1101e475b270STeppei Kamijou cmd->opcode, cmd->error);
1102aba9d646SGuennadi Liakhovetski host->sd_error = false;
1103f985da17SGuennadi Liakhovetski return false;
1104f985da17SGuennadi Liakhovetski }
1105f985da17SGuennadi Liakhovetski if (!(cmd->flags & MMC_RSP_PRESENT)) {
1106f985da17SGuennadi Liakhovetski cmd->error = 0;
1107f985da17SGuennadi Liakhovetski return false;
1108f985da17SGuennadi Liakhovetski }
1109f985da17SGuennadi Liakhovetski
1110f985da17SGuennadi Liakhovetski sh_mmcif_get_response(host, cmd);
1111f985da17SGuennadi Liakhovetski
111269983404SGuennadi Liakhovetski if (!data)
1113f985da17SGuennadi Liakhovetski return false;
1114f985da17SGuennadi Liakhovetski
111590f1cb43SGuennadi Liakhovetski /*
111690f1cb43SGuennadi Liakhovetski * Completion can be signalled from DMA callback and error, so, have to
111790f1cb43SGuennadi Liakhovetski * reset here, before setting .dma_active
111890f1cb43SGuennadi Liakhovetski */
111990f1cb43SGuennadi Liakhovetski init_completion(&host->dma_complete);
112090f1cb43SGuennadi Liakhovetski
112169983404SGuennadi Liakhovetski if (data->flags & MMC_DATA_READ) {
1122f985da17SGuennadi Liakhovetski if (host->chan_rx)
1123f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_rx(host);
1124f985da17SGuennadi Liakhovetski } else {
1125f985da17SGuennadi Liakhovetski if (host->chan_tx)
1126f985da17SGuennadi Liakhovetski sh_mmcif_start_dma_tx(host);
1127f985da17SGuennadi Liakhovetski }
1128f985da17SGuennadi Liakhovetski
1129f985da17SGuennadi Liakhovetski if (!host->dma_active) {
113069983404SGuennadi Liakhovetski data->error = sh_mmcif_data_trans(host, host->mrq, cmd->opcode);
113199eb9d8dSGuennadi Liakhovetski return !data->error;
1132f985da17SGuennadi Liakhovetski }
1133f985da17SGuennadi Liakhovetski
1134f985da17SGuennadi Liakhovetski /* Running in the IRQ thread, can sleep */
1135f985da17SGuennadi Liakhovetski time = wait_for_completion_interruptible_timeout(&host->dma_complete,
1136f985da17SGuennadi Liakhovetski host->timeout);
1137eae30983STeppei Kamijou
1138eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ)
1139eae30983STeppei Kamijou dma_unmap_sg(host->chan_rx->device->dev,
1140eae30983STeppei Kamijou data->sg, data->sg_len,
1141eae30983STeppei Kamijou DMA_FROM_DEVICE);
1142eae30983STeppei Kamijou else
1143eae30983STeppei Kamijou dma_unmap_sg(host->chan_tx->device->dev,
1144eae30983STeppei Kamijou data->sg, data->sg_len,
1145eae30983STeppei Kamijou DMA_TO_DEVICE);
1146eae30983STeppei Kamijou
1147f985da17SGuennadi Liakhovetski if (host->sd_error) {
1148f985da17SGuennadi Liakhovetski dev_err(host->mmc->parent,
1149f985da17SGuennadi Liakhovetski "Error IRQ while waiting for DMA completion!\n");
1150f985da17SGuennadi Liakhovetski /* Woken up by an error IRQ: abort DMA */
115169983404SGuennadi Liakhovetski data->error = sh_mmcif_error_manage(host);
1152f985da17SGuennadi Liakhovetski } else if (!time) {
1153e475b270STeppei Kamijou dev_err(host->mmc->parent, "DMA timeout!\n");
115469983404SGuennadi Liakhovetski data->error = -ETIMEDOUT;
1155f985da17SGuennadi Liakhovetski } else if (time < 0) {
1156e475b270STeppei Kamijou dev_err(host->mmc->parent,
1157e475b270STeppei Kamijou "wait_for_completion_...() error %ld!\n", time);
115869983404SGuennadi Liakhovetski data->error = time;
1159f985da17SGuennadi Liakhovetski }
1160f985da17SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_BUF_ACC,
1161f985da17SGuennadi Liakhovetski BUF_ACC_DMAREN | BUF_ACC_DMAWEN);
1162f985da17SGuennadi Liakhovetski host->dma_active = false;
1163f985da17SGuennadi Liakhovetski
1164eae30983STeppei Kamijou if (data->error) {
116569983404SGuennadi Liakhovetski data->bytes_xfered = 0;
1166eae30983STeppei Kamijou /* Abort DMA */
1167eae30983STeppei Kamijou if (data->flags & MMC_DATA_READ)
1168492200f2SWolfram Sang dmaengine_terminate_sync(host->chan_rx);
1169eae30983STeppei Kamijou else
1170492200f2SWolfram Sang dmaengine_terminate_sync(host->chan_tx);
1171eae30983STeppei Kamijou }
1172f985da17SGuennadi Liakhovetski
1173f985da17SGuennadi Liakhovetski return false;
1174f985da17SGuennadi Liakhovetski }
1175f985da17SGuennadi Liakhovetski
sh_mmcif_irqt(int irq,void * dev_id)1176f985da17SGuennadi Liakhovetski static irqreturn_t sh_mmcif_irqt(int irq, void *dev_id)
1177f985da17SGuennadi Liakhovetski {
1178f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = dev_id;
11798047310eSGuennadi Liakhovetski struct mmc_request *mrq;
1180585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
11815df460b1SGuennadi Liakhovetski bool wait = false;
1182dbb42d96SKouichi Tomita unsigned long flags;
1183dbb42d96SKouichi Tomita int wait_work;
1184dbb42d96SKouichi Tomita
1185dbb42d96SKouichi Tomita spin_lock_irqsave(&host->lock, flags);
1186dbb42d96SKouichi Tomita wait_work = host->wait_for;
1187dbb42d96SKouichi Tomita spin_unlock_irqrestore(&host->lock, flags);
1188f985da17SGuennadi Liakhovetski
1189f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work);
1190f985da17SGuennadi Liakhovetski
11918047310eSGuennadi Liakhovetski mutex_lock(&host->thread_lock);
11928047310eSGuennadi Liakhovetski
11938047310eSGuennadi Liakhovetski mrq = host->mrq;
11948047310eSGuennadi Liakhovetski if (!mrq) {
1195585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ thread state %u, wait %u: NULL mrq!\n",
11968047310eSGuennadi Liakhovetski host->state, host->wait_for);
11978047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock);
11988047310eSGuennadi Liakhovetski return IRQ_HANDLED;
11998047310eSGuennadi Liakhovetski }
12008047310eSGuennadi Liakhovetski
1201f985da17SGuennadi Liakhovetski /*
1202f985da17SGuennadi Liakhovetski * All handlers return true, if processing continues, and false, if the
1203f985da17SGuennadi Liakhovetski * request has to be completed - successfully or not
1204f985da17SGuennadi Liakhovetski */
1205dbb42d96SKouichi Tomita switch (wait_work) {
1206f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_REQUEST:
1207f985da17SGuennadi Liakhovetski /* We're too late, the timeout has already kicked in */
12088047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock);
1209f985da17SGuennadi Liakhovetski return IRQ_HANDLED;
1210f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD:
12115df460b1SGuennadi Liakhovetski /* Wait for data? */
12125df460b1SGuennadi Liakhovetski wait = sh_mmcif_end_cmd(host);
1213f985da17SGuennadi Liakhovetski break;
1214f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD:
12155df460b1SGuennadi Liakhovetski /* Wait for more data? */
12165df460b1SGuennadi Liakhovetski wait = sh_mmcif_mread_block(host);
1217f985da17SGuennadi Liakhovetski break;
1218f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ:
12195df460b1SGuennadi Liakhovetski /* Wait for data end? */
12205df460b1SGuennadi Liakhovetski wait = sh_mmcif_read_block(host);
1221f985da17SGuennadi Liakhovetski break;
1222f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE:
12235df460b1SGuennadi Liakhovetski /* Wait data to write? */
12245df460b1SGuennadi Liakhovetski wait = sh_mmcif_mwrite_block(host);
1225f985da17SGuennadi Liakhovetski break;
1226f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE:
12275df460b1SGuennadi Liakhovetski /* Wait for data end? */
12285df460b1SGuennadi Liakhovetski wait = sh_mmcif_write_block(host);
1229f985da17SGuennadi Liakhovetski break;
1230f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP:
1231f985da17SGuennadi Liakhovetski if (host->sd_error) {
1232f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host);
1233585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->stop->error);
1234f985da17SGuennadi Liakhovetski break;
1235f985da17SGuennadi Liakhovetski }
1236f985da17SGuennadi Liakhovetski sh_mmcif_get_cmd12response(host, mrq->stop);
1237f985da17SGuennadi Liakhovetski mrq->stop->error = 0;
1238f985da17SGuennadi Liakhovetski break;
1239f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END:
1240f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END:
1241e475b270STeppei Kamijou if (host->sd_error) {
124291ab252aSGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host);
1243585c3a5aSKuninori Morimoto dev_dbg(dev, "%s(): %d\n", __func__, mrq->data->error);
1244e475b270STeppei Kamijou }
1245f985da17SGuennadi Liakhovetski break;
1246f985da17SGuennadi Liakhovetski default:
1247f985da17SGuennadi Liakhovetski BUG();
1248f985da17SGuennadi Liakhovetski }
1249f985da17SGuennadi Liakhovetski
12505df460b1SGuennadi Liakhovetski if (wait) {
12515df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout);
12525df460b1SGuennadi Liakhovetski /* Wait for more data */
12538047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock);
12545df460b1SGuennadi Liakhovetski return IRQ_HANDLED;
12555df460b1SGuennadi Liakhovetski }
12565df460b1SGuennadi Liakhovetski
1257f985da17SGuennadi Liakhovetski if (host->wait_for != MMCIF_WAIT_FOR_STOP) {
125891ab252aSGuennadi Liakhovetski struct mmc_data *data = mrq->data;
125969983404SGuennadi Liakhovetski if (!mrq->cmd->error && data && !data->error)
126069983404SGuennadi Liakhovetski data->bytes_xfered =
126169983404SGuennadi Liakhovetski data->blocks * data->blksz;
1262f985da17SGuennadi Liakhovetski
126369983404SGuennadi Liakhovetski if (mrq->stop && !mrq->cmd->error && (!data || !data->error)) {
1264f985da17SGuennadi Liakhovetski sh_mmcif_stop_cmd(host, mrq);
12655df460b1SGuennadi Liakhovetski if (!mrq->stop->error) {
12665df460b1SGuennadi Liakhovetski schedule_delayed_work(&host->timeout_work, host->timeout);
12678047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock);
1268f985da17SGuennadi Liakhovetski return IRQ_HANDLED;
1269f985da17SGuennadi Liakhovetski }
1270f985da17SGuennadi Liakhovetski }
12715df460b1SGuennadi Liakhovetski }
1272f985da17SGuennadi Liakhovetski
1273f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1274f985da17SGuennadi Liakhovetski host->state = STATE_IDLE;
127569983404SGuennadi Liakhovetski host->mrq = NULL;
1276f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq);
1277f985da17SGuennadi Liakhovetski
12788047310eSGuennadi Liakhovetski mutex_unlock(&host->thread_lock);
12798047310eSGuennadi Liakhovetski
1280f985da17SGuennadi Liakhovetski return IRQ_HANDLED;
1281f985da17SGuennadi Liakhovetski }
1282f985da17SGuennadi Liakhovetski
sh_mmcif_intr(int irq,void * dev_id)1283fdc50a94SYusuke Goda static irqreturn_t sh_mmcif_intr(int irq, void *dev_id)
1284fdc50a94SYusuke Goda {
1285fdc50a94SYusuke Goda struct sh_mmcif_host *host = dev_id;
1286585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
1287967bcb77SGuennadi Liakhovetski u32 state, mask;
1288fdc50a94SYusuke Goda
1289487d9fc5SMagnus Damm state = sh_mmcif_readl(host->addr, MMCIF_CE_INT);
1290967bcb77SGuennadi Liakhovetski mask = sh_mmcif_readl(host->addr, MMCIF_CE_INT_MASK);
1291967bcb77SGuennadi Liakhovetski if (host->ccs_enable)
1292967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, ~(state & mask));
1293967bcb77SGuennadi Liakhovetski else
1294967bcb77SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT, INT_CCS | ~(state & mask));
12958af50750SGuennadi Liakhovetski sh_mmcif_bitclr(host, MMCIF_CE_INT_MASK, state & MASK_CLEAN);
1296fdc50a94SYusuke Goda
12978af50750SGuennadi Liakhovetski if (state & ~MASK_CLEAN)
1298585c3a5aSKuninori Morimoto dev_dbg(dev, "IRQ state = 0x%08x incompletely cleared\n",
12998af50750SGuennadi Liakhovetski state);
13008af50750SGuennadi Liakhovetski
13018af50750SGuennadi Liakhovetski if (state & INT_ERR_STS || state & ~INT_ALL) {
1302aa0787a9SGuennadi Liakhovetski host->sd_error = true;
1303585c3a5aSKuninori Morimoto dev_dbg(dev, "int err state = 0x%08x\n", state);
1304fdc50a94SYusuke Goda }
1305f985da17SGuennadi Liakhovetski if (state & ~(INT_CMD12RBE | INT_CMD12CRE)) {
13068af50750SGuennadi Liakhovetski if (!host->mrq)
1307585c3a5aSKuninori Morimoto dev_dbg(dev, "NULL IRQ state = 0x%08x\n", state);
1308f985da17SGuennadi Liakhovetski if (!host->dma_active)
1309f985da17SGuennadi Liakhovetski return IRQ_WAKE_THREAD;
1310f985da17SGuennadi Liakhovetski else if (host->sd_error)
13111b1a694dSKuninori Morimoto sh_mmcif_dma_complete(host);
1312f985da17SGuennadi Liakhovetski } else {
1313585c3a5aSKuninori Morimoto dev_dbg(dev, "Unexpected IRQ 0x%x\n", state);
1314f985da17SGuennadi Liakhovetski }
1315fdc50a94SYusuke Goda
1316fdc50a94SYusuke Goda return IRQ_HANDLED;
1317fdc50a94SYusuke Goda }
1318fdc50a94SYusuke Goda
sh_mmcif_timeout_work(struct work_struct * work)13191b1a694dSKuninori Morimoto static void sh_mmcif_timeout_work(struct work_struct *work)
1320f985da17SGuennadi Liakhovetski {
13211046a811SGeliang Tang struct delayed_work *d = to_delayed_work(work);
1322f985da17SGuennadi Liakhovetski struct sh_mmcif_host *host = container_of(d, struct sh_mmcif_host, timeout_work);
1323f985da17SGuennadi Liakhovetski struct mmc_request *mrq = host->mrq;
1324585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
13258047310eSGuennadi Liakhovetski unsigned long flags;
1326f985da17SGuennadi Liakhovetski
1327f985da17SGuennadi Liakhovetski if (host->dying)
1328f985da17SGuennadi Liakhovetski /* Don't run after mmc_remove_host() */
1329f985da17SGuennadi Liakhovetski return;
1330f985da17SGuennadi Liakhovetski
13318047310eSGuennadi Liakhovetski spin_lock_irqsave(&host->lock, flags);
13328047310eSGuennadi Liakhovetski if (host->state == STATE_IDLE) {
13338047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags);
13348047310eSGuennadi Liakhovetski return;
13358047310eSGuennadi Liakhovetski }
13368047310eSGuennadi Liakhovetski
1337585c3a5aSKuninori Morimoto dev_err(dev, "Timeout waiting for %u on CMD%u\n",
13384cbd5224SKouichi Tomita host->wait_for, mrq->cmd->opcode);
13394cbd5224SKouichi Tomita
13408047310eSGuennadi Liakhovetski host->state = STATE_TIMEOUT;
13418047310eSGuennadi Liakhovetski spin_unlock_irqrestore(&host->lock, flags);
13428047310eSGuennadi Liakhovetski
1343f985da17SGuennadi Liakhovetski /*
1344f985da17SGuennadi Liakhovetski * Handle races with cancel_delayed_work(), unless
1345f985da17SGuennadi Liakhovetski * cancel_delayed_work_sync() is used
1346f985da17SGuennadi Liakhovetski */
1347f985da17SGuennadi Liakhovetski switch (host->wait_for) {
1348f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_CMD:
1349f985da17SGuennadi Liakhovetski mrq->cmd->error = sh_mmcif_error_manage(host);
1350f985da17SGuennadi Liakhovetski break;
1351f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_STOP:
1352f985da17SGuennadi Liakhovetski mrq->stop->error = sh_mmcif_error_manage(host);
1353f985da17SGuennadi Liakhovetski break;
1354f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MREAD:
1355f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_MWRITE:
1356f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ:
1357f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE:
1358f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_READ_END:
1359f985da17SGuennadi Liakhovetski case MMCIF_WAIT_FOR_WRITE_END:
136069983404SGuennadi Liakhovetski mrq->data->error = sh_mmcif_error_manage(host);
1361f985da17SGuennadi Liakhovetski break;
1362f985da17SGuennadi Liakhovetski default:
1363f985da17SGuennadi Liakhovetski BUG();
1364f985da17SGuennadi Liakhovetski }
1365f985da17SGuennadi Liakhovetski
1366f985da17SGuennadi Liakhovetski host->state = STATE_IDLE;
1367f985da17SGuennadi Liakhovetski host->wait_for = MMCIF_WAIT_FOR_REQUEST;
1368f985da17SGuennadi Liakhovetski host->mrq = NULL;
1369f985da17SGuennadi Liakhovetski mmc_request_done(host->mmc, mrq);
1370f985da17SGuennadi Liakhovetski }
1371f985da17SGuennadi Liakhovetski
sh_mmcif_init_ocr(struct sh_mmcif_host * host)13727d17baa0SGuennadi Liakhovetski static void sh_mmcif_init_ocr(struct sh_mmcif_host *host)
13737d17baa0SGuennadi Liakhovetski {
1374585c3a5aSKuninori Morimoto struct device *dev = sh_mmcif_host_to_dev(host);
1375585c3a5aSKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data;
13767d17baa0SGuennadi Liakhovetski struct mmc_host *mmc = host->mmc;
13777d17baa0SGuennadi Liakhovetski
13787d17baa0SGuennadi Liakhovetski mmc_regulator_get_supply(mmc);
13797d17baa0SGuennadi Liakhovetski
1380bf68a812SGuennadi Liakhovetski if (!pd)
1381bf68a812SGuennadi Liakhovetski return;
1382bf68a812SGuennadi Liakhovetski
13837d17baa0SGuennadi Liakhovetski if (!mmc->ocr_avail)
13847d17baa0SGuennadi Liakhovetski mmc->ocr_avail = pd->ocr;
13857d17baa0SGuennadi Liakhovetski else if (pd->ocr)
13867d17baa0SGuennadi Liakhovetski dev_warn(mmc_dev(mmc), "Platform OCR mask is ignored\n");
13877d17baa0SGuennadi Liakhovetski }
13887d17baa0SGuennadi Liakhovetski
sh_mmcif_probe(struct platform_device * pdev)1389c3be1efdSBill Pemberton static int sh_mmcif_probe(struct platform_device *pdev)
1390fdc50a94SYusuke Goda {
1391fdc50a94SYusuke Goda int ret = 0, irq[2];
1392fdc50a94SYusuke Goda struct mmc_host *mmc;
1393e47bf32aSGuennadi Liakhovetski struct sh_mmcif_host *host;
139460985c39SKuninori Morimoto struct device *dev = &pdev->dev;
139560985c39SKuninori Morimoto struct sh_mmcif_plat_data *pd = dev->platform_data;
1396fdc50a94SYusuke Goda void __iomem *reg;
13972cd5b3e0SShinya Kuribayashi const char *name;
1398fdc50a94SYusuke Goda
1399fdc50a94SYusuke Goda irq[0] = platform_get_irq(pdev, 0);
1400faf97b84SGeert Uytterhoeven irq[1] = platform_get_irq_optional(pdev, 1);
1401faf97b84SGeert Uytterhoeven if (irq[0] < 0)
14025b067d7fSSergey Shtylyov return irq[0];
140318f55fccSBen Dooks
140434ac4509SYangtao Li reg = devm_platform_ioremap_resource(pdev, 0);
140518f55fccSBen Dooks if (IS_ERR(reg))
140618f55fccSBen Dooks return PTR_ERR(reg);
1407e1aae2ebSGuennadi Liakhovetski
140860985c39SKuninori Morimoto mmc = mmc_alloc_host(sizeof(struct sh_mmcif_host), dev);
140918f55fccSBen Dooks if (!mmc)
141018f55fccSBen Dooks return -ENOMEM;
14112c9054dcSSimon Baatz
14122c9054dcSSimon Baatz ret = mmc_of_parse(mmc);
14132c9054dcSSimon Baatz if (ret < 0)
141446991005SBen Dooks goto err_host;
14152c9054dcSSimon Baatz
1416fdc50a94SYusuke Goda host = mmc_priv(mmc);
1417fdc50a94SYusuke Goda host->mmc = mmc;
1418fdc50a94SYusuke Goda host->addr = reg;
1419bad4371dSTakeshi Kihara host->timeout = msecs_to_jiffies(10000);
14208020f711SUlf Hansson host->ccs_enable = true;
1421dba4bb48SUlf Hansson host->clk_ctrl2_enable = false;
1422fdc50a94SYusuke Goda
1423fdc50a94SYusuke Goda host->pd = pdev;
1424fdc50a94SYusuke Goda
14253b0beafcSGuennadi Liakhovetski spin_lock_init(&host->lock);
1426fdc50a94SYusuke Goda
1427fdc50a94SYusuke Goda mmc->ops = &sh_mmcif_ops;
14287d17baa0SGuennadi Liakhovetski sh_mmcif_init_ocr(host);
14297d17baa0SGuennadi Liakhovetski
1430eca889f6SGuennadi Liakhovetski mmc->caps |= MMC_CAP_MMC_HIGHSPEED | MMC_CAP_WAIT_WHILE_BUSY;
1431dab3a28bSUlf Hansson mmc->caps2 |= MMC_CAP2_NO_SD | MMC_CAP2_NO_SDIO;
1432549646a9SUlf Hansson mmc->max_busy_timeout = 10000;
1433dab3a28bSUlf Hansson
1434bf68a812SGuennadi Liakhovetski if (pd && pd->caps)
1435fdc50a94SYusuke Goda mmc->caps |= pd->caps;
1436a782d688SGuennadi Liakhovetski mmc->max_segs = 32;
1437fdc50a94SYusuke Goda mmc->max_blk_size = 512;
143809cbfeafSKirill A. Shutemov mmc->max_req_size = PAGE_SIZE * mmc->max_segs;
1439a782d688SGuennadi Liakhovetski mmc->max_blk_count = mmc->max_req_size / mmc->max_blk_size;
1440fdc50a94SYusuke Goda mmc->max_seg_size = mmc->max_req_size;
1441fdc50a94SYusuke Goda
1442fdc50a94SYusuke Goda platform_set_drvdata(pdev, host);
1443a782d688SGuennadi Liakhovetski
14446aed678bSKuninori Morimoto host->clk = devm_clk_get(dev, NULL);
14456aed678bSKuninori Morimoto if (IS_ERR(host->clk)) {
14466aed678bSKuninori Morimoto ret = PTR_ERR(host->clk);
144760985c39SKuninori Morimoto dev_err(dev, "cannot get clock: %d\n", ret);
144888ac2a2cSUlf Hansson goto err_host;
1449b289174fSGuennadi Liakhovetski }
14509bb09a30SKuninori Morimoto
14519bb09a30SKuninori Morimoto ret = clk_prepare_enable(host->clk);
1452a6609267SGuennadi Liakhovetski if (ret < 0)
145388ac2a2cSUlf Hansson goto err_host;
1454b289174fSGuennadi Liakhovetski
14559bb09a30SKuninori Morimoto sh_mmcif_clk_setup(host);
14569bb09a30SKuninori Morimoto
145788ac2a2cSUlf Hansson pm_runtime_enable(dev);
145888ac2a2cSUlf Hansson host->power = false;
145988ac2a2cSUlf Hansson
146088ac2a2cSUlf Hansson ret = pm_runtime_get_sync(dev);
1461faca6648SGuennadi Liakhovetski if (ret < 0)
146246991005SBen Dooks goto err_clk;
1463a782d688SGuennadi Liakhovetski
14641b1a694dSKuninori Morimoto INIT_DELAYED_WORK(&host->timeout_work, sh_mmcif_timeout_work);
1465fdc50a94SYusuke Goda
1466b289174fSGuennadi Liakhovetski sh_mmcif_sync_reset(host);
14673b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
14683b0beafcSGuennadi Liakhovetski
146960985c39SKuninori Morimoto name = irq[1] < 0 ? dev_name(dev) : "sh_mmc:error";
147060985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[0], sh_mmcif_intr,
14716f4789e6SBen Dooks sh_mmcif_irqt, 0, name, host);
1472fdc50a94SYusuke Goda if (ret) {
147360985c39SKuninori Morimoto dev_err(dev, "request_irq error (%s)\n", name);
147411a80852SBen Dooks goto err_clk;
1475fdc50a94SYusuke Goda }
14762cd5b3e0SShinya Kuribayashi if (irq[1] >= 0) {
147760985c39SKuninori Morimoto ret = devm_request_threaded_irq(dev, irq[1],
14786f4789e6SBen Dooks sh_mmcif_intr, sh_mmcif_irqt,
14792cd5b3e0SShinya Kuribayashi 0, "sh_mmc:int", host);
1480fdc50a94SYusuke Goda if (ret) {
148160985c39SKuninori Morimoto dev_err(dev, "request_irq error (sh_mmc:int)\n");
148211a80852SBen Dooks goto err_clk;
1483fdc50a94SYusuke Goda }
14842cd5b3e0SShinya Kuribayashi }
1485fdc50a94SYusuke Goda
14868047310eSGuennadi Liakhovetski mutex_init(&host->thread_lock);
14878047310eSGuennadi Liakhovetski
14885ba85d95SGuennadi Liakhovetski ret = mmc_add_host(mmc);
14895ba85d95SGuennadi Liakhovetski if (ret < 0)
14907f67f3a2SBen Dooks goto err_clk;
1491fdc50a94SYusuke Goda
149260985c39SKuninori Morimoto dev_pm_qos_expose_latency_limit(dev, 100);
1493efe6a8adSRafael J. Wysocki
149460985c39SKuninori Morimoto dev_info(dev, "Chip version 0x%04x, clock rate %luMHz\n",
1495ce7eb688SBen Dooks sh_mmcif_readl(host->addr, MMCIF_CE_VERSION) & 0xffff,
14966aed678bSKuninori Morimoto clk_get_rate(host->clk) / 1000000UL);
1497ce7eb688SBen Dooks
149888ac2a2cSUlf Hansson pm_runtime_put(dev);
14996aed678bSKuninori Morimoto clk_disable_unprepare(host->clk);
1500fdc50a94SYusuke Goda return ret;
1501fdc50a94SYusuke Goda
150246991005SBen Dooks err_clk:
15036aed678bSKuninori Morimoto clk_disable_unprepare(host->clk);
150488ac2a2cSUlf Hansson pm_runtime_put_sync(dev);
150560985c39SKuninori Morimoto pm_runtime_disable(dev);
150646991005SBen Dooks err_host:
1507fdc50a94SYusuke Goda mmc_free_host(mmc);
1508fdc50a94SYusuke Goda return ret;
1509fdc50a94SYusuke Goda }
1510fdc50a94SYusuke Goda
sh_mmcif_remove(struct platform_device * pdev)1511*8fc8c82dSYangtao Li static void sh_mmcif_remove(struct platform_device *pdev)
1512fdc50a94SYusuke Goda {
1513fdc50a94SYusuke Goda struct sh_mmcif_host *host = platform_get_drvdata(pdev);
1514fdc50a94SYusuke Goda
1515f985da17SGuennadi Liakhovetski host->dying = true;
15166aed678bSKuninori Morimoto clk_prepare_enable(host->clk);
1517faca6648SGuennadi Liakhovetski pm_runtime_get_sync(&pdev->dev);
1518aa0787a9SGuennadi Liakhovetski
1519efe6a8adSRafael J. Wysocki dev_pm_qos_hide_latency_limit(&pdev->dev);
1520efe6a8adSRafael J. Wysocki
1521faca6648SGuennadi Liakhovetski mmc_remove_host(host->mmc);
15223b0beafcSGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
15233b0beafcSGuennadi Liakhovetski
1524f985da17SGuennadi Liakhovetski /*
1525f985da17SGuennadi Liakhovetski * FIXME: cancel_delayed_work(_sync)() and free_irq() race with the
1526f985da17SGuennadi Liakhovetski * mmc_remove_host() call above. But swapping order doesn't help either
1527f985da17SGuennadi Liakhovetski * (a query on the linux-mmc mailing list didn't bring any replies).
1528f985da17SGuennadi Liakhovetski */
1529f985da17SGuennadi Liakhovetski cancel_delayed_work_sync(&host->timeout_work);
1530f985da17SGuennadi Liakhovetski
15316aed678bSKuninori Morimoto clk_disable_unprepare(host->clk);
1532fdc50a94SYusuke Goda mmc_free_host(host->mmc);
1533faca6648SGuennadi Liakhovetski pm_runtime_put_sync(&pdev->dev);
1534faca6648SGuennadi Liakhovetski pm_runtime_disable(&pdev->dev);
1535fdc50a94SYusuke Goda }
1536fdc50a94SYusuke Goda
153751129f31SUlf Hansson #ifdef CONFIG_PM_SLEEP
sh_mmcif_suspend(struct device * dev)1538faca6648SGuennadi Liakhovetski static int sh_mmcif_suspend(struct device *dev)
1539faca6648SGuennadi Liakhovetski {
1540b289174fSGuennadi Liakhovetski struct sh_mmcif_host *host = dev_get_drvdata(dev);
1541faca6648SGuennadi Liakhovetski
15425afc30fcSKoji Matsuoka pm_runtime_get_sync(dev);
1543faca6648SGuennadi Liakhovetski sh_mmcif_writel(host->addr, MMCIF_CE_INT_MASK, MASK_ALL);
15445afc30fcSKoji Matsuoka pm_runtime_put(dev);
1545faca6648SGuennadi Liakhovetski
1546cb3ca1aeSUlf Hansson return 0;
1547faca6648SGuennadi Liakhovetski }
1548faca6648SGuennadi Liakhovetski
sh_mmcif_resume(struct device * dev)1549faca6648SGuennadi Liakhovetski static int sh_mmcif_resume(struct device *dev)
1550faca6648SGuennadi Liakhovetski {
1551cb3ca1aeSUlf Hansson return 0;
1552faca6648SGuennadi Liakhovetski }
155351129f31SUlf Hansson #endif
1554faca6648SGuennadi Liakhovetski
1555faca6648SGuennadi Liakhovetski static const struct dev_pm_ops sh_mmcif_dev_pm_ops = {
155651129f31SUlf Hansson SET_SYSTEM_SLEEP_PM_OPS(sh_mmcif_suspend, sh_mmcif_resume)
1557faca6648SGuennadi Liakhovetski };
1558faca6648SGuennadi Liakhovetski
1559fdc50a94SYusuke Goda static struct platform_driver sh_mmcif_driver = {
1560fdc50a94SYusuke Goda .probe = sh_mmcif_probe,
1561*8fc8c82dSYangtao Li .remove_new = sh_mmcif_remove,
1562fdc50a94SYusuke Goda .driver = {
1563fdc50a94SYusuke Goda .name = DRIVER_NAME,
156421b2cec6SDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS,
1565faca6648SGuennadi Liakhovetski .pm = &sh_mmcif_dev_pm_ops,
15661b1a694dSKuninori Morimoto .of_match_table = sh_mmcif_of_match,
1567fdc50a94SYusuke Goda },
1568fdc50a94SYusuke Goda };
1569fdc50a94SYusuke Goda
1570d1f81a64SAxel Lin module_platform_driver(sh_mmcif_driver);
1571fdc50a94SYusuke Goda
1572fdc50a94SYusuke Goda MODULE_DESCRIPTION("SuperH on-chip MMC/eMMC interface driver");
1573f707079dSWolfram Sang MODULE_LICENSE("GPL v2");
1574aa0787a9SGuennadi Liakhovetski MODULE_ALIAS("platform:" DRIVER_NAME);
1575fdc50a94SYusuke Goda MODULE_AUTHOR("Yusuke Goda <yusuke.goda.sx@renesas.com>");
1576