xref: /openbmc/linux/drivers/mmc/host/sdhci_f_sdh30.c (revision 5914a9b1)
1 // SPDX-License-Identifier: GPL-2.0-only
2 /*
3  * linux/drivers/mmc/host/sdhci_f_sdh30.c
4  *
5  * Copyright (C) 2013 - 2015 Fujitsu Semiconductor, Ltd
6  *              Vincent Yang <vincent.yang@tw.fujitsu.com>
7  * Copyright (C) 2015 Linaro Ltd  Andy Green <andy.green@linaro.org>
8  * Copyright (C) 2019 Socionext Inc.
9  */
10 
11 #include <linux/acpi.h>
12 #include <linux/err.h>
13 #include <linux/delay.h>
14 #include <linux/module.h>
15 #include <linux/of.h>
16 #include <linux/property.h>
17 #include <linux/clk.h>
18 #include <linux/reset.h>
19 
20 #include "sdhci-pltfm.h"
21 #include "sdhci_f_sdh30.h"
22 
23 struct f_sdhost_priv {
24 	struct clk *clk_iface;
25 	struct clk *clk;
26 	struct reset_control *rst;
27 	u32 vendor_hs200;
28 	struct device *dev;
29 	bool enable_cmd_dat_delay;
30 };
31 
32 static void sdhci_f_sdh30_soft_voltage_switch(struct sdhci_host *host)
33 {
34 	struct f_sdhost_priv *priv = sdhci_priv(host);
35 	u32 ctrl = 0;
36 
37 	usleep_range(2500, 3000);
38 	ctrl = sdhci_readl(host, F_SDH30_IO_CONTROL2);
39 	ctrl |= F_SDH30_CRES_O_DN;
40 	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
41 	ctrl |= F_SDH30_MSEL_O_1_8;
42 	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
43 
44 	ctrl &= ~F_SDH30_CRES_O_DN;
45 	sdhci_writel(host, ctrl, F_SDH30_IO_CONTROL2);
46 	usleep_range(2500, 3000);
47 
48 	if (priv->vendor_hs200) {
49 		dev_info(priv->dev, "%s: setting hs200\n", __func__);
50 		ctrl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
51 		ctrl |= priv->vendor_hs200;
52 		sdhci_writel(host, ctrl, F_SDH30_ESD_CONTROL);
53 	}
54 
55 	ctrl = sdhci_readl(host, F_SDH30_TUNING_SETTING);
56 	ctrl |= F_SDH30_CMD_CHK_DIS;
57 	sdhci_writel(host, ctrl, F_SDH30_TUNING_SETTING);
58 }
59 
60 static unsigned int sdhci_f_sdh30_get_min_clock(struct sdhci_host *host)
61 {
62 	return F_SDH30_MIN_CLOCK;
63 }
64 
65 static void sdhci_f_sdh30_reset(struct sdhci_host *host, u8 mask)
66 {
67 	struct f_sdhost_priv *priv = sdhci_priv(host);
68 	u32 ctl;
69 
70 	if (sdhci_readw(host, SDHCI_CLOCK_CONTROL) == 0)
71 		sdhci_writew(host, 0xBC01, SDHCI_CLOCK_CONTROL);
72 
73 	sdhci_reset(host, mask);
74 
75 	if (priv->enable_cmd_dat_delay) {
76 		ctl = sdhci_readl(host, F_SDH30_ESD_CONTROL);
77 		ctl |= F_SDH30_CMD_DAT_DELAY;
78 		sdhci_writel(host, ctl, F_SDH30_ESD_CONTROL);
79 	}
80 }
81 
82 static const struct sdhci_ops sdhci_f_sdh30_ops = {
83 	.voltage_switch = sdhci_f_sdh30_soft_voltage_switch,
84 	.get_min_clock = sdhci_f_sdh30_get_min_clock,
85 	.reset = sdhci_f_sdh30_reset,
86 	.set_clock = sdhci_set_clock,
87 	.set_bus_width = sdhci_set_bus_width,
88 	.set_uhs_signaling = sdhci_set_uhs_signaling,
89 };
90 
91 static int sdhci_f_sdh30_probe(struct platform_device *pdev)
92 {
93 	struct sdhci_host *host;
94 	struct device *dev = &pdev->dev;
95 	int irq, ctrl = 0, ret = 0;
96 	struct f_sdhost_priv *priv;
97 	u32 reg = 0;
98 
99 	irq = platform_get_irq(pdev, 0);
100 	if (irq < 0)
101 		return irq;
102 
103 	host = sdhci_alloc_host(dev, sizeof(struct f_sdhost_priv));
104 	if (IS_ERR(host))
105 		return PTR_ERR(host);
106 
107 	priv = sdhci_priv(host);
108 	priv->dev = dev;
109 
110 	host->quirks = SDHCI_QUIRK_NO_ENDATTR_IN_NOPDESC |
111 		       SDHCI_QUIRK_INVERTED_WRITE_PROTECT;
112 	host->quirks2 = SDHCI_QUIRK2_SUPPORT_SINGLE |
113 			SDHCI_QUIRK2_TUNING_WORK_AROUND;
114 
115 	priv->enable_cmd_dat_delay = device_property_read_bool(dev,
116 						"fujitsu,cmd-dat-delay-select");
117 
118 	ret = mmc_of_parse(host->mmc);
119 	if (ret)
120 		goto err;
121 
122 	platform_set_drvdata(pdev, host);
123 
124 	host->hw_name = "f_sdh30";
125 	host->ops = &sdhci_f_sdh30_ops;
126 	host->irq = irq;
127 
128 	host->ioaddr = devm_platform_ioremap_resource(pdev, 0);
129 	if (IS_ERR(host->ioaddr)) {
130 		ret = PTR_ERR(host->ioaddr);
131 		goto err;
132 	}
133 
134 	if (dev_of_node(dev)) {
135 		sdhci_get_of_property(pdev);
136 
137 		priv->clk_iface = devm_clk_get(&pdev->dev, "iface");
138 		if (IS_ERR(priv->clk_iface)) {
139 			ret = PTR_ERR(priv->clk_iface);
140 			goto err;
141 		}
142 
143 		ret = clk_prepare_enable(priv->clk_iface);
144 		if (ret)
145 			goto err;
146 
147 		priv->clk = devm_clk_get(&pdev->dev, "core");
148 		if (IS_ERR(priv->clk)) {
149 			ret = PTR_ERR(priv->clk);
150 			goto err_clk;
151 		}
152 
153 		ret = clk_prepare_enable(priv->clk);
154 		if (ret)
155 			goto err_clk;
156 
157 		priv->rst = devm_reset_control_get_optional_shared(dev, NULL);
158 		if (IS_ERR(priv->rst)) {
159 			ret = PTR_ERR(priv->rst);
160 			goto err_rst;
161 		}
162 
163 		ret = reset_control_deassert(priv->rst);
164 		if (ret)
165 			goto err_rst;
166 	}
167 
168 	/* init vendor specific regs */
169 	ctrl = sdhci_readw(host, F_SDH30_AHB_CONFIG);
170 	ctrl |= F_SDH30_SIN | F_SDH30_AHB_INCR_16 | F_SDH30_AHB_INCR_8 |
171 		F_SDH30_AHB_INCR_4;
172 	ctrl &= ~(F_SDH30_AHB_BIGED | F_SDH30_BUSLOCK_EN);
173 	sdhci_writew(host, ctrl, F_SDH30_AHB_CONFIG);
174 
175 	reg = sdhci_readl(host, F_SDH30_ESD_CONTROL);
176 	sdhci_writel(host, reg & ~F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
177 	msleep(20);
178 	sdhci_writel(host, reg | F_SDH30_EMMC_RST, F_SDH30_ESD_CONTROL);
179 
180 	reg = sdhci_readl(host, SDHCI_CAPABILITIES);
181 	if (reg & SDHCI_CAN_DO_8BIT)
182 		priv->vendor_hs200 = F_SDH30_EMMC_HS200;
183 
184 	ret = sdhci_add_host(host);
185 	if (ret)
186 		goto err_add_host;
187 
188 	return 0;
189 
190 err_add_host:
191 	reset_control_assert(priv->rst);
192 err_rst:
193 	clk_disable_unprepare(priv->clk);
194 err_clk:
195 	clk_disable_unprepare(priv->clk_iface);
196 err:
197 	sdhci_free_host(host);
198 	return ret;
199 }
200 
201 static int sdhci_f_sdh30_remove(struct platform_device *pdev)
202 {
203 	struct sdhci_host *host = platform_get_drvdata(pdev);
204 	struct f_sdhost_priv *priv = sdhci_priv(host);
205 
206 	sdhci_remove_host(host, readl(host->ioaddr + SDHCI_INT_STATUS) ==
207 			  0xffffffff);
208 
209 	reset_control_assert(priv->rst);
210 	clk_disable_unprepare(priv->clk);
211 	clk_disable_unprepare(priv->clk_iface);
212 
213 	sdhci_free_host(host);
214 	platform_set_drvdata(pdev, NULL);
215 
216 	return 0;
217 }
218 
219 #ifdef CONFIG_OF
220 static const struct of_device_id f_sdh30_dt_ids[] = {
221 	{ .compatible = "fujitsu,mb86s70-sdhci-3.0" },
222 	{ .compatible = "socionext,f-sdh30-e51-mmc" },
223 	{ /* sentinel */ }
224 };
225 MODULE_DEVICE_TABLE(of, f_sdh30_dt_ids);
226 #endif
227 
228 #ifdef CONFIG_ACPI
229 static const struct acpi_device_id f_sdh30_acpi_ids[] = {
230 	{ "SCX0002" },
231 	{ /* sentinel */ }
232 };
233 MODULE_DEVICE_TABLE(acpi, f_sdh30_acpi_ids);
234 #endif
235 
236 static struct platform_driver sdhci_f_sdh30_driver = {
237 	.driver = {
238 		.name = "f_sdh30",
239 		.probe_type = PROBE_PREFER_ASYNCHRONOUS,
240 		.of_match_table = of_match_ptr(f_sdh30_dt_ids),
241 		.acpi_match_table = ACPI_PTR(f_sdh30_acpi_ids),
242 		.pm	= &sdhci_pltfm_pmops,
243 	},
244 	.probe	= sdhci_f_sdh30_probe,
245 	.remove	= sdhci_f_sdh30_remove,
246 };
247 
248 module_platform_driver(sdhci_f_sdh30_driver);
249 
250 MODULE_DESCRIPTION("F_SDH30 SD Card Controller driver");
251 MODULE_LICENSE("GPL v2");
252 MODULE_AUTHOR("FUJITSU SEMICONDUCTOR LTD., Socionext Inc.");
253 MODULE_ALIAS("platform:f_sdh30");
254