1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/of.h> 10 #include <linux/module.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/property.h> 13 #include <linux/regmap.h> 14 #include <linux/sys_soc.h> 15 16 #include "cqhci.h" 17 #include "sdhci-pltfm.h" 18 19 /* CTL_CFG Registers */ 20 #define CTL_CFG_2 0x14 21 22 #define SLOTTYPE_MASK GENMASK(31, 30) 23 #define SLOTTYPE_EMBEDDED BIT(30) 24 25 /* PHY Registers */ 26 #define PHY_CTRL1 0x100 27 #define PHY_CTRL2 0x104 28 #define PHY_CTRL3 0x108 29 #define PHY_CTRL4 0x10C 30 #define PHY_CTRL5 0x110 31 #define PHY_CTRL6 0x114 32 #define PHY_STAT1 0x130 33 #define PHY_STAT2 0x134 34 35 #define IOMUX_ENABLE_SHIFT 31 36 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 37 #define OTAPDLYENA_SHIFT 20 38 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 39 #define OTAPDLYSEL_SHIFT 12 40 #define OTAPDLYSEL_MASK GENMASK(15, 12) 41 #define STRBSEL_SHIFT 24 42 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 43 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 44 #define SEL50_SHIFT 8 45 #define SEL50_MASK BIT(SEL50_SHIFT) 46 #define SEL100_SHIFT 9 47 #define SEL100_MASK BIT(SEL100_SHIFT) 48 #define FREQSEL_SHIFT 8 49 #define FREQSEL_MASK GENMASK(10, 8) 50 #define DLL_TRIM_ICP_SHIFT 4 51 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 52 #define DR_TY_SHIFT 20 53 #define DR_TY_MASK GENMASK(22, 20) 54 #define ENDLL_SHIFT 1 55 #define ENDLL_MASK BIT(ENDLL_SHIFT) 56 #define DLLRDY_SHIFT 0 57 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 58 #define PDB_SHIFT 0 59 #define PDB_MASK BIT(PDB_SHIFT) 60 #define CALDONE_SHIFT 1 61 #define CALDONE_MASK BIT(CALDONE_SHIFT) 62 #define RETRIM_SHIFT 17 63 #define RETRIM_MASK BIT(RETRIM_SHIFT) 64 65 #define DRIVER_STRENGTH_50_OHM 0x0 66 #define DRIVER_STRENGTH_33_OHM 0x1 67 #define DRIVER_STRENGTH_66_OHM 0x2 68 #define DRIVER_STRENGTH_100_OHM 0x3 69 #define DRIVER_STRENGTH_40_OHM 0x4 70 71 #define CLOCK_TOO_SLOW_HZ 400000 72 73 /* Command Queue Host Controller Interface Base address */ 74 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 75 76 static struct regmap_config sdhci_am654_regmap_config = { 77 .reg_bits = 32, 78 .val_bits = 32, 79 .reg_stride = 4, 80 .fast_io = true, 81 }; 82 83 struct sdhci_am654_data { 84 struct regmap *base; 85 bool legacy_otapdly; 86 int otap_del_sel[11]; 87 int trm_icp; 88 int drv_strength; 89 bool dll_on; 90 int strb_sel; 91 u32 flags; 92 }; 93 94 struct sdhci_am654_driver_data { 95 const struct sdhci_pltfm_data *pdata; 96 u32 flags; 97 #define IOMUX_PRESENT (1 << 0) 98 #define FREQSEL_2_BIT (1 << 1) 99 #define STRBSEL_4_BIT (1 << 2) 100 #define DLL_PRESENT (1 << 3) 101 #define DLL_CALIB (1 << 4) 102 }; 103 104 struct timing_data { 105 const char *binding; 106 u32 capability; 107 }; 108 109 static const struct timing_data td[] = { 110 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0}, 111 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED}, 112 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED}, 113 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12}, 114 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25}, 115 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50}, 116 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 117 MMC_CAP_UHS_SDR104}, 118 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50}, 119 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR}, 120 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200}, 121 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400}, 122 }; 123 124 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 125 { 126 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 127 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 128 int sel50, sel100, freqsel; 129 u32 mask, val; 130 int ret; 131 132 if (sdhci_am654->flags & FREQSEL_2_BIT) { 133 switch (clock) { 134 case 200000000: 135 sel50 = 0; 136 sel100 = 0; 137 break; 138 case 100000000: 139 sel50 = 0; 140 sel100 = 1; 141 break; 142 default: 143 sel50 = 1; 144 sel100 = 0; 145 } 146 147 /* Configure PHY DLL frequency */ 148 mask = SEL50_MASK | SEL100_MASK; 149 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 150 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 151 152 } else { 153 switch (clock) { 154 case 200000000: 155 freqsel = 0x0; 156 break; 157 default: 158 freqsel = 0x4; 159 } 160 161 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 162 freqsel << FREQSEL_SHIFT); 163 } 164 /* Configure DLL TRIM */ 165 mask = DLL_TRIM_ICP_MASK; 166 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 167 168 /* Configure DLL driver strength */ 169 mask |= DR_TY_MASK; 170 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 171 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 172 173 /* Enable DLL */ 174 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 175 0x1 << ENDLL_SHIFT); 176 /* 177 * Poll for DLL ready. Use a one second timeout. 178 * Works in all experiments done so far 179 */ 180 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 181 val & DLLRDY_MASK, 1000, 1000000); 182 if (ret) { 183 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 184 return; 185 } 186 187 sdhci_am654->dll_on = true; 188 } 189 190 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 191 { 192 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 193 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 194 unsigned char timing = host->mmc->ios.timing; 195 u32 otap_del_sel; 196 u32 otap_del_ena; 197 u32 mask, val; 198 199 if (sdhci_am654->dll_on) { 200 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 201 202 sdhci_am654->dll_on = false; 203 } 204 205 sdhci_set_clock(host, clock); 206 207 /* Setup DLL Output TAP delay */ 208 if (sdhci_am654->legacy_otapdly) 209 otap_del_sel = sdhci_am654->otap_del_sel[0]; 210 else 211 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 212 213 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 214 215 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 216 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 217 (otap_del_sel << OTAPDLYSEL_SHIFT); 218 219 /* Write to STRBSEL for HS400 speed mode */ 220 if (timing == MMC_TIMING_MMC_HS400) { 221 if (sdhci_am654->flags & STRBSEL_4_BIT) 222 mask |= STRBSEL_4BIT_MASK; 223 else 224 mask |= STRBSEL_8BIT_MASK; 225 226 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 227 } 228 229 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 230 231 if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) 232 sdhci_am654_setup_dll(host, clock); 233 } 234 235 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 236 unsigned int clock) 237 { 238 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 239 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 240 unsigned char timing = host->mmc->ios.timing; 241 u32 otap_del_sel; 242 u32 mask, val; 243 244 /* Setup DLL Output TAP delay */ 245 if (sdhci_am654->legacy_otapdly) 246 otap_del_sel = sdhci_am654->otap_del_sel[0]; 247 else 248 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 249 250 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 251 val = (0x1 << OTAPDLYENA_SHIFT) | 252 (otap_del_sel << OTAPDLYSEL_SHIFT); 253 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 254 255 sdhci_set_clock(host, clock); 256 } 257 258 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 259 { 260 unsigned char timing = host->mmc->ios.timing; 261 262 if (reg == SDHCI_HOST_CONTROL) { 263 switch (timing) { 264 /* 265 * According to the data manual, HISPD bit 266 * should not be set in these speed modes. 267 */ 268 case MMC_TIMING_SD_HS: 269 case MMC_TIMING_MMC_HS: 270 case MMC_TIMING_UHS_SDR12: 271 case MMC_TIMING_UHS_SDR25: 272 val &= ~SDHCI_CTRL_HISPD; 273 } 274 } 275 276 writeb(val, host->ioaddr + reg); 277 } 278 279 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 280 { 281 struct sdhci_host *host = mmc_priv(mmc); 282 int err = sdhci_execute_tuning(mmc, opcode); 283 284 if (err) 285 return err; 286 /* 287 * Tuning data remains in the buffer after tuning. 288 * Do a command and data reset to get rid of it 289 */ 290 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 291 292 return 0; 293 } 294 295 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 296 { 297 int cmd_error = 0; 298 int data_error = 0; 299 300 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 301 return intmask; 302 303 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 304 305 return 0; 306 } 307 308 static struct sdhci_ops sdhci_am654_ops = { 309 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 310 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 311 .set_uhs_signaling = sdhci_set_uhs_signaling, 312 .set_bus_width = sdhci_set_bus_width, 313 .set_power = sdhci_set_power_and_bus_voltage, 314 .set_clock = sdhci_am654_set_clock, 315 .write_b = sdhci_am654_write_b, 316 .irq = sdhci_am654_cqhci_irq, 317 .reset = sdhci_reset, 318 }; 319 320 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 321 .ops = &sdhci_am654_ops, 322 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 323 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 324 }; 325 326 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 327 .pdata = &sdhci_am654_pdata, 328 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 329 DLL_CALIB, 330 }; 331 332 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 333 .pdata = &sdhci_am654_pdata, 334 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 335 }; 336 337 static struct sdhci_ops sdhci_j721e_8bit_ops = { 338 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 339 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 340 .set_uhs_signaling = sdhci_set_uhs_signaling, 341 .set_bus_width = sdhci_set_bus_width, 342 .set_power = sdhci_set_power_and_bus_voltage, 343 .set_clock = sdhci_am654_set_clock, 344 .write_b = sdhci_am654_write_b, 345 .irq = sdhci_am654_cqhci_irq, 346 .reset = sdhci_reset, 347 }; 348 349 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 350 .ops = &sdhci_j721e_8bit_ops, 351 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 352 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 353 }; 354 355 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 356 .pdata = &sdhci_j721e_8bit_pdata, 357 .flags = DLL_PRESENT | DLL_CALIB, 358 }; 359 360 static struct sdhci_ops sdhci_j721e_4bit_ops = { 361 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 362 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 363 .set_uhs_signaling = sdhci_set_uhs_signaling, 364 .set_bus_width = sdhci_set_bus_width, 365 .set_power = sdhci_set_power_and_bus_voltage, 366 .set_clock = sdhci_j721e_4bit_set_clock, 367 .write_b = sdhci_am654_write_b, 368 .irq = sdhci_am654_cqhci_irq, 369 .reset = sdhci_reset, 370 }; 371 372 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 373 .ops = &sdhci_j721e_4bit_ops, 374 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 375 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 376 }; 377 378 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 379 .pdata = &sdhci_j721e_4bit_pdata, 380 .flags = IOMUX_PRESENT, 381 }; 382 383 static const struct soc_device_attribute sdhci_am654_devices[] = { 384 { .family = "AM65X", 385 .revision = "SR1.0", 386 .data = &sdhci_am654_sr1_drvdata 387 }, 388 {/* sentinel */} 389 }; 390 391 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 392 { 393 sdhci_dumpregs(mmc_priv(mmc)); 394 } 395 396 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 397 .enable = sdhci_cqe_enable, 398 .disable = sdhci_cqe_disable, 399 .dumpregs = sdhci_am654_dumpregs, 400 }; 401 402 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 403 { 404 struct cqhci_host *cq_host; 405 int ret; 406 407 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 408 GFP_KERNEL); 409 if (!cq_host) 410 return -ENOMEM; 411 412 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 413 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 414 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 415 cq_host->ops = &sdhci_am654_cqhci_ops; 416 417 host->mmc->caps2 |= MMC_CAP2_CQE; 418 419 ret = cqhci_init(cq_host, host->mmc, 1); 420 421 return ret; 422 } 423 424 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 425 struct sdhci_am654_data *sdhci_am654) 426 { 427 struct device *dev = mmc_dev(host->mmc); 428 int i; 429 int ret; 430 431 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding, 432 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 433 if (ret) { 434 /* 435 * ti,otap-del-sel-legacy is mandatory, look for old binding 436 * if not found. 437 */ 438 ret = device_property_read_u32(dev, "ti,otap-del-sel", 439 &sdhci_am654->otap_del_sel[0]); 440 if (ret) { 441 dev_err(dev, "Couldn't find otap-del-sel\n"); 442 443 return ret; 444 } 445 446 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 447 sdhci_am654->legacy_otapdly = true; 448 449 return 0; 450 } 451 452 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 453 454 ret = device_property_read_u32(dev, td[i].binding, 455 &sdhci_am654->otap_del_sel[i]); 456 if (ret) { 457 dev_dbg(dev, "Couldn't find %s\n", 458 td[i].binding); 459 /* 460 * Remove the corresponding capability 461 * if an otap-del-sel value is not found 462 */ 463 if (i <= MMC_TIMING_MMC_DDR52) 464 host->mmc->caps &= ~td[i].capability; 465 else 466 host->mmc->caps2 &= ~td[i].capability; 467 } 468 } 469 470 return 0; 471 } 472 473 static int sdhci_am654_init(struct sdhci_host *host) 474 { 475 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 476 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 477 u32 ctl_cfg_2 = 0; 478 u32 mask; 479 u32 val; 480 int ret; 481 482 /* Reset OTAP to default value */ 483 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 484 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 485 486 if (sdhci_am654->flags & DLL_CALIB) { 487 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 488 if (~val & CALDONE_MASK) { 489 /* Calibrate IO lines */ 490 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 491 PDB_MASK, PDB_MASK); 492 ret = regmap_read_poll_timeout(sdhci_am654->base, 493 PHY_STAT1, val, 494 val & CALDONE_MASK, 495 1, 20); 496 if (ret) 497 return ret; 498 } 499 } 500 501 /* Enable pins by setting IO mux to 0 */ 502 if (sdhci_am654->flags & IOMUX_PRESENT) 503 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 504 IOMUX_ENABLE_MASK, 0); 505 506 /* Set slot type based on SD or eMMC */ 507 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 508 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 509 510 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 511 ctl_cfg_2); 512 513 ret = sdhci_setup_host(host); 514 if (ret) 515 return ret; 516 517 ret = sdhci_am654_cqe_add_host(host); 518 if (ret) 519 goto err_cleanup_host; 520 521 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 522 if (ret) 523 goto err_cleanup_host; 524 525 ret = __sdhci_add_host(host); 526 if (ret) 527 goto err_cleanup_host; 528 529 return 0; 530 531 err_cleanup_host: 532 sdhci_cleanup_host(host); 533 return ret; 534 } 535 536 static int sdhci_am654_get_of_property(struct platform_device *pdev, 537 struct sdhci_am654_data *sdhci_am654) 538 { 539 struct device *dev = &pdev->dev; 540 int drv_strength; 541 int ret; 542 543 if (sdhci_am654->flags & DLL_PRESENT) { 544 ret = device_property_read_u32(dev, "ti,trm-icp", 545 &sdhci_am654->trm_icp); 546 if (ret) 547 return ret; 548 549 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 550 &drv_strength); 551 if (ret) 552 return ret; 553 554 switch (drv_strength) { 555 case 50: 556 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 557 break; 558 case 33: 559 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 560 break; 561 case 66: 562 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 563 break; 564 case 100: 565 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 566 break; 567 case 40: 568 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 569 break; 570 default: 571 dev_err(dev, "Invalid driver strength\n"); 572 return -EINVAL; 573 } 574 } 575 576 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 577 578 sdhci_get_of_property(pdev); 579 580 return 0; 581 } 582 583 static const struct of_device_id sdhci_am654_of_match[] = { 584 { 585 .compatible = "ti,am654-sdhci-5.1", 586 .data = &sdhci_am654_drvdata, 587 }, 588 { 589 .compatible = "ti,j721e-sdhci-8bit", 590 .data = &sdhci_j721e_8bit_drvdata, 591 }, 592 { 593 .compatible = "ti,j721e-sdhci-4bit", 594 .data = &sdhci_j721e_4bit_drvdata, 595 }, 596 { /* sentinel */ } 597 }; 598 599 static int sdhci_am654_probe(struct platform_device *pdev) 600 { 601 const struct sdhci_am654_driver_data *drvdata; 602 const struct soc_device_attribute *soc; 603 struct sdhci_pltfm_host *pltfm_host; 604 struct sdhci_am654_data *sdhci_am654; 605 const struct of_device_id *match; 606 struct sdhci_host *host; 607 struct clk *clk_xin; 608 struct device *dev = &pdev->dev; 609 void __iomem *base; 610 int ret; 611 612 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 613 drvdata = match->data; 614 615 /* Update drvdata based on SoC revision */ 616 soc = soc_device_match(sdhci_am654_devices); 617 if (soc && soc->data) 618 drvdata = soc->data; 619 620 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 621 if (IS_ERR(host)) 622 return PTR_ERR(host); 623 624 pltfm_host = sdhci_priv(host); 625 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 626 sdhci_am654->flags = drvdata->flags; 627 628 clk_xin = devm_clk_get(dev, "clk_xin"); 629 if (IS_ERR(clk_xin)) { 630 dev_err(dev, "clk_xin clock not found.\n"); 631 ret = PTR_ERR(clk_xin); 632 goto err_pltfm_free; 633 } 634 635 pltfm_host->clk = clk_xin; 636 637 /* Clocks are enabled using pm_runtime */ 638 pm_runtime_enable(dev); 639 ret = pm_runtime_get_sync(dev); 640 if (ret < 0) { 641 pm_runtime_put_noidle(dev); 642 goto pm_runtime_disable; 643 } 644 645 base = devm_platform_ioremap_resource(pdev, 1); 646 if (IS_ERR(base)) { 647 ret = PTR_ERR(base); 648 goto pm_runtime_put; 649 } 650 651 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 652 &sdhci_am654_regmap_config); 653 if (IS_ERR(sdhci_am654->base)) { 654 dev_err(dev, "Failed to initialize regmap\n"); 655 ret = PTR_ERR(sdhci_am654->base); 656 goto pm_runtime_put; 657 } 658 659 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 660 if (ret) 661 goto pm_runtime_put; 662 663 ret = mmc_of_parse(host->mmc); 664 if (ret) { 665 dev_err(dev, "parsing dt failed (%d)\n", ret); 666 goto pm_runtime_put; 667 } 668 669 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 670 671 ret = sdhci_am654_init(host); 672 if (ret) 673 goto pm_runtime_put; 674 675 return 0; 676 677 pm_runtime_put: 678 pm_runtime_put_sync(dev); 679 pm_runtime_disable: 680 pm_runtime_disable(dev); 681 err_pltfm_free: 682 sdhci_pltfm_free(pdev); 683 return ret; 684 } 685 686 static int sdhci_am654_remove(struct platform_device *pdev) 687 { 688 struct sdhci_host *host = platform_get_drvdata(pdev); 689 int ret; 690 691 sdhci_remove_host(host, true); 692 ret = pm_runtime_put_sync(&pdev->dev); 693 if (ret < 0) 694 return ret; 695 696 pm_runtime_disable(&pdev->dev); 697 sdhci_pltfm_free(pdev); 698 699 return 0; 700 } 701 702 static struct platform_driver sdhci_am654_driver = { 703 .driver = { 704 .name = "sdhci-am654", 705 .of_match_table = sdhci_am654_of_match, 706 }, 707 .probe = sdhci_am654_probe, 708 .remove = sdhci_am654_remove, 709 }; 710 711 module_platform_driver(sdhci_am654_driver); 712 713 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 714 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 715 MODULE_LICENSE("GPL"); 716