1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 20 21 /* CTL_CFG Registers */ 22 #define CTL_CFG_2 0x14 23 #define CTL_CFG_3 0x18 24 25 #define SLOTTYPE_MASK GENMASK(31, 30) 26 #define SLOTTYPE_EMBEDDED BIT(30) 27 #define TUNINGFORSDR50_MASK BIT(13) 28 29 /* PHY Registers */ 30 #define PHY_CTRL1 0x100 31 #define PHY_CTRL2 0x104 32 #define PHY_CTRL3 0x108 33 #define PHY_CTRL4 0x10C 34 #define PHY_CTRL5 0x110 35 #define PHY_CTRL6 0x114 36 #define PHY_STAT1 0x130 37 #define PHY_STAT2 0x134 38 39 #define IOMUX_ENABLE_SHIFT 31 40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 41 #define OTAPDLYENA_SHIFT 20 42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 43 #define OTAPDLYSEL_SHIFT 12 44 #define OTAPDLYSEL_MASK GENMASK(15, 12) 45 #define STRBSEL_SHIFT 24 46 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 47 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 48 #define SEL50_SHIFT 8 49 #define SEL50_MASK BIT(SEL50_SHIFT) 50 #define SEL100_SHIFT 9 51 #define SEL100_MASK BIT(SEL100_SHIFT) 52 #define FREQSEL_SHIFT 8 53 #define FREQSEL_MASK GENMASK(10, 8) 54 #define CLKBUFSEL_SHIFT 0 55 #define CLKBUFSEL_MASK GENMASK(2, 0) 56 #define DLL_TRIM_ICP_SHIFT 4 57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 58 #define DR_TY_SHIFT 20 59 #define DR_TY_MASK GENMASK(22, 20) 60 #define ENDLL_SHIFT 1 61 #define ENDLL_MASK BIT(ENDLL_SHIFT) 62 #define DLLRDY_SHIFT 0 63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 64 #define PDB_SHIFT 0 65 #define PDB_MASK BIT(PDB_SHIFT) 66 #define CALDONE_SHIFT 1 67 #define CALDONE_MASK BIT(CALDONE_SHIFT) 68 #define RETRIM_SHIFT 17 69 #define RETRIM_MASK BIT(RETRIM_SHIFT) 70 #define SELDLYTXCLK_SHIFT 17 71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72 #define SELDLYRXCLK_SHIFT 16 73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74 #define ITAPDLYSEL_SHIFT 0 75 #define ITAPDLYSEL_MASK GENMASK(4, 0) 76 #define ITAPDLYENA_SHIFT 8 77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78 #define ITAPCHGWIN_SHIFT 9 79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 80 81 #define DRIVER_STRENGTH_50_OHM 0x0 82 #define DRIVER_STRENGTH_33_OHM 0x1 83 #define DRIVER_STRENGTH_66_OHM 0x2 84 #define DRIVER_STRENGTH_100_OHM 0x3 85 #define DRIVER_STRENGTH_40_OHM 0x4 86 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 89 90 /* Command Queue Host Controller Interface Base address */ 91 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92 93 static struct regmap_config sdhci_am654_regmap_config = { 94 .reg_bits = 32, 95 .val_bits = 32, 96 .reg_stride = 4, 97 .fast_io = true, 98 }; 99 100 struct timing_data { 101 const char *otap_binding; 102 const char *itap_binding; 103 u32 capability; 104 }; 105 106 static const struct timing_data td[] = { 107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108 "ti,itap-del-sel-legacy", 109 0}, 110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111 "ti,itap-del-sel-mmc-hs", 112 MMC_CAP_MMC_HIGHSPEED}, 113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114 "ti,itap-del-sel-sd-hs", 115 MMC_CAP_SD_HIGHSPEED}, 116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117 "ti,itap-del-sel-sdr12", 118 MMC_CAP_UHS_SDR12}, 119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120 "ti,itap-del-sel-sdr25", 121 MMC_CAP_UHS_SDR25}, 122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123 NULL, 124 MMC_CAP_UHS_SDR50}, 125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126 NULL, 127 MMC_CAP_UHS_SDR104}, 128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129 NULL, 130 MMC_CAP_UHS_DDR50}, 131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132 "ti,itap-del-sel-ddr52", 133 MMC_CAP_DDR}, 134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135 NULL, 136 MMC_CAP2_HS200}, 137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138 NULL, 139 MMC_CAP2_HS400}, 140 }; 141 142 struct sdhci_am654_data { 143 struct regmap *base; 144 bool legacy_otapdly; 145 int otap_del_sel[ARRAY_SIZE(td)]; 146 int itap_del_sel[ARRAY_SIZE(td)]; 147 int clkbuf_sel; 148 int trm_icp; 149 int drv_strength; 150 int strb_sel; 151 u32 flags; 152 u32 quirks; 153 bool dll_enable; 154 155 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 156 }; 157 158 struct window { 159 u8 start; 160 u8 end; 161 u8 length; 162 }; 163 164 struct sdhci_am654_driver_data { 165 const struct sdhci_pltfm_data *pdata; 166 u32 flags; 167 #define IOMUX_PRESENT (1 << 0) 168 #define FREQSEL_2_BIT (1 << 1) 169 #define STRBSEL_4_BIT (1 << 2) 170 #define DLL_PRESENT (1 << 3) 171 #define DLL_CALIB (1 << 4) 172 }; 173 174 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 175 { 176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 178 int sel50, sel100, freqsel; 179 u32 mask, val; 180 int ret; 181 182 /* Disable delay chain mode */ 183 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 184 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 185 186 if (sdhci_am654->flags & FREQSEL_2_BIT) { 187 switch (clock) { 188 case 200000000: 189 sel50 = 0; 190 sel100 = 0; 191 break; 192 case 100000000: 193 sel50 = 0; 194 sel100 = 1; 195 break; 196 default: 197 sel50 = 1; 198 sel100 = 0; 199 } 200 201 /* Configure PHY DLL frequency */ 202 mask = SEL50_MASK | SEL100_MASK; 203 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 204 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 205 206 } else { 207 switch (clock) { 208 case 200000000: 209 freqsel = 0x0; 210 break; 211 default: 212 freqsel = 0x4; 213 } 214 215 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 216 freqsel << FREQSEL_SHIFT); 217 } 218 /* Configure DLL TRIM */ 219 mask = DLL_TRIM_ICP_MASK; 220 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 221 222 /* Configure DLL driver strength */ 223 mask |= DR_TY_MASK; 224 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 225 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 226 227 /* Enable DLL */ 228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 229 0x1 << ENDLL_SHIFT); 230 /* 231 * Poll for DLL ready. Use a one second timeout. 232 * Works in all experiments done so far 233 */ 234 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 235 val & DLLRDY_MASK, 1000, 1000000); 236 if (ret) { 237 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 238 return; 239 } 240 } 241 242 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 243 u32 itapdly) 244 { 245 /* Set ITAPCHGWIN before writing to ITAPDLY */ 246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 247 1 << ITAPCHGWIN_SHIFT); 248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 249 itapdly << ITAPDLYSEL_SHIFT); 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 251 } 252 253 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 254 unsigned char timing) 255 { 256 u32 mask, val; 257 258 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 259 260 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 261 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 262 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 263 264 sdhci_am654_write_itapdly(sdhci_am654, 265 sdhci_am654->itap_del_sel[timing]); 266 } 267 268 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 269 { 270 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 271 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 272 unsigned char timing = host->mmc->ios.timing; 273 u32 otap_del_sel; 274 u32 otap_del_ena; 275 u32 mask, val; 276 277 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 278 279 sdhci_set_clock(host, clock); 280 281 /* Setup DLL Output TAP delay */ 282 if (sdhci_am654->legacy_otapdly) 283 otap_del_sel = sdhci_am654->otap_del_sel[0]; 284 else 285 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 286 287 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 288 289 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 290 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 291 (otap_del_sel << OTAPDLYSEL_SHIFT); 292 293 /* Write to STRBSEL for HS400 speed mode */ 294 if (timing == MMC_TIMING_MMC_HS400) { 295 if (sdhci_am654->flags & STRBSEL_4_BIT) 296 mask |= STRBSEL_4BIT_MASK; 297 else 298 mask |= STRBSEL_8BIT_MASK; 299 300 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 301 } 302 303 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 304 305 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 306 sdhci_am654_setup_dll(host, clock); 307 sdhci_am654->dll_enable = true; 308 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); 309 } else { 310 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 311 sdhci_am654->dll_enable = false; 312 } 313 314 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 315 sdhci_am654->clkbuf_sel); 316 } 317 318 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 319 unsigned int clock) 320 { 321 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 322 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 323 unsigned char timing = host->mmc->ios.timing; 324 u32 otap_del_sel; 325 u32 mask, val; 326 327 /* Setup DLL Output TAP delay */ 328 if (sdhci_am654->legacy_otapdly) 329 otap_del_sel = sdhci_am654->otap_del_sel[0]; 330 else 331 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 332 333 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 334 val = (0x1 << OTAPDLYENA_SHIFT) | 335 (otap_del_sel << OTAPDLYSEL_SHIFT); 336 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 337 338 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 339 sdhci_am654->clkbuf_sel); 340 341 sdhci_set_clock(host, clock); 342 } 343 344 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 345 { 346 writeb(val, host->ioaddr + reg); 347 usleep_range(1000, 10000); 348 return readb(host->ioaddr + reg); 349 } 350 351 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 352 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 353 { 354 unsigned char timing = host->mmc->ios.timing; 355 u8 pwr; 356 int ret; 357 358 if (reg == SDHCI_HOST_CONTROL) { 359 switch (timing) { 360 /* 361 * According to the data manual, HISPD bit 362 * should not be set in these speed modes. 363 */ 364 case MMC_TIMING_SD_HS: 365 case MMC_TIMING_MMC_HS: 366 val &= ~SDHCI_CTRL_HISPD; 367 } 368 } 369 370 writeb(val, host->ioaddr + reg); 371 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 372 /* 373 * Power on will not happen until the card detect debounce 374 * timer expires. Wait at least 1.5 seconds for the power on 375 * bit to be set 376 */ 377 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 378 pwr & SDHCI_POWER_ON, 0, 379 MAX_POWER_ON_TIMEOUT, false, host, val, 380 reg); 381 if (ret) 382 dev_info(mmc_dev(host->mmc), "Power on failed\n"); 383 } 384 } 385 386 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 387 { 388 u8 ctrl; 389 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 390 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 391 392 sdhci_and_cqhci_reset(host, mask); 393 394 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 395 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 396 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 397 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 398 } 399 } 400 401 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 402 { 403 struct sdhci_host *host = mmc_priv(mmc); 404 int err = sdhci_execute_tuning(mmc, opcode); 405 406 if (err) 407 return err; 408 /* 409 * Tuning data remains in the buffer after tuning. 410 * Do a command and data reset to get rid of it 411 */ 412 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 413 414 return 0; 415 } 416 417 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 418 { 419 int cmd_error = 0; 420 int data_error = 0; 421 422 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 423 return intmask; 424 425 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 426 427 return 0; 428 } 429 430 #define ITAPDLY_LENGTH 32 431 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 432 433 static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 434 *fail_window, u8 num_fails, bool circular_buffer) 435 { 436 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 437 u8 first_fail_start = 0, last_fail_end = 0; 438 struct device *dev = mmc_dev(host->mmc); 439 struct window pass_window = {0, 0, 0}; 440 int prev_fail_end = -1; 441 u8 i; 442 443 if (!num_fails) 444 return ITAPDLY_LAST_INDEX >> 1; 445 446 if (fail_window->length == ITAPDLY_LENGTH) { 447 dev_err(dev, "No passing ITAPDLY, return 0\n"); 448 return 0; 449 } 450 451 first_fail_start = fail_window->start; 452 last_fail_end = fail_window[num_fails - 1].end; 453 454 for (i = 0; i < num_fails; i++) { 455 start_fail = fail_window[i].start; 456 end_fail = fail_window[i].end; 457 pass_length = start_fail - (prev_fail_end + 1); 458 459 if (pass_length > pass_window.length) { 460 pass_window.start = prev_fail_end + 1; 461 pass_window.length = pass_length; 462 } 463 prev_fail_end = end_fail; 464 } 465 466 if (!circular_buffer) 467 pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 468 else 469 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 470 471 if (pass_length > pass_window.length) { 472 pass_window.start = last_fail_end + 1; 473 pass_window.length = pass_length; 474 } 475 476 if (!circular_buffer) 477 itap = pass_window.start + (pass_window.length >> 1); 478 else 479 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 480 481 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 482 } 483 484 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 485 u32 opcode) 486 { 487 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 488 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 489 struct window fail_window[ITAPDLY_LENGTH]; 490 u8 curr_pass, itap; 491 u8 fail_index = 0; 492 u8 prev_pass = 1; 493 494 memset(fail_window, 0, sizeof(fail_window)); 495 496 /* Enable ITAPDLY */ 497 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 498 1 << ITAPDLYENA_SHIFT); 499 500 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 501 sdhci_am654_write_itapdly(sdhci_am654, itap); 502 503 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 504 505 if (!curr_pass && prev_pass) 506 fail_window[fail_index].start = itap; 507 508 if (!curr_pass) { 509 fail_window[fail_index].end = itap; 510 fail_window[fail_index].length++; 511 } 512 513 if (curr_pass && !prev_pass) 514 fail_index++; 515 516 prev_pass = curr_pass; 517 } 518 519 if (fail_window[fail_index].length != 0) 520 fail_index++; 521 522 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 523 sdhci_am654->dll_enable); 524 525 sdhci_am654_write_itapdly(sdhci_am654, itap); 526 527 return 0; 528 } 529 530 static struct sdhci_ops sdhci_am654_ops = { 531 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 532 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 533 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 534 .set_uhs_signaling = sdhci_set_uhs_signaling, 535 .set_bus_width = sdhci_set_bus_width, 536 .set_power = sdhci_set_power_and_bus_voltage, 537 .set_clock = sdhci_am654_set_clock, 538 .write_b = sdhci_am654_write_b, 539 .irq = sdhci_am654_cqhci_irq, 540 .reset = sdhci_and_cqhci_reset, 541 }; 542 543 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 544 .ops = &sdhci_am654_ops, 545 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 546 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 547 }; 548 549 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 550 .pdata = &sdhci_am654_pdata, 551 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 552 DLL_CALIB, 553 }; 554 555 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 556 .pdata = &sdhci_am654_pdata, 557 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 558 }; 559 560 static struct sdhci_ops sdhci_j721e_8bit_ops = { 561 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 562 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 563 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 564 .set_uhs_signaling = sdhci_set_uhs_signaling, 565 .set_bus_width = sdhci_set_bus_width, 566 .set_power = sdhci_set_power_and_bus_voltage, 567 .set_clock = sdhci_am654_set_clock, 568 .write_b = sdhci_am654_write_b, 569 .irq = sdhci_am654_cqhci_irq, 570 .reset = sdhci_and_cqhci_reset, 571 }; 572 573 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 574 .ops = &sdhci_j721e_8bit_ops, 575 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 576 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 577 }; 578 579 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 580 .pdata = &sdhci_j721e_8bit_pdata, 581 .flags = DLL_PRESENT | DLL_CALIB, 582 }; 583 584 static struct sdhci_ops sdhci_j721e_4bit_ops = { 585 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 586 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 587 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 588 .set_uhs_signaling = sdhci_set_uhs_signaling, 589 .set_bus_width = sdhci_set_bus_width, 590 .set_power = sdhci_set_power_and_bus_voltage, 591 .set_clock = sdhci_j721e_4bit_set_clock, 592 .write_b = sdhci_am654_write_b, 593 .irq = sdhci_am654_cqhci_irq, 594 .reset = sdhci_am654_reset, 595 }; 596 597 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 598 .ops = &sdhci_j721e_4bit_ops, 599 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 600 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 601 }; 602 603 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 604 .pdata = &sdhci_j721e_4bit_pdata, 605 .flags = IOMUX_PRESENT, 606 }; 607 608 static const struct soc_device_attribute sdhci_am654_devices[] = { 609 { .family = "AM65X", 610 .revision = "SR1.0", 611 .data = &sdhci_am654_sr1_drvdata 612 }, 613 {/* sentinel */} 614 }; 615 616 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 617 { 618 sdhci_dumpregs(mmc_priv(mmc)); 619 } 620 621 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 622 .enable = sdhci_cqe_enable, 623 .disable = sdhci_cqe_disable, 624 .dumpregs = sdhci_am654_dumpregs, 625 }; 626 627 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 628 { 629 struct cqhci_host *cq_host; 630 631 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 632 GFP_KERNEL); 633 if (!cq_host) 634 return -ENOMEM; 635 636 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 637 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 638 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 639 cq_host->ops = &sdhci_am654_cqhci_ops; 640 641 host->mmc->caps2 |= MMC_CAP2_CQE; 642 643 return cqhci_init(cq_host, host->mmc, 1); 644 } 645 646 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 647 struct sdhci_am654_data *sdhci_am654) 648 { 649 struct device *dev = mmc_dev(host->mmc); 650 int i; 651 int ret; 652 653 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 654 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 655 if (ret) { 656 /* 657 * ti,otap-del-sel-legacy is mandatory, look for old binding 658 * if not found. 659 */ 660 ret = device_property_read_u32(dev, "ti,otap-del-sel", 661 &sdhci_am654->otap_del_sel[0]); 662 if (ret) { 663 dev_err(dev, "Couldn't find otap-del-sel\n"); 664 665 return ret; 666 } 667 668 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 669 sdhci_am654->legacy_otapdly = true; 670 671 return 0; 672 } 673 674 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) { 675 676 ret = device_property_read_u32(dev, td[i].otap_binding, 677 &sdhci_am654->otap_del_sel[i]); 678 if (ret) { 679 dev_dbg(dev, "Couldn't find %s\n", 680 td[i].otap_binding); 681 /* 682 * Remove the corresponding capability 683 * if an otap-del-sel value is not found 684 */ 685 if (i <= MMC_TIMING_MMC_DDR52) 686 host->mmc->caps &= ~td[i].capability; 687 else 688 host->mmc->caps2 &= ~td[i].capability; 689 } 690 691 if (td[i].itap_binding) 692 device_property_read_u32(dev, td[i].itap_binding, 693 &sdhci_am654->itap_del_sel[i]); 694 } 695 696 return 0; 697 } 698 699 static int sdhci_am654_init(struct sdhci_host *host) 700 { 701 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 702 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 703 u32 ctl_cfg_2 = 0; 704 u32 mask; 705 u32 val; 706 int ret; 707 708 /* Reset OTAP to default value */ 709 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 710 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 711 712 if (sdhci_am654->flags & DLL_CALIB) { 713 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 714 if (~val & CALDONE_MASK) { 715 /* Calibrate IO lines */ 716 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 717 PDB_MASK, PDB_MASK); 718 ret = regmap_read_poll_timeout(sdhci_am654->base, 719 PHY_STAT1, val, 720 val & CALDONE_MASK, 721 1, 20); 722 if (ret) 723 return ret; 724 } 725 } 726 727 /* Enable pins by setting IO mux to 0 */ 728 if (sdhci_am654->flags & IOMUX_PRESENT) 729 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 730 IOMUX_ENABLE_MASK, 0); 731 732 /* Set slot type based on SD or eMMC */ 733 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 734 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 735 736 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 737 ctl_cfg_2); 738 739 /* Enable tuning for SDR50 */ 740 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 741 TUNINGFORSDR50_MASK); 742 743 ret = sdhci_setup_host(host); 744 if (ret) 745 return ret; 746 747 ret = sdhci_am654_cqe_add_host(host); 748 if (ret) 749 goto err_cleanup_host; 750 751 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 752 if (ret) 753 goto err_cleanup_host; 754 755 ret = __sdhci_add_host(host); 756 if (ret) 757 goto err_cleanup_host; 758 759 return 0; 760 761 err_cleanup_host: 762 sdhci_cleanup_host(host); 763 return ret; 764 } 765 766 static int sdhci_am654_get_of_property(struct platform_device *pdev, 767 struct sdhci_am654_data *sdhci_am654) 768 { 769 struct device *dev = &pdev->dev; 770 int drv_strength; 771 int ret; 772 773 if (sdhci_am654->flags & DLL_PRESENT) { 774 ret = device_property_read_u32(dev, "ti,trm-icp", 775 &sdhci_am654->trm_icp); 776 if (ret) 777 return ret; 778 779 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 780 &drv_strength); 781 if (ret) 782 return ret; 783 784 switch (drv_strength) { 785 case 50: 786 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 787 break; 788 case 33: 789 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 790 break; 791 case 66: 792 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 793 break; 794 case 100: 795 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 796 break; 797 case 40: 798 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 799 break; 800 default: 801 dev_err(dev, "Invalid driver strength\n"); 802 return -EINVAL; 803 } 804 } 805 806 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 807 device_property_read_u32(dev, "ti,clkbuf-sel", 808 &sdhci_am654->clkbuf_sel); 809 810 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 811 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 812 813 sdhci_get_of_property(pdev); 814 815 return 0; 816 } 817 818 static const struct of_device_id sdhci_am654_of_match[] = { 819 { 820 .compatible = "ti,am654-sdhci-5.1", 821 .data = &sdhci_am654_drvdata, 822 }, 823 { 824 .compatible = "ti,j721e-sdhci-8bit", 825 .data = &sdhci_j721e_8bit_drvdata, 826 }, 827 { 828 .compatible = "ti,j721e-sdhci-4bit", 829 .data = &sdhci_j721e_4bit_drvdata, 830 }, 831 { 832 .compatible = "ti,am64-sdhci-8bit", 833 .data = &sdhci_j721e_8bit_drvdata, 834 }, 835 { 836 .compatible = "ti,am64-sdhci-4bit", 837 .data = &sdhci_j721e_4bit_drvdata, 838 }, 839 { 840 .compatible = "ti,am62-sdhci", 841 .data = &sdhci_j721e_4bit_drvdata, 842 }, 843 { /* sentinel */ } 844 }; 845 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 846 847 static int sdhci_am654_probe(struct platform_device *pdev) 848 { 849 const struct sdhci_am654_driver_data *drvdata; 850 const struct soc_device_attribute *soc; 851 struct sdhci_pltfm_host *pltfm_host; 852 struct sdhci_am654_data *sdhci_am654; 853 const struct of_device_id *match; 854 struct sdhci_host *host; 855 struct clk *clk_xin; 856 struct device *dev = &pdev->dev; 857 void __iomem *base; 858 int ret; 859 860 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 861 drvdata = match->data; 862 863 /* Update drvdata based on SoC revision */ 864 soc = soc_device_match(sdhci_am654_devices); 865 if (soc && soc->data) 866 drvdata = soc->data; 867 868 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 869 if (IS_ERR(host)) 870 return PTR_ERR(host); 871 872 pltfm_host = sdhci_priv(host); 873 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 874 sdhci_am654->flags = drvdata->flags; 875 876 clk_xin = devm_clk_get(dev, "clk_xin"); 877 if (IS_ERR(clk_xin)) { 878 dev_err(dev, "clk_xin clock not found.\n"); 879 ret = PTR_ERR(clk_xin); 880 goto err_pltfm_free; 881 } 882 883 pltfm_host->clk = clk_xin; 884 885 base = devm_platform_ioremap_resource(pdev, 1); 886 if (IS_ERR(base)) { 887 ret = PTR_ERR(base); 888 goto err_pltfm_free; 889 } 890 891 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 892 &sdhci_am654_regmap_config); 893 if (IS_ERR(sdhci_am654->base)) { 894 dev_err(dev, "Failed to initialize regmap\n"); 895 ret = PTR_ERR(sdhci_am654->base); 896 goto err_pltfm_free; 897 } 898 899 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 900 if (ret) 901 goto err_pltfm_free; 902 903 ret = mmc_of_parse(host->mmc); 904 if (ret) { 905 dev_err_probe(dev, ret, "parsing dt failed\n"); 906 goto err_pltfm_free; 907 } 908 909 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 910 911 pm_runtime_get_noresume(dev); 912 ret = pm_runtime_set_active(dev); 913 if (ret) 914 goto pm_put; 915 pm_runtime_enable(dev); 916 ret = clk_prepare_enable(pltfm_host->clk); 917 if (ret) 918 goto pm_disable; 919 920 ret = sdhci_am654_init(host); 921 if (ret) 922 goto clk_disable; 923 924 /* Setting up autosuspend */ 925 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 926 pm_runtime_use_autosuspend(dev); 927 pm_runtime_mark_last_busy(dev); 928 pm_runtime_put_autosuspend(dev); 929 return 0; 930 931 clk_disable: 932 clk_disable_unprepare(pltfm_host->clk); 933 pm_disable: 934 pm_runtime_disable(dev); 935 pm_put: 936 pm_runtime_put_noidle(dev); 937 err_pltfm_free: 938 sdhci_pltfm_free(pdev); 939 return ret; 940 } 941 942 static void sdhci_am654_remove(struct platform_device *pdev) 943 { 944 struct sdhci_host *host = platform_get_drvdata(pdev); 945 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 946 struct device *dev = &pdev->dev; 947 int ret; 948 949 ret = pm_runtime_get_sync(dev); 950 if (ret < 0) 951 dev_err(dev, "pm_runtime_get_sync() Failed\n"); 952 953 sdhci_remove_host(host, true); 954 clk_disable_unprepare(pltfm_host->clk); 955 pm_runtime_disable(dev); 956 pm_runtime_put_noidle(dev); 957 sdhci_pltfm_free(pdev); 958 } 959 960 #ifdef CONFIG_PM 961 static int sdhci_am654_restore(struct sdhci_host *host) 962 { 963 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 964 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 965 u32 ctl_cfg_2 = 0; 966 u32 val; 967 int ret; 968 969 if (sdhci_am654->flags & DLL_CALIB) { 970 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 971 if (~val & CALDONE_MASK) { 972 /* Calibrate IO lines */ 973 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 974 PDB_MASK, PDB_MASK); 975 ret = regmap_read_poll_timeout(sdhci_am654->base, 976 PHY_STAT1, val, 977 val & CALDONE_MASK, 978 1, 20); 979 if (ret) 980 return ret; 981 } 982 } 983 984 /* Enable pins by setting IO mux to 0 */ 985 if (sdhci_am654->flags & IOMUX_PRESENT) 986 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 987 IOMUX_ENABLE_MASK, 0); 988 989 /* Set slot type based on SD or eMMC */ 990 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 991 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 992 993 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 994 ctl_cfg_2); 995 996 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 997 if (~val & TUNINGFORSDR50_MASK) 998 /* Enable tuning for SDR50 */ 999 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 1000 TUNINGFORSDR50_MASK); 1001 1002 return 0; 1003 } 1004 1005 static int sdhci_am654_runtime_suspend(struct device *dev) 1006 { 1007 struct sdhci_host *host = dev_get_drvdata(dev); 1008 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1009 int ret; 1010 1011 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1012 mmc_retune_needed(host->mmc); 1013 1014 ret = cqhci_suspend(host->mmc); 1015 if (ret) 1016 return ret; 1017 1018 ret = sdhci_runtime_suspend_host(host); 1019 if (ret) 1020 return ret; 1021 1022 /* disable the clock */ 1023 clk_disable_unprepare(pltfm_host->clk); 1024 return 0; 1025 } 1026 1027 static int sdhci_am654_runtime_resume(struct device *dev) 1028 { 1029 struct sdhci_host *host = dev_get_drvdata(dev); 1030 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1031 int ret; 1032 1033 /* Enable the clock */ 1034 ret = clk_prepare_enable(pltfm_host->clk); 1035 if (ret) 1036 return ret; 1037 1038 ret = sdhci_am654_restore(host); 1039 if (ret) 1040 return ret; 1041 1042 ret = sdhci_runtime_resume_host(host, 0); 1043 if (ret) 1044 return ret; 1045 1046 ret = cqhci_resume(host->mmc); 1047 if (ret) 1048 return ret; 1049 1050 return 0; 1051 } 1052 #endif 1053 1054 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 1055 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 1056 sdhci_am654_runtime_resume, NULL) 1057 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1058 pm_runtime_force_resume) 1059 }; 1060 1061 static struct platform_driver sdhci_am654_driver = { 1062 .driver = { 1063 .name = "sdhci-am654", 1064 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1065 .pm = &sdhci_am654_dev_pm_ops, 1066 .of_match_table = sdhci_am654_of_match, 1067 }, 1068 .probe = sdhci_am654_probe, 1069 .remove_new = sdhci_am654_remove, 1070 }; 1071 1072 module_platform_driver(sdhci_am654_driver); 1073 1074 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 1075 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 1076 MODULE_LICENSE("GPL"); 1077