1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/of.h> 10 #include <linux/module.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/property.h> 13 #include <linux/regmap.h> 14 15 #include "cqhci.h" 16 #include "sdhci-pltfm.h" 17 18 /* CTL_CFG Registers */ 19 #define CTL_CFG_2 0x14 20 21 #define SLOTTYPE_MASK GENMASK(31, 30) 22 #define SLOTTYPE_EMBEDDED BIT(30) 23 24 /* PHY Registers */ 25 #define PHY_CTRL1 0x100 26 #define PHY_CTRL2 0x104 27 #define PHY_CTRL3 0x108 28 #define PHY_CTRL4 0x10C 29 #define PHY_CTRL5 0x110 30 #define PHY_CTRL6 0x114 31 #define PHY_STAT1 0x130 32 #define PHY_STAT2 0x134 33 34 #define IOMUX_ENABLE_SHIFT 31 35 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 36 #define OTAPDLYENA_SHIFT 20 37 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 38 #define OTAPDLYSEL_SHIFT 12 39 #define OTAPDLYSEL_MASK GENMASK(15, 12) 40 #define STRBSEL_SHIFT 24 41 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 42 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 43 #define SEL50_SHIFT 8 44 #define SEL50_MASK BIT(SEL50_SHIFT) 45 #define SEL100_SHIFT 9 46 #define SEL100_MASK BIT(SEL100_SHIFT) 47 #define FREQSEL_SHIFT 8 48 #define FREQSEL_MASK GENMASK(10, 8) 49 #define DLL_TRIM_ICP_SHIFT 4 50 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 51 #define DR_TY_SHIFT 20 52 #define DR_TY_MASK GENMASK(22, 20) 53 #define ENDLL_SHIFT 1 54 #define ENDLL_MASK BIT(ENDLL_SHIFT) 55 #define DLLRDY_SHIFT 0 56 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 57 #define PDB_SHIFT 0 58 #define PDB_MASK BIT(PDB_SHIFT) 59 #define CALDONE_SHIFT 1 60 #define CALDONE_MASK BIT(CALDONE_SHIFT) 61 #define RETRIM_SHIFT 17 62 #define RETRIM_MASK BIT(RETRIM_SHIFT) 63 64 #define DRIVER_STRENGTH_50_OHM 0x0 65 #define DRIVER_STRENGTH_33_OHM 0x1 66 #define DRIVER_STRENGTH_66_OHM 0x2 67 #define DRIVER_STRENGTH_100_OHM 0x3 68 #define DRIVER_STRENGTH_40_OHM 0x4 69 70 #define CLOCK_TOO_SLOW_HZ 400000 71 72 /* Command Queue Host Controller Interface Base address */ 73 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 74 75 static struct regmap_config sdhci_am654_regmap_config = { 76 .reg_bits = 32, 77 .val_bits = 32, 78 .reg_stride = 4, 79 .fast_io = true, 80 }; 81 82 struct sdhci_am654_data { 83 struct regmap *base; 84 int otap_del_sel; 85 int trm_icp; 86 int drv_strength; 87 bool dll_on; 88 int strb_sel; 89 u32 flags; 90 }; 91 92 struct sdhci_am654_driver_data { 93 const struct sdhci_pltfm_data *pdata; 94 u32 flags; 95 #define IOMUX_PRESENT (1 << 0) 96 #define FREQSEL_2_BIT (1 << 1) 97 #define STRBSEL_4_BIT (1 << 2) 98 #define DLL_PRESENT (1 << 3) 99 }; 100 101 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 102 { 103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 104 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 105 int sel50, sel100, freqsel; 106 u32 mask, val; 107 int ret; 108 109 if (sdhci_am654->dll_on) { 110 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 111 112 sdhci_am654->dll_on = false; 113 } 114 115 sdhci_set_clock(host, clock); 116 117 if (clock > CLOCK_TOO_SLOW_HZ) { 118 /* Setup DLL Output TAP delay */ 119 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 120 val = (1 << OTAPDLYENA_SHIFT) | 121 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 122 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 123 /* Write to STRBSEL for HS400 speed mode */ 124 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 125 if (sdhci_am654->flags & STRBSEL_4_BIT) 126 mask = STRBSEL_4BIT_MASK; 127 else 128 mask = STRBSEL_8BIT_MASK; 129 130 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 131 sdhci_am654->strb_sel << 132 STRBSEL_SHIFT); 133 } 134 135 if (sdhci_am654->flags & FREQSEL_2_BIT) { 136 switch (clock) { 137 case 200000000: 138 sel50 = 0; 139 sel100 = 0; 140 break; 141 case 100000000: 142 sel50 = 0; 143 sel100 = 1; 144 break; 145 default: 146 sel50 = 1; 147 sel100 = 0; 148 } 149 150 /* Configure PHY DLL frequency */ 151 mask = SEL50_MASK | SEL100_MASK; 152 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 153 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, 154 val); 155 } else { 156 switch (clock) { 157 case 200000000: 158 freqsel = 0x0; 159 break; 160 default: 161 freqsel = 0x4; 162 } 163 164 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 165 FREQSEL_MASK, 166 freqsel << FREQSEL_SHIFT); 167 } 168 169 /* Configure DLL TRIM */ 170 mask = DLL_TRIM_ICP_MASK; 171 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 172 173 /* Configure DLL driver strength */ 174 mask |= DR_TY_MASK; 175 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 176 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 177 /* Enable DLL */ 178 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 179 0x1 << ENDLL_SHIFT); 180 /* 181 * Poll for DLL ready. Use a one second timeout. 182 * Works in all experiments done so far 183 */ 184 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 185 val, val & DLLRDY_MASK, 1000, 186 1000000); 187 if (ret) { 188 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 189 return; 190 } 191 192 sdhci_am654->dll_on = true; 193 } 194 } 195 196 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 197 unsigned int clock) 198 { 199 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 200 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 201 int val, mask; 202 203 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 204 val = (1 << OTAPDLYENA_SHIFT) | 205 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 206 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 207 208 sdhci_set_clock(host, clock); 209 } 210 211 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 212 unsigned short vdd) 213 { 214 if (!IS_ERR(host->mmc->supply.vmmc)) { 215 struct mmc_host *mmc = host->mmc; 216 217 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 218 } 219 sdhci_set_power_noreg(host, mode, vdd); 220 } 221 222 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 223 { 224 unsigned char timing = host->mmc->ios.timing; 225 226 if (reg == SDHCI_HOST_CONTROL) { 227 switch (timing) { 228 /* 229 * According to the data manual, HISPD bit 230 * should not be set in these speed modes. 231 */ 232 case MMC_TIMING_SD_HS: 233 case MMC_TIMING_MMC_HS: 234 case MMC_TIMING_UHS_SDR12: 235 case MMC_TIMING_UHS_SDR25: 236 val &= ~SDHCI_CTRL_HISPD; 237 } 238 } 239 240 writeb(val, host->ioaddr + reg); 241 } 242 243 static struct sdhci_ops sdhci_am654_ops = { 244 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 245 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 246 .set_uhs_signaling = sdhci_set_uhs_signaling, 247 .set_bus_width = sdhci_set_bus_width, 248 .set_power = sdhci_am654_set_power, 249 .set_clock = sdhci_am654_set_clock, 250 .write_b = sdhci_am654_write_b, 251 .reset = sdhci_reset, 252 }; 253 254 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 255 .ops = &sdhci_am654_ops, 256 .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 257 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 258 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 259 }; 260 261 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 262 .pdata = &sdhci_am654_pdata, 263 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 264 }; 265 266 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 267 { 268 int cmd_error = 0; 269 int data_error = 0; 270 271 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 272 return intmask; 273 274 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 275 276 return 0; 277 } 278 279 static struct sdhci_ops sdhci_j721e_8bit_ops = { 280 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 281 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 282 .set_uhs_signaling = sdhci_set_uhs_signaling, 283 .set_bus_width = sdhci_set_bus_width, 284 .set_power = sdhci_am654_set_power, 285 .set_clock = sdhci_am654_set_clock, 286 .write_b = sdhci_am654_write_b, 287 .irq = sdhci_am654_cqhci_irq, 288 .reset = sdhci_reset, 289 }; 290 291 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 292 .ops = &sdhci_j721e_8bit_ops, 293 .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 294 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 295 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 296 }; 297 298 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 299 .pdata = &sdhci_j721e_8bit_pdata, 300 .flags = DLL_PRESENT, 301 }; 302 303 static struct sdhci_ops sdhci_j721e_4bit_ops = { 304 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 305 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 306 .set_uhs_signaling = sdhci_set_uhs_signaling, 307 .set_bus_width = sdhci_set_bus_width, 308 .set_power = sdhci_am654_set_power, 309 .set_clock = sdhci_j721e_4bit_set_clock, 310 .write_b = sdhci_am654_write_b, 311 .irq = sdhci_am654_cqhci_irq, 312 .reset = sdhci_reset, 313 }; 314 315 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 316 .ops = &sdhci_j721e_4bit_ops, 317 .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 318 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 319 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 320 }; 321 322 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 323 .pdata = &sdhci_j721e_4bit_pdata, 324 .flags = IOMUX_PRESENT, 325 }; 326 327 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 328 { 329 sdhci_dumpregs(mmc_priv(mmc)); 330 } 331 332 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 333 .enable = sdhci_cqe_enable, 334 .disable = sdhci_cqe_disable, 335 .dumpregs = sdhci_am654_dumpregs, 336 }; 337 338 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 339 { 340 struct cqhci_host *cq_host; 341 int ret; 342 343 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 344 GFP_KERNEL); 345 if (!cq_host) 346 return -ENOMEM; 347 348 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 349 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 350 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 351 cq_host->ops = &sdhci_am654_cqhci_ops; 352 353 host->mmc->caps2 |= MMC_CAP2_CQE; 354 355 ret = cqhci_init(cq_host, host->mmc, 1); 356 357 return ret; 358 } 359 360 static int sdhci_am654_init(struct sdhci_host *host) 361 { 362 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 363 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 364 u32 ctl_cfg_2 = 0; 365 u32 mask; 366 u32 val; 367 int ret; 368 369 /* Reset OTAP to default value */ 370 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 371 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 372 373 if (sdhci_am654->flags & DLL_PRESENT) { 374 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 375 if (~val & CALDONE_MASK) { 376 /* Calibrate IO lines */ 377 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 378 PDB_MASK, PDB_MASK); 379 ret = regmap_read_poll_timeout(sdhci_am654->base, 380 PHY_STAT1, val, 381 val & CALDONE_MASK, 382 1, 20); 383 if (ret) 384 return ret; 385 } 386 } 387 388 /* Enable pins by setting IO mux to 0 */ 389 if (sdhci_am654->flags & IOMUX_PRESENT) 390 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 391 IOMUX_ENABLE_MASK, 0); 392 393 /* Set slot type based on SD or eMMC */ 394 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 395 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 396 397 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 398 ctl_cfg_2); 399 400 ret = sdhci_setup_host(host); 401 if (ret) 402 return ret; 403 404 ret = sdhci_am654_cqe_add_host(host); 405 if (ret) 406 goto err_cleanup_host; 407 408 ret = __sdhci_add_host(host); 409 if (ret) 410 goto err_cleanup_host; 411 412 return 0; 413 414 err_cleanup_host: 415 sdhci_cleanup_host(host); 416 return ret; 417 } 418 419 static int sdhci_am654_get_of_property(struct platform_device *pdev, 420 struct sdhci_am654_data *sdhci_am654) 421 { 422 struct device *dev = &pdev->dev; 423 int drv_strength; 424 int ret; 425 426 ret = device_property_read_u32(dev, "ti,otap-del-sel", 427 &sdhci_am654->otap_del_sel); 428 if (ret) 429 return ret; 430 431 if (sdhci_am654->flags & DLL_PRESENT) { 432 ret = device_property_read_u32(dev, "ti,trm-icp", 433 &sdhci_am654->trm_icp); 434 if (ret) 435 return ret; 436 437 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 438 &drv_strength); 439 if (ret) 440 return ret; 441 442 switch (drv_strength) { 443 case 50: 444 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 445 break; 446 case 33: 447 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 448 break; 449 case 66: 450 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 451 break; 452 case 100: 453 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 454 break; 455 case 40: 456 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 457 break; 458 default: 459 dev_err(dev, "Invalid driver strength\n"); 460 return -EINVAL; 461 } 462 } 463 464 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 465 466 sdhci_get_of_property(pdev); 467 468 return 0; 469 } 470 471 static const struct of_device_id sdhci_am654_of_match[] = { 472 { 473 .compatible = "ti,am654-sdhci-5.1", 474 .data = &sdhci_am654_drvdata, 475 }, 476 { 477 .compatible = "ti,j721e-sdhci-8bit", 478 .data = &sdhci_j721e_8bit_drvdata, 479 }, 480 { 481 .compatible = "ti,j721e-sdhci-4bit", 482 .data = &sdhci_j721e_4bit_drvdata, 483 }, 484 { /* sentinel */ } 485 }; 486 487 static int sdhci_am654_probe(struct platform_device *pdev) 488 { 489 const struct sdhci_am654_driver_data *drvdata; 490 struct sdhci_pltfm_host *pltfm_host; 491 struct sdhci_am654_data *sdhci_am654; 492 const struct of_device_id *match; 493 struct sdhci_host *host; 494 struct resource *res; 495 struct clk *clk_xin; 496 struct device *dev = &pdev->dev; 497 void __iomem *base; 498 int ret; 499 500 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 501 drvdata = match->data; 502 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 503 if (IS_ERR(host)) 504 return PTR_ERR(host); 505 506 pltfm_host = sdhci_priv(host); 507 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 508 sdhci_am654->flags = drvdata->flags; 509 510 clk_xin = devm_clk_get(dev, "clk_xin"); 511 if (IS_ERR(clk_xin)) { 512 dev_err(dev, "clk_xin clock not found.\n"); 513 ret = PTR_ERR(clk_xin); 514 goto err_pltfm_free; 515 } 516 517 pltfm_host->clk = clk_xin; 518 519 /* Clocks are enabled using pm_runtime */ 520 pm_runtime_enable(dev); 521 ret = pm_runtime_get_sync(dev); 522 if (ret < 0) { 523 pm_runtime_put_noidle(dev); 524 goto pm_runtime_disable; 525 } 526 527 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 528 base = devm_ioremap_resource(dev, res); 529 if (IS_ERR(base)) { 530 ret = PTR_ERR(base); 531 goto pm_runtime_put; 532 } 533 534 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 535 &sdhci_am654_regmap_config); 536 if (IS_ERR(sdhci_am654->base)) { 537 dev_err(dev, "Failed to initialize regmap\n"); 538 ret = PTR_ERR(sdhci_am654->base); 539 goto pm_runtime_put; 540 } 541 542 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 543 if (ret) 544 goto pm_runtime_put; 545 546 ret = mmc_of_parse(host->mmc); 547 if (ret) { 548 dev_err(dev, "parsing dt failed (%d)\n", ret); 549 goto pm_runtime_put; 550 } 551 552 ret = sdhci_am654_init(host); 553 if (ret) 554 goto pm_runtime_put; 555 556 return 0; 557 558 pm_runtime_put: 559 pm_runtime_put_sync(dev); 560 pm_runtime_disable: 561 pm_runtime_disable(dev); 562 err_pltfm_free: 563 sdhci_pltfm_free(pdev); 564 return ret; 565 } 566 567 static int sdhci_am654_remove(struct platform_device *pdev) 568 { 569 struct sdhci_host *host = platform_get_drvdata(pdev); 570 int ret; 571 572 sdhci_remove_host(host, true); 573 ret = pm_runtime_put_sync(&pdev->dev); 574 if (ret < 0) 575 return ret; 576 577 pm_runtime_disable(&pdev->dev); 578 sdhci_pltfm_free(pdev); 579 580 return 0; 581 } 582 583 static struct platform_driver sdhci_am654_driver = { 584 .driver = { 585 .name = "sdhci-am654", 586 .of_match_table = sdhci_am654_of_match, 587 }, 588 .probe = sdhci_am654_probe, 589 .remove = sdhci_am654_remove, 590 }; 591 592 module_platform_driver(sdhci_am654_driver); 593 594 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 595 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 596 MODULE_LICENSE("GPL"); 597