1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/of.h> 10 #include <linux/module.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/property.h> 13 #include <linux/regmap.h> 14 15 #include "cqhci.h" 16 #include "sdhci-pltfm.h" 17 18 /* CTL_CFG Registers */ 19 #define CTL_CFG_2 0x14 20 21 #define SLOTTYPE_MASK GENMASK(31, 30) 22 #define SLOTTYPE_EMBEDDED BIT(30) 23 24 /* PHY Registers */ 25 #define PHY_CTRL1 0x100 26 #define PHY_CTRL2 0x104 27 #define PHY_CTRL3 0x108 28 #define PHY_CTRL4 0x10C 29 #define PHY_CTRL5 0x110 30 #define PHY_CTRL6 0x114 31 #define PHY_STAT1 0x130 32 #define PHY_STAT2 0x134 33 34 #define IOMUX_ENABLE_SHIFT 31 35 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 36 #define OTAPDLYENA_SHIFT 20 37 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 38 #define OTAPDLYSEL_SHIFT 12 39 #define OTAPDLYSEL_MASK GENMASK(15, 12) 40 #define STRBSEL_SHIFT 24 41 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 42 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 43 #define SEL50_SHIFT 8 44 #define SEL50_MASK BIT(SEL50_SHIFT) 45 #define SEL100_SHIFT 9 46 #define SEL100_MASK BIT(SEL100_SHIFT) 47 #define FREQSEL_SHIFT 8 48 #define FREQSEL_MASK GENMASK(10, 8) 49 #define DLL_TRIM_ICP_SHIFT 4 50 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 51 #define DR_TY_SHIFT 20 52 #define DR_TY_MASK GENMASK(22, 20) 53 #define ENDLL_SHIFT 1 54 #define ENDLL_MASK BIT(ENDLL_SHIFT) 55 #define DLLRDY_SHIFT 0 56 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 57 #define PDB_SHIFT 0 58 #define PDB_MASK BIT(PDB_SHIFT) 59 #define CALDONE_SHIFT 1 60 #define CALDONE_MASK BIT(CALDONE_SHIFT) 61 #define RETRIM_SHIFT 17 62 #define RETRIM_MASK BIT(RETRIM_SHIFT) 63 64 #define DRIVER_STRENGTH_50_OHM 0x0 65 #define DRIVER_STRENGTH_33_OHM 0x1 66 #define DRIVER_STRENGTH_66_OHM 0x2 67 #define DRIVER_STRENGTH_100_OHM 0x3 68 #define DRIVER_STRENGTH_40_OHM 0x4 69 70 #define CLOCK_TOO_SLOW_HZ 400000 71 72 /* Command Queue Host Controller Interface Base address */ 73 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 74 75 static struct regmap_config sdhci_am654_regmap_config = { 76 .reg_bits = 32, 77 .val_bits = 32, 78 .reg_stride = 4, 79 .fast_io = true, 80 }; 81 82 struct sdhci_am654_data { 83 struct regmap *base; 84 bool legacy_otapdly; 85 int otap_del_sel[11]; 86 int trm_icp; 87 int drv_strength; 88 bool dll_on; 89 int strb_sel; 90 u32 flags; 91 }; 92 93 struct sdhci_am654_driver_data { 94 const struct sdhci_pltfm_data *pdata; 95 u32 flags; 96 #define IOMUX_PRESENT (1 << 0) 97 #define FREQSEL_2_BIT (1 << 1) 98 #define STRBSEL_4_BIT (1 << 2) 99 #define DLL_PRESENT (1 << 3) 100 }; 101 102 struct timing_data { 103 const char *binding; 104 u32 capability; 105 }; 106 107 static const struct timing_data td[] = { 108 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0}, 109 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED}, 110 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED}, 111 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12}, 112 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25}, 113 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50}, 114 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 115 MMC_CAP_UHS_SDR104}, 116 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50}, 117 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR}, 118 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200}, 119 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400}, 120 }; 121 122 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 123 { 124 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 125 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 126 int sel50, sel100, freqsel; 127 u32 mask, val; 128 int ret; 129 130 if (sdhci_am654->flags & FREQSEL_2_BIT) { 131 switch (clock) { 132 case 200000000: 133 sel50 = 0; 134 sel100 = 0; 135 break; 136 case 100000000: 137 sel50 = 0; 138 sel100 = 1; 139 break; 140 default: 141 sel50 = 1; 142 sel100 = 0; 143 } 144 145 /* Configure PHY DLL frequency */ 146 mask = SEL50_MASK | SEL100_MASK; 147 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 148 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 149 150 } else { 151 switch (clock) { 152 case 200000000: 153 freqsel = 0x0; 154 break; 155 default: 156 freqsel = 0x4; 157 } 158 159 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 160 freqsel << FREQSEL_SHIFT); 161 } 162 /* Configure DLL TRIM */ 163 mask = DLL_TRIM_ICP_MASK; 164 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 165 166 /* Configure DLL driver strength */ 167 mask |= DR_TY_MASK; 168 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 169 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 170 171 /* Enable DLL */ 172 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 173 0x1 << ENDLL_SHIFT); 174 /* 175 * Poll for DLL ready. Use a one second timeout. 176 * Works in all experiments done so far 177 */ 178 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 179 val & DLLRDY_MASK, 1000, 1000000); 180 if (ret) { 181 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 182 return; 183 } 184 185 sdhci_am654->dll_on = true; 186 } 187 188 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 189 { 190 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 191 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 192 unsigned char timing = host->mmc->ios.timing; 193 u32 otap_del_sel; 194 u32 otap_del_ena; 195 u32 mask, val; 196 197 if (sdhci_am654->dll_on) { 198 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 199 200 sdhci_am654->dll_on = false; 201 } 202 203 sdhci_set_clock(host, clock); 204 205 if (clock > CLOCK_TOO_SLOW_HZ) { 206 /* Setup DLL Output TAP delay */ 207 if (sdhci_am654->legacy_otapdly) 208 otap_del_sel = sdhci_am654->otap_del_sel[0]; 209 else 210 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 211 212 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 213 214 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 215 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 216 (otap_del_sel << OTAPDLYSEL_SHIFT); 217 218 /* Write to STRBSEL for HS400 speed mode */ 219 if (timing == MMC_TIMING_MMC_HS400) { 220 if (sdhci_am654->flags & STRBSEL_4_BIT) 221 mask |= STRBSEL_4BIT_MASK; 222 else 223 mask |= STRBSEL_8BIT_MASK; 224 225 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 226 } 227 228 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 229 230 if (timing > MMC_TIMING_UHS_SDR25) 231 sdhci_am654_setup_dll(host, clock); 232 } 233 } 234 235 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 236 unsigned int clock) 237 { 238 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 239 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 240 unsigned char timing = host->mmc->ios.timing; 241 u32 otap_del_sel; 242 u32 mask, val; 243 244 /* Setup DLL Output TAP delay */ 245 if (sdhci_am654->legacy_otapdly) 246 otap_del_sel = sdhci_am654->otap_del_sel[0]; 247 else 248 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 249 250 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 251 val = (0x1 << OTAPDLYENA_SHIFT) | 252 (otap_del_sel << OTAPDLYSEL_SHIFT); 253 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 254 255 sdhci_set_clock(host, clock); 256 } 257 258 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 259 unsigned short vdd) 260 { 261 if (!IS_ERR(host->mmc->supply.vmmc)) { 262 struct mmc_host *mmc = host->mmc; 263 264 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 265 } 266 sdhci_set_power_noreg(host, mode, vdd); 267 } 268 269 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 270 { 271 unsigned char timing = host->mmc->ios.timing; 272 273 if (reg == SDHCI_HOST_CONTROL) { 274 switch (timing) { 275 /* 276 * According to the data manual, HISPD bit 277 * should not be set in these speed modes. 278 */ 279 case MMC_TIMING_SD_HS: 280 case MMC_TIMING_MMC_HS: 281 case MMC_TIMING_UHS_SDR12: 282 case MMC_TIMING_UHS_SDR25: 283 val &= ~SDHCI_CTRL_HISPD; 284 } 285 } 286 287 writeb(val, host->ioaddr + reg); 288 } 289 290 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 291 { 292 struct sdhci_host *host = mmc_priv(mmc); 293 int err = sdhci_execute_tuning(mmc, opcode); 294 295 if (err) 296 return err; 297 /* 298 * Tuning data remains in the buffer after tuning. 299 * Do a command and data reset to get rid of it 300 */ 301 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 302 303 return 0; 304 } 305 306 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 307 { 308 int cmd_error = 0; 309 int data_error = 0; 310 311 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 312 return intmask; 313 314 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 315 316 return 0; 317 } 318 319 static struct sdhci_ops sdhci_am654_ops = { 320 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 321 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 322 .set_uhs_signaling = sdhci_set_uhs_signaling, 323 .set_bus_width = sdhci_set_bus_width, 324 .set_power = sdhci_am654_set_power, 325 .set_clock = sdhci_am654_set_clock, 326 .write_b = sdhci_am654_write_b, 327 .irq = sdhci_am654_cqhci_irq, 328 .reset = sdhci_reset, 329 }; 330 331 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 332 .ops = &sdhci_am654_ops, 333 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 334 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 335 }; 336 337 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 338 .pdata = &sdhci_am654_pdata, 339 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 340 }; 341 342 static struct sdhci_ops sdhci_j721e_8bit_ops = { 343 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 344 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 345 .set_uhs_signaling = sdhci_set_uhs_signaling, 346 .set_bus_width = sdhci_set_bus_width, 347 .set_power = sdhci_am654_set_power, 348 .set_clock = sdhci_am654_set_clock, 349 .write_b = sdhci_am654_write_b, 350 .irq = sdhci_am654_cqhci_irq, 351 .reset = sdhci_reset, 352 }; 353 354 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 355 .ops = &sdhci_j721e_8bit_ops, 356 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 357 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 358 }; 359 360 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 361 .pdata = &sdhci_j721e_8bit_pdata, 362 .flags = DLL_PRESENT, 363 }; 364 365 static struct sdhci_ops sdhci_j721e_4bit_ops = { 366 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 367 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 368 .set_uhs_signaling = sdhci_set_uhs_signaling, 369 .set_bus_width = sdhci_set_bus_width, 370 .set_power = sdhci_am654_set_power, 371 .set_clock = sdhci_j721e_4bit_set_clock, 372 .write_b = sdhci_am654_write_b, 373 .irq = sdhci_am654_cqhci_irq, 374 .reset = sdhci_reset, 375 }; 376 377 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 378 .ops = &sdhci_j721e_4bit_ops, 379 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 380 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 381 }; 382 383 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 384 .pdata = &sdhci_j721e_4bit_pdata, 385 .flags = IOMUX_PRESENT, 386 }; 387 388 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 389 { 390 sdhci_dumpregs(mmc_priv(mmc)); 391 } 392 393 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 394 .enable = sdhci_cqe_enable, 395 .disable = sdhci_cqe_disable, 396 .dumpregs = sdhci_am654_dumpregs, 397 }; 398 399 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 400 { 401 struct cqhci_host *cq_host; 402 int ret; 403 404 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 405 GFP_KERNEL); 406 if (!cq_host) 407 return -ENOMEM; 408 409 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 410 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 411 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 412 cq_host->ops = &sdhci_am654_cqhci_ops; 413 414 host->mmc->caps2 |= MMC_CAP2_CQE; 415 416 ret = cqhci_init(cq_host, host->mmc, 1); 417 418 return ret; 419 } 420 421 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 422 struct sdhci_am654_data *sdhci_am654) 423 { 424 struct device *dev = mmc_dev(host->mmc); 425 int i; 426 int ret; 427 428 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding, 429 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 430 if (ret) { 431 /* 432 * ti,otap-del-sel-legacy is mandatory, look for old binding 433 * if not found. 434 */ 435 ret = device_property_read_u32(dev, "ti,otap-del-sel", 436 &sdhci_am654->otap_del_sel[0]); 437 if (ret) { 438 dev_err(dev, "Couldn't find otap-del-sel\n"); 439 440 return ret; 441 } 442 443 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 444 sdhci_am654->legacy_otapdly = true; 445 446 return 0; 447 } 448 449 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 450 451 ret = device_property_read_u32(dev, td[i].binding, 452 &sdhci_am654->otap_del_sel[i]); 453 if (ret) { 454 dev_dbg(dev, "Couldn't find %s\n", 455 td[i].binding); 456 /* 457 * Remove the corresponding capability 458 * if an otap-del-sel value is not found 459 */ 460 if (i <= MMC_TIMING_MMC_DDR52) 461 host->mmc->caps &= ~td[i].capability; 462 else 463 host->mmc->caps2 &= ~td[i].capability; 464 } 465 } 466 467 return 0; 468 } 469 470 static int sdhci_am654_init(struct sdhci_host *host) 471 { 472 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 473 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 474 u32 ctl_cfg_2 = 0; 475 u32 mask; 476 u32 val; 477 int ret; 478 479 /* Reset OTAP to default value */ 480 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 481 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 482 483 if (sdhci_am654->flags & DLL_PRESENT) { 484 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 485 if (~val & CALDONE_MASK) { 486 /* Calibrate IO lines */ 487 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 488 PDB_MASK, PDB_MASK); 489 ret = regmap_read_poll_timeout(sdhci_am654->base, 490 PHY_STAT1, val, 491 val & CALDONE_MASK, 492 1, 20); 493 if (ret) 494 return ret; 495 } 496 } 497 498 /* Enable pins by setting IO mux to 0 */ 499 if (sdhci_am654->flags & IOMUX_PRESENT) 500 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 501 IOMUX_ENABLE_MASK, 0); 502 503 /* Set slot type based on SD or eMMC */ 504 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 505 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 506 507 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 508 ctl_cfg_2); 509 510 ret = sdhci_setup_host(host); 511 if (ret) 512 return ret; 513 514 ret = sdhci_am654_cqe_add_host(host); 515 if (ret) 516 goto err_cleanup_host; 517 518 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 519 if (ret) 520 goto err_cleanup_host; 521 522 ret = __sdhci_add_host(host); 523 if (ret) 524 goto err_cleanup_host; 525 526 return 0; 527 528 err_cleanup_host: 529 sdhci_cleanup_host(host); 530 return ret; 531 } 532 533 static int sdhci_am654_get_of_property(struct platform_device *pdev, 534 struct sdhci_am654_data *sdhci_am654) 535 { 536 struct device *dev = &pdev->dev; 537 int drv_strength; 538 int ret; 539 540 if (sdhci_am654->flags & DLL_PRESENT) { 541 ret = device_property_read_u32(dev, "ti,trm-icp", 542 &sdhci_am654->trm_icp); 543 if (ret) 544 return ret; 545 546 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 547 &drv_strength); 548 if (ret) 549 return ret; 550 551 switch (drv_strength) { 552 case 50: 553 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 554 break; 555 case 33: 556 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 557 break; 558 case 66: 559 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 560 break; 561 case 100: 562 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 563 break; 564 case 40: 565 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 566 break; 567 default: 568 dev_err(dev, "Invalid driver strength\n"); 569 return -EINVAL; 570 } 571 } 572 573 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 574 575 sdhci_get_of_property(pdev); 576 577 return 0; 578 } 579 580 static const struct of_device_id sdhci_am654_of_match[] = { 581 { 582 .compatible = "ti,am654-sdhci-5.1", 583 .data = &sdhci_am654_drvdata, 584 }, 585 { 586 .compatible = "ti,j721e-sdhci-8bit", 587 .data = &sdhci_j721e_8bit_drvdata, 588 }, 589 { 590 .compatible = "ti,j721e-sdhci-4bit", 591 .data = &sdhci_j721e_4bit_drvdata, 592 }, 593 { /* sentinel */ } 594 }; 595 596 static int sdhci_am654_probe(struct platform_device *pdev) 597 { 598 const struct sdhci_am654_driver_data *drvdata; 599 struct sdhci_pltfm_host *pltfm_host; 600 struct sdhci_am654_data *sdhci_am654; 601 const struct of_device_id *match; 602 struct sdhci_host *host; 603 struct clk *clk_xin; 604 struct device *dev = &pdev->dev; 605 void __iomem *base; 606 int ret; 607 608 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 609 drvdata = match->data; 610 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 611 if (IS_ERR(host)) 612 return PTR_ERR(host); 613 614 pltfm_host = sdhci_priv(host); 615 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 616 sdhci_am654->flags = drvdata->flags; 617 618 clk_xin = devm_clk_get(dev, "clk_xin"); 619 if (IS_ERR(clk_xin)) { 620 dev_err(dev, "clk_xin clock not found.\n"); 621 ret = PTR_ERR(clk_xin); 622 goto err_pltfm_free; 623 } 624 625 pltfm_host->clk = clk_xin; 626 627 /* Clocks are enabled using pm_runtime */ 628 pm_runtime_enable(dev); 629 ret = pm_runtime_get_sync(dev); 630 if (ret < 0) { 631 pm_runtime_put_noidle(dev); 632 goto pm_runtime_disable; 633 } 634 635 base = devm_platform_ioremap_resource(pdev, 1); 636 if (IS_ERR(base)) { 637 ret = PTR_ERR(base); 638 goto pm_runtime_put; 639 } 640 641 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 642 &sdhci_am654_regmap_config); 643 if (IS_ERR(sdhci_am654->base)) { 644 dev_err(dev, "Failed to initialize regmap\n"); 645 ret = PTR_ERR(sdhci_am654->base); 646 goto pm_runtime_put; 647 } 648 649 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 650 if (ret) 651 goto pm_runtime_put; 652 653 ret = mmc_of_parse(host->mmc); 654 if (ret) { 655 dev_err(dev, "parsing dt failed (%d)\n", ret); 656 goto pm_runtime_put; 657 } 658 659 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 660 661 ret = sdhci_am654_init(host); 662 if (ret) 663 goto pm_runtime_put; 664 665 return 0; 666 667 pm_runtime_put: 668 pm_runtime_put_sync(dev); 669 pm_runtime_disable: 670 pm_runtime_disable(dev); 671 err_pltfm_free: 672 sdhci_pltfm_free(pdev); 673 return ret; 674 } 675 676 static int sdhci_am654_remove(struct platform_device *pdev) 677 { 678 struct sdhci_host *host = platform_get_drvdata(pdev); 679 int ret; 680 681 sdhci_remove_host(host, true); 682 ret = pm_runtime_put_sync(&pdev->dev); 683 if (ret < 0) 684 return ret; 685 686 pm_runtime_disable(&pdev->dev); 687 sdhci_pltfm_free(pdev); 688 689 return 0; 690 } 691 692 static struct platform_driver sdhci_am654_driver = { 693 .driver = { 694 .name = "sdhci-am654", 695 .of_match_table = sdhci_am654_of_match, 696 }, 697 .probe = sdhci_am654_probe, 698 .remove = sdhci_am654_remove, 699 }; 700 701 module_platform_driver(sdhci_am654_driver); 702 703 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 704 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 705 MODULE_LICENSE("GPL"); 706