1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-pltfm.h" 19 20 /* CTL_CFG Registers */ 21 #define CTL_CFG_2 0x14 22 23 #define SLOTTYPE_MASK GENMASK(31, 30) 24 #define SLOTTYPE_EMBEDDED BIT(30) 25 26 /* PHY Registers */ 27 #define PHY_CTRL1 0x100 28 #define PHY_CTRL2 0x104 29 #define PHY_CTRL3 0x108 30 #define PHY_CTRL4 0x10C 31 #define PHY_CTRL5 0x110 32 #define PHY_CTRL6 0x114 33 #define PHY_STAT1 0x130 34 #define PHY_STAT2 0x134 35 36 #define IOMUX_ENABLE_SHIFT 31 37 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 38 #define OTAPDLYENA_SHIFT 20 39 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 40 #define OTAPDLYSEL_SHIFT 12 41 #define OTAPDLYSEL_MASK GENMASK(15, 12) 42 #define STRBSEL_SHIFT 24 43 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 44 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 45 #define SEL50_SHIFT 8 46 #define SEL50_MASK BIT(SEL50_SHIFT) 47 #define SEL100_SHIFT 9 48 #define SEL100_MASK BIT(SEL100_SHIFT) 49 #define FREQSEL_SHIFT 8 50 #define FREQSEL_MASK GENMASK(10, 8) 51 #define CLKBUFSEL_SHIFT 0 52 #define CLKBUFSEL_MASK GENMASK(2, 0) 53 #define DLL_TRIM_ICP_SHIFT 4 54 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 55 #define DR_TY_SHIFT 20 56 #define DR_TY_MASK GENMASK(22, 20) 57 #define ENDLL_SHIFT 1 58 #define ENDLL_MASK BIT(ENDLL_SHIFT) 59 #define DLLRDY_SHIFT 0 60 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 61 #define PDB_SHIFT 0 62 #define PDB_MASK BIT(PDB_SHIFT) 63 #define CALDONE_SHIFT 1 64 #define CALDONE_MASK BIT(CALDONE_SHIFT) 65 #define RETRIM_SHIFT 17 66 #define RETRIM_MASK BIT(RETRIM_SHIFT) 67 #define SELDLYTXCLK_SHIFT 17 68 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 69 #define SELDLYRXCLK_SHIFT 16 70 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 71 #define ITAPDLYSEL_SHIFT 0 72 #define ITAPDLYSEL_MASK GENMASK(4, 0) 73 #define ITAPDLYENA_SHIFT 8 74 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 75 #define ITAPCHGWIN_SHIFT 9 76 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 77 78 #define DRIVER_STRENGTH_50_OHM 0x0 79 #define DRIVER_STRENGTH_33_OHM 0x1 80 #define DRIVER_STRENGTH_66_OHM 0x2 81 #define DRIVER_STRENGTH_100_OHM 0x3 82 #define DRIVER_STRENGTH_40_OHM 0x4 83 84 #define CLOCK_TOO_SLOW_HZ 50000000 85 86 /* Command Queue Host Controller Interface Base address */ 87 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 88 89 static struct regmap_config sdhci_am654_regmap_config = { 90 .reg_bits = 32, 91 .val_bits = 32, 92 .reg_stride = 4, 93 .fast_io = true, 94 }; 95 96 struct timing_data { 97 const char *otap_binding; 98 const char *itap_binding; 99 u32 capability; 100 }; 101 102 static const struct timing_data td[] = { 103 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 104 "ti,itap-del-sel-legacy", 105 0}, 106 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 107 "ti,itap-del-sel-mmc-hs", 108 MMC_CAP_MMC_HIGHSPEED}, 109 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 110 "ti,itap-del-sel-sd-hs", 111 MMC_CAP_SD_HIGHSPEED}, 112 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 113 "ti,itap-del-sel-sdr12", 114 MMC_CAP_UHS_SDR12}, 115 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 116 "ti,itap-del-sel-sdr25", 117 MMC_CAP_UHS_SDR25}, 118 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 119 NULL, 120 MMC_CAP_UHS_SDR50}, 121 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 122 NULL, 123 MMC_CAP_UHS_SDR104}, 124 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 125 NULL, 126 MMC_CAP_UHS_DDR50}, 127 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 128 "ti,itap-del-sel-ddr52", 129 MMC_CAP_DDR}, 130 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 131 NULL, 132 MMC_CAP2_HS200}, 133 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 134 NULL, 135 MMC_CAP2_HS400}, 136 }; 137 138 struct sdhci_am654_data { 139 struct regmap *base; 140 bool legacy_otapdly; 141 int otap_del_sel[ARRAY_SIZE(td)]; 142 int itap_del_sel[ARRAY_SIZE(td)]; 143 int clkbuf_sel; 144 int trm_icp; 145 int drv_strength; 146 int strb_sel; 147 u32 flags; 148 }; 149 150 struct sdhci_am654_driver_data { 151 const struct sdhci_pltfm_data *pdata; 152 u32 flags; 153 #define IOMUX_PRESENT (1 << 0) 154 #define FREQSEL_2_BIT (1 << 1) 155 #define STRBSEL_4_BIT (1 << 2) 156 #define DLL_PRESENT (1 << 3) 157 #define DLL_CALIB (1 << 4) 158 }; 159 160 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 161 { 162 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 163 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 164 int sel50, sel100, freqsel; 165 u32 mask, val; 166 int ret; 167 168 /* Disable delay chain mode */ 169 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 170 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 171 172 if (sdhci_am654->flags & FREQSEL_2_BIT) { 173 switch (clock) { 174 case 200000000: 175 sel50 = 0; 176 sel100 = 0; 177 break; 178 case 100000000: 179 sel50 = 0; 180 sel100 = 1; 181 break; 182 default: 183 sel50 = 1; 184 sel100 = 0; 185 } 186 187 /* Configure PHY DLL frequency */ 188 mask = SEL50_MASK | SEL100_MASK; 189 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 190 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 191 192 } else { 193 switch (clock) { 194 case 200000000: 195 freqsel = 0x0; 196 break; 197 default: 198 freqsel = 0x4; 199 } 200 201 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 202 freqsel << FREQSEL_SHIFT); 203 } 204 /* Configure DLL TRIM */ 205 mask = DLL_TRIM_ICP_MASK; 206 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 207 208 /* Configure DLL driver strength */ 209 mask |= DR_TY_MASK; 210 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 211 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 212 213 /* Enable DLL */ 214 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 215 0x1 << ENDLL_SHIFT); 216 /* 217 * Poll for DLL ready. Use a one second timeout. 218 * Works in all experiments done so far 219 */ 220 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 221 val & DLLRDY_MASK, 1000, 1000000); 222 if (ret) { 223 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 224 return; 225 } 226 } 227 228 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 229 u32 itapdly) 230 { 231 /* Set ITAPCHGWIN before writing to ITAPDLY */ 232 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 233 1 << ITAPCHGWIN_SHIFT); 234 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 235 itapdly << ITAPDLYSEL_SHIFT); 236 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 237 } 238 239 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 240 unsigned char timing) 241 { 242 u32 mask, val; 243 244 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 245 246 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 247 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 248 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 249 250 sdhci_am654_write_itapdly(sdhci_am654, 251 sdhci_am654->itap_del_sel[timing]); 252 } 253 254 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 255 { 256 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 257 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 258 unsigned char timing = host->mmc->ios.timing; 259 u32 otap_del_sel; 260 u32 otap_del_ena; 261 u32 mask, val; 262 263 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 264 265 sdhci_set_clock(host, clock); 266 267 /* Setup DLL Output TAP delay */ 268 if (sdhci_am654->legacy_otapdly) 269 otap_del_sel = sdhci_am654->otap_del_sel[0]; 270 else 271 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 272 273 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 274 275 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 276 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 277 (otap_del_sel << OTAPDLYSEL_SHIFT); 278 279 /* Write to STRBSEL for HS400 speed mode */ 280 if (timing == MMC_TIMING_MMC_HS400) { 281 if (sdhci_am654->flags & STRBSEL_4_BIT) 282 mask |= STRBSEL_4BIT_MASK; 283 else 284 mask |= STRBSEL_8BIT_MASK; 285 286 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 287 } 288 289 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 290 291 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 292 sdhci_am654_setup_dll(host, clock); 293 else 294 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 295 296 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 297 sdhci_am654->clkbuf_sel); 298 } 299 300 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 301 unsigned int clock) 302 { 303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 304 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 305 unsigned char timing = host->mmc->ios.timing; 306 u32 otap_del_sel; 307 u32 mask, val; 308 309 /* Setup DLL Output TAP delay */ 310 if (sdhci_am654->legacy_otapdly) 311 otap_del_sel = sdhci_am654->otap_del_sel[0]; 312 else 313 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 314 315 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 316 val = (0x1 << OTAPDLYENA_SHIFT) | 317 (otap_del_sel << OTAPDLYSEL_SHIFT); 318 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 319 320 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 321 sdhci_am654->clkbuf_sel); 322 323 sdhci_set_clock(host, clock); 324 } 325 326 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 327 { 328 writeb(val, host->ioaddr + reg); 329 usleep_range(1000, 10000); 330 return readb(host->ioaddr + reg); 331 } 332 333 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 334 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 335 { 336 unsigned char timing = host->mmc->ios.timing; 337 u8 pwr; 338 int ret; 339 340 if (reg == SDHCI_HOST_CONTROL) { 341 switch (timing) { 342 /* 343 * According to the data manual, HISPD bit 344 * should not be set in these speed modes. 345 */ 346 case MMC_TIMING_SD_HS: 347 case MMC_TIMING_MMC_HS: 348 case MMC_TIMING_UHS_SDR12: 349 case MMC_TIMING_UHS_SDR25: 350 val &= ~SDHCI_CTRL_HISPD; 351 } 352 } 353 354 writeb(val, host->ioaddr + reg); 355 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 356 /* 357 * Power on will not happen until the card detect debounce 358 * timer expires. Wait at least 1.5 seconds for the power on 359 * bit to be set 360 */ 361 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 362 pwr & SDHCI_POWER_ON, 0, 363 MAX_POWER_ON_TIMEOUT, false, host, val, 364 reg); 365 if (ret) 366 dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 367 } 368 } 369 370 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 371 { 372 struct sdhci_host *host = mmc_priv(mmc); 373 int err = sdhci_execute_tuning(mmc, opcode); 374 375 if (err) 376 return err; 377 /* 378 * Tuning data remains in the buffer after tuning. 379 * Do a command and data reset to get rid of it 380 */ 381 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 382 383 return 0; 384 } 385 386 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 387 { 388 int cmd_error = 0; 389 int data_error = 0; 390 391 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 392 return intmask; 393 394 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 395 396 return 0; 397 } 398 399 static struct sdhci_ops sdhci_am654_ops = { 400 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 401 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 402 .set_uhs_signaling = sdhci_set_uhs_signaling, 403 .set_bus_width = sdhci_set_bus_width, 404 .set_power = sdhci_set_power_and_bus_voltage, 405 .set_clock = sdhci_am654_set_clock, 406 .write_b = sdhci_am654_write_b, 407 .irq = sdhci_am654_cqhci_irq, 408 .reset = sdhci_reset, 409 }; 410 411 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 412 .ops = &sdhci_am654_ops, 413 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 414 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 415 }; 416 417 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 418 .pdata = &sdhci_am654_pdata, 419 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 420 DLL_CALIB, 421 }; 422 423 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 424 .pdata = &sdhci_am654_pdata, 425 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 426 }; 427 428 static struct sdhci_ops sdhci_j721e_8bit_ops = { 429 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 430 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 431 .set_uhs_signaling = sdhci_set_uhs_signaling, 432 .set_bus_width = sdhci_set_bus_width, 433 .set_power = sdhci_set_power_and_bus_voltage, 434 .set_clock = sdhci_am654_set_clock, 435 .write_b = sdhci_am654_write_b, 436 .irq = sdhci_am654_cqhci_irq, 437 .reset = sdhci_reset, 438 }; 439 440 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 441 .ops = &sdhci_j721e_8bit_ops, 442 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 443 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 444 }; 445 446 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 447 .pdata = &sdhci_j721e_8bit_pdata, 448 .flags = DLL_PRESENT | DLL_CALIB, 449 }; 450 451 static struct sdhci_ops sdhci_j721e_4bit_ops = { 452 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 453 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 454 .set_uhs_signaling = sdhci_set_uhs_signaling, 455 .set_bus_width = sdhci_set_bus_width, 456 .set_power = sdhci_set_power_and_bus_voltage, 457 .set_clock = sdhci_j721e_4bit_set_clock, 458 .write_b = sdhci_am654_write_b, 459 .irq = sdhci_am654_cqhci_irq, 460 .reset = sdhci_reset, 461 }; 462 463 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 464 .ops = &sdhci_j721e_4bit_ops, 465 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 466 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 467 }; 468 469 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 470 .pdata = &sdhci_j721e_4bit_pdata, 471 .flags = IOMUX_PRESENT, 472 }; 473 474 static const struct soc_device_attribute sdhci_am654_devices[] = { 475 { .family = "AM65X", 476 .revision = "SR1.0", 477 .data = &sdhci_am654_sr1_drvdata 478 }, 479 {/* sentinel */} 480 }; 481 482 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 483 { 484 sdhci_dumpregs(mmc_priv(mmc)); 485 } 486 487 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 488 .enable = sdhci_cqe_enable, 489 .disable = sdhci_cqe_disable, 490 .dumpregs = sdhci_am654_dumpregs, 491 }; 492 493 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 494 { 495 struct cqhci_host *cq_host; 496 int ret; 497 498 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 499 GFP_KERNEL); 500 if (!cq_host) 501 return -ENOMEM; 502 503 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 504 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 505 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 506 cq_host->ops = &sdhci_am654_cqhci_ops; 507 508 host->mmc->caps2 |= MMC_CAP2_CQE; 509 510 ret = cqhci_init(cq_host, host->mmc, 1); 511 512 return ret; 513 } 514 515 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 516 struct sdhci_am654_data *sdhci_am654) 517 { 518 struct device *dev = mmc_dev(host->mmc); 519 int i; 520 int ret; 521 522 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 523 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 524 if (ret) { 525 /* 526 * ti,otap-del-sel-legacy is mandatory, look for old binding 527 * if not found. 528 */ 529 ret = device_property_read_u32(dev, "ti,otap-del-sel", 530 &sdhci_am654->otap_del_sel[0]); 531 if (ret) { 532 dev_err(dev, "Couldn't find otap-del-sel\n"); 533 534 return ret; 535 } 536 537 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 538 sdhci_am654->legacy_otapdly = true; 539 540 return 0; 541 } 542 543 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 544 545 ret = device_property_read_u32(dev, td[i].otap_binding, 546 &sdhci_am654->otap_del_sel[i]); 547 if (ret) { 548 dev_dbg(dev, "Couldn't find %s\n", 549 td[i].otap_binding); 550 /* 551 * Remove the corresponding capability 552 * if an otap-del-sel value is not found 553 */ 554 if (i <= MMC_TIMING_MMC_DDR52) 555 host->mmc->caps &= ~td[i].capability; 556 else 557 host->mmc->caps2 &= ~td[i].capability; 558 } 559 560 if (td[i].itap_binding) 561 device_property_read_u32(dev, td[i].itap_binding, 562 &sdhci_am654->itap_del_sel[i]); 563 } 564 565 return 0; 566 } 567 568 static int sdhci_am654_init(struct sdhci_host *host) 569 { 570 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 571 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 572 u32 ctl_cfg_2 = 0; 573 u32 mask; 574 u32 val; 575 int ret; 576 577 /* Reset OTAP to default value */ 578 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 579 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 580 581 if (sdhci_am654->flags & DLL_CALIB) { 582 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 583 if (~val & CALDONE_MASK) { 584 /* Calibrate IO lines */ 585 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 586 PDB_MASK, PDB_MASK); 587 ret = regmap_read_poll_timeout(sdhci_am654->base, 588 PHY_STAT1, val, 589 val & CALDONE_MASK, 590 1, 20); 591 if (ret) 592 return ret; 593 } 594 } 595 596 /* Enable pins by setting IO mux to 0 */ 597 if (sdhci_am654->flags & IOMUX_PRESENT) 598 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 599 IOMUX_ENABLE_MASK, 0); 600 601 /* Set slot type based on SD or eMMC */ 602 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 603 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 604 605 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 606 ctl_cfg_2); 607 608 ret = sdhci_setup_host(host); 609 if (ret) 610 return ret; 611 612 ret = sdhci_am654_cqe_add_host(host); 613 if (ret) 614 goto err_cleanup_host; 615 616 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 617 if (ret) 618 goto err_cleanup_host; 619 620 ret = __sdhci_add_host(host); 621 if (ret) 622 goto err_cleanup_host; 623 624 return 0; 625 626 err_cleanup_host: 627 sdhci_cleanup_host(host); 628 return ret; 629 } 630 631 static int sdhci_am654_get_of_property(struct platform_device *pdev, 632 struct sdhci_am654_data *sdhci_am654) 633 { 634 struct device *dev = &pdev->dev; 635 int drv_strength; 636 int ret; 637 638 if (sdhci_am654->flags & DLL_PRESENT) { 639 ret = device_property_read_u32(dev, "ti,trm-icp", 640 &sdhci_am654->trm_icp); 641 if (ret) 642 return ret; 643 644 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 645 &drv_strength); 646 if (ret) 647 return ret; 648 649 switch (drv_strength) { 650 case 50: 651 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 652 break; 653 case 33: 654 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 655 break; 656 case 66: 657 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 658 break; 659 case 100: 660 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 661 break; 662 case 40: 663 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 664 break; 665 default: 666 dev_err(dev, "Invalid driver strength\n"); 667 return -EINVAL; 668 } 669 } 670 671 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 672 device_property_read_u32(dev, "ti,clkbuf-sel", 673 &sdhci_am654->clkbuf_sel); 674 675 sdhci_get_of_property(pdev); 676 677 return 0; 678 } 679 680 static const struct of_device_id sdhci_am654_of_match[] = { 681 { 682 .compatible = "ti,am654-sdhci-5.1", 683 .data = &sdhci_am654_drvdata, 684 }, 685 { 686 .compatible = "ti,j721e-sdhci-8bit", 687 .data = &sdhci_j721e_8bit_drvdata, 688 }, 689 { 690 .compatible = "ti,j721e-sdhci-4bit", 691 .data = &sdhci_j721e_4bit_drvdata, 692 }, 693 { /* sentinel */ } 694 }; 695 696 static int sdhci_am654_probe(struct platform_device *pdev) 697 { 698 const struct sdhci_am654_driver_data *drvdata; 699 const struct soc_device_attribute *soc; 700 struct sdhci_pltfm_host *pltfm_host; 701 struct sdhci_am654_data *sdhci_am654; 702 const struct of_device_id *match; 703 struct sdhci_host *host; 704 struct clk *clk_xin; 705 struct device *dev = &pdev->dev; 706 void __iomem *base; 707 int ret; 708 709 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 710 drvdata = match->data; 711 712 /* Update drvdata based on SoC revision */ 713 soc = soc_device_match(sdhci_am654_devices); 714 if (soc && soc->data) 715 drvdata = soc->data; 716 717 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 718 if (IS_ERR(host)) 719 return PTR_ERR(host); 720 721 pltfm_host = sdhci_priv(host); 722 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 723 sdhci_am654->flags = drvdata->flags; 724 725 clk_xin = devm_clk_get(dev, "clk_xin"); 726 if (IS_ERR(clk_xin)) { 727 dev_err(dev, "clk_xin clock not found.\n"); 728 ret = PTR_ERR(clk_xin); 729 goto err_pltfm_free; 730 } 731 732 pltfm_host->clk = clk_xin; 733 734 /* Clocks are enabled using pm_runtime */ 735 pm_runtime_enable(dev); 736 ret = pm_runtime_get_sync(dev); 737 if (ret < 0) { 738 pm_runtime_put_noidle(dev); 739 goto pm_runtime_disable; 740 } 741 742 base = devm_platform_ioremap_resource(pdev, 1); 743 if (IS_ERR(base)) { 744 ret = PTR_ERR(base); 745 goto pm_runtime_put; 746 } 747 748 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 749 &sdhci_am654_regmap_config); 750 if (IS_ERR(sdhci_am654->base)) { 751 dev_err(dev, "Failed to initialize regmap\n"); 752 ret = PTR_ERR(sdhci_am654->base); 753 goto pm_runtime_put; 754 } 755 756 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 757 if (ret) 758 goto pm_runtime_put; 759 760 ret = mmc_of_parse(host->mmc); 761 if (ret) { 762 dev_err(dev, "parsing dt failed (%d)\n", ret); 763 goto pm_runtime_put; 764 } 765 766 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 767 768 ret = sdhci_am654_init(host); 769 if (ret) 770 goto pm_runtime_put; 771 772 return 0; 773 774 pm_runtime_put: 775 pm_runtime_put_sync(dev); 776 pm_runtime_disable: 777 pm_runtime_disable(dev); 778 err_pltfm_free: 779 sdhci_pltfm_free(pdev); 780 return ret; 781 } 782 783 static int sdhci_am654_remove(struct platform_device *pdev) 784 { 785 struct sdhci_host *host = platform_get_drvdata(pdev); 786 int ret; 787 788 sdhci_remove_host(host, true); 789 ret = pm_runtime_put_sync(&pdev->dev); 790 if (ret < 0) 791 return ret; 792 793 pm_runtime_disable(&pdev->dev); 794 sdhci_pltfm_free(pdev); 795 796 return 0; 797 } 798 799 static struct platform_driver sdhci_am654_driver = { 800 .driver = { 801 .name = "sdhci-am654", 802 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 803 .of_match_table = sdhci_am654_of_match, 804 }, 805 .probe = sdhci_am654_probe, 806 .remove = sdhci_am654_remove, 807 }; 808 809 module_platform_driver(sdhci_am654_driver); 810 811 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 812 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 813 MODULE_LICENSE("GPL"); 814