1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 20 21 /* CTL_CFG Registers */ 22 #define CTL_CFG_2 0x14 23 #define CTL_CFG_3 0x18 24 25 #define SLOTTYPE_MASK GENMASK(31, 30) 26 #define SLOTTYPE_EMBEDDED BIT(30) 27 #define TUNINGFORSDR50_MASK BIT(13) 28 29 /* PHY Registers */ 30 #define PHY_CTRL1 0x100 31 #define PHY_CTRL2 0x104 32 #define PHY_CTRL3 0x108 33 #define PHY_CTRL4 0x10C 34 #define PHY_CTRL5 0x110 35 #define PHY_CTRL6 0x114 36 #define PHY_STAT1 0x130 37 #define PHY_STAT2 0x134 38 39 #define IOMUX_ENABLE_SHIFT 31 40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 41 #define OTAPDLYENA_SHIFT 20 42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 43 #define OTAPDLYSEL_SHIFT 12 44 #define OTAPDLYSEL_MASK GENMASK(15, 12) 45 #define STRBSEL_SHIFT 24 46 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 47 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 48 #define SEL50_SHIFT 8 49 #define SEL50_MASK BIT(SEL50_SHIFT) 50 #define SEL100_SHIFT 9 51 #define SEL100_MASK BIT(SEL100_SHIFT) 52 #define FREQSEL_SHIFT 8 53 #define FREQSEL_MASK GENMASK(10, 8) 54 #define CLKBUFSEL_SHIFT 0 55 #define CLKBUFSEL_MASK GENMASK(2, 0) 56 #define DLL_TRIM_ICP_SHIFT 4 57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 58 #define DR_TY_SHIFT 20 59 #define DR_TY_MASK GENMASK(22, 20) 60 #define ENDLL_SHIFT 1 61 #define ENDLL_MASK BIT(ENDLL_SHIFT) 62 #define DLLRDY_SHIFT 0 63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 64 #define PDB_SHIFT 0 65 #define PDB_MASK BIT(PDB_SHIFT) 66 #define CALDONE_SHIFT 1 67 #define CALDONE_MASK BIT(CALDONE_SHIFT) 68 #define RETRIM_SHIFT 17 69 #define RETRIM_MASK BIT(RETRIM_SHIFT) 70 #define SELDLYTXCLK_SHIFT 17 71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72 #define SELDLYRXCLK_SHIFT 16 73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74 #define ITAPDLYSEL_SHIFT 0 75 #define ITAPDLYSEL_MASK GENMASK(4, 0) 76 #define ITAPDLYENA_SHIFT 8 77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78 #define ITAPCHGWIN_SHIFT 9 79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 80 81 #define DRIVER_STRENGTH_50_OHM 0x0 82 #define DRIVER_STRENGTH_33_OHM 0x1 83 #define DRIVER_STRENGTH_66_OHM 0x2 84 #define DRIVER_STRENGTH_100_OHM 0x3 85 #define DRIVER_STRENGTH_40_OHM 0x4 86 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 89 /* Command Queue Host Controller Interface Base address */ 90 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 91 92 static struct regmap_config sdhci_am654_regmap_config = { 93 .reg_bits = 32, 94 .val_bits = 32, 95 .reg_stride = 4, 96 .fast_io = true, 97 }; 98 99 struct timing_data { 100 const char *otap_binding; 101 const char *itap_binding; 102 u32 capability; 103 }; 104 105 static const struct timing_data td[] = { 106 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 107 "ti,itap-del-sel-legacy", 108 0}, 109 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 110 "ti,itap-del-sel-mmc-hs", 111 MMC_CAP_MMC_HIGHSPEED}, 112 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 113 "ti,itap-del-sel-sd-hs", 114 MMC_CAP_SD_HIGHSPEED}, 115 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 116 "ti,itap-del-sel-sdr12", 117 MMC_CAP_UHS_SDR12}, 118 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 119 "ti,itap-del-sel-sdr25", 120 MMC_CAP_UHS_SDR25}, 121 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 122 NULL, 123 MMC_CAP_UHS_SDR50}, 124 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 125 NULL, 126 MMC_CAP_UHS_SDR104}, 127 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 128 NULL, 129 MMC_CAP_UHS_DDR50}, 130 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 131 "ti,itap-del-sel-ddr52", 132 MMC_CAP_DDR}, 133 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 134 NULL, 135 MMC_CAP2_HS200}, 136 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 137 NULL, 138 MMC_CAP2_HS400}, 139 }; 140 141 struct sdhci_am654_data { 142 struct regmap *base; 143 bool legacy_otapdly; 144 int otap_del_sel[ARRAY_SIZE(td)]; 145 int itap_del_sel[ARRAY_SIZE(td)]; 146 int clkbuf_sel; 147 int trm_icp; 148 int drv_strength; 149 int strb_sel; 150 u32 flags; 151 u32 quirks; 152 153 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 154 }; 155 156 struct sdhci_am654_driver_data { 157 const struct sdhci_pltfm_data *pdata; 158 u32 flags; 159 #define IOMUX_PRESENT (1 << 0) 160 #define FREQSEL_2_BIT (1 << 1) 161 #define STRBSEL_4_BIT (1 << 2) 162 #define DLL_PRESENT (1 << 3) 163 #define DLL_CALIB (1 << 4) 164 }; 165 166 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 167 { 168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 169 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 170 int sel50, sel100, freqsel; 171 u32 mask, val; 172 int ret; 173 174 /* Disable delay chain mode */ 175 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 176 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 177 178 if (sdhci_am654->flags & FREQSEL_2_BIT) { 179 switch (clock) { 180 case 200000000: 181 sel50 = 0; 182 sel100 = 0; 183 break; 184 case 100000000: 185 sel50 = 0; 186 sel100 = 1; 187 break; 188 default: 189 sel50 = 1; 190 sel100 = 0; 191 } 192 193 /* Configure PHY DLL frequency */ 194 mask = SEL50_MASK | SEL100_MASK; 195 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 196 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 197 198 } else { 199 switch (clock) { 200 case 200000000: 201 freqsel = 0x0; 202 break; 203 default: 204 freqsel = 0x4; 205 } 206 207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 208 freqsel << FREQSEL_SHIFT); 209 } 210 /* Configure DLL TRIM */ 211 mask = DLL_TRIM_ICP_MASK; 212 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 213 214 /* Configure DLL driver strength */ 215 mask |= DR_TY_MASK; 216 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 217 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 218 219 /* Enable DLL */ 220 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 221 0x1 << ENDLL_SHIFT); 222 /* 223 * Poll for DLL ready. Use a one second timeout. 224 * Works in all experiments done so far 225 */ 226 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 227 val & DLLRDY_MASK, 1000, 1000000); 228 if (ret) { 229 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 230 return; 231 } 232 } 233 234 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 235 u32 itapdly) 236 { 237 /* Set ITAPCHGWIN before writing to ITAPDLY */ 238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 239 1 << ITAPCHGWIN_SHIFT); 240 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 241 itapdly << ITAPDLYSEL_SHIFT); 242 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 243 } 244 245 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 246 unsigned char timing) 247 { 248 u32 mask, val; 249 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 251 252 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 253 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 254 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 255 256 sdhci_am654_write_itapdly(sdhci_am654, 257 sdhci_am654->itap_del_sel[timing]); 258 } 259 260 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 261 { 262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 263 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 264 unsigned char timing = host->mmc->ios.timing; 265 u32 otap_del_sel; 266 u32 otap_del_ena; 267 u32 mask, val; 268 269 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 270 271 sdhci_set_clock(host, clock); 272 273 /* Setup DLL Output TAP delay */ 274 if (sdhci_am654->legacy_otapdly) 275 otap_del_sel = sdhci_am654->otap_del_sel[0]; 276 else 277 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 278 279 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 280 281 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 282 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 283 (otap_del_sel << OTAPDLYSEL_SHIFT); 284 285 /* Write to STRBSEL for HS400 speed mode */ 286 if (timing == MMC_TIMING_MMC_HS400) { 287 if (sdhci_am654->flags & STRBSEL_4_BIT) 288 mask |= STRBSEL_4BIT_MASK; 289 else 290 mask |= STRBSEL_8BIT_MASK; 291 292 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 293 } 294 295 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 296 297 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 298 sdhci_am654_setup_dll(host, clock); 299 else 300 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 301 302 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 303 sdhci_am654->clkbuf_sel); 304 } 305 306 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 307 unsigned int clock) 308 { 309 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 310 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 311 unsigned char timing = host->mmc->ios.timing; 312 u32 otap_del_sel; 313 u32 mask, val; 314 315 /* Setup DLL Output TAP delay */ 316 if (sdhci_am654->legacy_otapdly) 317 otap_del_sel = sdhci_am654->otap_del_sel[0]; 318 else 319 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 320 321 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 322 val = (0x1 << OTAPDLYENA_SHIFT) | 323 (otap_del_sel << OTAPDLYSEL_SHIFT); 324 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 325 326 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 327 sdhci_am654->clkbuf_sel); 328 329 sdhci_set_clock(host, clock); 330 } 331 332 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 333 { 334 writeb(val, host->ioaddr + reg); 335 usleep_range(1000, 10000); 336 return readb(host->ioaddr + reg); 337 } 338 339 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 340 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 341 { 342 unsigned char timing = host->mmc->ios.timing; 343 u8 pwr; 344 int ret; 345 346 if (reg == SDHCI_HOST_CONTROL) { 347 switch (timing) { 348 /* 349 * According to the data manual, HISPD bit 350 * should not be set in these speed modes. 351 */ 352 case MMC_TIMING_SD_HS: 353 case MMC_TIMING_MMC_HS: 354 case MMC_TIMING_UHS_SDR12: 355 case MMC_TIMING_UHS_SDR25: 356 val &= ~SDHCI_CTRL_HISPD; 357 } 358 } 359 360 writeb(val, host->ioaddr + reg); 361 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 362 /* 363 * Power on will not happen until the card detect debounce 364 * timer expires. Wait at least 1.5 seconds for the power on 365 * bit to be set 366 */ 367 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 368 pwr & SDHCI_POWER_ON, 0, 369 MAX_POWER_ON_TIMEOUT, false, host, val, 370 reg); 371 if (ret) 372 dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 373 } 374 } 375 376 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 377 { 378 u8 ctrl; 379 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 380 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 381 382 sdhci_and_cqhci_reset(host, mask); 383 384 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 385 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 386 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 387 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 388 } 389 } 390 391 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 392 { 393 struct sdhci_host *host = mmc_priv(mmc); 394 int err = sdhci_execute_tuning(mmc, opcode); 395 396 if (err) 397 return err; 398 /* 399 * Tuning data remains in the buffer after tuning. 400 * Do a command and data reset to get rid of it 401 */ 402 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 403 404 return 0; 405 } 406 407 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 408 { 409 int cmd_error = 0; 410 int data_error = 0; 411 412 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 413 return intmask; 414 415 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 416 417 return 0; 418 } 419 420 #define ITAP_MAX 32 421 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 422 u32 opcode) 423 { 424 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 425 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 426 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; 427 u32 itap; 428 429 /* Enable ITAPDLY */ 430 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 431 1 << ITAPDLYENA_SHIFT); 432 433 for (itap = 0; itap < ITAP_MAX; itap++) { 434 sdhci_am654_write_itapdly(sdhci_am654, itap); 435 436 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); 437 if (cur_val && !prev_val) 438 pass_window = itap; 439 440 if (!cur_val) 441 fail_len++; 442 443 prev_val = cur_val; 444 } 445 /* 446 * Having determined the length of the failing window and start of 447 * the passing window calculate the length of the passing window and 448 * set the final value halfway through it considering the range as a 449 * circular buffer 450 */ 451 pass_len = ITAP_MAX - fail_len; 452 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; 453 sdhci_am654_write_itapdly(sdhci_am654, itap); 454 455 return 0; 456 } 457 458 static struct sdhci_ops sdhci_am654_ops = { 459 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 460 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 461 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 462 .set_uhs_signaling = sdhci_set_uhs_signaling, 463 .set_bus_width = sdhci_set_bus_width, 464 .set_power = sdhci_set_power_and_bus_voltage, 465 .set_clock = sdhci_am654_set_clock, 466 .write_b = sdhci_am654_write_b, 467 .irq = sdhci_am654_cqhci_irq, 468 .reset = sdhci_and_cqhci_reset, 469 }; 470 471 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 472 .ops = &sdhci_am654_ops, 473 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 474 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 475 }; 476 477 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 478 .pdata = &sdhci_am654_pdata, 479 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 480 DLL_CALIB, 481 }; 482 483 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 484 .pdata = &sdhci_am654_pdata, 485 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 486 }; 487 488 static struct sdhci_ops sdhci_j721e_8bit_ops = { 489 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 490 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 491 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 492 .set_uhs_signaling = sdhci_set_uhs_signaling, 493 .set_bus_width = sdhci_set_bus_width, 494 .set_power = sdhci_set_power_and_bus_voltage, 495 .set_clock = sdhci_am654_set_clock, 496 .write_b = sdhci_am654_write_b, 497 .irq = sdhci_am654_cqhci_irq, 498 .reset = sdhci_and_cqhci_reset, 499 }; 500 501 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 502 .ops = &sdhci_j721e_8bit_ops, 503 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 504 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 505 }; 506 507 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 508 .pdata = &sdhci_j721e_8bit_pdata, 509 .flags = DLL_PRESENT | DLL_CALIB, 510 }; 511 512 static struct sdhci_ops sdhci_j721e_4bit_ops = { 513 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 514 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 515 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 516 .set_uhs_signaling = sdhci_set_uhs_signaling, 517 .set_bus_width = sdhci_set_bus_width, 518 .set_power = sdhci_set_power_and_bus_voltage, 519 .set_clock = sdhci_j721e_4bit_set_clock, 520 .write_b = sdhci_am654_write_b, 521 .irq = sdhci_am654_cqhci_irq, 522 .reset = sdhci_am654_reset, 523 }; 524 525 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 526 .ops = &sdhci_j721e_4bit_ops, 527 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 528 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 529 }; 530 531 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 532 .pdata = &sdhci_j721e_4bit_pdata, 533 .flags = IOMUX_PRESENT, 534 }; 535 536 static const struct soc_device_attribute sdhci_am654_devices[] = { 537 { .family = "AM65X", 538 .revision = "SR1.0", 539 .data = &sdhci_am654_sr1_drvdata 540 }, 541 {/* sentinel */} 542 }; 543 544 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 545 { 546 sdhci_dumpregs(mmc_priv(mmc)); 547 } 548 549 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 550 .enable = sdhci_cqe_enable, 551 .disable = sdhci_cqe_disable, 552 .dumpregs = sdhci_am654_dumpregs, 553 }; 554 555 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 556 { 557 struct cqhci_host *cq_host; 558 int ret; 559 560 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 561 GFP_KERNEL); 562 if (!cq_host) 563 return -ENOMEM; 564 565 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 566 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 567 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 568 cq_host->ops = &sdhci_am654_cqhci_ops; 569 570 host->mmc->caps2 |= MMC_CAP2_CQE; 571 572 ret = cqhci_init(cq_host, host->mmc, 1); 573 574 return ret; 575 } 576 577 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 578 struct sdhci_am654_data *sdhci_am654) 579 { 580 struct device *dev = mmc_dev(host->mmc); 581 int i; 582 int ret; 583 584 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 585 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 586 if (ret) { 587 /* 588 * ti,otap-del-sel-legacy is mandatory, look for old binding 589 * if not found. 590 */ 591 ret = device_property_read_u32(dev, "ti,otap-del-sel", 592 &sdhci_am654->otap_del_sel[0]); 593 if (ret) { 594 dev_err(dev, "Couldn't find otap-del-sel\n"); 595 596 return ret; 597 } 598 599 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 600 sdhci_am654->legacy_otapdly = true; 601 602 return 0; 603 } 604 605 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 606 607 ret = device_property_read_u32(dev, td[i].otap_binding, 608 &sdhci_am654->otap_del_sel[i]); 609 if (ret) { 610 dev_dbg(dev, "Couldn't find %s\n", 611 td[i].otap_binding); 612 /* 613 * Remove the corresponding capability 614 * if an otap-del-sel value is not found 615 */ 616 if (i <= MMC_TIMING_MMC_DDR52) 617 host->mmc->caps &= ~td[i].capability; 618 else 619 host->mmc->caps2 &= ~td[i].capability; 620 } 621 622 if (td[i].itap_binding) 623 device_property_read_u32(dev, td[i].itap_binding, 624 &sdhci_am654->itap_del_sel[i]); 625 } 626 627 return 0; 628 } 629 630 static int sdhci_am654_init(struct sdhci_host *host) 631 { 632 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 633 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 634 u32 ctl_cfg_2 = 0; 635 u32 mask; 636 u32 val; 637 int ret; 638 639 /* Reset OTAP to default value */ 640 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 641 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 642 643 if (sdhci_am654->flags & DLL_CALIB) { 644 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 645 if (~val & CALDONE_MASK) { 646 /* Calibrate IO lines */ 647 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 648 PDB_MASK, PDB_MASK); 649 ret = regmap_read_poll_timeout(sdhci_am654->base, 650 PHY_STAT1, val, 651 val & CALDONE_MASK, 652 1, 20); 653 if (ret) 654 return ret; 655 } 656 } 657 658 /* Enable pins by setting IO mux to 0 */ 659 if (sdhci_am654->flags & IOMUX_PRESENT) 660 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 661 IOMUX_ENABLE_MASK, 0); 662 663 /* Set slot type based on SD or eMMC */ 664 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 665 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 666 667 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 668 ctl_cfg_2); 669 670 /* Enable tuning for SDR50 */ 671 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 672 TUNINGFORSDR50_MASK); 673 674 ret = sdhci_setup_host(host); 675 if (ret) 676 return ret; 677 678 ret = sdhci_am654_cqe_add_host(host); 679 if (ret) 680 goto err_cleanup_host; 681 682 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 683 if (ret) 684 goto err_cleanup_host; 685 686 ret = __sdhci_add_host(host); 687 if (ret) 688 goto err_cleanup_host; 689 690 return 0; 691 692 err_cleanup_host: 693 sdhci_cleanup_host(host); 694 return ret; 695 } 696 697 static int sdhci_am654_get_of_property(struct platform_device *pdev, 698 struct sdhci_am654_data *sdhci_am654) 699 { 700 struct device *dev = &pdev->dev; 701 int drv_strength; 702 int ret; 703 704 if (sdhci_am654->flags & DLL_PRESENT) { 705 ret = device_property_read_u32(dev, "ti,trm-icp", 706 &sdhci_am654->trm_icp); 707 if (ret) 708 return ret; 709 710 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 711 &drv_strength); 712 if (ret) 713 return ret; 714 715 switch (drv_strength) { 716 case 50: 717 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 718 break; 719 case 33: 720 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 721 break; 722 case 66: 723 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 724 break; 725 case 100: 726 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 727 break; 728 case 40: 729 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 730 break; 731 default: 732 dev_err(dev, "Invalid driver strength\n"); 733 return -EINVAL; 734 } 735 } 736 737 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 738 device_property_read_u32(dev, "ti,clkbuf-sel", 739 &sdhci_am654->clkbuf_sel); 740 741 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 742 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 743 744 sdhci_get_of_property(pdev); 745 746 return 0; 747 } 748 749 static const struct of_device_id sdhci_am654_of_match[] = { 750 { 751 .compatible = "ti,am654-sdhci-5.1", 752 .data = &sdhci_am654_drvdata, 753 }, 754 { 755 .compatible = "ti,j721e-sdhci-8bit", 756 .data = &sdhci_j721e_8bit_drvdata, 757 }, 758 { 759 .compatible = "ti,j721e-sdhci-4bit", 760 .data = &sdhci_j721e_4bit_drvdata, 761 }, 762 { 763 .compatible = "ti,am64-sdhci-8bit", 764 .data = &sdhci_j721e_8bit_drvdata, 765 }, 766 { 767 .compatible = "ti,am64-sdhci-4bit", 768 .data = &sdhci_j721e_4bit_drvdata, 769 }, 770 { /* sentinel */ } 771 }; 772 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 773 774 static int sdhci_am654_probe(struct platform_device *pdev) 775 { 776 const struct sdhci_am654_driver_data *drvdata; 777 const struct soc_device_attribute *soc; 778 struct sdhci_pltfm_host *pltfm_host; 779 struct sdhci_am654_data *sdhci_am654; 780 const struct of_device_id *match; 781 struct sdhci_host *host; 782 struct clk *clk_xin; 783 struct device *dev = &pdev->dev; 784 void __iomem *base; 785 int ret; 786 787 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 788 drvdata = match->data; 789 790 /* Update drvdata based on SoC revision */ 791 soc = soc_device_match(sdhci_am654_devices); 792 if (soc && soc->data) 793 drvdata = soc->data; 794 795 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 796 if (IS_ERR(host)) 797 return PTR_ERR(host); 798 799 pltfm_host = sdhci_priv(host); 800 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 801 sdhci_am654->flags = drvdata->flags; 802 803 clk_xin = devm_clk_get(dev, "clk_xin"); 804 if (IS_ERR(clk_xin)) { 805 dev_err(dev, "clk_xin clock not found.\n"); 806 ret = PTR_ERR(clk_xin); 807 goto err_pltfm_free; 808 } 809 810 pltfm_host->clk = clk_xin; 811 812 /* Clocks are enabled using pm_runtime */ 813 pm_runtime_enable(dev); 814 ret = pm_runtime_resume_and_get(dev); 815 if (ret) 816 goto pm_runtime_disable; 817 818 base = devm_platform_ioremap_resource(pdev, 1); 819 if (IS_ERR(base)) { 820 ret = PTR_ERR(base); 821 goto pm_runtime_put; 822 } 823 824 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 825 &sdhci_am654_regmap_config); 826 if (IS_ERR(sdhci_am654->base)) { 827 dev_err(dev, "Failed to initialize regmap\n"); 828 ret = PTR_ERR(sdhci_am654->base); 829 goto pm_runtime_put; 830 } 831 832 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 833 if (ret) 834 goto pm_runtime_put; 835 836 ret = mmc_of_parse(host->mmc); 837 if (ret) { 838 dev_err(dev, "parsing dt failed (%d)\n", ret); 839 goto pm_runtime_put; 840 } 841 842 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 843 844 ret = sdhci_am654_init(host); 845 if (ret) 846 goto pm_runtime_put; 847 848 return 0; 849 850 pm_runtime_put: 851 pm_runtime_put_sync(dev); 852 pm_runtime_disable: 853 pm_runtime_disable(dev); 854 err_pltfm_free: 855 sdhci_pltfm_free(pdev); 856 return ret; 857 } 858 859 static int sdhci_am654_remove(struct platform_device *pdev) 860 { 861 struct sdhci_host *host = platform_get_drvdata(pdev); 862 int ret; 863 864 sdhci_remove_host(host, true); 865 ret = pm_runtime_put_sync(&pdev->dev); 866 if (ret < 0) 867 return ret; 868 869 pm_runtime_disable(&pdev->dev); 870 sdhci_pltfm_free(pdev); 871 872 return 0; 873 } 874 875 static struct platform_driver sdhci_am654_driver = { 876 .driver = { 877 .name = "sdhci-am654", 878 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 879 .of_match_table = sdhci_am654_of_match, 880 }, 881 .probe = sdhci_am654_probe, 882 .remove = sdhci_am654_remove, 883 }; 884 885 module_platform_driver(sdhci_am654_driver); 886 887 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 888 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 889 MODULE_LICENSE("GPL"); 890