1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/module.h> 10 #include <linux/pm_runtime.h> 11 #include <linux/property.h> 12 #include <linux/regmap.h> 13 14 #include "sdhci-pltfm.h" 15 16 /* CTL_CFG Registers */ 17 #define CTL_CFG_2 0x14 18 19 #define SLOTTYPE_MASK GENMASK(31, 30) 20 #define SLOTTYPE_EMBEDDED BIT(30) 21 22 /* PHY Registers */ 23 #define PHY_CTRL1 0x100 24 #define PHY_CTRL2 0x104 25 #define PHY_CTRL3 0x108 26 #define PHY_CTRL4 0x10C 27 #define PHY_CTRL5 0x110 28 #define PHY_CTRL6 0x114 29 #define PHY_STAT1 0x130 30 #define PHY_STAT2 0x134 31 32 #define IOMUX_ENABLE_SHIFT 31 33 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 34 #define OTAPDLYENA_SHIFT 20 35 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 36 #define OTAPDLYSEL_SHIFT 12 37 #define OTAPDLYSEL_MASK GENMASK(15, 12) 38 #define STRBSEL_SHIFT 24 39 #define STRBSEL_MASK GENMASK(27, 24) 40 #define SEL50_SHIFT 8 41 #define SEL50_MASK BIT(SEL50_SHIFT) 42 #define SEL100_SHIFT 9 43 #define SEL100_MASK BIT(SEL100_SHIFT) 44 #define DLL_TRIM_ICP_SHIFT 4 45 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 46 #define DR_TY_SHIFT 20 47 #define DR_TY_MASK GENMASK(22, 20) 48 #define ENDLL_SHIFT 1 49 #define ENDLL_MASK BIT(ENDLL_SHIFT) 50 #define DLLRDY_SHIFT 0 51 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 52 #define PDB_SHIFT 0 53 #define PDB_MASK BIT(PDB_SHIFT) 54 #define CALDONE_SHIFT 1 55 #define CALDONE_MASK BIT(CALDONE_SHIFT) 56 #define RETRIM_SHIFT 17 57 #define RETRIM_MASK BIT(RETRIM_SHIFT) 58 59 #define DRIVER_STRENGTH_50_OHM 0x0 60 #define DRIVER_STRENGTH_33_OHM 0x1 61 #define DRIVER_STRENGTH_66_OHM 0x2 62 #define DRIVER_STRENGTH_100_OHM 0x3 63 #define DRIVER_STRENGTH_40_OHM 0x4 64 65 #define CLOCK_TOO_SLOW_HZ 400000 66 67 static struct regmap_config sdhci_am654_regmap_config = { 68 .reg_bits = 32, 69 .val_bits = 32, 70 .reg_stride = 4, 71 .fast_io = true, 72 }; 73 74 struct sdhci_am654_data { 75 struct regmap *base; 76 int otap_del_sel; 77 int trm_icp; 78 int drv_strength; 79 bool dll_on; 80 }; 81 82 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 83 { 84 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 85 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 86 int sel50, sel100; 87 u32 mask, val; 88 int ret; 89 90 if (sdhci_am654->dll_on) { 91 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 92 93 sdhci_am654->dll_on = false; 94 } 95 96 sdhci_set_clock(host, clock); 97 98 if (clock > CLOCK_TOO_SLOW_HZ) { 99 /* Setup DLL Output TAP delay */ 100 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 101 val = (1 << OTAPDLYENA_SHIFT) | 102 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 103 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 104 switch (clock) { 105 case 200000000: 106 sel50 = 0; 107 sel100 = 0; 108 break; 109 case 100000000: 110 sel50 = 0; 111 sel100 = 1; 112 break; 113 default: 114 sel50 = 1; 115 sel100 = 0; 116 } 117 118 /* Configure PHY DLL frequency */ 119 mask = SEL50_MASK | SEL100_MASK; 120 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 121 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 122 /* Configure DLL TRIM */ 123 mask = DLL_TRIM_ICP_MASK; 124 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 125 126 /* Configure DLL driver strength */ 127 mask |= DR_TY_MASK; 128 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 129 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 130 /* Enable DLL */ 131 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 132 0x1 << ENDLL_SHIFT); 133 /* 134 * Poll for DLL ready. Use a one second timeout. 135 * Works in all experiments done so far 136 */ 137 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 138 val, val & DLLRDY_MASK, 1000, 139 1000000); 140 if (ret) { 141 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 142 return; 143 } 144 145 sdhci_am654->dll_on = true; 146 } 147 } 148 149 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 150 unsigned short vdd) 151 { 152 if (!IS_ERR(host->mmc->supply.vmmc)) { 153 struct mmc_host *mmc = host->mmc; 154 155 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 156 } 157 sdhci_set_power_noreg(host, mode, vdd); 158 } 159 160 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 161 { 162 unsigned char timing = host->mmc->ios.timing; 163 164 if (reg == SDHCI_HOST_CONTROL) { 165 switch (timing) { 166 /* 167 * According to the data manual, HISPD bit 168 * should not be set in these speed modes. 169 */ 170 case MMC_TIMING_SD_HS: 171 case MMC_TIMING_MMC_HS: 172 case MMC_TIMING_UHS_SDR12: 173 case MMC_TIMING_UHS_SDR25: 174 val &= ~SDHCI_CTRL_HISPD; 175 } 176 } 177 178 writeb(val, host->ioaddr + reg); 179 } 180 181 static struct sdhci_ops sdhci_am654_ops = { 182 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 183 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 184 .set_uhs_signaling = sdhci_set_uhs_signaling, 185 .set_bus_width = sdhci_set_bus_width, 186 .set_power = sdhci_am654_set_power, 187 .set_clock = sdhci_am654_set_clock, 188 .write_b = sdhci_am654_write_b, 189 .reset = sdhci_reset, 190 }; 191 192 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 193 .ops = &sdhci_am654_ops, 194 .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 195 SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 196 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 197 }; 198 199 static int sdhci_am654_init(struct sdhci_host *host) 200 { 201 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 202 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 203 u32 ctl_cfg_2 = 0; 204 u32 mask; 205 u32 val; 206 int ret; 207 208 /* Reset OTAP to default value */ 209 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 210 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 211 212 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 213 if (~val & CALDONE_MASK) { 214 /* Calibrate IO lines */ 215 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 216 PDB_MASK, PDB_MASK); 217 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 218 val, val & CALDONE_MASK, 1, 20); 219 if (ret) 220 return ret; 221 } 222 223 /* Enable pins by setting IO mux to 0 */ 224 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0); 225 226 /* Set slot type based on SD or eMMC */ 227 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 228 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 229 230 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 231 ctl_cfg_2); 232 233 return sdhci_add_host(host); 234 } 235 236 static int sdhci_am654_get_of_property(struct platform_device *pdev, 237 struct sdhci_am654_data *sdhci_am654) 238 { 239 struct device *dev = &pdev->dev; 240 int drv_strength; 241 int ret; 242 243 ret = device_property_read_u32(dev, "ti,trm-icp", 244 &sdhci_am654->trm_icp); 245 if (ret) 246 return ret; 247 248 ret = device_property_read_u32(dev, "ti,otap-del-sel", 249 &sdhci_am654->otap_del_sel); 250 if (ret) 251 return ret; 252 253 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 254 &drv_strength); 255 if (ret) 256 return ret; 257 258 switch (drv_strength) { 259 case 50: 260 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 261 break; 262 case 33: 263 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 264 break; 265 case 66: 266 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 267 break; 268 case 100: 269 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 270 break; 271 case 40: 272 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 273 break; 274 default: 275 dev_err(dev, "Invalid driver strength\n"); 276 return -EINVAL; 277 } 278 279 sdhci_get_of_property(pdev); 280 281 return 0; 282 } 283 284 static int sdhci_am654_probe(struct platform_device *pdev) 285 { 286 struct sdhci_pltfm_host *pltfm_host; 287 struct sdhci_am654_data *sdhci_am654; 288 struct sdhci_host *host; 289 struct resource *res; 290 struct clk *clk_xin; 291 struct device *dev = &pdev->dev; 292 void __iomem *base; 293 int ret; 294 295 host = sdhci_pltfm_init(pdev, &sdhci_am654_pdata, sizeof(*sdhci_am654)); 296 if (IS_ERR(host)) 297 return PTR_ERR(host); 298 299 pltfm_host = sdhci_priv(host); 300 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 301 302 clk_xin = devm_clk_get(dev, "clk_xin"); 303 if (IS_ERR(clk_xin)) { 304 dev_err(dev, "clk_xin clock not found.\n"); 305 ret = PTR_ERR(clk_xin); 306 goto err_pltfm_free; 307 } 308 309 pltfm_host->clk = clk_xin; 310 311 /* Clocks are enabled using pm_runtime */ 312 pm_runtime_enable(dev); 313 ret = pm_runtime_get_sync(dev); 314 if (ret < 0) { 315 pm_runtime_put_noidle(dev); 316 goto pm_runtime_disable; 317 } 318 319 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 320 base = devm_ioremap_resource(dev, res); 321 if (IS_ERR(base)) { 322 ret = PTR_ERR(base); 323 goto pm_runtime_put; 324 } 325 326 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 327 &sdhci_am654_regmap_config); 328 if (IS_ERR(sdhci_am654->base)) { 329 dev_err(dev, "Failed to initialize regmap\n"); 330 ret = PTR_ERR(sdhci_am654->base); 331 goto pm_runtime_put; 332 } 333 334 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 335 if (ret) 336 goto pm_runtime_put; 337 338 ret = mmc_of_parse(host->mmc); 339 if (ret) { 340 dev_err(dev, "parsing dt failed (%d)\n", ret); 341 goto pm_runtime_put; 342 } 343 344 ret = sdhci_am654_init(host); 345 if (ret) 346 goto pm_runtime_put; 347 348 return 0; 349 350 pm_runtime_put: 351 pm_runtime_put_sync(dev); 352 pm_runtime_disable: 353 pm_runtime_disable(dev); 354 err_pltfm_free: 355 sdhci_pltfm_free(pdev); 356 return ret; 357 } 358 359 static int sdhci_am654_remove(struct platform_device *pdev) 360 { 361 struct sdhci_host *host = platform_get_drvdata(pdev); 362 int ret; 363 364 sdhci_remove_host(host, true); 365 ret = pm_runtime_put_sync(&pdev->dev); 366 if (ret < 0) 367 return ret; 368 369 pm_runtime_disable(&pdev->dev); 370 sdhci_pltfm_free(pdev); 371 372 return 0; 373 } 374 375 static const struct of_device_id sdhci_am654_of_match[] = { 376 { .compatible = "ti,am654-sdhci-5.1" }, 377 { /* sentinel */ } 378 }; 379 380 static struct platform_driver sdhci_am654_driver = { 381 .driver = { 382 .name = "sdhci-am654", 383 .of_match_table = sdhci_am654_of_match, 384 }, 385 .probe = sdhci_am654_probe, 386 .remove = sdhci_am654_remove, 387 }; 388 389 module_platform_driver(sdhci_am654_driver); 390 391 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 392 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 393 MODULE_LICENSE("GPL"); 394