1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-pltfm.h" 19 20 /* CTL_CFG Registers */ 21 #define CTL_CFG_2 0x14 22 23 #define SLOTTYPE_MASK GENMASK(31, 30) 24 #define SLOTTYPE_EMBEDDED BIT(30) 25 26 /* PHY Registers */ 27 #define PHY_CTRL1 0x100 28 #define PHY_CTRL2 0x104 29 #define PHY_CTRL3 0x108 30 #define PHY_CTRL4 0x10C 31 #define PHY_CTRL5 0x110 32 #define PHY_CTRL6 0x114 33 #define PHY_STAT1 0x130 34 #define PHY_STAT2 0x134 35 36 #define IOMUX_ENABLE_SHIFT 31 37 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 38 #define OTAPDLYENA_SHIFT 20 39 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 40 #define OTAPDLYSEL_SHIFT 12 41 #define OTAPDLYSEL_MASK GENMASK(15, 12) 42 #define STRBSEL_SHIFT 24 43 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 44 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 45 #define SEL50_SHIFT 8 46 #define SEL50_MASK BIT(SEL50_SHIFT) 47 #define SEL100_SHIFT 9 48 #define SEL100_MASK BIT(SEL100_SHIFT) 49 #define FREQSEL_SHIFT 8 50 #define FREQSEL_MASK GENMASK(10, 8) 51 #define CLKBUFSEL_SHIFT 0 52 #define CLKBUFSEL_MASK GENMASK(2, 0) 53 #define DLL_TRIM_ICP_SHIFT 4 54 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 55 #define DR_TY_SHIFT 20 56 #define DR_TY_MASK GENMASK(22, 20) 57 #define ENDLL_SHIFT 1 58 #define ENDLL_MASK BIT(ENDLL_SHIFT) 59 #define DLLRDY_SHIFT 0 60 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 61 #define PDB_SHIFT 0 62 #define PDB_MASK BIT(PDB_SHIFT) 63 #define CALDONE_SHIFT 1 64 #define CALDONE_MASK BIT(CALDONE_SHIFT) 65 #define RETRIM_SHIFT 17 66 #define RETRIM_MASK BIT(RETRIM_SHIFT) 67 #define SELDLYTXCLK_SHIFT 17 68 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 69 70 #define DRIVER_STRENGTH_50_OHM 0x0 71 #define DRIVER_STRENGTH_33_OHM 0x1 72 #define DRIVER_STRENGTH_66_OHM 0x2 73 #define DRIVER_STRENGTH_100_OHM 0x3 74 #define DRIVER_STRENGTH_40_OHM 0x4 75 76 #define CLOCK_TOO_SLOW_HZ 400000 77 78 /* Command Queue Host Controller Interface Base address */ 79 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 80 81 static struct regmap_config sdhci_am654_regmap_config = { 82 .reg_bits = 32, 83 .val_bits = 32, 84 .reg_stride = 4, 85 .fast_io = true, 86 }; 87 88 struct sdhci_am654_data { 89 struct regmap *base; 90 bool legacy_otapdly; 91 int otap_del_sel[11]; 92 int clkbuf_sel; 93 int trm_icp; 94 int drv_strength; 95 bool dll_on; 96 int strb_sel; 97 u32 flags; 98 }; 99 100 struct sdhci_am654_driver_data { 101 const struct sdhci_pltfm_data *pdata; 102 u32 flags; 103 #define IOMUX_PRESENT (1 << 0) 104 #define FREQSEL_2_BIT (1 << 1) 105 #define STRBSEL_4_BIT (1 << 2) 106 #define DLL_PRESENT (1 << 3) 107 #define DLL_CALIB (1 << 4) 108 }; 109 110 struct timing_data { 111 const char *binding; 112 u32 capability; 113 }; 114 115 static const struct timing_data td[] = { 116 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0}, 117 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED}, 118 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED}, 119 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12}, 120 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25}, 121 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50}, 122 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 123 MMC_CAP_UHS_SDR104}, 124 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50}, 125 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR}, 126 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200}, 127 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400}, 128 }; 129 130 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 131 { 132 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 133 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 134 int sel50, sel100, freqsel; 135 u32 mask, val; 136 int ret; 137 138 if (sdhci_am654->flags & FREQSEL_2_BIT) { 139 switch (clock) { 140 case 200000000: 141 sel50 = 0; 142 sel100 = 0; 143 break; 144 case 100000000: 145 sel50 = 0; 146 sel100 = 1; 147 break; 148 default: 149 sel50 = 1; 150 sel100 = 0; 151 } 152 153 /* Configure PHY DLL frequency */ 154 mask = SEL50_MASK | SEL100_MASK; 155 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 156 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 157 158 } else { 159 switch (clock) { 160 case 200000000: 161 freqsel = 0x0; 162 break; 163 default: 164 freqsel = 0x4; 165 } 166 167 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 168 freqsel << FREQSEL_SHIFT); 169 } 170 /* Configure DLL TRIM */ 171 mask = DLL_TRIM_ICP_MASK; 172 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 173 174 /* Configure DLL driver strength */ 175 mask |= DR_TY_MASK; 176 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 177 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 178 179 /* Enable DLL */ 180 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 181 0x1 << ENDLL_SHIFT); 182 /* 183 * Poll for DLL ready. Use a one second timeout. 184 * Works in all experiments done so far 185 */ 186 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 187 val & DLLRDY_MASK, 1000, 1000000); 188 if (ret) { 189 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 190 return; 191 } 192 193 sdhci_am654->dll_on = true; 194 } 195 196 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 197 { 198 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 199 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 200 unsigned char timing = host->mmc->ios.timing; 201 u32 otap_del_sel; 202 u32 otap_del_ena; 203 u32 mask, val; 204 205 if (sdhci_am654->dll_on) { 206 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 207 208 sdhci_am654->dll_on = false; 209 } 210 211 sdhci_set_clock(host, clock); 212 213 /* Setup DLL Output TAP delay */ 214 if (sdhci_am654->legacy_otapdly) 215 otap_del_sel = sdhci_am654->otap_del_sel[0]; 216 else 217 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 218 219 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 220 221 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 222 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 223 (otap_del_sel << OTAPDLYSEL_SHIFT); 224 225 /* Write to STRBSEL for HS400 speed mode */ 226 if (timing == MMC_TIMING_MMC_HS400) { 227 if (sdhci_am654->flags & STRBSEL_4_BIT) 228 mask |= STRBSEL_4BIT_MASK; 229 else 230 mask |= STRBSEL_8BIT_MASK; 231 232 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 233 } 234 235 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 236 237 if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) { 238 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 239 SELDLYTXCLK_MASK, 0); 240 sdhci_am654_setup_dll(host, clock); 241 } else { 242 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 243 SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT); 244 } 245 246 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 247 sdhci_am654->clkbuf_sel); 248 } 249 250 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 251 unsigned int clock) 252 { 253 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 254 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 255 unsigned char timing = host->mmc->ios.timing; 256 u32 otap_del_sel; 257 u32 mask, val; 258 259 /* Setup DLL Output TAP delay */ 260 if (sdhci_am654->legacy_otapdly) 261 otap_del_sel = sdhci_am654->otap_del_sel[0]; 262 else 263 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 264 265 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 266 val = (0x1 << OTAPDLYENA_SHIFT) | 267 (otap_del_sel << OTAPDLYSEL_SHIFT); 268 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 269 270 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 271 sdhci_am654->clkbuf_sel); 272 273 sdhci_set_clock(host, clock); 274 } 275 276 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 277 { 278 writeb(val, host->ioaddr + reg); 279 usleep_range(1000, 10000); 280 return readb(host->ioaddr + reg); 281 } 282 283 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 284 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 285 { 286 unsigned char timing = host->mmc->ios.timing; 287 u8 pwr; 288 int ret; 289 290 if (reg == SDHCI_HOST_CONTROL) { 291 switch (timing) { 292 /* 293 * According to the data manual, HISPD bit 294 * should not be set in these speed modes. 295 */ 296 case MMC_TIMING_SD_HS: 297 case MMC_TIMING_MMC_HS: 298 case MMC_TIMING_UHS_SDR12: 299 case MMC_TIMING_UHS_SDR25: 300 val &= ~SDHCI_CTRL_HISPD; 301 } 302 } 303 304 writeb(val, host->ioaddr + reg); 305 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 306 /* 307 * Power on will not happen until the card detect debounce 308 * timer expires. Wait at least 1.5 seconds for the power on 309 * bit to be set 310 */ 311 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 312 pwr & SDHCI_POWER_ON, 0, 313 MAX_POWER_ON_TIMEOUT, false, host, val, 314 reg); 315 if (ret) 316 dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 317 } 318 } 319 320 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 321 { 322 struct sdhci_host *host = mmc_priv(mmc); 323 int err = sdhci_execute_tuning(mmc, opcode); 324 325 if (err) 326 return err; 327 /* 328 * Tuning data remains in the buffer after tuning. 329 * Do a command and data reset to get rid of it 330 */ 331 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 332 333 return 0; 334 } 335 336 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 337 { 338 int cmd_error = 0; 339 int data_error = 0; 340 341 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 342 return intmask; 343 344 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 345 346 return 0; 347 } 348 349 static struct sdhci_ops sdhci_am654_ops = { 350 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 351 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 352 .set_uhs_signaling = sdhci_set_uhs_signaling, 353 .set_bus_width = sdhci_set_bus_width, 354 .set_power = sdhci_set_power_and_bus_voltage, 355 .set_clock = sdhci_am654_set_clock, 356 .write_b = sdhci_am654_write_b, 357 .irq = sdhci_am654_cqhci_irq, 358 .reset = sdhci_reset, 359 }; 360 361 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 362 .ops = &sdhci_am654_ops, 363 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 364 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 365 }; 366 367 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 368 .pdata = &sdhci_am654_pdata, 369 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 370 DLL_CALIB, 371 }; 372 373 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 374 .pdata = &sdhci_am654_pdata, 375 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 376 }; 377 378 static struct sdhci_ops sdhci_j721e_8bit_ops = { 379 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 380 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 381 .set_uhs_signaling = sdhci_set_uhs_signaling, 382 .set_bus_width = sdhci_set_bus_width, 383 .set_power = sdhci_set_power_and_bus_voltage, 384 .set_clock = sdhci_am654_set_clock, 385 .write_b = sdhci_am654_write_b, 386 .irq = sdhci_am654_cqhci_irq, 387 .reset = sdhci_reset, 388 }; 389 390 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 391 .ops = &sdhci_j721e_8bit_ops, 392 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 393 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 394 }; 395 396 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 397 .pdata = &sdhci_j721e_8bit_pdata, 398 .flags = DLL_PRESENT | DLL_CALIB, 399 }; 400 401 static struct sdhci_ops sdhci_j721e_4bit_ops = { 402 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 403 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 404 .set_uhs_signaling = sdhci_set_uhs_signaling, 405 .set_bus_width = sdhci_set_bus_width, 406 .set_power = sdhci_set_power_and_bus_voltage, 407 .set_clock = sdhci_j721e_4bit_set_clock, 408 .write_b = sdhci_am654_write_b, 409 .irq = sdhci_am654_cqhci_irq, 410 .reset = sdhci_reset, 411 }; 412 413 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 414 .ops = &sdhci_j721e_4bit_ops, 415 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 416 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 417 }; 418 419 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 420 .pdata = &sdhci_j721e_4bit_pdata, 421 .flags = IOMUX_PRESENT, 422 }; 423 424 static const struct soc_device_attribute sdhci_am654_devices[] = { 425 { .family = "AM65X", 426 .revision = "SR1.0", 427 .data = &sdhci_am654_sr1_drvdata 428 }, 429 {/* sentinel */} 430 }; 431 432 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 433 { 434 sdhci_dumpregs(mmc_priv(mmc)); 435 } 436 437 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 438 .enable = sdhci_cqe_enable, 439 .disable = sdhci_cqe_disable, 440 .dumpregs = sdhci_am654_dumpregs, 441 }; 442 443 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 444 { 445 struct cqhci_host *cq_host; 446 int ret; 447 448 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 449 GFP_KERNEL); 450 if (!cq_host) 451 return -ENOMEM; 452 453 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 454 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 455 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 456 cq_host->ops = &sdhci_am654_cqhci_ops; 457 458 host->mmc->caps2 |= MMC_CAP2_CQE; 459 460 ret = cqhci_init(cq_host, host->mmc, 1); 461 462 return ret; 463 } 464 465 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 466 struct sdhci_am654_data *sdhci_am654) 467 { 468 struct device *dev = mmc_dev(host->mmc); 469 int i; 470 int ret; 471 472 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding, 473 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 474 if (ret) { 475 /* 476 * ti,otap-del-sel-legacy is mandatory, look for old binding 477 * if not found. 478 */ 479 ret = device_property_read_u32(dev, "ti,otap-del-sel", 480 &sdhci_am654->otap_del_sel[0]); 481 if (ret) { 482 dev_err(dev, "Couldn't find otap-del-sel\n"); 483 484 return ret; 485 } 486 487 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 488 sdhci_am654->legacy_otapdly = true; 489 490 return 0; 491 } 492 493 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 494 495 ret = device_property_read_u32(dev, td[i].binding, 496 &sdhci_am654->otap_del_sel[i]); 497 if (ret) { 498 dev_dbg(dev, "Couldn't find %s\n", 499 td[i].binding); 500 /* 501 * Remove the corresponding capability 502 * if an otap-del-sel value is not found 503 */ 504 if (i <= MMC_TIMING_MMC_DDR52) 505 host->mmc->caps &= ~td[i].capability; 506 else 507 host->mmc->caps2 &= ~td[i].capability; 508 } 509 } 510 511 return 0; 512 } 513 514 static int sdhci_am654_init(struct sdhci_host *host) 515 { 516 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 517 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 518 u32 ctl_cfg_2 = 0; 519 u32 mask; 520 u32 val; 521 int ret; 522 523 /* Reset OTAP to default value */ 524 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 525 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 526 527 if (sdhci_am654->flags & DLL_CALIB) { 528 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 529 if (~val & CALDONE_MASK) { 530 /* Calibrate IO lines */ 531 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 532 PDB_MASK, PDB_MASK); 533 ret = regmap_read_poll_timeout(sdhci_am654->base, 534 PHY_STAT1, val, 535 val & CALDONE_MASK, 536 1, 20); 537 if (ret) 538 return ret; 539 } 540 } 541 542 /* Enable pins by setting IO mux to 0 */ 543 if (sdhci_am654->flags & IOMUX_PRESENT) 544 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 545 IOMUX_ENABLE_MASK, 0); 546 547 /* Set slot type based on SD or eMMC */ 548 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 549 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 550 551 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 552 ctl_cfg_2); 553 554 ret = sdhci_setup_host(host); 555 if (ret) 556 return ret; 557 558 ret = sdhci_am654_cqe_add_host(host); 559 if (ret) 560 goto err_cleanup_host; 561 562 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 563 if (ret) 564 goto err_cleanup_host; 565 566 ret = __sdhci_add_host(host); 567 if (ret) 568 goto err_cleanup_host; 569 570 return 0; 571 572 err_cleanup_host: 573 sdhci_cleanup_host(host); 574 return ret; 575 } 576 577 static int sdhci_am654_get_of_property(struct platform_device *pdev, 578 struct sdhci_am654_data *sdhci_am654) 579 { 580 struct device *dev = &pdev->dev; 581 int drv_strength; 582 int ret; 583 584 if (sdhci_am654->flags & DLL_PRESENT) { 585 ret = device_property_read_u32(dev, "ti,trm-icp", 586 &sdhci_am654->trm_icp); 587 if (ret) 588 return ret; 589 590 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 591 &drv_strength); 592 if (ret) 593 return ret; 594 595 switch (drv_strength) { 596 case 50: 597 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 598 break; 599 case 33: 600 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 601 break; 602 case 66: 603 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 604 break; 605 case 100: 606 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 607 break; 608 case 40: 609 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 610 break; 611 default: 612 dev_err(dev, "Invalid driver strength\n"); 613 return -EINVAL; 614 } 615 } 616 617 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 618 device_property_read_u32(dev, "ti,clkbuf-sel", 619 &sdhci_am654->clkbuf_sel); 620 621 sdhci_get_of_property(pdev); 622 623 return 0; 624 } 625 626 static const struct of_device_id sdhci_am654_of_match[] = { 627 { 628 .compatible = "ti,am654-sdhci-5.1", 629 .data = &sdhci_am654_drvdata, 630 }, 631 { 632 .compatible = "ti,j721e-sdhci-8bit", 633 .data = &sdhci_j721e_8bit_drvdata, 634 }, 635 { 636 .compatible = "ti,j721e-sdhci-4bit", 637 .data = &sdhci_j721e_4bit_drvdata, 638 }, 639 { /* sentinel */ } 640 }; 641 642 static int sdhci_am654_probe(struct platform_device *pdev) 643 { 644 const struct sdhci_am654_driver_data *drvdata; 645 const struct soc_device_attribute *soc; 646 struct sdhci_pltfm_host *pltfm_host; 647 struct sdhci_am654_data *sdhci_am654; 648 const struct of_device_id *match; 649 struct sdhci_host *host; 650 struct clk *clk_xin; 651 struct device *dev = &pdev->dev; 652 void __iomem *base; 653 int ret; 654 655 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 656 drvdata = match->data; 657 658 /* Update drvdata based on SoC revision */ 659 soc = soc_device_match(sdhci_am654_devices); 660 if (soc && soc->data) 661 drvdata = soc->data; 662 663 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 664 if (IS_ERR(host)) 665 return PTR_ERR(host); 666 667 pltfm_host = sdhci_priv(host); 668 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 669 sdhci_am654->flags = drvdata->flags; 670 671 clk_xin = devm_clk_get(dev, "clk_xin"); 672 if (IS_ERR(clk_xin)) { 673 dev_err(dev, "clk_xin clock not found.\n"); 674 ret = PTR_ERR(clk_xin); 675 goto err_pltfm_free; 676 } 677 678 pltfm_host->clk = clk_xin; 679 680 /* Clocks are enabled using pm_runtime */ 681 pm_runtime_enable(dev); 682 ret = pm_runtime_get_sync(dev); 683 if (ret < 0) { 684 pm_runtime_put_noidle(dev); 685 goto pm_runtime_disable; 686 } 687 688 base = devm_platform_ioremap_resource(pdev, 1); 689 if (IS_ERR(base)) { 690 ret = PTR_ERR(base); 691 goto pm_runtime_put; 692 } 693 694 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 695 &sdhci_am654_regmap_config); 696 if (IS_ERR(sdhci_am654->base)) { 697 dev_err(dev, "Failed to initialize regmap\n"); 698 ret = PTR_ERR(sdhci_am654->base); 699 goto pm_runtime_put; 700 } 701 702 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 703 if (ret) 704 goto pm_runtime_put; 705 706 ret = mmc_of_parse(host->mmc); 707 if (ret) { 708 dev_err(dev, "parsing dt failed (%d)\n", ret); 709 goto pm_runtime_put; 710 } 711 712 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 713 714 ret = sdhci_am654_init(host); 715 if (ret) 716 goto pm_runtime_put; 717 718 return 0; 719 720 pm_runtime_put: 721 pm_runtime_put_sync(dev); 722 pm_runtime_disable: 723 pm_runtime_disable(dev); 724 err_pltfm_free: 725 sdhci_pltfm_free(pdev); 726 return ret; 727 } 728 729 static int sdhci_am654_remove(struct platform_device *pdev) 730 { 731 struct sdhci_host *host = platform_get_drvdata(pdev); 732 int ret; 733 734 sdhci_remove_host(host, true); 735 ret = pm_runtime_put_sync(&pdev->dev); 736 if (ret < 0) 737 return ret; 738 739 pm_runtime_disable(&pdev->dev); 740 sdhci_pltfm_free(pdev); 741 742 return 0; 743 } 744 745 static struct platform_driver sdhci_am654_driver = { 746 .driver = { 747 .name = "sdhci-am654", 748 .of_match_table = sdhci_am654_of_match, 749 }, 750 .probe = sdhci_am654_probe, 751 .remove = sdhci_am654_remove, 752 }; 753 754 module_platform_driver(sdhci_am654_driver); 755 756 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 757 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 758 MODULE_LICENSE("GPL"); 759