1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 20 21 /* CTL_CFG Registers */ 22 #define CTL_CFG_2 0x14 23 #define CTL_CFG_3 0x18 24 25 #define SLOTTYPE_MASK GENMASK(31, 30) 26 #define SLOTTYPE_EMBEDDED BIT(30) 27 #define TUNINGFORSDR50_MASK BIT(13) 28 29 /* PHY Registers */ 30 #define PHY_CTRL1 0x100 31 #define PHY_CTRL2 0x104 32 #define PHY_CTRL3 0x108 33 #define PHY_CTRL4 0x10C 34 #define PHY_CTRL5 0x110 35 #define PHY_CTRL6 0x114 36 #define PHY_STAT1 0x130 37 #define PHY_STAT2 0x134 38 39 #define IOMUX_ENABLE_SHIFT 31 40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 41 #define OTAPDLYENA_SHIFT 20 42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 43 #define OTAPDLYSEL_SHIFT 12 44 #define OTAPDLYSEL_MASK GENMASK(15, 12) 45 #define STRBSEL_SHIFT 24 46 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 47 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 48 #define SEL50_SHIFT 8 49 #define SEL50_MASK BIT(SEL50_SHIFT) 50 #define SEL100_SHIFT 9 51 #define SEL100_MASK BIT(SEL100_SHIFT) 52 #define FREQSEL_SHIFT 8 53 #define FREQSEL_MASK GENMASK(10, 8) 54 #define CLKBUFSEL_SHIFT 0 55 #define CLKBUFSEL_MASK GENMASK(2, 0) 56 #define DLL_TRIM_ICP_SHIFT 4 57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 58 #define DR_TY_SHIFT 20 59 #define DR_TY_MASK GENMASK(22, 20) 60 #define ENDLL_SHIFT 1 61 #define ENDLL_MASK BIT(ENDLL_SHIFT) 62 #define DLLRDY_SHIFT 0 63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 64 #define PDB_SHIFT 0 65 #define PDB_MASK BIT(PDB_SHIFT) 66 #define CALDONE_SHIFT 1 67 #define CALDONE_MASK BIT(CALDONE_SHIFT) 68 #define RETRIM_SHIFT 17 69 #define RETRIM_MASK BIT(RETRIM_SHIFT) 70 #define SELDLYTXCLK_SHIFT 17 71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72 #define SELDLYRXCLK_SHIFT 16 73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74 #define ITAPDLYSEL_SHIFT 0 75 #define ITAPDLYSEL_MASK GENMASK(4, 0) 76 #define ITAPDLYENA_SHIFT 8 77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78 #define ITAPCHGWIN_SHIFT 9 79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 80 81 #define DRIVER_STRENGTH_50_OHM 0x0 82 #define DRIVER_STRENGTH_33_OHM 0x1 83 #define DRIVER_STRENGTH_66_OHM 0x2 84 #define DRIVER_STRENGTH_100_OHM 0x3 85 #define DRIVER_STRENGTH_40_OHM 0x4 86 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 89 90 /* Command Queue Host Controller Interface Base address */ 91 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92 93 static struct regmap_config sdhci_am654_regmap_config = { 94 .reg_bits = 32, 95 .val_bits = 32, 96 .reg_stride = 4, 97 .fast_io = true, 98 }; 99 100 struct timing_data { 101 const char *otap_binding; 102 const char *itap_binding; 103 u32 capability; 104 }; 105 106 static const struct timing_data td[] = { 107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108 "ti,itap-del-sel-legacy", 109 0}, 110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111 "ti,itap-del-sel-mmc-hs", 112 MMC_CAP_MMC_HIGHSPEED}, 113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114 "ti,itap-del-sel-sd-hs", 115 MMC_CAP_SD_HIGHSPEED}, 116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117 "ti,itap-del-sel-sdr12", 118 MMC_CAP_UHS_SDR12}, 119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120 "ti,itap-del-sel-sdr25", 121 MMC_CAP_UHS_SDR25}, 122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123 NULL, 124 MMC_CAP_UHS_SDR50}, 125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126 NULL, 127 MMC_CAP_UHS_SDR104}, 128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129 NULL, 130 MMC_CAP_UHS_DDR50}, 131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132 "ti,itap-del-sel-ddr52", 133 MMC_CAP_DDR}, 134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135 NULL, 136 MMC_CAP2_HS200}, 137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138 NULL, 139 MMC_CAP2_HS400}, 140 }; 141 142 struct sdhci_am654_data { 143 struct regmap *base; 144 bool legacy_otapdly; 145 int otap_del_sel[ARRAY_SIZE(td)]; 146 int itap_del_sel[ARRAY_SIZE(td)]; 147 int clkbuf_sel; 148 int trm_icp; 149 int drv_strength; 150 int strb_sel; 151 u32 flags; 152 u32 quirks; 153 bool dll_enable; 154 155 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 156 }; 157 158 struct window { 159 u8 start; 160 u8 end; 161 u8 length; 162 }; 163 164 struct sdhci_am654_driver_data { 165 const struct sdhci_pltfm_data *pdata; 166 u32 flags; 167 #define IOMUX_PRESENT (1 << 0) 168 #define FREQSEL_2_BIT (1 << 1) 169 #define STRBSEL_4_BIT (1 << 2) 170 #define DLL_PRESENT (1 << 3) 171 #define DLL_CALIB (1 << 4) 172 }; 173 174 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 175 { 176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 178 int sel50, sel100, freqsel; 179 u32 mask, val; 180 int ret; 181 182 /* Disable delay chain mode */ 183 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 184 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 185 186 if (sdhci_am654->flags & FREQSEL_2_BIT) { 187 switch (clock) { 188 case 200000000: 189 sel50 = 0; 190 sel100 = 0; 191 break; 192 case 100000000: 193 sel50 = 0; 194 sel100 = 1; 195 break; 196 default: 197 sel50 = 1; 198 sel100 = 0; 199 } 200 201 /* Configure PHY DLL frequency */ 202 mask = SEL50_MASK | SEL100_MASK; 203 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 204 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 205 206 } else { 207 switch (clock) { 208 case 200000000: 209 freqsel = 0x0; 210 break; 211 default: 212 freqsel = 0x4; 213 } 214 215 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 216 freqsel << FREQSEL_SHIFT); 217 } 218 /* Configure DLL TRIM */ 219 mask = DLL_TRIM_ICP_MASK; 220 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 221 222 /* Configure DLL driver strength */ 223 mask |= DR_TY_MASK; 224 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 225 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 226 227 /* Enable DLL */ 228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 229 0x1 << ENDLL_SHIFT); 230 /* 231 * Poll for DLL ready. Use a one second timeout. 232 * Works in all experiments done so far 233 */ 234 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 235 val & DLLRDY_MASK, 1000, 1000000); 236 if (ret) { 237 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 238 return; 239 } 240 } 241 242 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 243 u32 itapdly) 244 { 245 /* Set ITAPCHGWIN before writing to ITAPDLY */ 246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 247 1 << ITAPCHGWIN_SHIFT); 248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 249 itapdly << ITAPDLYSEL_SHIFT); 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 251 } 252 253 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 254 unsigned char timing) 255 { 256 u32 mask, val; 257 258 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 259 260 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 261 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 262 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 263 264 sdhci_am654_write_itapdly(sdhci_am654, 265 sdhci_am654->itap_del_sel[timing]); 266 } 267 268 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 269 { 270 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 271 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 272 unsigned char timing = host->mmc->ios.timing; 273 u32 otap_del_sel; 274 u32 otap_del_ena; 275 u32 mask, val; 276 277 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 278 279 sdhci_set_clock(host, clock); 280 281 /* Setup DLL Output TAP delay */ 282 if (sdhci_am654->legacy_otapdly) 283 otap_del_sel = sdhci_am654->otap_del_sel[0]; 284 else 285 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 286 287 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 288 289 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 290 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 291 (otap_del_sel << OTAPDLYSEL_SHIFT); 292 293 /* Write to STRBSEL for HS400 speed mode */ 294 if (timing == MMC_TIMING_MMC_HS400) { 295 if (sdhci_am654->flags & STRBSEL_4_BIT) 296 mask |= STRBSEL_4BIT_MASK; 297 else 298 mask |= STRBSEL_8BIT_MASK; 299 300 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 301 } 302 303 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 304 305 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 306 sdhci_am654_setup_dll(host, clock); 307 sdhci_am654->dll_enable = true; 308 } else { 309 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 310 sdhci_am654->dll_enable = false; 311 } 312 313 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 314 sdhci_am654->clkbuf_sel); 315 } 316 317 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 318 unsigned int clock) 319 { 320 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 321 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 322 unsigned char timing = host->mmc->ios.timing; 323 u32 otap_del_sel; 324 u32 mask, val; 325 326 /* Setup DLL Output TAP delay */ 327 if (sdhci_am654->legacy_otapdly) 328 otap_del_sel = sdhci_am654->otap_del_sel[0]; 329 else 330 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 331 332 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 333 val = (0x1 << OTAPDLYENA_SHIFT) | 334 (otap_del_sel << OTAPDLYSEL_SHIFT); 335 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 336 337 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 338 sdhci_am654->clkbuf_sel); 339 340 sdhci_set_clock(host, clock); 341 } 342 343 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 344 { 345 writeb(val, host->ioaddr + reg); 346 usleep_range(1000, 10000); 347 return readb(host->ioaddr + reg); 348 } 349 350 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 351 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 352 { 353 unsigned char timing = host->mmc->ios.timing; 354 u8 pwr; 355 int ret; 356 357 if (reg == SDHCI_HOST_CONTROL) { 358 switch (timing) { 359 /* 360 * According to the data manual, HISPD bit 361 * should not be set in these speed modes. 362 */ 363 case MMC_TIMING_SD_HS: 364 case MMC_TIMING_MMC_HS: 365 val &= ~SDHCI_CTRL_HISPD; 366 } 367 } 368 369 writeb(val, host->ioaddr + reg); 370 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 371 /* 372 * Power on will not happen until the card detect debounce 373 * timer expires. Wait at least 1.5 seconds for the power on 374 * bit to be set 375 */ 376 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 377 pwr & SDHCI_POWER_ON, 0, 378 MAX_POWER_ON_TIMEOUT, false, host, val, 379 reg); 380 if (ret) 381 dev_info(mmc_dev(host->mmc), "Power on failed\n"); 382 } 383 } 384 385 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 386 { 387 u8 ctrl; 388 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 389 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 390 391 sdhci_and_cqhci_reset(host, mask); 392 393 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 394 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 395 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 396 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 397 } 398 } 399 400 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 401 { 402 struct sdhci_host *host = mmc_priv(mmc); 403 int err = sdhci_execute_tuning(mmc, opcode); 404 405 if (err) 406 return err; 407 /* 408 * Tuning data remains in the buffer after tuning. 409 * Do a command and data reset to get rid of it 410 */ 411 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 412 413 return 0; 414 } 415 416 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 417 { 418 int cmd_error = 0; 419 int data_error = 0; 420 421 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 422 return intmask; 423 424 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 425 426 return 0; 427 } 428 429 #define ITAPDLY_LENGTH 32 430 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 431 432 static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 433 *fail_window, u8 num_fails, bool circular_buffer) 434 { 435 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 436 u8 first_fail_start = 0, last_fail_end = 0; 437 struct device *dev = mmc_dev(host->mmc); 438 struct window pass_window = {0, 0, 0}; 439 int prev_fail_end = -1; 440 u8 i; 441 442 if (!num_fails) 443 return ITAPDLY_LAST_INDEX >> 1; 444 445 if (fail_window->length == ITAPDLY_LENGTH) { 446 dev_err(dev, "No passing ITAPDLY, return 0\n"); 447 return 0; 448 } 449 450 first_fail_start = fail_window->start; 451 last_fail_end = fail_window[num_fails - 1].end; 452 453 for (i = 0; i < num_fails; i++) { 454 start_fail = fail_window[i].start; 455 end_fail = fail_window[i].end; 456 pass_length = start_fail - (prev_fail_end + 1); 457 458 if (pass_length > pass_window.length) { 459 pass_window.start = prev_fail_end + 1; 460 pass_window.length = pass_length; 461 } 462 prev_fail_end = end_fail; 463 } 464 465 if (!circular_buffer) 466 pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 467 else 468 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 469 470 if (pass_length > pass_window.length) { 471 pass_window.start = last_fail_end + 1; 472 pass_window.length = pass_length; 473 } 474 475 if (!circular_buffer) 476 itap = pass_window.start + (pass_window.length >> 1); 477 else 478 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 479 480 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 481 } 482 483 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 484 u32 opcode) 485 { 486 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 487 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 488 struct window fail_window[ITAPDLY_LENGTH]; 489 u8 curr_pass, itap; 490 u8 fail_index = 0; 491 u8 prev_pass = 1; 492 493 memset(fail_window, 0, sizeof(fail_window)); 494 495 /* Enable ITAPDLY */ 496 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 497 1 << ITAPDLYENA_SHIFT); 498 499 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 500 sdhci_am654_write_itapdly(sdhci_am654, itap); 501 502 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 503 504 if (!curr_pass && prev_pass) 505 fail_window[fail_index].start = itap; 506 507 if (!curr_pass) { 508 fail_window[fail_index].end = itap; 509 fail_window[fail_index].length++; 510 } 511 512 if (curr_pass && !prev_pass) 513 fail_index++; 514 515 prev_pass = curr_pass; 516 } 517 518 if (fail_window[fail_index].length != 0) 519 fail_index++; 520 521 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 522 sdhci_am654->dll_enable); 523 524 sdhci_am654_write_itapdly(sdhci_am654, itap); 525 526 return 0; 527 } 528 529 static struct sdhci_ops sdhci_am654_ops = { 530 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 531 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 532 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 533 .set_uhs_signaling = sdhci_set_uhs_signaling, 534 .set_bus_width = sdhci_set_bus_width, 535 .set_power = sdhci_set_power_and_bus_voltage, 536 .set_clock = sdhci_am654_set_clock, 537 .write_b = sdhci_am654_write_b, 538 .irq = sdhci_am654_cqhci_irq, 539 .reset = sdhci_and_cqhci_reset, 540 }; 541 542 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 543 .ops = &sdhci_am654_ops, 544 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 545 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 546 }; 547 548 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 549 .pdata = &sdhci_am654_pdata, 550 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 551 DLL_CALIB, 552 }; 553 554 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 555 .pdata = &sdhci_am654_pdata, 556 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 557 }; 558 559 static struct sdhci_ops sdhci_j721e_8bit_ops = { 560 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 561 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 562 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 563 .set_uhs_signaling = sdhci_set_uhs_signaling, 564 .set_bus_width = sdhci_set_bus_width, 565 .set_power = sdhci_set_power_and_bus_voltage, 566 .set_clock = sdhci_am654_set_clock, 567 .write_b = sdhci_am654_write_b, 568 .irq = sdhci_am654_cqhci_irq, 569 .reset = sdhci_and_cqhci_reset, 570 }; 571 572 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 573 .ops = &sdhci_j721e_8bit_ops, 574 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 575 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 576 }; 577 578 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 579 .pdata = &sdhci_j721e_8bit_pdata, 580 .flags = DLL_PRESENT | DLL_CALIB, 581 }; 582 583 static struct sdhci_ops sdhci_j721e_4bit_ops = { 584 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 585 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 586 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 587 .set_uhs_signaling = sdhci_set_uhs_signaling, 588 .set_bus_width = sdhci_set_bus_width, 589 .set_power = sdhci_set_power_and_bus_voltage, 590 .set_clock = sdhci_j721e_4bit_set_clock, 591 .write_b = sdhci_am654_write_b, 592 .irq = sdhci_am654_cqhci_irq, 593 .reset = sdhci_am654_reset, 594 }; 595 596 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 597 .ops = &sdhci_j721e_4bit_ops, 598 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 599 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 600 }; 601 602 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 603 .pdata = &sdhci_j721e_4bit_pdata, 604 .flags = IOMUX_PRESENT, 605 }; 606 607 static const struct soc_device_attribute sdhci_am654_devices[] = { 608 { .family = "AM65X", 609 .revision = "SR1.0", 610 .data = &sdhci_am654_sr1_drvdata 611 }, 612 {/* sentinel */} 613 }; 614 615 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 616 { 617 sdhci_dumpregs(mmc_priv(mmc)); 618 } 619 620 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 621 .enable = sdhci_cqe_enable, 622 .disable = sdhci_cqe_disable, 623 .dumpregs = sdhci_am654_dumpregs, 624 }; 625 626 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 627 { 628 struct cqhci_host *cq_host; 629 630 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 631 GFP_KERNEL); 632 if (!cq_host) 633 return -ENOMEM; 634 635 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 636 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 637 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 638 cq_host->ops = &sdhci_am654_cqhci_ops; 639 640 host->mmc->caps2 |= MMC_CAP2_CQE; 641 642 return cqhci_init(cq_host, host->mmc, 1); 643 } 644 645 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 646 struct sdhci_am654_data *sdhci_am654) 647 { 648 struct device *dev = mmc_dev(host->mmc); 649 int i; 650 int ret; 651 652 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 653 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 654 if (ret) { 655 /* 656 * ti,otap-del-sel-legacy is mandatory, look for old binding 657 * if not found. 658 */ 659 ret = device_property_read_u32(dev, "ti,otap-del-sel", 660 &sdhci_am654->otap_del_sel[0]); 661 if (ret) { 662 dev_err(dev, "Couldn't find otap-del-sel\n"); 663 664 return ret; 665 } 666 667 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 668 sdhci_am654->legacy_otapdly = true; 669 670 return 0; 671 } 672 673 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) { 674 675 ret = device_property_read_u32(dev, td[i].otap_binding, 676 &sdhci_am654->otap_del_sel[i]); 677 if (ret) { 678 dev_dbg(dev, "Couldn't find %s\n", 679 td[i].otap_binding); 680 /* 681 * Remove the corresponding capability 682 * if an otap-del-sel value is not found 683 */ 684 if (i <= MMC_TIMING_MMC_DDR52) 685 host->mmc->caps &= ~td[i].capability; 686 else 687 host->mmc->caps2 &= ~td[i].capability; 688 } 689 690 if (td[i].itap_binding) 691 device_property_read_u32(dev, td[i].itap_binding, 692 &sdhci_am654->itap_del_sel[i]); 693 } 694 695 return 0; 696 } 697 698 static int sdhci_am654_init(struct sdhci_host *host) 699 { 700 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 701 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 702 u32 ctl_cfg_2 = 0; 703 u32 mask; 704 u32 val; 705 int ret; 706 707 /* Reset OTAP to default value */ 708 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 709 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 710 711 if (sdhci_am654->flags & DLL_CALIB) { 712 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 713 if (~val & CALDONE_MASK) { 714 /* Calibrate IO lines */ 715 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 716 PDB_MASK, PDB_MASK); 717 ret = regmap_read_poll_timeout(sdhci_am654->base, 718 PHY_STAT1, val, 719 val & CALDONE_MASK, 720 1, 20); 721 if (ret) 722 return ret; 723 } 724 } 725 726 /* Enable pins by setting IO mux to 0 */ 727 if (sdhci_am654->flags & IOMUX_PRESENT) 728 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 729 IOMUX_ENABLE_MASK, 0); 730 731 /* Set slot type based on SD or eMMC */ 732 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 733 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 734 735 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 736 ctl_cfg_2); 737 738 /* Enable tuning for SDR50 */ 739 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 740 TUNINGFORSDR50_MASK); 741 742 ret = sdhci_setup_host(host); 743 if (ret) 744 return ret; 745 746 ret = sdhci_am654_cqe_add_host(host); 747 if (ret) 748 goto err_cleanup_host; 749 750 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 751 if (ret) 752 goto err_cleanup_host; 753 754 ret = __sdhci_add_host(host); 755 if (ret) 756 goto err_cleanup_host; 757 758 return 0; 759 760 err_cleanup_host: 761 sdhci_cleanup_host(host); 762 return ret; 763 } 764 765 static int sdhci_am654_get_of_property(struct platform_device *pdev, 766 struct sdhci_am654_data *sdhci_am654) 767 { 768 struct device *dev = &pdev->dev; 769 int drv_strength; 770 int ret; 771 772 if (sdhci_am654->flags & DLL_PRESENT) { 773 ret = device_property_read_u32(dev, "ti,trm-icp", 774 &sdhci_am654->trm_icp); 775 if (ret) 776 return ret; 777 778 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 779 &drv_strength); 780 if (ret) 781 return ret; 782 783 switch (drv_strength) { 784 case 50: 785 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 786 break; 787 case 33: 788 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 789 break; 790 case 66: 791 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 792 break; 793 case 100: 794 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 795 break; 796 case 40: 797 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 798 break; 799 default: 800 dev_err(dev, "Invalid driver strength\n"); 801 return -EINVAL; 802 } 803 } 804 805 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 806 device_property_read_u32(dev, "ti,clkbuf-sel", 807 &sdhci_am654->clkbuf_sel); 808 809 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 810 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 811 812 sdhci_get_of_property(pdev); 813 814 return 0; 815 } 816 817 static const struct of_device_id sdhci_am654_of_match[] = { 818 { 819 .compatible = "ti,am654-sdhci-5.1", 820 .data = &sdhci_am654_drvdata, 821 }, 822 { 823 .compatible = "ti,j721e-sdhci-8bit", 824 .data = &sdhci_j721e_8bit_drvdata, 825 }, 826 { 827 .compatible = "ti,j721e-sdhci-4bit", 828 .data = &sdhci_j721e_4bit_drvdata, 829 }, 830 { 831 .compatible = "ti,am64-sdhci-8bit", 832 .data = &sdhci_j721e_8bit_drvdata, 833 }, 834 { 835 .compatible = "ti,am64-sdhci-4bit", 836 .data = &sdhci_j721e_4bit_drvdata, 837 }, 838 { 839 .compatible = "ti,am62-sdhci", 840 .data = &sdhci_j721e_4bit_drvdata, 841 }, 842 { /* sentinel */ } 843 }; 844 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 845 846 static int sdhci_am654_probe(struct platform_device *pdev) 847 { 848 const struct sdhci_am654_driver_data *drvdata; 849 const struct soc_device_attribute *soc; 850 struct sdhci_pltfm_host *pltfm_host; 851 struct sdhci_am654_data *sdhci_am654; 852 const struct of_device_id *match; 853 struct sdhci_host *host; 854 struct clk *clk_xin; 855 struct device *dev = &pdev->dev; 856 void __iomem *base; 857 int ret; 858 859 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 860 drvdata = match->data; 861 862 /* Update drvdata based on SoC revision */ 863 soc = soc_device_match(sdhci_am654_devices); 864 if (soc && soc->data) 865 drvdata = soc->data; 866 867 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 868 if (IS_ERR(host)) 869 return PTR_ERR(host); 870 871 pltfm_host = sdhci_priv(host); 872 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 873 sdhci_am654->flags = drvdata->flags; 874 875 clk_xin = devm_clk_get(dev, "clk_xin"); 876 if (IS_ERR(clk_xin)) { 877 dev_err(dev, "clk_xin clock not found.\n"); 878 ret = PTR_ERR(clk_xin); 879 goto err_pltfm_free; 880 } 881 882 pltfm_host->clk = clk_xin; 883 884 base = devm_platform_ioremap_resource(pdev, 1); 885 if (IS_ERR(base)) { 886 ret = PTR_ERR(base); 887 goto err_pltfm_free; 888 } 889 890 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 891 &sdhci_am654_regmap_config); 892 if (IS_ERR(sdhci_am654->base)) { 893 dev_err(dev, "Failed to initialize regmap\n"); 894 ret = PTR_ERR(sdhci_am654->base); 895 goto err_pltfm_free; 896 } 897 898 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 899 if (ret) 900 goto err_pltfm_free; 901 902 ret = mmc_of_parse(host->mmc); 903 if (ret) { 904 dev_err_probe(dev, ret, "parsing dt failed\n"); 905 goto err_pltfm_free; 906 } 907 908 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 909 910 pm_runtime_get_noresume(dev); 911 ret = pm_runtime_set_active(dev); 912 if (ret) 913 goto pm_put; 914 pm_runtime_enable(dev); 915 ret = clk_prepare_enable(pltfm_host->clk); 916 if (ret) 917 goto pm_disable; 918 919 ret = sdhci_am654_init(host); 920 if (ret) 921 goto clk_disable; 922 923 /* Setting up autosuspend */ 924 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 925 pm_runtime_use_autosuspend(dev); 926 pm_runtime_mark_last_busy(dev); 927 pm_runtime_put_autosuspend(dev); 928 return 0; 929 930 clk_disable: 931 clk_disable_unprepare(pltfm_host->clk); 932 pm_disable: 933 pm_runtime_disable(dev); 934 pm_put: 935 pm_runtime_put_noidle(dev); 936 err_pltfm_free: 937 sdhci_pltfm_free(pdev); 938 return ret; 939 } 940 941 static void sdhci_am654_remove(struct platform_device *pdev) 942 { 943 struct sdhci_host *host = platform_get_drvdata(pdev); 944 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 945 struct device *dev = &pdev->dev; 946 int ret; 947 948 ret = pm_runtime_get_sync(dev); 949 if (ret < 0) 950 dev_err(dev, "pm_runtime_get_sync() Failed\n"); 951 952 sdhci_remove_host(host, true); 953 clk_disable_unprepare(pltfm_host->clk); 954 pm_runtime_disable(dev); 955 pm_runtime_put_noidle(dev); 956 sdhci_pltfm_free(pdev); 957 } 958 959 #ifdef CONFIG_PM 960 static int sdhci_am654_restore(struct sdhci_host *host) 961 { 962 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 963 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 964 u32 ctl_cfg_2 = 0; 965 u32 val; 966 int ret; 967 968 if (sdhci_am654->flags & DLL_CALIB) { 969 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 970 if (~val & CALDONE_MASK) { 971 /* Calibrate IO lines */ 972 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 973 PDB_MASK, PDB_MASK); 974 ret = regmap_read_poll_timeout(sdhci_am654->base, 975 PHY_STAT1, val, 976 val & CALDONE_MASK, 977 1, 20); 978 if (ret) 979 return ret; 980 } 981 } 982 983 /* Enable pins by setting IO mux to 0 */ 984 if (sdhci_am654->flags & IOMUX_PRESENT) 985 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 986 IOMUX_ENABLE_MASK, 0); 987 988 /* Set slot type based on SD or eMMC */ 989 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 990 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 991 992 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 993 ctl_cfg_2); 994 995 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 996 if (~val & TUNINGFORSDR50_MASK) 997 /* Enable tuning for SDR50 */ 998 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 999 TUNINGFORSDR50_MASK); 1000 1001 return 0; 1002 } 1003 1004 static int sdhci_am654_runtime_suspend(struct device *dev) 1005 { 1006 struct sdhci_host *host = dev_get_drvdata(dev); 1007 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1008 int ret; 1009 1010 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1011 mmc_retune_needed(host->mmc); 1012 1013 ret = cqhci_suspend(host->mmc); 1014 if (ret) 1015 return ret; 1016 1017 ret = sdhci_runtime_suspend_host(host); 1018 if (ret) 1019 return ret; 1020 1021 /* disable the clock */ 1022 clk_disable_unprepare(pltfm_host->clk); 1023 return 0; 1024 } 1025 1026 static int sdhci_am654_runtime_resume(struct device *dev) 1027 { 1028 struct sdhci_host *host = dev_get_drvdata(dev); 1029 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1030 int ret; 1031 1032 /* Enable the clock */ 1033 ret = clk_prepare_enable(pltfm_host->clk); 1034 if (ret) 1035 return ret; 1036 1037 ret = sdhci_am654_restore(host); 1038 if (ret) 1039 return ret; 1040 1041 ret = sdhci_runtime_resume_host(host, 0); 1042 if (ret) 1043 return ret; 1044 1045 ret = cqhci_resume(host->mmc); 1046 if (ret) 1047 return ret; 1048 1049 return 0; 1050 } 1051 #endif 1052 1053 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 1054 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 1055 sdhci_am654_runtime_resume, NULL) 1056 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1057 pm_runtime_force_resume) 1058 }; 1059 1060 static struct platform_driver sdhci_am654_driver = { 1061 .driver = { 1062 .name = "sdhci-am654", 1063 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1064 .pm = &sdhci_am654_dev_pm_ops, 1065 .of_match_table = sdhci_am654_of_match, 1066 }, 1067 .probe = sdhci_am654_probe, 1068 .remove_new = sdhci_am654_remove, 1069 }; 1070 1071 module_platform_driver(sdhci_am654_driver); 1072 1073 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 1074 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 1075 MODULE_LICENSE("GPL"); 1076