1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/of.h> 10 #include <linux/module.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/property.h> 13 #include <linux/regmap.h> 14 15 #include "cqhci.h" 16 #include "sdhci-pltfm.h" 17 18 /* CTL_CFG Registers */ 19 #define CTL_CFG_2 0x14 20 21 #define SLOTTYPE_MASK GENMASK(31, 30) 22 #define SLOTTYPE_EMBEDDED BIT(30) 23 24 /* PHY Registers */ 25 #define PHY_CTRL1 0x100 26 #define PHY_CTRL2 0x104 27 #define PHY_CTRL3 0x108 28 #define PHY_CTRL4 0x10C 29 #define PHY_CTRL5 0x110 30 #define PHY_CTRL6 0x114 31 #define PHY_STAT1 0x130 32 #define PHY_STAT2 0x134 33 34 #define IOMUX_ENABLE_SHIFT 31 35 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 36 #define OTAPDLYENA_SHIFT 20 37 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 38 #define OTAPDLYSEL_SHIFT 12 39 #define OTAPDLYSEL_MASK GENMASK(15, 12) 40 #define STRBSEL_SHIFT 24 41 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 42 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 43 #define SEL50_SHIFT 8 44 #define SEL50_MASK BIT(SEL50_SHIFT) 45 #define SEL100_SHIFT 9 46 #define SEL100_MASK BIT(SEL100_SHIFT) 47 #define FREQSEL_SHIFT 8 48 #define FREQSEL_MASK GENMASK(10, 8) 49 #define DLL_TRIM_ICP_SHIFT 4 50 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 51 #define DR_TY_SHIFT 20 52 #define DR_TY_MASK GENMASK(22, 20) 53 #define ENDLL_SHIFT 1 54 #define ENDLL_MASK BIT(ENDLL_SHIFT) 55 #define DLLRDY_SHIFT 0 56 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 57 #define PDB_SHIFT 0 58 #define PDB_MASK BIT(PDB_SHIFT) 59 #define CALDONE_SHIFT 1 60 #define CALDONE_MASK BIT(CALDONE_SHIFT) 61 #define RETRIM_SHIFT 17 62 #define RETRIM_MASK BIT(RETRIM_SHIFT) 63 64 #define DRIVER_STRENGTH_50_OHM 0x0 65 #define DRIVER_STRENGTH_33_OHM 0x1 66 #define DRIVER_STRENGTH_66_OHM 0x2 67 #define DRIVER_STRENGTH_100_OHM 0x3 68 #define DRIVER_STRENGTH_40_OHM 0x4 69 70 #define CLOCK_TOO_SLOW_HZ 400000 71 72 /* Command Queue Host Controller Interface Base address */ 73 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 74 75 static struct regmap_config sdhci_am654_regmap_config = { 76 .reg_bits = 32, 77 .val_bits = 32, 78 .reg_stride = 4, 79 .fast_io = true, 80 }; 81 82 struct sdhci_am654_data { 83 struct regmap *base; 84 int otap_del_sel; 85 int trm_icp; 86 int drv_strength; 87 bool dll_on; 88 int strb_sel; 89 u32 flags; 90 }; 91 92 struct sdhci_am654_driver_data { 93 const struct sdhci_pltfm_data *pdata; 94 u32 flags; 95 #define IOMUX_PRESENT (1 << 0) 96 #define FREQSEL_2_BIT (1 << 1) 97 #define STRBSEL_4_BIT (1 << 2) 98 #define DLL_PRESENT (1 << 3) 99 }; 100 101 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 102 { 103 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 104 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 105 int sel50, sel100, freqsel; 106 u32 mask, val; 107 int ret; 108 109 if (sdhci_am654->dll_on) { 110 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 111 112 sdhci_am654->dll_on = false; 113 } 114 115 sdhci_set_clock(host, clock); 116 117 if (clock > CLOCK_TOO_SLOW_HZ) { 118 /* Setup DLL Output TAP delay */ 119 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 120 val = (1 << OTAPDLYENA_SHIFT) | 121 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 122 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 123 /* Write to STRBSEL for HS400 speed mode */ 124 if (host->mmc->ios.timing == MMC_TIMING_MMC_HS400) { 125 if (sdhci_am654->flags & STRBSEL_4_BIT) 126 mask = STRBSEL_4BIT_MASK; 127 else 128 mask = STRBSEL_8BIT_MASK; 129 130 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 131 sdhci_am654->strb_sel << 132 STRBSEL_SHIFT); 133 } 134 135 if (sdhci_am654->flags & FREQSEL_2_BIT) { 136 switch (clock) { 137 case 200000000: 138 sel50 = 0; 139 sel100 = 0; 140 break; 141 case 100000000: 142 sel50 = 0; 143 sel100 = 1; 144 break; 145 default: 146 sel50 = 1; 147 sel100 = 0; 148 } 149 150 /* Configure PHY DLL frequency */ 151 mask = SEL50_MASK | SEL100_MASK; 152 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 153 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, 154 val); 155 } else { 156 switch (clock) { 157 case 200000000: 158 freqsel = 0x0; 159 break; 160 default: 161 freqsel = 0x4; 162 } 163 164 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 165 FREQSEL_MASK, 166 freqsel << FREQSEL_SHIFT); 167 } 168 169 /* Configure DLL TRIM */ 170 mask = DLL_TRIM_ICP_MASK; 171 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 172 173 /* Configure DLL driver strength */ 174 mask |= DR_TY_MASK; 175 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 176 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 177 /* Enable DLL */ 178 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 179 0x1 << ENDLL_SHIFT); 180 /* 181 * Poll for DLL ready. Use a one second timeout. 182 * Works in all experiments done so far 183 */ 184 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 185 val, val & DLLRDY_MASK, 1000, 186 1000000); 187 if (ret) { 188 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 189 return; 190 } 191 192 sdhci_am654->dll_on = true; 193 } 194 } 195 196 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 197 unsigned int clock) 198 { 199 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 200 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 201 int val, mask; 202 203 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 204 val = (1 << OTAPDLYENA_SHIFT) | 205 (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 206 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 207 208 sdhci_set_clock(host, clock); 209 } 210 211 static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 212 unsigned short vdd) 213 { 214 if (!IS_ERR(host->mmc->supply.vmmc)) { 215 struct mmc_host *mmc = host->mmc; 216 217 mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 218 } 219 sdhci_set_power_noreg(host, mode, vdd); 220 } 221 222 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 223 { 224 unsigned char timing = host->mmc->ios.timing; 225 226 if (reg == SDHCI_HOST_CONTROL) { 227 switch (timing) { 228 /* 229 * According to the data manual, HISPD bit 230 * should not be set in these speed modes. 231 */ 232 case MMC_TIMING_SD_HS: 233 case MMC_TIMING_MMC_HS: 234 case MMC_TIMING_UHS_SDR12: 235 case MMC_TIMING_UHS_SDR25: 236 val &= ~SDHCI_CTRL_HISPD; 237 } 238 } 239 240 writeb(val, host->ioaddr + reg); 241 } 242 243 static struct sdhci_ops sdhci_am654_ops = { 244 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 245 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 246 .set_uhs_signaling = sdhci_set_uhs_signaling, 247 .set_bus_width = sdhci_set_bus_width, 248 .set_power = sdhci_am654_set_power, 249 .set_clock = sdhci_am654_set_clock, 250 .write_b = sdhci_am654_write_b, 251 .reset = sdhci_reset, 252 }; 253 254 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 255 .ops = &sdhci_am654_ops, 256 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 257 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 258 }; 259 260 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 261 .pdata = &sdhci_am654_pdata, 262 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 263 }; 264 265 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 266 { 267 int cmd_error = 0; 268 int data_error = 0; 269 270 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 271 return intmask; 272 273 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 274 275 return 0; 276 } 277 278 static struct sdhci_ops sdhci_j721e_8bit_ops = { 279 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 280 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 281 .set_uhs_signaling = sdhci_set_uhs_signaling, 282 .set_bus_width = sdhci_set_bus_width, 283 .set_power = sdhci_am654_set_power, 284 .set_clock = sdhci_am654_set_clock, 285 .write_b = sdhci_am654_write_b, 286 .irq = sdhci_am654_cqhci_irq, 287 .reset = sdhci_reset, 288 }; 289 290 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 291 .ops = &sdhci_j721e_8bit_ops, 292 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 293 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 294 }; 295 296 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 297 .pdata = &sdhci_j721e_8bit_pdata, 298 .flags = DLL_PRESENT, 299 }; 300 301 static struct sdhci_ops sdhci_j721e_4bit_ops = { 302 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 303 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 304 .set_uhs_signaling = sdhci_set_uhs_signaling, 305 .set_bus_width = sdhci_set_bus_width, 306 .set_power = sdhci_am654_set_power, 307 .set_clock = sdhci_j721e_4bit_set_clock, 308 .write_b = sdhci_am654_write_b, 309 .irq = sdhci_am654_cqhci_irq, 310 .reset = sdhci_reset, 311 }; 312 313 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 314 .ops = &sdhci_j721e_4bit_ops, 315 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 316 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 317 }; 318 319 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 320 .pdata = &sdhci_j721e_4bit_pdata, 321 .flags = IOMUX_PRESENT, 322 }; 323 324 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 325 { 326 sdhci_dumpregs(mmc_priv(mmc)); 327 } 328 329 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 330 .enable = sdhci_cqe_enable, 331 .disable = sdhci_cqe_disable, 332 .dumpregs = sdhci_am654_dumpregs, 333 }; 334 335 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 336 { 337 struct cqhci_host *cq_host; 338 int ret; 339 340 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 341 GFP_KERNEL); 342 if (!cq_host) 343 return -ENOMEM; 344 345 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 346 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 347 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 348 cq_host->ops = &sdhci_am654_cqhci_ops; 349 350 host->mmc->caps2 |= MMC_CAP2_CQE; 351 352 ret = cqhci_init(cq_host, host->mmc, 1); 353 354 return ret; 355 } 356 357 static int sdhci_am654_init(struct sdhci_host *host) 358 { 359 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 360 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 361 u32 ctl_cfg_2 = 0; 362 u32 mask; 363 u32 val; 364 int ret; 365 366 /* Reset OTAP to default value */ 367 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 368 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 369 370 if (sdhci_am654->flags & DLL_PRESENT) { 371 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 372 if (~val & CALDONE_MASK) { 373 /* Calibrate IO lines */ 374 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 375 PDB_MASK, PDB_MASK); 376 ret = regmap_read_poll_timeout(sdhci_am654->base, 377 PHY_STAT1, val, 378 val & CALDONE_MASK, 379 1, 20); 380 if (ret) 381 return ret; 382 } 383 } 384 385 /* Enable pins by setting IO mux to 0 */ 386 if (sdhci_am654->flags & IOMUX_PRESENT) 387 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 388 IOMUX_ENABLE_MASK, 0); 389 390 /* Set slot type based on SD or eMMC */ 391 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 392 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 393 394 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 395 ctl_cfg_2); 396 397 ret = sdhci_setup_host(host); 398 if (ret) 399 return ret; 400 401 ret = sdhci_am654_cqe_add_host(host); 402 if (ret) 403 goto err_cleanup_host; 404 405 ret = __sdhci_add_host(host); 406 if (ret) 407 goto err_cleanup_host; 408 409 return 0; 410 411 err_cleanup_host: 412 sdhci_cleanup_host(host); 413 return ret; 414 } 415 416 static int sdhci_am654_get_of_property(struct platform_device *pdev, 417 struct sdhci_am654_data *sdhci_am654) 418 { 419 struct device *dev = &pdev->dev; 420 int drv_strength; 421 int ret; 422 423 ret = device_property_read_u32(dev, "ti,otap-del-sel", 424 &sdhci_am654->otap_del_sel); 425 if (ret) 426 return ret; 427 428 if (sdhci_am654->flags & DLL_PRESENT) { 429 ret = device_property_read_u32(dev, "ti,trm-icp", 430 &sdhci_am654->trm_icp); 431 if (ret) 432 return ret; 433 434 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 435 &drv_strength); 436 if (ret) 437 return ret; 438 439 switch (drv_strength) { 440 case 50: 441 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 442 break; 443 case 33: 444 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 445 break; 446 case 66: 447 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 448 break; 449 case 100: 450 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 451 break; 452 case 40: 453 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 454 break; 455 default: 456 dev_err(dev, "Invalid driver strength\n"); 457 return -EINVAL; 458 } 459 } 460 461 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 462 463 sdhci_get_of_property(pdev); 464 465 return 0; 466 } 467 468 static const struct of_device_id sdhci_am654_of_match[] = { 469 { 470 .compatible = "ti,am654-sdhci-5.1", 471 .data = &sdhci_am654_drvdata, 472 }, 473 { 474 .compatible = "ti,j721e-sdhci-8bit", 475 .data = &sdhci_j721e_8bit_drvdata, 476 }, 477 { 478 .compatible = "ti,j721e-sdhci-4bit", 479 .data = &sdhci_j721e_4bit_drvdata, 480 }, 481 { /* sentinel */ } 482 }; 483 484 static int sdhci_am654_probe(struct platform_device *pdev) 485 { 486 const struct sdhci_am654_driver_data *drvdata; 487 struct sdhci_pltfm_host *pltfm_host; 488 struct sdhci_am654_data *sdhci_am654; 489 const struct of_device_id *match; 490 struct sdhci_host *host; 491 struct resource *res; 492 struct clk *clk_xin; 493 struct device *dev = &pdev->dev; 494 void __iomem *base; 495 int ret; 496 497 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 498 drvdata = match->data; 499 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 500 if (IS_ERR(host)) 501 return PTR_ERR(host); 502 503 pltfm_host = sdhci_priv(host); 504 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 505 sdhci_am654->flags = drvdata->flags; 506 507 clk_xin = devm_clk_get(dev, "clk_xin"); 508 if (IS_ERR(clk_xin)) { 509 dev_err(dev, "clk_xin clock not found.\n"); 510 ret = PTR_ERR(clk_xin); 511 goto err_pltfm_free; 512 } 513 514 pltfm_host->clk = clk_xin; 515 516 /* Clocks are enabled using pm_runtime */ 517 pm_runtime_enable(dev); 518 ret = pm_runtime_get_sync(dev); 519 if (ret < 0) { 520 pm_runtime_put_noidle(dev); 521 goto pm_runtime_disable; 522 } 523 524 res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 525 base = devm_ioremap_resource(dev, res); 526 if (IS_ERR(base)) { 527 ret = PTR_ERR(base); 528 goto pm_runtime_put; 529 } 530 531 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 532 &sdhci_am654_regmap_config); 533 if (IS_ERR(sdhci_am654->base)) { 534 dev_err(dev, "Failed to initialize regmap\n"); 535 ret = PTR_ERR(sdhci_am654->base); 536 goto pm_runtime_put; 537 } 538 539 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 540 if (ret) 541 goto pm_runtime_put; 542 543 ret = mmc_of_parse(host->mmc); 544 if (ret) { 545 dev_err(dev, "parsing dt failed (%d)\n", ret); 546 goto pm_runtime_put; 547 } 548 549 ret = sdhci_am654_init(host); 550 if (ret) 551 goto pm_runtime_put; 552 553 return 0; 554 555 pm_runtime_put: 556 pm_runtime_put_sync(dev); 557 pm_runtime_disable: 558 pm_runtime_disable(dev); 559 err_pltfm_free: 560 sdhci_pltfm_free(pdev); 561 return ret; 562 } 563 564 static int sdhci_am654_remove(struct platform_device *pdev) 565 { 566 struct sdhci_host *host = platform_get_drvdata(pdev); 567 int ret; 568 569 sdhci_remove_host(host, true); 570 ret = pm_runtime_put_sync(&pdev->dev); 571 if (ret < 0) 572 return ret; 573 574 pm_runtime_disable(&pdev->dev); 575 sdhci_pltfm_free(pdev); 576 577 return 0; 578 } 579 580 static struct platform_driver sdhci_am654_driver = { 581 .driver = { 582 .name = "sdhci-am654", 583 .of_match_table = sdhci_am654_of_match, 584 }, 585 .probe = sdhci_am654_probe, 586 .remove = sdhci_am654_remove, 587 }; 588 589 module_platform_driver(sdhci_am654_driver); 590 591 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 592 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 593 MODULE_LICENSE("GPL"); 594