1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 20 21 /* CTL_CFG Registers */ 22 #define CTL_CFG_2 0x14 23 #define CTL_CFG_3 0x18 24 25 #define SLOTTYPE_MASK GENMASK(31, 30) 26 #define SLOTTYPE_EMBEDDED BIT(30) 27 #define TUNINGFORSDR50_MASK BIT(13) 28 29 /* PHY Registers */ 30 #define PHY_CTRL1 0x100 31 #define PHY_CTRL2 0x104 32 #define PHY_CTRL3 0x108 33 #define PHY_CTRL4 0x10C 34 #define PHY_CTRL5 0x110 35 #define PHY_CTRL6 0x114 36 #define PHY_STAT1 0x130 37 #define PHY_STAT2 0x134 38 39 #define IOMUX_ENABLE_SHIFT 31 40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 41 #define OTAPDLYENA_SHIFT 20 42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 43 #define OTAPDLYSEL_SHIFT 12 44 #define OTAPDLYSEL_MASK GENMASK(15, 12) 45 #define STRBSEL_SHIFT 24 46 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 47 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 48 #define SEL50_SHIFT 8 49 #define SEL50_MASK BIT(SEL50_SHIFT) 50 #define SEL100_SHIFT 9 51 #define SEL100_MASK BIT(SEL100_SHIFT) 52 #define FREQSEL_SHIFT 8 53 #define FREQSEL_MASK GENMASK(10, 8) 54 #define CLKBUFSEL_SHIFT 0 55 #define CLKBUFSEL_MASK GENMASK(2, 0) 56 #define DLL_TRIM_ICP_SHIFT 4 57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 58 #define DR_TY_SHIFT 20 59 #define DR_TY_MASK GENMASK(22, 20) 60 #define ENDLL_SHIFT 1 61 #define ENDLL_MASK BIT(ENDLL_SHIFT) 62 #define DLLRDY_SHIFT 0 63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 64 #define PDB_SHIFT 0 65 #define PDB_MASK BIT(PDB_SHIFT) 66 #define CALDONE_SHIFT 1 67 #define CALDONE_MASK BIT(CALDONE_SHIFT) 68 #define RETRIM_SHIFT 17 69 #define RETRIM_MASK BIT(RETRIM_SHIFT) 70 #define SELDLYTXCLK_SHIFT 17 71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72 #define SELDLYRXCLK_SHIFT 16 73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74 #define ITAPDLYSEL_SHIFT 0 75 #define ITAPDLYSEL_MASK GENMASK(4, 0) 76 #define ITAPDLYENA_SHIFT 8 77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78 #define ITAPCHGWIN_SHIFT 9 79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 80 81 #define DRIVER_STRENGTH_50_OHM 0x0 82 #define DRIVER_STRENGTH_33_OHM 0x1 83 #define DRIVER_STRENGTH_66_OHM 0x2 84 #define DRIVER_STRENGTH_100_OHM 0x3 85 #define DRIVER_STRENGTH_40_OHM 0x4 86 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 89 90 /* Command Queue Host Controller Interface Base address */ 91 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92 93 static struct regmap_config sdhci_am654_regmap_config = { 94 .reg_bits = 32, 95 .val_bits = 32, 96 .reg_stride = 4, 97 .fast_io = true, 98 }; 99 100 struct timing_data { 101 const char *otap_binding; 102 const char *itap_binding; 103 u32 capability; 104 }; 105 106 static const struct timing_data td[] = { 107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108 "ti,itap-del-sel-legacy", 109 0}, 110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111 "ti,itap-del-sel-mmc-hs", 112 MMC_CAP_MMC_HIGHSPEED}, 113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114 "ti,itap-del-sel-sd-hs", 115 MMC_CAP_SD_HIGHSPEED}, 116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117 "ti,itap-del-sel-sdr12", 118 MMC_CAP_UHS_SDR12}, 119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120 "ti,itap-del-sel-sdr25", 121 MMC_CAP_UHS_SDR25}, 122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123 NULL, 124 MMC_CAP_UHS_SDR50}, 125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126 NULL, 127 MMC_CAP_UHS_SDR104}, 128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129 NULL, 130 MMC_CAP_UHS_DDR50}, 131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132 "ti,itap-del-sel-ddr52", 133 MMC_CAP_DDR}, 134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135 NULL, 136 MMC_CAP2_HS200}, 137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138 NULL, 139 MMC_CAP2_HS400}, 140 }; 141 142 struct sdhci_am654_data { 143 struct regmap *base; 144 int otap_del_sel[ARRAY_SIZE(td)]; 145 int itap_del_sel[ARRAY_SIZE(td)]; 146 int clkbuf_sel; 147 int trm_icp; 148 int drv_strength; 149 int strb_sel; 150 u32 flags; 151 u32 quirks; 152 bool dll_enable; 153 154 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 155 }; 156 157 struct window { 158 u8 start; 159 u8 end; 160 u8 length; 161 }; 162 163 struct sdhci_am654_driver_data { 164 const struct sdhci_pltfm_data *pdata; 165 u32 flags; 166 #define IOMUX_PRESENT (1 << 0) 167 #define FREQSEL_2_BIT (1 << 1) 168 #define STRBSEL_4_BIT (1 << 2) 169 #define DLL_PRESENT (1 << 3) 170 #define DLL_CALIB (1 << 4) 171 }; 172 173 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 174 { 175 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 176 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 177 int sel50, sel100, freqsel; 178 u32 mask, val; 179 int ret; 180 181 /* Disable delay chain mode */ 182 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 183 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 184 185 if (sdhci_am654->flags & FREQSEL_2_BIT) { 186 switch (clock) { 187 case 200000000: 188 sel50 = 0; 189 sel100 = 0; 190 break; 191 case 100000000: 192 sel50 = 0; 193 sel100 = 1; 194 break; 195 default: 196 sel50 = 1; 197 sel100 = 0; 198 } 199 200 /* Configure PHY DLL frequency */ 201 mask = SEL50_MASK | SEL100_MASK; 202 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 203 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 204 205 } else { 206 switch (clock) { 207 case 200000000: 208 freqsel = 0x0; 209 break; 210 default: 211 freqsel = 0x4; 212 } 213 214 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 215 freqsel << FREQSEL_SHIFT); 216 } 217 /* Configure DLL TRIM */ 218 mask = DLL_TRIM_ICP_MASK; 219 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 220 221 /* Configure DLL driver strength */ 222 mask |= DR_TY_MASK; 223 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 224 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 225 226 /* Enable DLL */ 227 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 228 0x1 << ENDLL_SHIFT); 229 /* 230 * Poll for DLL ready. Use a one second timeout. 231 * Works in all experiments done so far 232 */ 233 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 234 val & DLLRDY_MASK, 1000, 1000000); 235 if (ret) { 236 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 237 return; 238 } 239 } 240 241 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 242 u32 itapdly) 243 { 244 /* Set ITAPCHGWIN before writing to ITAPDLY */ 245 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 246 1 << ITAPCHGWIN_SHIFT); 247 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 248 itapdly << ITAPDLYSEL_SHIFT); 249 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 250 } 251 252 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 253 unsigned char timing) 254 { 255 u32 mask, val; 256 257 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 258 259 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 260 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 261 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 262 263 sdhci_am654_write_itapdly(sdhci_am654, 264 sdhci_am654->itap_del_sel[timing]); 265 } 266 267 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 268 { 269 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 270 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 271 unsigned char timing = host->mmc->ios.timing; 272 u32 otap_del_sel; 273 u32 otap_del_ena; 274 u32 mask, val; 275 276 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 277 278 sdhci_set_clock(host, clock); 279 280 /* Setup DLL Output TAP delay */ 281 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 282 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 283 284 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 285 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 286 (otap_del_sel << OTAPDLYSEL_SHIFT); 287 288 /* Write to STRBSEL for HS400 speed mode */ 289 if (timing == MMC_TIMING_MMC_HS400) { 290 if (sdhci_am654->flags & STRBSEL_4_BIT) 291 mask |= STRBSEL_4BIT_MASK; 292 else 293 mask |= STRBSEL_8BIT_MASK; 294 295 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 296 } 297 298 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 299 300 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 301 sdhci_am654_setup_dll(host, clock); 302 sdhci_am654->dll_enable = true; 303 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing]); 304 } else { 305 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 306 sdhci_am654->dll_enable = false; 307 } 308 309 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 310 sdhci_am654->clkbuf_sel); 311 } 312 313 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 314 unsigned int clock) 315 { 316 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 317 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 318 unsigned char timing = host->mmc->ios.timing; 319 u32 otap_del_sel; 320 u32 mask, val; 321 322 /* Setup DLL Output TAP delay */ 323 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 324 325 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 326 val = (0x1 << OTAPDLYENA_SHIFT) | 327 (otap_del_sel << OTAPDLYSEL_SHIFT); 328 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 329 330 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 331 sdhci_am654->clkbuf_sel); 332 333 sdhci_set_clock(host, clock); 334 } 335 336 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 337 { 338 writeb(val, host->ioaddr + reg); 339 usleep_range(1000, 10000); 340 return readb(host->ioaddr + reg); 341 } 342 343 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 344 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 345 { 346 unsigned char timing = host->mmc->ios.timing; 347 u8 pwr; 348 int ret; 349 350 if (reg == SDHCI_HOST_CONTROL) { 351 switch (timing) { 352 /* 353 * According to the data manual, HISPD bit 354 * should not be set in these speed modes. 355 */ 356 case MMC_TIMING_SD_HS: 357 case MMC_TIMING_MMC_HS: 358 val &= ~SDHCI_CTRL_HISPD; 359 } 360 } 361 362 writeb(val, host->ioaddr + reg); 363 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 364 /* 365 * Power on will not happen until the card detect debounce 366 * timer expires. Wait at least 1.5 seconds for the power on 367 * bit to be set 368 */ 369 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 370 pwr & SDHCI_POWER_ON, 0, 371 MAX_POWER_ON_TIMEOUT, false, host, val, 372 reg); 373 if (ret) 374 dev_info(mmc_dev(host->mmc), "Power on failed\n"); 375 } 376 } 377 378 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 379 { 380 u8 ctrl; 381 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 382 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 383 384 sdhci_and_cqhci_reset(host, mask); 385 386 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 387 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 388 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 389 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 390 } 391 } 392 393 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 394 { 395 struct sdhci_host *host = mmc_priv(mmc); 396 int err = sdhci_execute_tuning(mmc, opcode); 397 398 if (err) 399 return err; 400 /* 401 * Tuning data remains in the buffer after tuning. 402 * Do a command and data reset to get rid of it 403 */ 404 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 405 406 return 0; 407 } 408 409 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 410 { 411 int cmd_error = 0; 412 int data_error = 0; 413 414 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 415 return intmask; 416 417 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 418 419 return 0; 420 } 421 422 #define ITAPDLY_LENGTH 32 423 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 424 425 static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 426 *fail_window, u8 num_fails, bool circular_buffer) 427 { 428 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 429 u8 first_fail_start = 0, last_fail_end = 0; 430 struct device *dev = mmc_dev(host->mmc); 431 struct window pass_window = {0, 0, 0}; 432 int prev_fail_end = -1; 433 u8 i; 434 435 if (!num_fails) 436 return ITAPDLY_LAST_INDEX >> 1; 437 438 if (fail_window->length == ITAPDLY_LENGTH) { 439 dev_err(dev, "No passing ITAPDLY, return 0\n"); 440 return 0; 441 } 442 443 first_fail_start = fail_window->start; 444 last_fail_end = fail_window[num_fails - 1].end; 445 446 for (i = 0; i < num_fails; i++) { 447 start_fail = fail_window[i].start; 448 end_fail = fail_window[i].end; 449 pass_length = start_fail - (prev_fail_end + 1); 450 451 if (pass_length > pass_window.length) { 452 pass_window.start = prev_fail_end + 1; 453 pass_window.length = pass_length; 454 } 455 prev_fail_end = end_fail; 456 } 457 458 if (!circular_buffer) 459 pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 460 else 461 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 462 463 if (pass_length > pass_window.length) { 464 pass_window.start = last_fail_end + 1; 465 pass_window.length = pass_length; 466 } 467 468 if (!circular_buffer) 469 itap = pass_window.start + (pass_window.length >> 1); 470 else 471 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 472 473 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 474 } 475 476 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 477 u32 opcode) 478 { 479 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 480 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 481 struct window fail_window[ITAPDLY_LENGTH]; 482 u8 curr_pass, itap; 483 u8 fail_index = 0; 484 u8 prev_pass = 1; 485 486 memset(fail_window, 0, sizeof(fail_window)); 487 488 /* Enable ITAPDLY */ 489 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 490 1 << ITAPDLYENA_SHIFT); 491 492 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 493 sdhci_am654_write_itapdly(sdhci_am654, itap); 494 495 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 496 497 if (!curr_pass && prev_pass) 498 fail_window[fail_index].start = itap; 499 500 if (!curr_pass) { 501 fail_window[fail_index].end = itap; 502 fail_window[fail_index].length++; 503 } 504 505 if (curr_pass && !prev_pass) 506 fail_index++; 507 508 prev_pass = curr_pass; 509 } 510 511 if (fail_window[fail_index].length != 0) 512 fail_index++; 513 514 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 515 sdhci_am654->dll_enable); 516 517 sdhci_am654_write_itapdly(sdhci_am654, itap); 518 519 return 0; 520 } 521 522 static struct sdhci_ops sdhci_am654_ops = { 523 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 524 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 525 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 526 .set_uhs_signaling = sdhci_set_uhs_signaling, 527 .set_bus_width = sdhci_set_bus_width, 528 .set_power = sdhci_set_power_and_bus_voltage, 529 .set_clock = sdhci_am654_set_clock, 530 .write_b = sdhci_am654_write_b, 531 .irq = sdhci_am654_cqhci_irq, 532 .reset = sdhci_and_cqhci_reset, 533 }; 534 535 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 536 .ops = &sdhci_am654_ops, 537 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 538 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 539 }; 540 541 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 542 .pdata = &sdhci_am654_pdata, 543 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 544 DLL_CALIB, 545 }; 546 547 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 548 .pdata = &sdhci_am654_pdata, 549 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 550 }; 551 552 static struct sdhci_ops sdhci_j721e_8bit_ops = { 553 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 554 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 555 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 556 .set_uhs_signaling = sdhci_set_uhs_signaling, 557 .set_bus_width = sdhci_set_bus_width, 558 .set_power = sdhci_set_power_and_bus_voltage, 559 .set_clock = sdhci_am654_set_clock, 560 .write_b = sdhci_am654_write_b, 561 .irq = sdhci_am654_cqhci_irq, 562 .reset = sdhci_and_cqhci_reset, 563 }; 564 565 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 566 .ops = &sdhci_j721e_8bit_ops, 567 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 568 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 569 }; 570 571 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 572 .pdata = &sdhci_j721e_8bit_pdata, 573 .flags = DLL_PRESENT | DLL_CALIB, 574 }; 575 576 static struct sdhci_ops sdhci_j721e_4bit_ops = { 577 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 578 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 579 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 580 .set_uhs_signaling = sdhci_set_uhs_signaling, 581 .set_bus_width = sdhci_set_bus_width, 582 .set_power = sdhci_set_power_and_bus_voltage, 583 .set_clock = sdhci_j721e_4bit_set_clock, 584 .write_b = sdhci_am654_write_b, 585 .irq = sdhci_am654_cqhci_irq, 586 .reset = sdhci_am654_reset, 587 }; 588 589 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 590 .ops = &sdhci_j721e_4bit_ops, 591 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 592 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 593 }; 594 595 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 596 .pdata = &sdhci_j721e_4bit_pdata, 597 .flags = IOMUX_PRESENT, 598 }; 599 600 static const struct soc_device_attribute sdhci_am654_devices[] = { 601 { .family = "AM65X", 602 .revision = "SR1.0", 603 .data = &sdhci_am654_sr1_drvdata 604 }, 605 {/* sentinel */} 606 }; 607 608 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 609 { 610 sdhci_dumpregs(mmc_priv(mmc)); 611 } 612 613 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 614 .enable = sdhci_cqe_enable, 615 .disable = sdhci_cqe_disable, 616 .dumpregs = sdhci_am654_dumpregs, 617 }; 618 619 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 620 { 621 struct cqhci_host *cq_host; 622 623 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 624 GFP_KERNEL); 625 if (!cq_host) 626 return -ENOMEM; 627 628 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 629 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 630 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 631 cq_host->ops = &sdhci_am654_cqhci_ops; 632 633 host->mmc->caps2 |= MMC_CAP2_CQE; 634 635 return cqhci_init(cq_host, host->mmc, 1); 636 } 637 638 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 639 struct sdhci_am654_data *sdhci_am654) 640 { 641 struct device *dev = mmc_dev(host->mmc); 642 int i; 643 int ret; 644 645 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) { 646 647 ret = device_property_read_u32(dev, td[i].otap_binding, 648 &sdhci_am654->otap_del_sel[i]); 649 if (ret) { 650 if (i == MMC_TIMING_LEGACY) { 651 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); 652 return ret; 653 } 654 dev_dbg(dev, "Couldn't find %s\n", 655 td[i].otap_binding); 656 /* 657 * Remove the corresponding capability 658 * if an otap-del-sel value is not found 659 */ 660 if (i <= MMC_TIMING_MMC_DDR52) 661 host->mmc->caps &= ~td[i].capability; 662 else 663 host->mmc->caps2 &= ~td[i].capability; 664 } 665 666 if (td[i].itap_binding) 667 device_property_read_u32(dev, td[i].itap_binding, 668 &sdhci_am654->itap_del_sel[i]); 669 } 670 671 return 0; 672 } 673 674 static int sdhci_am654_init(struct sdhci_host *host) 675 { 676 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 677 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 678 u32 ctl_cfg_2 = 0; 679 u32 mask; 680 u32 val; 681 int ret; 682 683 /* Reset OTAP to default value */ 684 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 685 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 686 687 if (sdhci_am654->flags & DLL_CALIB) { 688 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 689 if (~val & CALDONE_MASK) { 690 /* Calibrate IO lines */ 691 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 692 PDB_MASK, PDB_MASK); 693 ret = regmap_read_poll_timeout(sdhci_am654->base, 694 PHY_STAT1, val, 695 val & CALDONE_MASK, 696 1, 20); 697 if (ret) 698 return ret; 699 } 700 } 701 702 /* Enable pins by setting IO mux to 0 */ 703 if (sdhci_am654->flags & IOMUX_PRESENT) 704 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 705 IOMUX_ENABLE_MASK, 0); 706 707 /* Set slot type based on SD or eMMC */ 708 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 709 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 710 711 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 712 ctl_cfg_2); 713 714 /* Enable tuning for SDR50 */ 715 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 716 TUNINGFORSDR50_MASK); 717 718 ret = sdhci_setup_host(host); 719 if (ret) 720 return ret; 721 722 ret = sdhci_am654_cqe_add_host(host); 723 if (ret) 724 goto err_cleanup_host; 725 726 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 727 if (ret) 728 goto err_cleanup_host; 729 730 ret = __sdhci_add_host(host); 731 if (ret) 732 goto err_cleanup_host; 733 734 return 0; 735 736 err_cleanup_host: 737 sdhci_cleanup_host(host); 738 return ret; 739 } 740 741 static int sdhci_am654_get_of_property(struct platform_device *pdev, 742 struct sdhci_am654_data *sdhci_am654) 743 { 744 struct device *dev = &pdev->dev; 745 int drv_strength; 746 int ret; 747 748 if (sdhci_am654->flags & DLL_PRESENT) { 749 ret = device_property_read_u32(dev, "ti,trm-icp", 750 &sdhci_am654->trm_icp); 751 if (ret) 752 return ret; 753 754 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 755 &drv_strength); 756 if (ret) 757 return ret; 758 759 switch (drv_strength) { 760 case 50: 761 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 762 break; 763 case 33: 764 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 765 break; 766 case 66: 767 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 768 break; 769 case 100: 770 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 771 break; 772 case 40: 773 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 774 break; 775 default: 776 dev_err(dev, "Invalid driver strength\n"); 777 return -EINVAL; 778 } 779 } 780 781 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 782 device_property_read_u32(dev, "ti,clkbuf-sel", 783 &sdhci_am654->clkbuf_sel); 784 785 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 786 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 787 788 sdhci_get_of_property(pdev); 789 790 return 0; 791 } 792 793 static const struct of_device_id sdhci_am654_of_match[] = { 794 { 795 .compatible = "ti,am654-sdhci-5.1", 796 .data = &sdhci_am654_drvdata, 797 }, 798 { 799 .compatible = "ti,j721e-sdhci-8bit", 800 .data = &sdhci_j721e_8bit_drvdata, 801 }, 802 { 803 .compatible = "ti,j721e-sdhci-4bit", 804 .data = &sdhci_j721e_4bit_drvdata, 805 }, 806 { 807 .compatible = "ti,am64-sdhci-8bit", 808 .data = &sdhci_j721e_8bit_drvdata, 809 }, 810 { 811 .compatible = "ti,am64-sdhci-4bit", 812 .data = &sdhci_j721e_4bit_drvdata, 813 }, 814 { 815 .compatible = "ti,am62-sdhci", 816 .data = &sdhci_j721e_4bit_drvdata, 817 }, 818 { /* sentinel */ } 819 }; 820 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 821 822 static int sdhci_am654_probe(struct platform_device *pdev) 823 { 824 const struct sdhci_am654_driver_data *drvdata; 825 const struct soc_device_attribute *soc; 826 struct sdhci_pltfm_host *pltfm_host; 827 struct sdhci_am654_data *sdhci_am654; 828 const struct of_device_id *match; 829 struct sdhci_host *host; 830 struct clk *clk_xin; 831 struct device *dev = &pdev->dev; 832 void __iomem *base; 833 int ret; 834 835 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 836 drvdata = match->data; 837 838 /* Update drvdata based on SoC revision */ 839 soc = soc_device_match(sdhci_am654_devices); 840 if (soc && soc->data) 841 drvdata = soc->data; 842 843 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 844 if (IS_ERR(host)) 845 return PTR_ERR(host); 846 847 pltfm_host = sdhci_priv(host); 848 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 849 sdhci_am654->flags = drvdata->flags; 850 851 clk_xin = devm_clk_get(dev, "clk_xin"); 852 if (IS_ERR(clk_xin)) { 853 dev_err(dev, "clk_xin clock not found.\n"); 854 ret = PTR_ERR(clk_xin); 855 goto err_pltfm_free; 856 } 857 858 pltfm_host->clk = clk_xin; 859 860 base = devm_platform_ioremap_resource(pdev, 1); 861 if (IS_ERR(base)) { 862 ret = PTR_ERR(base); 863 goto err_pltfm_free; 864 } 865 866 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 867 &sdhci_am654_regmap_config); 868 if (IS_ERR(sdhci_am654->base)) { 869 dev_err(dev, "Failed to initialize regmap\n"); 870 ret = PTR_ERR(sdhci_am654->base); 871 goto err_pltfm_free; 872 } 873 874 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 875 if (ret) 876 goto err_pltfm_free; 877 878 ret = mmc_of_parse(host->mmc); 879 if (ret) { 880 dev_err_probe(dev, ret, "parsing dt failed\n"); 881 goto err_pltfm_free; 882 } 883 884 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 885 886 pm_runtime_get_noresume(dev); 887 ret = pm_runtime_set_active(dev); 888 if (ret) 889 goto pm_put; 890 pm_runtime_enable(dev); 891 ret = clk_prepare_enable(pltfm_host->clk); 892 if (ret) 893 goto pm_disable; 894 895 ret = sdhci_am654_init(host); 896 if (ret) 897 goto clk_disable; 898 899 /* Setting up autosuspend */ 900 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 901 pm_runtime_use_autosuspend(dev); 902 pm_runtime_mark_last_busy(dev); 903 pm_runtime_put_autosuspend(dev); 904 return 0; 905 906 clk_disable: 907 clk_disable_unprepare(pltfm_host->clk); 908 pm_disable: 909 pm_runtime_disable(dev); 910 pm_put: 911 pm_runtime_put_noidle(dev); 912 err_pltfm_free: 913 sdhci_pltfm_free(pdev); 914 return ret; 915 } 916 917 static void sdhci_am654_remove(struct platform_device *pdev) 918 { 919 struct sdhci_host *host = platform_get_drvdata(pdev); 920 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 921 struct device *dev = &pdev->dev; 922 int ret; 923 924 ret = pm_runtime_get_sync(dev); 925 if (ret < 0) 926 dev_err(dev, "pm_runtime_get_sync() Failed\n"); 927 928 sdhci_remove_host(host, true); 929 clk_disable_unprepare(pltfm_host->clk); 930 pm_runtime_disable(dev); 931 pm_runtime_put_noidle(dev); 932 sdhci_pltfm_free(pdev); 933 } 934 935 #ifdef CONFIG_PM 936 static int sdhci_am654_restore(struct sdhci_host *host) 937 { 938 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 939 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 940 u32 ctl_cfg_2 = 0; 941 u32 val; 942 int ret; 943 944 if (sdhci_am654->flags & DLL_CALIB) { 945 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 946 if (~val & CALDONE_MASK) { 947 /* Calibrate IO lines */ 948 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 949 PDB_MASK, PDB_MASK); 950 ret = regmap_read_poll_timeout(sdhci_am654->base, 951 PHY_STAT1, val, 952 val & CALDONE_MASK, 953 1, 20); 954 if (ret) 955 return ret; 956 } 957 } 958 959 /* Enable pins by setting IO mux to 0 */ 960 if (sdhci_am654->flags & IOMUX_PRESENT) 961 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 962 IOMUX_ENABLE_MASK, 0); 963 964 /* Set slot type based on SD or eMMC */ 965 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 966 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 967 968 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 969 ctl_cfg_2); 970 971 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 972 if (~val & TUNINGFORSDR50_MASK) 973 /* Enable tuning for SDR50 */ 974 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 975 TUNINGFORSDR50_MASK); 976 977 return 0; 978 } 979 980 static int sdhci_am654_runtime_suspend(struct device *dev) 981 { 982 struct sdhci_host *host = dev_get_drvdata(dev); 983 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 984 int ret; 985 986 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 987 mmc_retune_needed(host->mmc); 988 989 ret = cqhci_suspend(host->mmc); 990 if (ret) 991 return ret; 992 993 ret = sdhci_runtime_suspend_host(host); 994 if (ret) 995 return ret; 996 997 /* disable the clock */ 998 clk_disable_unprepare(pltfm_host->clk); 999 return 0; 1000 } 1001 1002 static int sdhci_am654_runtime_resume(struct device *dev) 1003 { 1004 struct sdhci_host *host = dev_get_drvdata(dev); 1005 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1006 int ret; 1007 1008 /* Enable the clock */ 1009 ret = clk_prepare_enable(pltfm_host->clk); 1010 if (ret) 1011 return ret; 1012 1013 ret = sdhci_am654_restore(host); 1014 if (ret) 1015 return ret; 1016 1017 ret = sdhci_runtime_resume_host(host, 0); 1018 if (ret) 1019 return ret; 1020 1021 ret = cqhci_resume(host->mmc); 1022 if (ret) 1023 return ret; 1024 1025 return 0; 1026 } 1027 #endif 1028 1029 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 1030 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 1031 sdhci_am654_runtime_resume, NULL) 1032 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1033 pm_runtime_force_resume) 1034 }; 1035 1036 static struct platform_driver sdhci_am654_driver = { 1037 .driver = { 1038 .name = "sdhci-am654", 1039 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1040 .pm = &sdhci_am654_dev_pm_ops, 1041 .of_match_table = sdhci_am654_of_match, 1042 }, 1043 .probe = sdhci_am654_probe, 1044 .remove_new = sdhci_am654_remove, 1045 }; 1046 1047 module_platform_driver(sdhci_am654_driver); 1048 1049 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 1050 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 1051 MODULE_LICENSE("GPL"); 1052