1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 20 21 /* CTL_CFG Registers */ 22 #define CTL_CFG_2 0x14 23 #define CTL_CFG_3 0x18 24 25 #define SLOTTYPE_MASK GENMASK(31, 30) 26 #define SLOTTYPE_EMBEDDED BIT(30) 27 #define TUNINGFORSDR50_MASK BIT(13) 28 29 /* PHY Registers */ 30 #define PHY_CTRL1 0x100 31 #define PHY_CTRL2 0x104 32 #define PHY_CTRL3 0x108 33 #define PHY_CTRL4 0x10C 34 #define PHY_CTRL5 0x110 35 #define PHY_CTRL6 0x114 36 #define PHY_STAT1 0x130 37 #define PHY_STAT2 0x134 38 39 #define IOMUX_ENABLE_SHIFT 31 40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 41 #define OTAPDLYENA_SHIFT 20 42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 43 #define OTAPDLYSEL_SHIFT 12 44 #define OTAPDLYSEL_MASK GENMASK(15, 12) 45 #define STRBSEL_SHIFT 24 46 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 47 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 48 #define SEL50_SHIFT 8 49 #define SEL50_MASK BIT(SEL50_SHIFT) 50 #define SEL100_SHIFT 9 51 #define SEL100_MASK BIT(SEL100_SHIFT) 52 #define FREQSEL_SHIFT 8 53 #define FREQSEL_MASK GENMASK(10, 8) 54 #define CLKBUFSEL_SHIFT 0 55 #define CLKBUFSEL_MASK GENMASK(2, 0) 56 #define DLL_TRIM_ICP_SHIFT 4 57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 58 #define DR_TY_SHIFT 20 59 #define DR_TY_MASK GENMASK(22, 20) 60 #define ENDLL_SHIFT 1 61 #define ENDLL_MASK BIT(ENDLL_SHIFT) 62 #define DLLRDY_SHIFT 0 63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 64 #define PDB_SHIFT 0 65 #define PDB_MASK BIT(PDB_SHIFT) 66 #define CALDONE_SHIFT 1 67 #define CALDONE_MASK BIT(CALDONE_SHIFT) 68 #define RETRIM_SHIFT 17 69 #define RETRIM_MASK BIT(RETRIM_SHIFT) 70 #define SELDLYTXCLK_SHIFT 17 71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72 #define SELDLYRXCLK_SHIFT 16 73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74 #define ITAPDLYSEL_SHIFT 0 75 #define ITAPDLYSEL_MASK GENMASK(4, 0) 76 #define ITAPDLYENA_SHIFT 8 77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78 #define ITAPCHGWIN_SHIFT 9 79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 80 81 #define DRIVER_STRENGTH_50_OHM 0x0 82 #define DRIVER_STRENGTH_33_OHM 0x1 83 #define DRIVER_STRENGTH_66_OHM 0x2 84 #define DRIVER_STRENGTH_100_OHM 0x3 85 #define DRIVER_STRENGTH_40_OHM 0x4 86 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 89 90 /* Command Queue Host Controller Interface Base address */ 91 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92 93 static struct regmap_config sdhci_am654_regmap_config = { 94 .reg_bits = 32, 95 .val_bits = 32, 96 .reg_stride = 4, 97 .fast_io = true, 98 }; 99 100 struct timing_data { 101 const char *otap_binding; 102 const char *itap_binding; 103 u32 capability; 104 }; 105 106 static const struct timing_data td[] = { 107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108 "ti,itap-del-sel-legacy", 109 0}, 110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111 "ti,itap-del-sel-mmc-hs", 112 MMC_CAP_MMC_HIGHSPEED}, 113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114 "ti,itap-del-sel-sd-hs", 115 MMC_CAP_SD_HIGHSPEED}, 116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117 "ti,itap-del-sel-sdr12", 118 MMC_CAP_UHS_SDR12}, 119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120 "ti,itap-del-sel-sdr25", 121 MMC_CAP_UHS_SDR25}, 122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123 NULL, 124 MMC_CAP_UHS_SDR50}, 125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126 NULL, 127 MMC_CAP_UHS_SDR104}, 128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129 NULL, 130 MMC_CAP_UHS_DDR50}, 131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132 "ti,itap-del-sel-ddr52", 133 MMC_CAP_DDR}, 134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135 NULL, 136 MMC_CAP2_HS200}, 137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138 NULL, 139 MMC_CAP2_HS400}, 140 }; 141 142 struct sdhci_am654_data { 143 struct regmap *base; 144 int otap_del_sel[ARRAY_SIZE(td)]; 145 int itap_del_sel[ARRAY_SIZE(td)]; 146 u32 itap_del_ena[ARRAY_SIZE(td)]; 147 int clkbuf_sel; 148 int trm_icp; 149 int drv_strength; 150 int strb_sel; 151 u32 flags; 152 u32 quirks; 153 bool dll_enable; 154 155 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 156 }; 157 158 struct window { 159 u8 start; 160 u8 end; 161 u8 length; 162 }; 163 164 struct sdhci_am654_driver_data { 165 const struct sdhci_pltfm_data *pdata; 166 u32 flags; 167 #define IOMUX_PRESENT (1 << 0) 168 #define FREQSEL_2_BIT (1 << 1) 169 #define STRBSEL_4_BIT (1 << 2) 170 #define DLL_PRESENT (1 << 3) 171 #define DLL_CALIB (1 << 4) 172 }; 173 174 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 175 { 176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 178 int sel50, sel100, freqsel; 179 u32 mask, val; 180 int ret; 181 182 /* Disable delay chain mode */ 183 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 184 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 185 186 if (sdhci_am654->flags & FREQSEL_2_BIT) { 187 switch (clock) { 188 case 200000000: 189 sel50 = 0; 190 sel100 = 0; 191 break; 192 case 100000000: 193 sel50 = 0; 194 sel100 = 1; 195 break; 196 default: 197 sel50 = 1; 198 sel100 = 0; 199 } 200 201 /* Configure PHY DLL frequency */ 202 mask = SEL50_MASK | SEL100_MASK; 203 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 204 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 205 206 } else { 207 switch (clock) { 208 case 200000000: 209 freqsel = 0x0; 210 break; 211 default: 212 freqsel = 0x4; 213 } 214 215 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 216 freqsel << FREQSEL_SHIFT); 217 } 218 /* Configure DLL TRIM */ 219 mask = DLL_TRIM_ICP_MASK; 220 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 221 222 /* Configure DLL driver strength */ 223 mask |= DR_TY_MASK; 224 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 225 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 226 227 /* Enable DLL */ 228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 229 0x1 << ENDLL_SHIFT); 230 /* 231 * Poll for DLL ready. Use a one second timeout. 232 * Works in all experiments done so far 233 */ 234 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 235 val & DLLRDY_MASK, 1000, 1000000); 236 if (ret) { 237 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 238 return; 239 } 240 } 241 242 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 243 u32 itapdly, u32 enable) 244 { 245 /* Set ITAPCHGWIN before writing to ITAPDLY */ 246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 247 1 << ITAPCHGWIN_SHIFT); 248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 249 enable << ITAPDLYENA_SHIFT); 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 251 itapdly << ITAPDLYSEL_SHIFT); 252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 253 } 254 255 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 256 unsigned char timing) 257 { 258 u32 mask, val; 259 260 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 261 262 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 263 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 264 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 265 266 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 267 sdhci_am654->itap_del_ena[timing]); 268 } 269 270 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 271 { 272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 273 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 274 unsigned char timing = host->mmc->ios.timing; 275 u32 otap_del_sel; 276 u32 mask, val; 277 278 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 279 280 sdhci_set_clock(host, clock); 281 282 /* Setup DLL Output TAP delay */ 283 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 284 285 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 286 val = (0x1 << OTAPDLYENA_SHIFT) | 287 (otap_del_sel << OTAPDLYSEL_SHIFT); 288 289 /* Write to STRBSEL for HS400 speed mode */ 290 if (timing == MMC_TIMING_MMC_HS400) { 291 if (sdhci_am654->flags & STRBSEL_4_BIT) 292 mask |= STRBSEL_4BIT_MASK; 293 else 294 mask |= STRBSEL_8BIT_MASK; 295 296 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 297 } 298 299 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 300 301 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 302 sdhci_am654_setup_dll(host, clock); 303 sdhci_am654->dll_enable = true; 304 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 305 sdhci_am654->itap_del_ena[timing]); 306 } else { 307 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 308 sdhci_am654->dll_enable = false; 309 } 310 311 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 312 sdhci_am654->clkbuf_sel); 313 } 314 315 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 316 unsigned int clock) 317 { 318 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 319 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 320 unsigned char timing = host->mmc->ios.timing; 321 u32 otap_del_sel; 322 u32 itap_del_ena; 323 u32 mask, val; 324 325 /* Setup DLL Output TAP delay */ 326 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 327 328 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 329 val = (0x1 << OTAPDLYENA_SHIFT) | 330 (otap_del_sel << OTAPDLYSEL_SHIFT); 331 332 itap_del_ena = sdhci_am654->itap_del_ena[timing]; 333 334 mask |= ITAPDLYENA_MASK; 335 val |= (itap_del_ena << ITAPDLYENA_SHIFT); 336 337 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 338 339 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 340 sdhci_am654->clkbuf_sel); 341 342 sdhci_set_clock(host, clock); 343 } 344 345 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 346 { 347 writeb(val, host->ioaddr + reg); 348 usleep_range(1000, 10000); 349 return readb(host->ioaddr + reg); 350 } 351 352 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 353 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 354 { 355 unsigned char timing = host->mmc->ios.timing; 356 u8 pwr; 357 int ret; 358 359 if (reg == SDHCI_HOST_CONTROL) { 360 switch (timing) { 361 /* 362 * According to the data manual, HISPD bit 363 * should not be set in these speed modes. 364 */ 365 case MMC_TIMING_SD_HS: 366 case MMC_TIMING_MMC_HS: 367 val &= ~SDHCI_CTRL_HISPD; 368 } 369 } 370 371 writeb(val, host->ioaddr + reg); 372 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 373 /* 374 * Power on will not happen until the card detect debounce 375 * timer expires. Wait at least 1.5 seconds for the power on 376 * bit to be set 377 */ 378 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 379 pwr & SDHCI_POWER_ON, 0, 380 MAX_POWER_ON_TIMEOUT, false, host, val, 381 reg); 382 if (ret) 383 dev_info(mmc_dev(host->mmc), "Power on failed\n"); 384 } 385 } 386 387 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 388 { 389 u8 ctrl; 390 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 391 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 392 393 sdhci_and_cqhci_reset(host, mask); 394 395 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 396 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 397 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 398 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 399 } 400 } 401 402 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 403 { 404 struct sdhci_host *host = mmc_priv(mmc); 405 int err = sdhci_execute_tuning(mmc, opcode); 406 407 if (err) 408 return err; 409 /* 410 * Tuning data remains in the buffer after tuning. 411 * Do a command and data reset to get rid of it 412 */ 413 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 414 415 return 0; 416 } 417 418 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 419 { 420 int cmd_error = 0; 421 int data_error = 0; 422 423 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 424 return intmask; 425 426 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 427 428 return 0; 429 } 430 431 #define ITAPDLY_LENGTH 32 432 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 433 434 static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 435 *fail_window, u8 num_fails, bool circular_buffer) 436 { 437 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 438 u8 first_fail_start = 0, last_fail_end = 0; 439 struct device *dev = mmc_dev(host->mmc); 440 struct window pass_window = {0, 0, 0}; 441 int prev_fail_end = -1; 442 u8 i; 443 444 if (!num_fails) 445 return ITAPDLY_LAST_INDEX >> 1; 446 447 if (fail_window->length == ITAPDLY_LENGTH) { 448 dev_err(dev, "No passing ITAPDLY, return 0\n"); 449 return 0; 450 } 451 452 first_fail_start = fail_window->start; 453 last_fail_end = fail_window[num_fails - 1].end; 454 455 for (i = 0; i < num_fails; i++) { 456 start_fail = fail_window[i].start; 457 end_fail = fail_window[i].end; 458 pass_length = start_fail - (prev_fail_end + 1); 459 460 if (pass_length > pass_window.length) { 461 pass_window.start = prev_fail_end + 1; 462 pass_window.length = pass_length; 463 } 464 prev_fail_end = end_fail; 465 } 466 467 if (!circular_buffer) 468 pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 469 else 470 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 471 472 if (pass_length > pass_window.length) { 473 pass_window.start = last_fail_end + 1; 474 pass_window.length = pass_length; 475 } 476 477 if (!circular_buffer) 478 itap = pass_window.start + (pass_window.length >> 1); 479 else 480 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 481 482 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 483 } 484 485 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 486 u32 opcode) 487 { 488 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 489 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 490 unsigned char timing = host->mmc->ios.timing; 491 struct window fail_window[ITAPDLY_LENGTH]; 492 u8 curr_pass, itap; 493 u8 fail_index = 0; 494 u8 prev_pass = 1; 495 496 memset(fail_window, 0, sizeof(fail_window)); 497 498 /* Enable ITAPDLY */ 499 sdhci_am654->itap_del_ena[timing] = 0x1; 500 501 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 502 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 503 504 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 505 506 if (!curr_pass && prev_pass) 507 fail_window[fail_index].start = itap; 508 509 if (!curr_pass) { 510 fail_window[fail_index].end = itap; 511 fail_window[fail_index].length++; 512 } 513 514 if (curr_pass && !prev_pass) 515 fail_index++; 516 517 prev_pass = curr_pass; 518 } 519 520 if (fail_window[fail_index].length != 0) 521 fail_index++; 522 523 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 524 sdhci_am654->dll_enable); 525 526 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 527 528 return 0; 529 } 530 531 static struct sdhci_ops sdhci_am654_ops = { 532 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 533 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 534 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 535 .set_uhs_signaling = sdhci_set_uhs_signaling, 536 .set_bus_width = sdhci_set_bus_width, 537 .set_power = sdhci_set_power_and_bus_voltage, 538 .set_clock = sdhci_am654_set_clock, 539 .write_b = sdhci_am654_write_b, 540 .irq = sdhci_am654_cqhci_irq, 541 .reset = sdhci_and_cqhci_reset, 542 }; 543 544 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 545 .ops = &sdhci_am654_ops, 546 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 547 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 548 }; 549 550 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 551 .pdata = &sdhci_am654_pdata, 552 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 553 DLL_CALIB, 554 }; 555 556 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 557 .pdata = &sdhci_am654_pdata, 558 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 559 }; 560 561 static struct sdhci_ops sdhci_j721e_8bit_ops = { 562 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 563 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 564 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 565 .set_uhs_signaling = sdhci_set_uhs_signaling, 566 .set_bus_width = sdhci_set_bus_width, 567 .set_power = sdhci_set_power_and_bus_voltage, 568 .set_clock = sdhci_am654_set_clock, 569 .write_b = sdhci_am654_write_b, 570 .irq = sdhci_am654_cqhci_irq, 571 .reset = sdhci_and_cqhci_reset, 572 }; 573 574 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 575 .ops = &sdhci_j721e_8bit_ops, 576 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 577 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 578 }; 579 580 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 581 .pdata = &sdhci_j721e_8bit_pdata, 582 .flags = DLL_PRESENT | DLL_CALIB, 583 }; 584 585 static struct sdhci_ops sdhci_j721e_4bit_ops = { 586 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 587 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 588 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 589 .set_uhs_signaling = sdhci_set_uhs_signaling, 590 .set_bus_width = sdhci_set_bus_width, 591 .set_power = sdhci_set_power_and_bus_voltage, 592 .set_clock = sdhci_j721e_4bit_set_clock, 593 .write_b = sdhci_am654_write_b, 594 .irq = sdhci_am654_cqhci_irq, 595 .reset = sdhci_am654_reset, 596 }; 597 598 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 599 .ops = &sdhci_j721e_4bit_ops, 600 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 601 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 602 }; 603 604 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 605 .pdata = &sdhci_j721e_4bit_pdata, 606 .flags = IOMUX_PRESENT, 607 }; 608 609 static const struct soc_device_attribute sdhci_am654_devices[] = { 610 { .family = "AM65X", 611 .revision = "SR1.0", 612 .data = &sdhci_am654_sr1_drvdata 613 }, 614 {/* sentinel */} 615 }; 616 617 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 618 { 619 sdhci_dumpregs(mmc_priv(mmc)); 620 } 621 622 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 623 .enable = sdhci_cqe_enable, 624 .disable = sdhci_cqe_disable, 625 .dumpregs = sdhci_am654_dumpregs, 626 }; 627 628 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 629 { 630 struct cqhci_host *cq_host; 631 632 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 633 GFP_KERNEL); 634 if (!cq_host) 635 return -ENOMEM; 636 637 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 638 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 639 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 640 cq_host->ops = &sdhci_am654_cqhci_ops; 641 642 host->mmc->caps2 |= MMC_CAP2_CQE; 643 644 return cqhci_init(cq_host, host->mmc, 1); 645 } 646 647 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 648 struct sdhci_am654_data *sdhci_am654) 649 { 650 struct device *dev = mmc_dev(host->mmc); 651 int i; 652 int ret; 653 654 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) { 655 656 ret = device_property_read_u32(dev, td[i].otap_binding, 657 &sdhci_am654->otap_del_sel[i]); 658 if (ret) { 659 if (i == MMC_TIMING_LEGACY) { 660 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); 661 return ret; 662 } 663 dev_dbg(dev, "Couldn't find %s\n", 664 td[i].otap_binding); 665 /* 666 * Remove the corresponding capability 667 * if an otap-del-sel value is not found 668 */ 669 if (i <= MMC_TIMING_MMC_DDR52) 670 host->mmc->caps &= ~td[i].capability; 671 else 672 host->mmc->caps2 &= ~td[i].capability; 673 } 674 675 if (td[i].itap_binding) { 676 ret = device_property_read_u32(dev, td[i].itap_binding, 677 &sdhci_am654->itap_del_sel[i]); 678 if (!ret) 679 sdhci_am654->itap_del_ena[i] = 0x1; 680 } 681 } 682 683 return 0; 684 } 685 686 static int sdhci_am654_init(struct sdhci_host *host) 687 { 688 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 689 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 690 u32 ctl_cfg_2 = 0; 691 u32 mask; 692 u32 val; 693 int ret; 694 695 /* Reset OTAP to default value */ 696 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 697 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 698 699 if (sdhci_am654->flags & DLL_CALIB) { 700 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 701 if (~val & CALDONE_MASK) { 702 /* Calibrate IO lines */ 703 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 704 PDB_MASK, PDB_MASK); 705 ret = regmap_read_poll_timeout(sdhci_am654->base, 706 PHY_STAT1, val, 707 val & CALDONE_MASK, 708 1, 20); 709 if (ret) 710 return ret; 711 } 712 } 713 714 /* Enable pins by setting IO mux to 0 */ 715 if (sdhci_am654->flags & IOMUX_PRESENT) 716 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 717 IOMUX_ENABLE_MASK, 0); 718 719 /* Set slot type based on SD or eMMC */ 720 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 721 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 722 723 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 724 ctl_cfg_2); 725 726 /* Enable tuning for SDR50 */ 727 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 728 TUNINGFORSDR50_MASK); 729 730 ret = sdhci_setup_host(host); 731 if (ret) 732 return ret; 733 734 ret = sdhci_am654_cqe_add_host(host); 735 if (ret) 736 goto err_cleanup_host; 737 738 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 739 if (ret) 740 goto err_cleanup_host; 741 742 ret = __sdhci_add_host(host); 743 if (ret) 744 goto err_cleanup_host; 745 746 return 0; 747 748 err_cleanup_host: 749 sdhci_cleanup_host(host); 750 return ret; 751 } 752 753 static int sdhci_am654_get_of_property(struct platform_device *pdev, 754 struct sdhci_am654_data *sdhci_am654) 755 { 756 struct device *dev = &pdev->dev; 757 int drv_strength; 758 int ret; 759 760 if (sdhci_am654->flags & DLL_PRESENT) { 761 ret = device_property_read_u32(dev, "ti,trm-icp", 762 &sdhci_am654->trm_icp); 763 if (ret) 764 return ret; 765 766 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 767 &drv_strength); 768 if (ret) 769 return ret; 770 771 switch (drv_strength) { 772 case 50: 773 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 774 break; 775 case 33: 776 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 777 break; 778 case 66: 779 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 780 break; 781 case 100: 782 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 783 break; 784 case 40: 785 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 786 break; 787 default: 788 dev_err(dev, "Invalid driver strength\n"); 789 return -EINVAL; 790 } 791 } 792 793 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 794 device_property_read_u32(dev, "ti,clkbuf-sel", 795 &sdhci_am654->clkbuf_sel); 796 797 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 798 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 799 800 sdhci_get_of_property(pdev); 801 802 return 0; 803 } 804 805 static const struct of_device_id sdhci_am654_of_match[] = { 806 { 807 .compatible = "ti,am654-sdhci-5.1", 808 .data = &sdhci_am654_drvdata, 809 }, 810 { 811 .compatible = "ti,j721e-sdhci-8bit", 812 .data = &sdhci_j721e_8bit_drvdata, 813 }, 814 { 815 .compatible = "ti,j721e-sdhci-4bit", 816 .data = &sdhci_j721e_4bit_drvdata, 817 }, 818 { 819 .compatible = "ti,am64-sdhci-8bit", 820 .data = &sdhci_j721e_8bit_drvdata, 821 }, 822 { 823 .compatible = "ti,am64-sdhci-4bit", 824 .data = &sdhci_j721e_4bit_drvdata, 825 }, 826 { 827 .compatible = "ti,am62-sdhci", 828 .data = &sdhci_j721e_4bit_drvdata, 829 }, 830 { /* sentinel */ } 831 }; 832 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 833 834 static int sdhci_am654_probe(struct platform_device *pdev) 835 { 836 const struct sdhci_am654_driver_data *drvdata; 837 const struct soc_device_attribute *soc; 838 struct sdhci_pltfm_host *pltfm_host; 839 struct sdhci_am654_data *sdhci_am654; 840 const struct of_device_id *match; 841 struct sdhci_host *host; 842 struct clk *clk_xin; 843 struct device *dev = &pdev->dev; 844 void __iomem *base; 845 int ret; 846 847 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 848 drvdata = match->data; 849 850 /* Update drvdata based on SoC revision */ 851 soc = soc_device_match(sdhci_am654_devices); 852 if (soc && soc->data) 853 drvdata = soc->data; 854 855 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 856 if (IS_ERR(host)) 857 return PTR_ERR(host); 858 859 pltfm_host = sdhci_priv(host); 860 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 861 sdhci_am654->flags = drvdata->flags; 862 863 clk_xin = devm_clk_get(dev, "clk_xin"); 864 if (IS_ERR(clk_xin)) { 865 dev_err(dev, "clk_xin clock not found.\n"); 866 ret = PTR_ERR(clk_xin); 867 goto err_pltfm_free; 868 } 869 870 pltfm_host->clk = clk_xin; 871 872 base = devm_platform_ioremap_resource(pdev, 1); 873 if (IS_ERR(base)) { 874 ret = PTR_ERR(base); 875 goto err_pltfm_free; 876 } 877 878 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 879 &sdhci_am654_regmap_config); 880 if (IS_ERR(sdhci_am654->base)) { 881 dev_err(dev, "Failed to initialize regmap\n"); 882 ret = PTR_ERR(sdhci_am654->base); 883 goto err_pltfm_free; 884 } 885 886 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 887 if (ret) 888 goto err_pltfm_free; 889 890 ret = mmc_of_parse(host->mmc); 891 if (ret) { 892 dev_err_probe(dev, ret, "parsing dt failed\n"); 893 goto err_pltfm_free; 894 } 895 896 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 897 898 pm_runtime_get_noresume(dev); 899 ret = pm_runtime_set_active(dev); 900 if (ret) 901 goto pm_put; 902 pm_runtime_enable(dev); 903 ret = clk_prepare_enable(pltfm_host->clk); 904 if (ret) 905 goto pm_disable; 906 907 ret = sdhci_am654_init(host); 908 if (ret) 909 goto clk_disable; 910 911 /* Setting up autosuspend */ 912 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 913 pm_runtime_use_autosuspend(dev); 914 pm_runtime_mark_last_busy(dev); 915 pm_runtime_put_autosuspend(dev); 916 return 0; 917 918 clk_disable: 919 clk_disable_unprepare(pltfm_host->clk); 920 pm_disable: 921 pm_runtime_disable(dev); 922 pm_put: 923 pm_runtime_put_noidle(dev); 924 err_pltfm_free: 925 sdhci_pltfm_free(pdev); 926 return ret; 927 } 928 929 static void sdhci_am654_remove(struct platform_device *pdev) 930 { 931 struct sdhci_host *host = platform_get_drvdata(pdev); 932 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 933 struct device *dev = &pdev->dev; 934 int ret; 935 936 ret = pm_runtime_get_sync(dev); 937 if (ret < 0) 938 dev_err(dev, "pm_runtime_get_sync() Failed\n"); 939 940 sdhci_remove_host(host, true); 941 clk_disable_unprepare(pltfm_host->clk); 942 pm_runtime_disable(dev); 943 pm_runtime_put_noidle(dev); 944 sdhci_pltfm_free(pdev); 945 } 946 947 #ifdef CONFIG_PM 948 static int sdhci_am654_restore(struct sdhci_host *host) 949 { 950 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 951 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 952 u32 ctl_cfg_2 = 0; 953 u32 val; 954 int ret; 955 956 if (sdhci_am654->flags & DLL_CALIB) { 957 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 958 if (~val & CALDONE_MASK) { 959 /* Calibrate IO lines */ 960 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 961 PDB_MASK, PDB_MASK); 962 ret = regmap_read_poll_timeout(sdhci_am654->base, 963 PHY_STAT1, val, 964 val & CALDONE_MASK, 965 1, 20); 966 if (ret) 967 return ret; 968 } 969 } 970 971 /* Enable pins by setting IO mux to 0 */ 972 if (sdhci_am654->flags & IOMUX_PRESENT) 973 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 974 IOMUX_ENABLE_MASK, 0); 975 976 /* Set slot type based on SD or eMMC */ 977 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 978 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 979 980 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 981 ctl_cfg_2); 982 983 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 984 if (~val & TUNINGFORSDR50_MASK) 985 /* Enable tuning for SDR50 */ 986 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 987 TUNINGFORSDR50_MASK); 988 989 return 0; 990 } 991 992 static int sdhci_am654_runtime_suspend(struct device *dev) 993 { 994 struct sdhci_host *host = dev_get_drvdata(dev); 995 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 996 int ret; 997 998 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 999 mmc_retune_needed(host->mmc); 1000 1001 ret = cqhci_suspend(host->mmc); 1002 if (ret) 1003 return ret; 1004 1005 ret = sdhci_runtime_suspend_host(host); 1006 if (ret) 1007 return ret; 1008 1009 /* disable the clock */ 1010 clk_disable_unprepare(pltfm_host->clk); 1011 return 0; 1012 } 1013 1014 static int sdhci_am654_runtime_resume(struct device *dev) 1015 { 1016 struct sdhci_host *host = dev_get_drvdata(dev); 1017 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1018 int ret; 1019 1020 /* Enable the clock */ 1021 ret = clk_prepare_enable(pltfm_host->clk); 1022 if (ret) 1023 return ret; 1024 1025 ret = sdhci_am654_restore(host); 1026 if (ret) 1027 return ret; 1028 1029 ret = sdhci_runtime_resume_host(host, 0); 1030 if (ret) 1031 return ret; 1032 1033 ret = cqhci_resume(host->mmc); 1034 if (ret) 1035 return ret; 1036 1037 return 0; 1038 } 1039 #endif 1040 1041 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 1042 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 1043 sdhci_am654_runtime_resume, NULL) 1044 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1045 pm_runtime_force_resume) 1046 }; 1047 1048 static struct platform_driver sdhci_am654_driver = { 1049 .driver = { 1050 .name = "sdhci-am654", 1051 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1052 .pm = &sdhci_am654_dev_pm_ops, 1053 .of_match_table = sdhci_am654_of_match, 1054 }, 1055 .probe = sdhci_am654_probe, 1056 .remove_new = sdhci_am654_remove, 1057 }; 1058 1059 module_platform_driver(sdhci_am654_driver); 1060 1061 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 1062 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 1063 MODULE_LICENSE("GPL"); 1064