1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 20 21 /* CTL_CFG Registers */ 22 #define CTL_CFG_2 0x14 23 #define CTL_CFG_3 0x18 24 25 #define SLOTTYPE_MASK GENMASK(31, 30) 26 #define SLOTTYPE_EMBEDDED BIT(30) 27 #define TUNINGFORSDR50_MASK BIT(13) 28 29 /* PHY Registers */ 30 #define PHY_CTRL1 0x100 31 #define PHY_CTRL2 0x104 32 #define PHY_CTRL3 0x108 33 #define PHY_CTRL4 0x10C 34 #define PHY_CTRL5 0x110 35 #define PHY_CTRL6 0x114 36 #define PHY_STAT1 0x130 37 #define PHY_STAT2 0x134 38 39 #define IOMUX_ENABLE_SHIFT 31 40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 41 #define OTAPDLYENA_SHIFT 20 42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 43 #define OTAPDLYSEL_SHIFT 12 44 #define OTAPDLYSEL_MASK GENMASK(15, 12) 45 #define STRBSEL_SHIFT 24 46 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 47 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 48 #define SEL50_SHIFT 8 49 #define SEL50_MASK BIT(SEL50_SHIFT) 50 #define SEL100_SHIFT 9 51 #define SEL100_MASK BIT(SEL100_SHIFT) 52 #define FREQSEL_SHIFT 8 53 #define FREQSEL_MASK GENMASK(10, 8) 54 #define CLKBUFSEL_SHIFT 0 55 #define CLKBUFSEL_MASK GENMASK(2, 0) 56 #define DLL_TRIM_ICP_SHIFT 4 57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 58 #define DR_TY_SHIFT 20 59 #define DR_TY_MASK GENMASK(22, 20) 60 #define ENDLL_SHIFT 1 61 #define ENDLL_MASK BIT(ENDLL_SHIFT) 62 #define DLLRDY_SHIFT 0 63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 64 #define PDB_SHIFT 0 65 #define PDB_MASK BIT(PDB_SHIFT) 66 #define CALDONE_SHIFT 1 67 #define CALDONE_MASK BIT(CALDONE_SHIFT) 68 #define RETRIM_SHIFT 17 69 #define RETRIM_MASK BIT(RETRIM_SHIFT) 70 #define SELDLYTXCLK_SHIFT 17 71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72 #define SELDLYRXCLK_SHIFT 16 73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74 #define ITAPDLYSEL_SHIFT 0 75 #define ITAPDLYSEL_MASK GENMASK(4, 0) 76 #define ITAPDLYENA_SHIFT 8 77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78 #define ITAPCHGWIN_SHIFT 9 79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 80 81 #define DRIVER_STRENGTH_50_OHM 0x0 82 #define DRIVER_STRENGTH_33_OHM 0x1 83 #define DRIVER_STRENGTH_66_OHM 0x2 84 #define DRIVER_STRENGTH_100_OHM 0x3 85 #define DRIVER_STRENGTH_40_OHM 0x4 86 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 89 90 /* Command Queue Host Controller Interface Base address */ 91 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92 93 static struct regmap_config sdhci_am654_regmap_config = { 94 .reg_bits = 32, 95 .val_bits = 32, 96 .reg_stride = 4, 97 .fast_io = true, 98 }; 99 100 struct timing_data { 101 const char *otap_binding; 102 const char *itap_binding; 103 u32 capability; 104 }; 105 106 static const struct timing_data td[] = { 107 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108 "ti,itap-del-sel-legacy", 109 0}, 110 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111 "ti,itap-del-sel-mmc-hs", 112 MMC_CAP_MMC_HIGHSPEED}, 113 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114 "ti,itap-del-sel-sd-hs", 115 MMC_CAP_SD_HIGHSPEED}, 116 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117 "ti,itap-del-sel-sdr12", 118 MMC_CAP_UHS_SDR12}, 119 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120 "ti,itap-del-sel-sdr25", 121 MMC_CAP_UHS_SDR25}, 122 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123 NULL, 124 MMC_CAP_UHS_SDR50}, 125 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126 NULL, 127 MMC_CAP_UHS_SDR104}, 128 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129 NULL, 130 MMC_CAP_UHS_DDR50}, 131 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132 "ti,itap-del-sel-ddr52", 133 MMC_CAP_DDR}, 134 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135 NULL, 136 MMC_CAP2_HS200}, 137 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138 NULL, 139 MMC_CAP2_HS400}, 140 }; 141 142 struct sdhci_am654_data { 143 struct regmap *base; 144 int otap_del_sel[ARRAY_SIZE(td)]; 145 int itap_del_sel[ARRAY_SIZE(td)]; 146 u32 itap_del_ena[ARRAY_SIZE(td)]; 147 int clkbuf_sel; 148 int trm_icp; 149 int drv_strength; 150 int strb_sel; 151 u32 flags; 152 u32 quirks; 153 bool dll_enable; 154 155 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 156 }; 157 158 struct window { 159 u8 start; 160 u8 end; 161 u8 length; 162 }; 163 164 struct sdhci_am654_driver_data { 165 const struct sdhci_pltfm_data *pdata; 166 u32 flags; 167 #define IOMUX_PRESENT (1 << 0) 168 #define FREQSEL_2_BIT (1 << 1) 169 #define STRBSEL_4_BIT (1 << 2) 170 #define DLL_PRESENT (1 << 3) 171 #define DLL_CALIB (1 << 4) 172 }; 173 174 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 175 { 176 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 177 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 178 int sel50, sel100, freqsel; 179 u32 mask, val; 180 int ret; 181 182 /* Disable delay chain mode */ 183 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 184 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 185 186 if (sdhci_am654->flags & FREQSEL_2_BIT) { 187 switch (clock) { 188 case 200000000: 189 sel50 = 0; 190 sel100 = 0; 191 break; 192 case 100000000: 193 sel50 = 0; 194 sel100 = 1; 195 break; 196 default: 197 sel50 = 1; 198 sel100 = 0; 199 } 200 201 /* Configure PHY DLL frequency */ 202 mask = SEL50_MASK | SEL100_MASK; 203 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 204 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 205 206 } else { 207 switch (clock) { 208 case 200000000: 209 freqsel = 0x0; 210 break; 211 default: 212 freqsel = 0x4; 213 } 214 215 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 216 freqsel << FREQSEL_SHIFT); 217 } 218 /* Configure DLL TRIM */ 219 mask = DLL_TRIM_ICP_MASK; 220 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 221 222 /* Configure DLL driver strength */ 223 mask |= DR_TY_MASK; 224 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 225 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 226 227 /* Enable DLL */ 228 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 229 0x1 << ENDLL_SHIFT); 230 /* 231 * Poll for DLL ready. Use a one second timeout. 232 * Works in all experiments done so far 233 */ 234 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 235 val & DLLRDY_MASK, 1000, 1000000); 236 if (ret) { 237 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 238 return; 239 } 240 } 241 242 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 243 u32 itapdly, u32 enable) 244 { 245 /* Set ITAPCHGWIN before writing to ITAPDLY */ 246 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 247 1 << ITAPCHGWIN_SHIFT); 248 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 249 enable << ITAPDLYENA_SHIFT); 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 251 itapdly << ITAPDLYSEL_SHIFT); 252 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 253 } 254 255 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 256 unsigned char timing) 257 { 258 u32 mask, val; 259 260 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 261 262 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 263 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 264 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 265 266 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 267 sdhci_am654->itap_del_ena[timing]); 268 } 269 270 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 271 { 272 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 273 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 274 unsigned char timing = host->mmc->ios.timing; 275 u32 otap_del_sel; 276 u32 mask, val; 277 278 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 279 280 sdhci_set_clock(host, clock); 281 282 /* Setup DLL Output TAP delay */ 283 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 284 285 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 286 val = (0x1 << OTAPDLYENA_SHIFT) | 287 (otap_del_sel << OTAPDLYSEL_SHIFT); 288 289 /* Write to STRBSEL for HS400 speed mode */ 290 if (timing == MMC_TIMING_MMC_HS400) { 291 if (sdhci_am654->flags & STRBSEL_4_BIT) 292 mask |= STRBSEL_4BIT_MASK; 293 else 294 mask |= STRBSEL_8BIT_MASK; 295 296 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 297 } 298 299 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 300 301 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) { 302 sdhci_am654_setup_dll(host, clock); 303 sdhci_am654->dll_enable = true; 304 sdhci_am654_write_itapdly(sdhci_am654, sdhci_am654->itap_del_sel[timing], 305 sdhci_am654->itap_del_ena[timing]); 306 } else { 307 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 308 sdhci_am654->dll_enable = false; 309 } 310 311 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 312 sdhci_am654->clkbuf_sel); 313 } 314 315 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 316 unsigned int clock) 317 { 318 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 319 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 320 unsigned char timing = host->mmc->ios.timing; 321 u32 otap_del_sel; 322 u32 itap_del_ena; 323 u32 itap_del_sel; 324 u32 mask, val; 325 326 /* Setup DLL Output TAP delay */ 327 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 328 329 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 330 val = (0x1 << OTAPDLYENA_SHIFT) | 331 (otap_del_sel << OTAPDLYSEL_SHIFT); 332 333 /* Setup Input TAP delay */ 334 itap_del_ena = sdhci_am654->itap_del_ena[timing]; 335 itap_del_sel = sdhci_am654->itap_del_sel[timing]; 336 337 mask |= ITAPDLYENA_MASK | ITAPDLYSEL_MASK; 338 val |= (itap_del_ena << ITAPDLYENA_SHIFT) | 339 (itap_del_sel << ITAPDLYSEL_SHIFT); 340 341 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 342 1 << ITAPCHGWIN_SHIFT); 343 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 344 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 345 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 346 sdhci_am654->clkbuf_sel); 347 348 sdhci_set_clock(host, clock); 349 } 350 351 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 352 { 353 writeb(val, host->ioaddr + reg); 354 usleep_range(1000, 10000); 355 return readb(host->ioaddr + reg); 356 } 357 358 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 359 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 360 { 361 unsigned char timing = host->mmc->ios.timing; 362 u8 pwr; 363 int ret; 364 365 if (reg == SDHCI_HOST_CONTROL) { 366 switch (timing) { 367 /* 368 * According to the data manual, HISPD bit 369 * should not be set in these speed modes. 370 */ 371 case MMC_TIMING_SD_HS: 372 case MMC_TIMING_MMC_HS: 373 val &= ~SDHCI_CTRL_HISPD; 374 } 375 } 376 377 writeb(val, host->ioaddr + reg); 378 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 379 /* 380 * Power on will not happen until the card detect debounce 381 * timer expires. Wait at least 1.5 seconds for the power on 382 * bit to be set 383 */ 384 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 385 pwr & SDHCI_POWER_ON, 0, 386 MAX_POWER_ON_TIMEOUT, false, host, val, 387 reg); 388 if (ret) 389 dev_info(mmc_dev(host->mmc), "Power on failed\n"); 390 } 391 } 392 393 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 394 { 395 u8 ctrl; 396 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 397 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 398 399 sdhci_and_cqhci_reset(host, mask); 400 401 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 402 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 403 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 404 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 405 } 406 } 407 408 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 409 { 410 struct sdhci_host *host = mmc_priv(mmc); 411 int err = sdhci_execute_tuning(mmc, opcode); 412 413 if (err) 414 return err; 415 /* 416 * Tuning data remains in the buffer after tuning. 417 * Do a command and data reset to get rid of it 418 */ 419 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 420 421 return 0; 422 } 423 424 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 425 { 426 int cmd_error = 0; 427 int data_error = 0; 428 429 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 430 return intmask; 431 432 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 433 434 return 0; 435 } 436 437 #define ITAPDLY_LENGTH 32 438 #define ITAPDLY_LAST_INDEX (ITAPDLY_LENGTH - 1) 439 440 static u32 sdhci_am654_calculate_itap(struct sdhci_host *host, struct window 441 *fail_window, u8 num_fails, bool circular_buffer) 442 { 443 u8 itap = 0, start_fail = 0, end_fail = 0, pass_length = 0; 444 u8 first_fail_start = 0, last_fail_end = 0; 445 struct device *dev = mmc_dev(host->mmc); 446 struct window pass_window = {0, 0, 0}; 447 int prev_fail_end = -1; 448 u8 i; 449 450 if (!num_fails) 451 return ITAPDLY_LAST_INDEX >> 1; 452 453 if (fail_window->length == ITAPDLY_LENGTH) { 454 dev_err(dev, "No passing ITAPDLY, return 0\n"); 455 return 0; 456 } 457 458 first_fail_start = fail_window->start; 459 last_fail_end = fail_window[num_fails - 1].end; 460 461 for (i = 0; i < num_fails; i++) { 462 start_fail = fail_window[i].start; 463 end_fail = fail_window[i].end; 464 pass_length = start_fail - (prev_fail_end + 1); 465 466 if (pass_length > pass_window.length) { 467 pass_window.start = prev_fail_end + 1; 468 pass_window.length = pass_length; 469 } 470 prev_fail_end = end_fail; 471 } 472 473 if (!circular_buffer) 474 pass_length = ITAPDLY_LAST_INDEX - last_fail_end; 475 else 476 pass_length = ITAPDLY_LAST_INDEX - last_fail_end + first_fail_start; 477 478 if (pass_length > pass_window.length) { 479 pass_window.start = last_fail_end + 1; 480 pass_window.length = pass_length; 481 } 482 483 if (!circular_buffer) 484 itap = pass_window.start + (pass_window.length >> 1); 485 else 486 itap = (pass_window.start + (pass_window.length >> 1)) % ITAPDLY_LENGTH; 487 488 return (itap > ITAPDLY_LAST_INDEX) ? ITAPDLY_LAST_INDEX >> 1 : itap; 489 } 490 491 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 492 u32 opcode) 493 { 494 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 495 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 496 unsigned char timing = host->mmc->ios.timing; 497 struct window fail_window[ITAPDLY_LENGTH]; 498 u8 curr_pass, itap; 499 u8 fail_index = 0; 500 u8 prev_pass = 1; 501 502 memset(fail_window, 0, sizeof(fail_window)); 503 504 /* Enable ITAPDLY */ 505 sdhci_am654->itap_del_ena[timing] = 0x1; 506 507 for (itap = 0; itap < ITAPDLY_LENGTH; itap++) { 508 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 509 510 curr_pass = !mmc_send_tuning(host->mmc, opcode, NULL); 511 512 if (!curr_pass && prev_pass) 513 fail_window[fail_index].start = itap; 514 515 if (!curr_pass) { 516 fail_window[fail_index].end = itap; 517 fail_window[fail_index].length++; 518 } 519 520 if (curr_pass && !prev_pass) 521 fail_index++; 522 523 prev_pass = curr_pass; 524 } 525 526 if (fail_window[fail_index].length != 0) 527 fail_index++; 528 529 itap = sdhci_am654_calculate_itap(host, fail_window, fail_index, 530 sdhci_am654->dll_enable); 531 532 sdhci_am654_write_itapdly(sdhci_am654, itap, sdhci_am654->itap_del_ena[timing]); 533 534 return 0; 535 } 536 537 static struct sdhci_ops sdhci_am654_ops = { 538 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 539 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 540 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 541 .set_uhs_signaling = sdhci_set_uhs_signaling, 542 .set_bus_width = sdhci_set_bus_width, 543 .set_power = sdhci_set_power_and_bus_voltage, 544 .set_clock = sdhci_am654_set_clock, 545 .write_b = sdhci_am654_write_b, 546 .irq = sdhci_am654_cqhci_irq, 547 .reset = sdhci_and_cqhci_reset, 548 }; 549 550 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 551 .ops = &sdhci_am654_ops, 552 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 553 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 554 }; 555 556 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 557 .pdata = &sdhci_am654_pdata, 558 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 559 DLL_CALIB, 560 }; 561 562 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 563 .pdata = &sdhci_am654_pdata, 564 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 565 }; 566 567 static struct sdhci_ops sdhci_j721e_8bit_ops = { 568 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 569 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 570 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 571 .set_uhs_signaling = sdhci_set_uhs_signaling, 572 .set_bus_width = sdhci_set_bus_width, 573 .set_power = sdhci_set_power_and_bus_voltage, 574 .set_clock = sdhci_am654_set_clock, 575 .write_b = sdhci_am654_write_b, 576 .irq = sdhci_am654_cqhci_irq, 577 .reset = sdhci_and_cqhci_reset, 578 }; 579 580 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 581 .ops = &sdhci_j721e_8bit_ops, 582 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 583 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 584 }; 585 586 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 587 .pdata = &sdhci_j721e_8bit_pdata, 588 .flags = DLL_PRESENT | DLL_CALIB, 589 }; 590 591 static struct sdhci_ops sdhci_j721e_4bit_ops = { 592 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 593 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 594 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 595 .set_uhs_signaling = sdhci_set_uhs_signaling, 596 .set_bus_width = sdhci_set_bus_width, 597 .set_power = sdhci_set_power_and_bus_voltage, 598 .set_clock = sdhci_j721e_4bit_set_clock, 599 .write_b = sdhci_am654_write_b, 600 .irq = sdhci_am654_cqhci_irq, 601 .reset = sdhci_am654_reset, 602 }; 603 604 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 605 .ops = &sdhci_j721e_4bit_ops, 606 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 607 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 608 }; 609 610 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 611 .pdata = &sdhci_j721e_4bit_pdata, 612 .flags = IOMUX_PRESENT, 613 }; 614 615 static const struct soc_device_attribute sdhci_am654_devices[] = { 616 { .family = "AM65X", 617 .revision = "SR1.0", 618 .data = &sdhci_am654_sr1_drvdata 619 }, 620 {/* sentinel */} 621 }; 622 623 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 624 { 625 sdhci_dumpregs(mmc_priv(mmc)); 626 } 627 628 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 629 .enable = sdhci_cqe_enable, 630 .disable = sdhci_cqe_disable, 631 .dumpregs = sdhci_am654_dumpregs, 632 }; 633 634 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 635 { 636 struct cqhci_host *cq_host; 637 638 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 639 GFP_KERNEL); 640 if (!cq_host) 641 return -ENOMEM; 642 643 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 644 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 645 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 646 cq_host->ops = &sdhci_am654_cqhci_ops; 647 648 host->mmc->caps2 |= MMC_CAP2_CQE; 649 650 return cqhci_init(cq_host, host->mmc, 1); 651 } 652 653 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 654 struct sdhci_am654_data *sdhci_am654) 655 { 656 struct device *dev = mmc_dev(host->mmc); 657 int i; 658 int ret; 659 660 for (i = MMC_TIMING_LEGACY; i <= MMC_TIMING_MMC_HS400; i++) { 661 662 ret = device_property_read_u32(dev, td[i].otap_binding, 663 &sdhci_am654->otap_del_sel[i]); 664 if (ret) { 665 if (i == MMC_TIMING_LEGACY) { 666 dev_err(dev, "Couldn't find mandatory ti,otap-del-sel-legacy\n"); 667 return ret; 668 } 669 dev_dbg(dev, "Couldn't find %s\n", 670 td[i].otap_binding); 671 /* 672 * Remove the corresponding capability 673 * if an otap-del-sel value is not found 674 */ 675 if (i <= MMC_TIMING_MMC_DDR52) 676 host->mmc->caps &= ~td[i].capability; 677 else 678 host->mmc->caps2 &= ~td[i].capability; 679 } 680 681 if (td[i].itap_binding) { 682 ret = device_property_read_u32(dev, td[i].itap_binding, 683 &sdhci_am654->itap_del_sel[i]); 684 if (!ret) 685 sdhci_am654->itap_del_ena[i] = 0x1; 686 } 687 } 688 689 return 0; 690 } 691 692 static int sdhci_am654_init(struct sdhci_host *host) 693 { 694 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 695 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 696 u32 ctl_cfg_2 = 0; 697 u32 mask; 698 u32 val; 699 int ret; 700 701 /* Reset OTAP to default value */ 702 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 703 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 704 705 if (sdhci_am654->flags & DLL_CALIB) { 706 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 707 if (~val & CALDONE_MASK) { 708 /* Calibrate IO lines */ 709 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 710 PDB_MASK, PDB_MASK); 711 ret = regmap_read_poll_timeout(sdhci_am654->base, 712 PHY_STAT1, val, 713 val & CALDONE_MASK, 714 1, 20); 715 if (ret) 716 return ret; 717 } 718 } 719 720 /* Enable pins by setting IO mux to 0 */ 721 if (sdhci_am654->flags & IOMUX_PRESENT) 722 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 723 IOMUX_ENABLE_MASK, 0); 724 725 /* Set slot type based on SD or eMMC */ 726 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 727 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 728 729 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 730 ctl_cfg_2); 731 732 /* Enable tuning for SDR50 */ 733 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 734 TUNINGFORSDR50_MASK); 735 736 ret = sdhci_setup_host(host); 737 if (ret) 738 return ret; 739 740 ret = sdhci_am654_cqe_add_host(host); 741 if (ret) 742 goto err_cleanup_host; 743 744 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 745 if (ret) 746 goto err_cleanup_host; 747 748 ret = __sdhci_add_host(host); 749 if (ret) 750 goto err_cleanup_host; 751 752 return 0; 753 754 err_cleanup_host: 755 sdhci_cleanup_host(host); 756 return ret; 757 } 758 759 static int sdhci_am654_get_of_property(struct platform_device *pdev, 760 struct sdhci_am654_data *sdhci_am654) 761 { 762 struct device *dev = &pdev->dev; 763 int drv_strength; 764 int ret; 765 766 if (sdhci_am654->flags & DLL_PRESENT) { 767 ret = device_property_read_u32(dev, "ti,trm-icp", 768 &sdhci_am654->trm_icp); 769 if (ret) 770 return ret; 771 772 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 773 &drv_strength); 774 if (ret) 775 return ret; 776 777 switch (drv_strength) { 778 case 50: 779 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 780 break; 781 case 33: 782 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 783 break; 784 case 66: 785 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 786 break; 787 case 100: 788 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 789 break; 790 case 40: 791 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 792 break; 793 default: 794 dev_err(dev, "Invalid driver strength\n"); 795 return -EINVAL; 796 } 797 } 798 799 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 800 device_property_read_u32(dev, "ti,clkbuf-sel", 801 &sdhci_am654->clkbuf_sel); 802 803 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 804 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 805 806 sdhci_get_of_property(pdev); 807 808 return 0; 809 } 810 811 static const struct of_device_id sdhci_am654_of_match[] = { 812 { 813 .compatible = "ti,am654-sdhci-5.1", 814 .data = &sdhci_am654_drvdata, 815 }, 816 { 817 .compatible = "ti,j721e-sdhci-8bit", 818 .data = &sdhci_j721e_8bit_drvdata, 819 }, 820 { 821 .compatible = "ti,j721e-sdhci-4bit", 822 .data = &sdhci_j721e_4bit_drvdata, 823 }, 824 { 825 .compatible = "ti,am64-sdhci-8bit", 826 .data = &sdhci_j721e_8bit_drvdata, 827 }, 828 { 829 .compatible = "ti,am64-sdhci-4bit", 830 .data = &sdhci_j721e_4bit_drvdata, 831 }, 832 { 833 .compatible = "ti,am62-sdhci", 834 .data = &sdhci_j721e_4bit_drvdata, 835 }, 836 { /* sentinel */ } 837 }; 838 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 839 840 static int sdhci_am654_probe(struct platform_device *pdev) 841 { 842 const struct sdhci_am654_driver_data *drvdata; 843 const struct soc_device_attribute *soc; 844 struct sdhci_pltfm_host *pltfm_host; 845 struct sdhci_am654_data *sdhci_am654; 846 const struct of_device_id *match; 847 struct sdhci_host *host; 848 struct clk *clk_xin; 849 struct device *dev = &pdev->dev; 850 void __iomem *base; 851 int ret; 852 853 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 854 drvdata = match->data; 855 856 /* Update drvdata based on SoC revision */ 857 soc = soc_device_match(sdhci_am654_devices); 858 if (soc && soc->data) 859 drvdata = soc->data; 860 861 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 862 if (IS_ERR(host)) 863 return PTR_ERR(host); 864 865 pltfm_host = sdhci_priv(host); 866 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 867 sdhci_am654->flags = drvdata->flags; 868 869 clk_xin = devm_clk_get(dev, "clk_xin"); 870 if (IS_ERR(clk_xin)) { 871 dev_err(dev, "clk_xin clock not found.\n"); 872 ret = PTR_ERR(clk_xin); 873 goto err_pltfm_free; 874 } 875 876 pltfm_host->clk = clk_xin; 877 878 base = devm_platform_ioremap_resource(pdev, 1); 879 if (IS_ERR(base)) { 880 ret = PTR_ERR(base); 881 goto err_pltfm_free; 882 } 883 884 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 885 &sdhci_am654_regmap_config); 886 if (IS_ERR(sdhci_am654->base)) { 887 dev_err(dev, "Failed to initialize regmap\n"); 888 ret = PTR_ERR(sdhci_am654->base); 889 goto err_pltfm_free; 890 } 891 892 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 893 if (ret) 894 goto err_pltfm_free; 895 896 ret = mmc_of_parse(host->mmc); 897 if (ret) { 898 dev_err_probe(dev, ret, "parsing dt failed\n"); 899 goto err_pltfm_free; 900 } 901 902 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 903 904 pm_runtime_get_noresume(dev); 905 ret = pm_runtime_set_active(dev); 906 if (ret) 907 goto pm_put; 908 pm_runtime_enable(dev); 909 ret = clk_prepare_enable(pltfm_host->clk); 910 if (ret) 911 goto pm_disable; 912 913 ret = sdhci_am654_init(host); 914 if (ret) 915 goto clk_disable; 916 917 /* Setting up autosuspend */ 918 pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 919 pm_runtime_use_autosuspend(dev); 920 pm_runtime_mark_last_busy(dev); 921 pm_runtime_put_autosuspend(dev); 922 return 0; 923 924 clk_disable: 925 clk_disable_unprepare(pltfm_host->clk); 926 pm_disable: 927 pm_runtime_disable(dev); 928 pm_put: 929 pm_runtime_put_noidle(dev); 930 err_pltfm_free: 931 sdhci_pltfm_free(pdev); 932 return ret; 933 } 934 935 static void sdhci_am654_remove(struct platform_device *pdev) 936 { 937 struct sdhci_host *host = platform_get_drvdata(pdev); 938 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 939 struct device *dev = &pdev->dev; 940 int ret; 941 942 ret = pm_runtime_get_sync(dev); 943 if (ret < 0) 944 dev_err(dev, "pm_runtime_get_sync() Failed\n"); 945 946 sdhci_remove_host(host, true); 947 clk_disable_unprepare(pltfm_host->clk); 948 pm_runtime_disable(dev); 949 pm_runtime_put_noidle(dev); 950 sdhci_pltfm_free(pdev); 951 } 952 953 #ifdef CONFIG_PM 954 static int sdhci_am654_restore(struct sdhci_host *host) 955 { 956 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 957 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 958 u32 ctl_cfg_2 = 0; 959 u32 val; 960 int ret; 961 962 if (sdhci_am654->flags & DLL_CALIB) { 963 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 964 if (~val & CALDONE_MASK) { 965 /* Calibrate IO lines */ 966 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 967 PDB_MASK, PDB_MASK); 968 ret = regmap_read_poll_timeout(sdhci_am654->base, 969 PHY_STAT1, val, 970 val & CALDONE_MASK, 971 1, 20); 972 if (ret) 973 return ret; 974 } 975 } 976 977 /* Enable pins by setting IO mux to 0 */ 978 if (sdhci_am654->flags & IOMUX_PRESENT) 979 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 980 IOMUX_ENABLE_MASK, 0); 981 982 /* Set slot type based on SD or eMMC */ 983 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 984 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 985 986 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 987 ctl_cfg_2); 988 989 regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 990 if (~val & TUNINGFORSDR50_MASK) 991 /* Enable tuning for SDR50 */ 992 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 993 TUNINGFORSDR50_MASK); 994 995 return 0; 996 } 997 998 static int sdhci_am654_runtime_suspend(struct device *dev) 999 { 1000 struct sdhci_host *host = dev_get_drvdata(dev); 1001 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1002 int ret; 1003 1004 if (host->tuning_mode != SDHCI_TUNING_MODE_3) 1005 mmc_retune_needed(host->mmc); 1006 1007 ret = cqhci_suspend(host->mmc); 1008 if (ret) 1009 return ret; 1010 1011 ret = sdhci_runtime_suspend_host(host); 1012 if (ret) 1013 return ret; 1014 1015 /* disable the clock */ 1016 clk_disable_unprepare(pltfm_host->clk); 1017 return 0; 1018 } 1019 1020 static int sdhci_am654_runtime_resume(struct device *dev) 1021 { 1022 struct sdhci_host *host = dev_get_drvdata(dev); 1023 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 1024 int ret; 1025 1026 /* Enable the clock */ 1027 ret = clk_prepare_enable(pltfm_host->clk); 1028 if (ret) 1029 return ret; 1030 1031 ret = sdhci_am654_restore(host); 1032 if (ret) 1033 return ret; 1034 1035 ret = sdhci_runtime_resume_host(host, 0); 1036 if (ret) 1037 return ret; 1038 1039 ret = cqhci_resume(host->mmc); 1040 if (ret) 1041 return ret; 1042 1043 return 0; 1044 } 1045 #endif 1046 1047 static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 1048 SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 1049 sdhci_am654_runtime_resume, NULL) 1050 SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 1051 pm_runtime_force_resume) 1052 }; 1053 1054 static struct platform_driver sdhci_am654_driver = { 1055 .driver = { 1056 .name = "sdhci-am654", 1057 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 1058 .pm = &sdhci_am654_dev_pm_ops, 1059 .of_match_table = sdhci_am654_of_match, 1060 }, 1061 .probe = sdhci_am654_probe, 1062 .remove_new = sdhci_am654_remove, 1063 }; 1064 1065 module_platform_driver(sdhci_am654_driver); 1066 1067 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 1068 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 1069 MODULE_LICENSE("GPL"); 1070