1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-cqhci.h" 19 #include "sdhci-pltfm.h" 20 21 /* CTL_CFG Registers */ 22 #define CTL_CFG_2 0x14 23 #define CTL_CFG_3 0x18 24 25 #define SLOTTYPE_MASK GENMASK(31, 30) 26 #define SLOTTYPE_EMBEDDED BIT(30) 27 #define TUNINGFORSDR50_MASK BIT(13) 28 29 /* PHY Registers */ 30 #define PHY_CTRL1 0x100 31 #define PHY_CTRL2 0x104 32 #define PHY_CTRL3 0x108 33 #define PHY_CTRL4 0x10C 34 #define PHY_CTRL5 0x110 35 #define PHY_CTRL6 0x114 36 #define PHY_STAT1 0x130 37 #define PHY_STAT2 0x134 38 39 #define IOMUX_ENABLE_SHIFT 31 40 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 41 #define OTAPDLYENA_SHIFT 20 42 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 43 #define OTAPDLYSEL_SHIFT 12 44 #define OTAPDLYSEL_MASK GENMASK(15, 12) 45 #define STRBSEL_SHIFT 24 46 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 47 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 48 #define SEL50_SHIFT 8 49 #define SEL50_MASK BIT(SEL50_SHIFT) 50 #define SEL100_SHIFT 9 51 #define SEL100_MASK BIT(SEL100_SHIFT) 52 #define FREQSEL_SHIFT 8 53 #define FREQSEL_MASK GENMASK(10, 8) 54 #define CLKBUFSEL_SHIFT 0 55 #define CLKBUFSEL_MASK GENMASK(2, 0) 56 #define DLL_TRIM_ICP_SHIFT 4 57 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 58 #define DR_TY_SHIFT 20 59 #define DR_TY_MASK GENMASK(22, 20) 60 #define ENDLL_SHIFT 1 61 #define ENDLL_MASK BIT(ENDLL_SHIFT) 62 #define DLLRDY_SHIFT 0 63 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 64 #define PDB_SHIFT 0 65 #define PDB_MASK BIT(PDB_SHIFT) 66 #define CALDONE_SHIFT 1 67 #define CALDONE_MASK BIT(CALDONE_SHIFT) 68 #define RETRIM_SHIFT 17 69 #define RETRIM_MASK BIT(RETRIM_SHIFT) 70 #define SELDLYTXCLK_SHIFT 17 71 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72 #define SELDLYRXCLK_SHIFT 16 73 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74 #define ITAPDLYSEL_SHIFT 0 75 #define ITAPDLYSEL_MASK GENMASK(4, 0) 76 #define ITAPDLYENA_SHIFT 8 77 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78 #define ITAPCHGWIN_SHIFT 9 79 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 80 81 #define DRIVER_STRENGTH_50_OHM 0x0 82 #define DRIVER_STRENGTH_33_OHM 0x1 83 #define DRIVER_STRENGTH_66_OHM 0x2 84 #define DRIVER_STRENGTH_100_OHM 0x3 85 #define DRIVER_STRENGTH_40_OHM 0x4 86 87 #define CLOCK_TOO_SLOW_HZ 50000000 88 89 /* Command Queue Host Controller Interface Base address */ 90 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 91 92 static struct regmap_config sdhci_am654_regmap_config = { 93 .reg_bits = 32, 94 .val_bits = 32, 95 .reg_stride = 4, 96 .fast_io = true, 97 }; 98 99 struct timing_data { 100 const char *otap_binding; 101 const char *itap_binding; 102 u32 capability; 103 }; 104 105 static const struct timing_data td[] = { 106 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 107 "ti,itap-del-sel-legacy", 108 0}, 109 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 110 "ti,itap-del-sel-mmc-hs", 111 MMC_CAP_MMC_HIGHSPEED}, 112 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 113 "ti,itap-del-sel-sd-hs", 114 MMC_CAP_SD_HIGHSPEED}, 115 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 116 "ti,itap-del-sel-sdr12", 117 MMC_CAP_UHS_SDR12}, 118 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 119 "ti,itap-del-sel-sdr25", 120 MMC_CAP_UHS_SDR25}, 121 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 122 NULL, 123 MMC_CAP_UHS_SDR50}, 124 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 125 NULL, 126 MMC_CAP_UHS_SDR104}, 127 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 128 NULL, 129 MMC_CAP_UHS_DDR50}, 130 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 131 "ti,itap-del-sel-ddr52", 132 MMC_CAP_DDR}, 133 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 134 NULL, 135 MMC_CAP2_HS200}, 136 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 137 NULL, 138 MMC_CAP2_HS400}, 139 }; 140 141 struct sdhci_am654_data { 142 struct regmap *base; 143 bool legacy_otapdly; 144 int otap_del_sel[ARRAY_SIZE(td)]; 145 int itap_del_sel[ARRAY_SIZE(td)]; 146 int clkbuf_sel; 147 int trm_icp; 148 int drv_strength; 149 int strb_sel; 150 u32 flags; 151 u32 quirks; 152 153 #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 154 }; 155 156 struct sdhci_am654_driver_data { 157 const struct sdhci_pltfm_data *pdata; 158 u32 flags; 159 #define IOMUX_PRESENT (1 << 0) 160 #define FREQSEL_2_BIT (1 << 1) 161 #define STRBSEL_4_BIT (1 << 2) 162 #define DLL_PRESENT (1 << 3) 163 #define DLL_CALIB (1 << 4) 164 }; 165 166 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 167 { 168 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 169 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 170 int sel50, sel100, freqsel; 171 u32 mask, val; 172 int ret; 173 174 /* Disable delay chain mode */ 175 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 176 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 177 178 if (sdhci_am654->flags & FREQSEL_2_BIT) { 179 switch (clock) { 180 case 200000000: 181 sel50 = 0; 182 sel100 = 0; 183 break; 184 case 100000000: 185 sel50 = 0; 186 sel100 = 1; 187 break; 188 default: 189 sel50 = 1; 190 sel100 = 0; 191 } 192 193 /* Configure PHY DLL frequency */ 194 mask = SEL50_MASK | SEL100_MASK; 195 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 196 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 197 198 } else { 199 switch (clock) { 200 case 200000000: 201 freqsel = 0x0; 202 break; 203 default: 204 freqsel = 0x4; 205 } 206 207 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 208 freqsel << FREQSEL_SHIFT); 209 } 210 /* Configure DLL TRIM */ 211 mask = DLL_TRIM_ICP_MASK; 212 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 213 214 /* Configure DLL driver strength */ 215 mask |= DR_TY_MASK; 216 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 217 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 218 219 /* Enable DLL */ 220 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 221 0x1 << ENDLL_SHIFT); 222 /* 223 * Poll for DLL ready. Use a one second timeout. 224 * Works in all experiments done so far 225 */ 226 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 227 val & DLLRDY_MASK, 1000, 1000000); 228 if (ret) { 229 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 230 return; 231 } 232 } 233 234 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 235 u32 itapdly) 236 { 237 /* Set ITAPCHGWIN before writing to ITAPDLY */ 238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 239 1 << ITAPCHGWIN_SHIFT); 240 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 241 itapdly << ITAPDLYSEL_SHIFT); 242 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 243 } 244 245 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 246 unsigned char timing) 247 { 248 u32 mask, val; 249 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 251 252 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 253 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 254 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 255 256 sdhci_am654_write_itapdly(sdhci_am654, 257 sdhci_am654->itap_del_sel[timing]); 258 } 259 260 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 261 { 262 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 263 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 264 unsigned char timing = host->mmc->ios.timing; 265 u32 otap_del_sel; 266 u32 otap_del_ena; 267 u32 mask, val; 268 269 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 270 271 sdhci_set_clock(host, clock); 272 273 /* Setup DLL Output TAP delay */ 274 if (sdhci_am654->legacy_otapdly) 275 otap_del_sel = sdhci_am654->otap_del_sel[0]; 276 else 277 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 278 279 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 280 281 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 282 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 283 (otap_del_sel << OTAPDLYSEL_SHIFT); 284 285 /* Write to STRBSEL for HS400 speed mode */ 286 if (timing == MMC_TIMING_MMC_HS400) { 287 if (sdhci_am654->flags & STRBSEL_4_BIT) 288 mask |= STRBSEL_4BIT_MASK; 289 else 290 mask |= STRBSEL_8BIT_MASK; 291 292 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 293 } 294 295 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 296 297 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 298 sdhci_am654_setup_dll(host, clock); 299 else 300 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 301 302 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 303 sdhci_am654->clkbuf_sel); 304 } 305 306 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 307 unsigned int clock) 308 { 309 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 310 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 311 unsigned char timing = host->mmc->ios.timing; 312 u32 otap_del_sel; 313 u32 mask, val; 314 315 /* Setup DLL Output TAP delay */ 316 if (sdhci_am654->legacy_otapdly) 317 otap_del_sel = sdhci_am654->otap_del_sel[0]; 318 else 319 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 320 321 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 322 val = (0x1 << OTAPDLYENA_SHIFT) | 323 (otap_del_sel << OTAPDLYSEL_SHIFT); 324 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 325 326 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 327 sdhci_am654->clkbuf_sel); 328 329 sdhci_set_clock(host, clock); 330 } 331 332 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 333 { 334 writeb(val, host->ioaddr + reg); 335 usleep_range(1000, 10000); 336 return readb(host->ioaddr + reg); 337 } 338 339 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 340 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 341 { 342 unsigned char timing = host->mmc->ios.timing; 343 u8 pwr; 344 int ret; 345 346 if (reg == SDHCI_HOST_CONTROL) { 347 switch (timing) { 348 /* 349 * According to the data manual, HISPD bit 350 * should not be set in these speed modes. 351 */ 352 case MMC_TIMING_SD_HS: 353 case MMC_TIMING_MMC_HS: 354 val &= ~SDHCI_CTRL_HISPD; 355 } 356 } 357 358 writeb(val, host->ioaddr + reg); 359 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 360 /* 361 * Power on will not happen until the card detect debounce 362 * timer expires. Wait at least 1.5 seconds for the power on 363 * bit to be set 364 */ 365 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 366 pwr & SDHCI_POWER_ON, 0, 367 MAX_POWER_ON_TIMEOUT, false, host, val, 368 reg); 369 if (ret) 370 dev_info(mmc_dev(host->mmc), "Power on failed\n"); 371 } 372 } 373 374 static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 375 { 376 u8 ctrl; 377 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 378 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 379 380 sdhci_and_cqhci_reset(host, mask); 381 382 if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 383 ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 384 ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 385 sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 386 } 387 } 388 389 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 390 { 391 struct sdhci_host *host = mmc_priv(mmc); 392 int err = sdhci_execute_tuning(mmc, opcode); 393 394 if (err) 395 return err; 396 /* 397 * Tuning data remains in the buffer after tuning. 398 * Do a command and data reset to get rid of it 399 */ 400 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 401 402 return 0; 403 } 404 405 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 406 { 407 int cmd_error = 0; 408 int data_error = 0; 409 410 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 411 return intmask; 412 413 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 414 415 return 0; 416 } 417 418 #define ITAP_MAX 32 419 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 420 u32 opcode) 421 { 422 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 423 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 424 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; 425 u32 itap; 426 427 /* Enable ITAPDLY */ 428 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 429 1 << ITAPDLYENA_SHIFT); 430 431 for (itap = 0; itap < ITAP_MAX; itap++) { 432 sdhci_am654_write_itapdly(sdhci_am654, itap); 433 434 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); 435 if (cur_val && !prev_val) 436 pass_window = itap; 437 438 if (!cur_val) 439 fail_len++; 440 441 prev_val = cur_val; 442 } 443 /* 444 * Having determined the length of the failing window and start of 445 * the passing window calculate the length of the passing window and 446 * set the final value halfway through it considering the range as a 447 * circular buffer 448 */ 449 pass_len = ITAP_MAX - fail_len; 450 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; 451 sdhci_am654_write_itapdly(sdhci_am654, itap); 452 453 return 0; 454 } 455 456 static struct sdhci_ops sdhci_am654_ops = { 457 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 458 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 459 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 460 .set_uhs_signaling = sdhci_set_uhs_signaling, 461 .set_bus_width = sdhci_set_bus_width, 462 .set_power = sdhci_set_power_and_bus_voltage, 463 .set_clock = sdhci_am654_set_clock, 464 .write_b = sdhci_am654_write_b, 465 .irq = sdhci_am654_cqhci_irq, 466 .reset = sdhci_and_cqhci_reset, 467 }; 468 469 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 470 .ops = &sdhci_am654_ops, 471 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 472 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 473 }; 474 475 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 476 .pdata = &sdhci_am654_pdata, 477 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 478 DLL_CALIB, 479 }; 480 481 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 482 .pdata = &sdhci_am654_pdata, 483 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 484 }; 485 486 static struct sdhci_ops sdhci_j721e_8bit_ops = { 487 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 488 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 489 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 490 .set_uhs_signaling = sdhci_set_uhs_signaling, 491 .set_bus_width = sdhci_set_bus_width, 492 .set_power = sdhci_set_power_and_bus_voltage, 493 .set_clock = sdhci_am654_set_clock, 494 .write_b = sdhci_am654_write_b, 495 .irq = sdhci_am654_cqhci_irq, 496 .reset = sdhci_and_cqhci_reset, 497 }; 498 499 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 500 .ops = &sdhci_j721e_8bit_ops, 501 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 502 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 503 }; 504 505 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 506 .pdata = &sdhci_j721e_8bit_pdata, 507 .flags = DLL_PRESENT | DLL_CALIB, 508 }; 509 510 static struct sdhci_ops sdhci_j721e_4bit_ops = { 511 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 512 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 513 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 514 .set_uhs_signaling = sdhci_set_uhs_signaling, 515 .set_bus_width = sdhci_set_bus_width, 516 .set_power = sdhci_set_power_and_bus_voltage, 517 .set_clock = sdhci_j721e_4bit_set_clock, 518 .write_b = sdhci_am654_write_b, 519 .irq = sdhci_am654_cqhci_irq, 520 .reset = sdhci_am654_reset, 521 }; 522 523 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 524 .ops = &sdhci_j721e_4bit_ops, 525 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 526 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 527 }; 528 529 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 530 .pdata = &sdhci_j721e_4bit_pdata, 531 .flags = IOMUX_PRESENT, 532 }; 533 534 static const struct soc_device_attribute sdhci_am654_devices[] = { 535 { .family = "AM65X", 536 .revision = "SR1.0", 537 .data = &sdhci_am654_sr1_drvdata 538 }, 539 {/* sentinel */} 540 }; 541 542 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 543 { 544 sdhci_dumpregs(mmc_priv(mmc)); 545 } 546 547 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 548 .enable = sdhci_cqe_enable, 549 .disable = sdhci_cqe_disable, 550 .dumpregs = sdhci_am654_dumpregs, 551 }; 552 553 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 554 { 555 struct cqhci_host *cq_host; 556 557 cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 558 GFP_KERNEL); 559 if (!cq_host) 560 return -ENOMEM; 561 562 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 563 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 564 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 565 cq_host->ops = &sdhci_am654_cqhci_ops; 566 567 host->mmc->caps2 |= MMC_CAP2_CQE; 568 569 return cqhci_init(cq_host, host->mmc, 1); 570 } 571 572 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 573 struct sdhci_am654_data *sdhci_am654) 574 { 575 struct device *dev = mmc_dev(host->mmc); 576 int i; 577 int ret; 578 579 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 580 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 581 if (ret) { 582 /* 583 * ti,otap-del-sel-legacy is mandatory, look for old binding 584 * if not found. 585 */ 586 ret = device_property_read_u32(dev, "ti,otap-del-sel", 587 &sdhci_am654->otap_del_sel[0]); 588 if (ret) { 589 dev_err(dev, "Couldn't find otap-del-sel\n"); 590 591 return ret; 592 } 593 594 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 595 sdhci_am654->legacy_otapdly = true; 596 597 return 0; 598 } 599 600 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 601 602 ret = device_property_read_u32(dev, td[i].otap_binding, 603 &sdhci_am654->otap_del_sel[i]); 604 if (ret) { 605 dev_dbg(dev, "Couldn't find %s\n", 606 td[i].otap_binding); 607 /* 608 * Remove the corresponding capability 609 * if an otap-del-sel value is not found 610 */ 611 if (i <= MMC_TIMING_MMC_DDR52) 612 host->mmc->caps &= ~td[i].capability; 613 else 614 host->mmc->caps2 &= ~td[i].capability; 615 } 616 617 if (td[i].itap_binding) 618 device_property_read_u32(dev, td[i].itap_binding, 619 &sdhci_am654->itap_del_sel[i]); 620 } 621 622 return 0; 623 } 624 625 static int sdhci_am654_init(struct sdhci_host *host) 626 { 627 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 628 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 629 u32 ctl_cfg_2 = 0; 630 u32 mask; 631 u32 val; 632 int ret; 633 634 /* Reset OTAP to default value */ 635 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 636 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 637 638 if (sdhci_am654->flags & DLL_CALIB) { 639 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 640 if (~val & CALDONE_MASK) { 641 /* Calibrate IO lines */ 642 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 643 PDB_MASK, PDB_MASK); 644 ret = regmap_read_poll_timeout(sdhci_am654->base, 645 PHY_STAT1, val, 646 val & CALDONE_MASK, 647 1, 20); 648 if (ret) 649 return ret; 650 } 651 } 652 653 /* Enable pins by setting IO mux to 0 */ 654 if (sdhci_am654->flags & IOMUX_PRESENT) 655 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 656 IOMUX_ENABLE_MASK, 0); 657 658 /* Set slot type based on SD or eMMC */ 659 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 660 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 661 662 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 663 ctl_cfg_2); 664 665 /* Enable tuning for SDR50 */ 666 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 667 TUNINGFORSDR50_MASK); 668 669 ret = sdhci_setup_host(host); 670 if (ret) 671 return ret; 672 673 ret = sdhci_am654_cqe_add_host(host); 674 if (ret) 675 goto err_cleanup_host; 676 677 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 678 if (ret) 679 goto err_cleanup_host; 680 681 ret = __sdhci_add_host(host); 682 if (ret) 683 goto err_cleanup_host; 684 685 return 0; 686 687 err_cleanup_host: 688 sdhci_cleanup_host(host); 689 return ret; 690 } 691 692 static int sdhci_am654_get_of_property(struct platform_device *pdev, 693 struct sdhci_am654_data *sdhci_am654) 694 { 695 struct device *dev = &pdev->dev; 696 int drv_strength; 697 int ret; 698 699 if (sdhci_am654->flags & DLL_PRESENT) { 700 ret = device_property_read_u32(dev, "ti,trm-icp", 701 &sdhci_am654->trm_icp); 702 if (ret) 703 return ret; 704 705 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 706 &drv_strength); 707 if (ret) 708 return ret; 709 710 switch (drv_strength) { 711 case 50: 712 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 713 break; 714 case 33: 715 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 716 break; 717 case 66: 718 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 719 break; 720 case 100: 721 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 722 break; 723 case 40: 724 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 725 break; 726 default: 727 dev_err(dev, "Invalid driver strength\n"); 728 return -EINVAL; 729 } 730 } 731 732 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 733 device_property_read_u32(dev, "ti,clkbuf-sel", 734 &sdhci_am654->clkbuf_sel); 735 736 if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 737 sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 738 739 sdhci_get_of_property(pdev); 740 741 return 0; 742 } 743 744 static const struct of_device_id sdhci_am654_of_match[] = { 745 { 746 .compatible = "ti,am654-sdhci-5.1", 747 .data = &sdhci_am654_drvdata, 748 }, 749 { 750 .compatible = "ti,j721e-sdhci-8bit", 751 .data = &sdhci_j721e_8bit_drvdata, 752 }, 753 { 754 .compatible = "ti,j721e-sdhci-4bit", 755 .data = &sdhci_j721e_4bit_drvdata, 756 }, 757 { 758 .compatible = "ti,am64-sdhci-8bit", 759 .data = &sdhci_j721e_8bit_drvdata, 760 }, 761 { 762 .compatible = "ti,am64-sdhci-4bit", 763 .data = &sdhci_j721e_4bit_drvdata, 764 }, 765 { 766 .compatible = "ti,am62-sdhci", 767 .data = &sdhci_j721e_4bit_drvdata, 768 }, 769 { /* sentinel */ } 770 }; 771 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 772 773 static int sdhci_am654_probe(struct platform_device *pdev) 774 { 775 const struct sdhci_am654_driver_data *drvdata; 776 const struct soc_device_attribute *soc; 777 struct sdhci_pltfm_host *pltfm_host; 778 struct sdhci_am654_data *sdhci_am654; 779 const struct of_device_id *match; 780 struct sdhci_host *host; 781 struct clk *clk_xin; 782 struct device *dev = &pdev->dev; 783 void __iomem *base; 784 int ret; 785 786 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 787 drvdata = match->data; 788 789 /* Update drvdata based on SoC revision */ 790 soc = soc_device_match(sdhci_am654_devices); 791 if (soc && soc->data) 792 drvdata = soc->data; 793 794 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 795 if (IS_ERR(host)) 796 return PTR_ERR(host); 797 798 pltfm_host = sdhci_priv(host); 799 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 800 sdhci_am654->flags = drvdata->flags; 801 802 clk_xin = devm_clk_get(dev, "clk_xin"); 803 if (IS_ERR(clk_xin)) { 804 dev_err(dev, "clk_xin clock not found.\n"); 805 ret = PTR_ERR(clk_xin); 806 goto err_pltfm_free; 807 } 808 809 pltfm_host->clk = clk_xin; 810 811 /* Clocks are enabled using pm_runtime */ 812 pm_runtime_enable(dev); 813 ret = pm_runtime_resume_and_get(dev); 814 if (ret) 815 goto pm_runtime_disable; 816 817 base = devm_platform_ioremap_resource(pdev, 1); 818 if (IS_ERR(base)) { 819 ret = PTR_ERR(base); 820 goto pm_runtime_put; 821 } 822 823 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 824 &sdhci_am654_regmap_config); 825 if (IS_ERR(sdhci_am654->base)) { 826 dev_err(dev, "Failed to initialize regmap\n"); 827 ret = PTR_ERR(sdhci_am654->base); 828 goto pm_runtime_put; 829 } 830 831 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 832 if (ret) 833 goto pm_runtime_put; 834 835 ret = mmc_of_parse(host->mmc); 836 if (ret) { 837 dev_err_probe(dev, ret, "parsing dt failed\n"); 838 goto pm_runtime_put; 839 } 840 841 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 842 843 ret = sdhci_am654_init(host); 844 if (ret) 845 goto pm_runtime_put; 846 847 return 0; 848 849 pm_runtime_put: 850 pm_runtime_put_sync(dev); 851 pm_runtime_disable: 852 pm_runtime_disable(dev); 853 err_pltfm_free: 854 sdhci_pltfm_free(pdev); 855 return ret; 856 } 857 858 static int sdhci_am654_remove(struct platform_device *pdev) 859 { 860 struct sdhci_host *host = platform_get_drvdata(pdev); 861 int ret; 862 863 sdhci_remove_host(host, true); 864 ret = pm_runtime_put_sync(&pdev->dev); 865 if (ret < 0) 866 return ret; 867 868 pm_runtime_disable(&pdev->dev); 869 sdhci_pltfm_free(pdev); 870 871 return 0; 872 } 873 874 static struct platform_driver sdhci_am654_driver = { 875 .driver = { 876 .name = "sdhci-am654", 877 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 878 .of_match_table = sdhci_am654_of_match, 879 }, 880 .probe = sdhci_am654_probe, 881 .remove = sdhci_am654_remove, 882 }; 883 884 module_platform_driver(sdhci_am654_driver); 885 886 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 887 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 888 MODULE_LICENSE("GPL"); 889