1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-pltfm.h" 19 20 /* CTL_CFG Registers */ 21 #define CTL_CFG_2 0x14 22 23 #define SLOTTYPE_MASK GENMASK(31, 30) 24 #define SLOTTYPE_EMBEDDED BIT(30) 25 26 /* PHY Registers */ 27 #define PHY_CTRL1 0x100 28 #define PHY_CTRL2 0x104 29 #define PHY_CTRL3 0x108 30 #define PHY_CTRL4 0x10C 31 #define PHY_CTRL5 0x110 32 #define PHY_CTRL6 0x114 33 #define PHY_STAT1 0x130 34 #define PHY_STAT2 0x134 35 36 #define IOMUX_ENABLE_SHIFT 31 37 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 38 #define OTAPDLYENA_SHIFT 20 39 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 40 #define OTAPDLYSEL_SHIFT 12 41 #define OTAPDLYSEL_MASK GENMASK(15, 12) 42 #define STRBSEL_SHIFT 24 43 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 44 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 45 #define SEL50_SHIFT 8 46 #define SEL50_MASK BIT(SEL50_SHIFT) 47 #define SEL100_SHIFT 9 48 #define SEL100_MASK BIT(SEL100_SHIFT) 49 #define FREQSEL_SHIFT 8 50 #define FREQSEL_MASK GENMASK(10, 8) 51 #define CLKBUFSEL_SHIFT 0 52 #define CLKBUFSEL_MASK GENMASK(2, 0) 53 #define DLL_TRIM_ICP_SHIFT 4 54 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 55 #define DR_TY_SHIFT 20 56 #define DR_TY_MASK GENMASK(22, 20) 57 #define ENDLL_SHIFT 1 58 #define ENDLL_MASK BIT(ENDLL_SHIFT) 59 #define DLLRDY_SHIFT 0 60 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 61 #define PDB_SHIFT 0 62 #define PDB_MASK BIT(PDB_SHIFT) 63 #define CALDONE_SHIFT 1 64 #define CALDONE_MASK BIT(CALDONE_SHIFT) 65 #define RETRIM_SHIFT 17 66 #define RETRIM_MASK BIT(RETRIM_SHIFT) 67 #define SELDLYTXCLK_SHIFT 17 68 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 69 #define SELDLYRXCLK_SHIFT 16 70 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 71 #define ITAPDLYSEL_SHIFT 0 72 #define ITAPDLYSEL_MASK GENMASK(4, 0) 73 #define ITAPDLYENA_SHIFT 8 74 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 75 #define ITAPCHGWIN_SHIFT 9 76 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 77 78 #define DRIVER_STRENGTH_50_OHM 0x0 79 #define DRIVER_STRENGTH_33_OHM 0x1 80 #define DRIVER_STRENGTH_66_OHM 0x2 81 #define DRIVER_STRENGTH_100_OHM 0x3 82 #define DRIVER_STRENGTH_40_OHM 0x4 83 84 #define CLOCK_TOO_SLOW_HZ 50000000 85 86 /* Command Queue Host Controller Interface Base address */ 87 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 88 89 static struct regmap_config sdhci_am654_regmap_config = { 90 .reg_bits = 32, 91 .val_bits = 32, 92 .reg_stride = 4, 93 .fast_io = true, 94 }; 95 96 struct timing_data { 97 const char *otap_binding; 98 const char *itap_binding; 99 u32 capability; 100 }; 101 102 static const struct timing_data td[] = { 103 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 104 "ti,itap-del-sel-legacy", 105 0}, 106 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 107 "ti,itap-del-sel-mmc-hs", 108 MMC_CAP_MMC_HIGHSPEED}, 109 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 110 "ti,itap-del-sel-sd-hs", 111 MMC_CAP_SD_HIGHSPEED}, 112 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 113 "ti,itap-del-sel-sdr12", 114 MMC_CAP_UHS_SDR12}, 115 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 116 "ti,itap-del-sel-sdr25", 117 MMC_CAP_UHS_SDR25}, 118 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 119 NULL, 120 MMC_CAP_UHS_SDR50}, 121 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 122 NULL, 123 MMC_CAP_UHS_SDR104}, 124 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 125 NULL, 126 MMC_CAP_UHS_DDR50}, 127 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 128 "ti,itap-del-sel-ddr52", 129 MMC_CAP_DDR}, 130 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 131 NULL, 132 MMC_CAP2_HS200}, 133 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 134 NULL, 135 MMC_CAP2_HS400}, 136 }; 137 138 struct sdhci_am654_data { 139 struct regmap *base; 140 bool legacy_otapdly; 141 int otap_del_sel[ARRAY_SIZE(td)]; 142 int itap_del_sel[ARRAY_SIZE(td)]; 143 int clkbuf_sel; 144 int trm_icp; 145 int drv_strength; 146 int strb_sel; 147 u32 flags; 148 }; 149 150 struct sdhci_am654_driver_data { 151 const struct sdhci_pltfm_data *pdata; 152 u32 flags; 153 #define IOMUX_PRESENT (1 << 0) 154 #define FREQSEL_2_BIT (1 << 1) 155 #define STRBSEL_4_BIT (1 << 2) 156 #define DLL_PRESENT (1 << 3) 157 #define DLL_CALIB (1 << 4) 158 }; 159 160 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 161 { 162 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 163 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 164 int sel50, sel100, freqsel; 165 u32 mask, val; 166 int ret; 167 168 /* Disable delay chain mode */ 169 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 170 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 171 172 if (sdhci_am654->flags & FREQSEL_2_BIT) { 173 switch (clock) { 174 case 200000000: 175 sel50 = 0; 176 sel100 = 0; 177 break; 178 case 100000000: 179 sel50 = 0; 180 sel100 = 1; 181 break; 182 default: 183 sel50 = 1; 184 sel100 = 0; 185 } 186 187 /* Configure PHY DLL frequency */ 188 mask = SEL50_MASK | SEL100_MASK; 189 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 190 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 191 192 } else { 193 switch (clock) { 194 case 200000000: 195 freqsel = 0x0; 196 break; 197 default: 198 freqsel = 0x4; 199 } 200 201 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 202 freqsel << FREQSEL_SHIFT); 203 } 204 /* Configure DLL TRIM */ 205 mask = DLL_TRIM_ICP_MASK; 206 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 207 208 /* Configure DLL driver strength */ 209 mask |= DR_TY_MASK; 210 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 211 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 212 213 /* Enable DLL */ 214 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 215 0x1 << ENDLL_SHIFT); 216 /* 217 * Poll for DLL ready. Use a one second timeout. 218 * Works in all experiments done so far 219 */ 220 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 221 val & DLLRDY_MASK, 1000, 1000000); 222 if (ret) { 223 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 224 return; 225 } 226 } 227 228 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 229 u32 itapdly) 230 { 231 /* Set ITAPCHGWIN before writing to ITAPDLY */ 232 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 233 1 << ITAPCHGWIN_SHIFT); 234 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 235 itapdly << ITAPDLYSEL_SHIFT); 236 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 237 } 238 239 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 240 unsigned char timing) 241 { 242 u32 mask, val; 243 244 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 245 246 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 247 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 248 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 249 250 sdhci_am654_write_itapdly(sdhci_am654, 251 sdhci_am654->itap_del_sel[timing]); 252 } 253 254 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 255 { 256 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 257 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 258 unsigned char timing = host->mmc->ios.timing; 259 u32 otap_del_sel; 260 u32 otap_del_ena; 261 u32 mask, val; 262 263 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 264 265 sdhci_set_clock(host, clock); 266 267 /* Setup DLL Output TAP delay */ 268 if (sdhci_am654->legacy_otapdly) 269 otap_del_sel = sdhci_am654->otap_del_sel[0]; 270 else 271 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 272 273 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 274 275 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 276 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 277 (otap_del_sel << OTAPDLYSEL_SHIFT); 278 279 /* Write to STRBSEL for HS400 speed mode */ 280 if (timing == MMC_TIMING_MMC_HS400) { 281 if (sdhci_am654->flags & STRBSEL_4_BIT) 282 mask |= STRBSEL_4BIT_MASK; 283 else 284 mask |= STRBSEL_8BIT_MASK; 285 286 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 287 } 288 289 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 290 291 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 292 sdhci_am654_setup_dll(host, clock); 293 else 294 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 295 296 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 297 sdhci_am654->clkbuf_sel); 298 } 299 300 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 301 unsigned int clock) 302 { 303 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 304 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 305 unsigned char timing = host->mmc->ios.timing; 306 u32 otap_del_sel; 307 u32 mask, val; 308 309 /* Setup DLL Output TAP delay */ 310 if (sdhci_am654->legacy_otapdly) 311 otap_del_sel = sdhci_am654->otap_del_sel[0]; 312 else 313 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 314 315 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 316 val = (0x1 << OTAPDLYENA_SHIFT) | 317 (otap_del_sel << OTAPDLYSEL_SHIFT); 318 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 319 320 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 321 sdhci_am654->clkbuf_sel); 322 323 sdhci_set_clock(host, clock); 324 } 325 326 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 327 { 328 writeb(val, host->ioaddr + reg); 329 usleep_range(1000, 10000); 330 return readb(host->ioaddr + reg); 331 } 332 333 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 334 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 335 { 336 unsigned char timing = host->mmc->ios.timing; 337 u8 pwr; 338 int ret; 339 340 if (reg == SDHCI_HOST_CONTROL) { 341 switch (timing) { 342 /* 343 * According to the data manual, HISPD bit 344 * should not be set in these speed modes. 345 */ 346 case MMC_TIMING_SD_HS: 347 case MMC_TIMING_MMC_HS: 348 case MMC_TIMING_UHS_SDR12: 349 case MMC_TIMING_UHS_SDR25: 350 val &= ~SDHCI_CTRL_HISPD; 351 } 352 } 353 354 writeb(val, host->ioaddr + reg); 355 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 356 /* 357 * Power on will not happen until the card detect debounce 358 * timer expires. Wait at least 1.5 seconds for the power on 359 * bit to be set 360 */ 361 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 362 pwr & SDHCI_POWER_ON, 0, 363 MAX_POWER_ON_TIMEOUT, false, host, val, 364 reg); 365 if (ret) 366 dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 367 } 368 } 369 370 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 371 { 372 struct sdhci_host *host = mmc_priv(mmc); 373 int err = sdhci_execute_tuning(mmc, opcode); 374 375 if (err) 376 return err; 377 /* 378 * Tuning data remains in the buffer after tuning. 379 * Do a command and data reset to get rid of it 380 */ 381 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 382 383 return 0; 384 } 385 386 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 387 { 388 int cmd_error = 0; 389 int data_error = 0; 390 391 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 392 return intmask; 393 394 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 395 396 return 0; 397 } 398 399 #define ITAP_MAX 32 400 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 401 u32 opcode) 402 { 403 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 404 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 405 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; 406 u32 itap; 407 408 /* Enable ITAPDLY */ 409 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 410 1 << ITAPDLYENA_SHIFT); 411 412 for (itap = 0; itap < ITAP_MAX; itap++) { 413 sdhci_am654_write_itapdly(sdhci_am654, itap); 414 415 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); 416 if (cur_val && !prev_val) 417 pass_window = itap; 418 419 if (!cur_val) 420 fail_len++; 421 422 prev_val = cur_val; 423 } 424 /* 425 * Having determined the length of the failing window and start of 426 * the passing window calculate the length of the passing window and 427 * set the final value halfway through it considering the range as a 428 * circular buffer 429 */ 430 pass_len = ITAP_MAX - fail_len; 431 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; 432 sdhci_am654_write_itapdly(sdhci_am654, itap); 433 434 return 0; 435 } 436 437 static struct sdhci_ops sdhci_am654_ops = { 438 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 439 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 440 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 441 .set_uhs_signaling = sdhci_set_uhs_signaling, 442 .set_bus_width = sdhci_set_bus_width, 443 .set_power = sdhci_set_power_and_bus_voltage, 444 .set_clock = sdhci_am654_set_clock, 445 .write_b = sdhci_am654_write_b, 446 .irq = sdhci_am654_cqhci_irq, 447 .reset = sdhci_reset, 448 }; 449 450 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 451 .ops = &sdhci_am654_ops, 452 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 453 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 454 }; 455 456 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 457 .pdata = &sdhci_am654_pdata, 458 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 459 DLL_CALIB, 460 }; 461 462 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 463 .pdata = &sdhci_am654_pdata, 464 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 465 }; 466 467 static struct sdhci_ops sdhci_j721e_8bit_ops = { 468 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 469 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 470 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 471 .set_uhs_signaling = sdhci_set_uhs_signaling, 472 .set_bus_width = sdhci_set_bus_width, 473 .set_power = sdhci_set_power_and_bus_voltage, 474 .set_clock = sdhci_am654_set_clock, 475 .write_b = sdhci_am654_write_b, 476 .irq = sdhci_am654_cqhci_irq, 477 .reset = sdhci_reset, 478 }; 479 480 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 481 .ops = &sdhci_j721e_8bit_ops, 482 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 483 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 484 }; 485 486 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 487 .pdata = &sdhci_j721e_8bit_pdata, 488 .flags = DLL_PRESENT | DLL_CALIB, 489 }; 490 491 static struct sdhci_ops sdhci_j721e_4bit_ops = { 492 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 493 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 494 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 495 .set_uhs_signaling = sdhci_set_uhs_signaling, 496 .set_bus_width = sdhci_set_bus_width, 497 .set_power = sdhci_set_power_and_bus_voltage, 498 .set_clock = sdhci_j721e_4bit_set_clock, 499 .write_b = sdhci_am654_write_b, 500 .irq = sdhci_am654_cqhci_irq, 501 .reset = sdhci_reset, 502 }; 503 504 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 505 .ops = &sdhci_j721e_4bit_ops, 506 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 507 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 508 }; 509 510 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 511 .pdata = &sdhci_j721e_4bit_pdata, 512 .flags = IOMUX_PRESENT, 513 }; 514 515 static const struct soc_device_attribute sdhci_am654_devices[] = { 516 { .family = "AM65X", 517 .revision = "SR1.0", 518 .data = &sdhci_am654_sr1_drvdata 519 }, 520 {/* sentinel */} 521 }; 522 523 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 524 { 525 sdhci_dumpregs(mmc_priv(mmc)); 526 } 527 528 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 529 .enable = sdhci_cqe_enable, 530 .disable = sdhci_cqe_disable, 531 .dumpregs = sdhci_am654_dumpregs, 532 }; 533 534 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 535 { 536 struct cqhci_host *cq_host; 537 int ret; 538 539 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 540 GFP_KERNEL); 541 if (!cq_host) 542 return -ENOMEM; 543 544 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 545 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 546 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 547 cq_host->ops = &sdhci_am654_cqhci_ops; 548 549 host->mmc->caps2 |= MMC_CAP2_CQE; 550 551 ret = cqhci_init(cq_host, host->mmc, 1); 552 553 return ret; 554 } 555 556 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 557 struct sdhci_am654_data *sdhci_am654) 558 { 559 struct device *dev = mmc_dev(host->mmc); 560 int i; 561 int ret; 562 563 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 564 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 565 if (ret) { 566 /* 567 * ti,otap-del-sel-legacy is mandatory, look for old binding 568 * if not found. 569 */ 570 ret = device_property_read_u32(dev, "ti,otap-del-sel", 571 &sdhci_am654->otap_del_sel[0]); 572 if (ret) { 573 dev_err(dev, "Couldn't find otap-del-sel\n"); 574 575 return ret; 576 } 577 578 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 579 sdhci_am654->legacy_otapdly = true; 580 581 return 0; 582 } 583 584 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 585 586 ret = device_property_read_u32(dev, td[i].otap_binding, 587 &sdhci_am654->otap_del_sel[i]); 588 if (ret) { 589 dev_dbg(dev, "Couldn't find %s\n", 590 td[i].otap_binding); 591 /* 592 * Remove the corresponding capability 593 * if an otap-del-sel value is not found 594 */ 595 if (i <= MMC_TIMING_MMC_DDR52) 596 host->mmc->caps &= ~td[i].capability; 597 else 598 host->mmc->caps2 &= ~td[i].capability; 599 } 600 601 if (td[i].itap_binding) 602 device_property_read_u32(dev, td[i].itap_binding, 603 &sdhci_am654->itap_del_sel[i]); 604 } 605 606 return 0; 607 } 608 609 static int sdhci_am654_init(struct sdhci_host *host) 610 { 611 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 612 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 613 u32 ctl_cfg_2 = 0; 614 u32 mask; 615 u32 val; 616 int ret; 617 618 /* Reset OTAP to default value */ 619 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 620 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 621 622 if (sdhci_am654->flags & DLL_CALIB) { 623 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 624 if (~val & CALDONE_MASK) { 625 /* Calibrate IO lines */ 626 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 627 PDB_MASK, PDB_MASK); 628 ret = regmap_read_poll_timeout(sdhci_am654->base, 629 PHY_STAT1, val, 630 val & CALDONE_MASK, 631 1, 20); 632 if (ret) 633 return ret; 634 } 635 } 636 637 /* Enable pins by setting IO mux to 0 */ 638 if (sdhci_am654->flags & IOMUX_PRESENT) 639 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 640 IOMUX_ENABLE_MASK, 0); 641 642 /* Set slot type based on SD or eMMC */ 643 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 644 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 645 646 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 647 ctl_cfg_2); 648 649 ret = sdhci_setup_host(host); 650 if (ret) 651 return ret; 652 653 ret = sdhci_am654_cqe_add_host(host); 654 if (ret) 655 goto err_cleanup_host; 656 657 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 658 if (ret) 659 goto err_cleanup_host; 660 661 ret = __sdhci_add_host(host); 662 if (ret) 663 goto err_cleanup_host; 664 665 return 0; 666 667 err_cleanup_host: 668 sdhci_cleanup_host(host); 669 return ret; 670 } 671 672 static int sdhci_am654_get_of_property(struct platform_device *pdev, 673 struct sdhci_am654_data *sdhci_am654) 674 { 675 struct device *dev = &pdev->dev; 676 int drv_strength; 677 int ret; 678 679 if (sdhci_am654->flags & DLL_PRESENT) { 680 ret = device_property_read_u32(dev, "ti,trm-icp", 681 &sdhci_am654->trm_icp); 682 if (ret) 683 return ret; 684 685 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 686 &drv_strength); 687 if (ret) 688 return ret; 689 690 switch (drv_strength) { 691 case 50: 692 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 693 break; 694 case 33: 695 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 696 break; 697 case 66: 698 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 699 break; 700 case 100: 701 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 702 break; 703 case 40: 704 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 705 break; 706 default: 707 dev_err(dev, "Invalid driver strength\n"); 708 return -EINVAL; 709 } 710 } 711 712 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 713 device_property_read_u32(dev, "ti,clkbuf-sel", 714 &sdhci_am654->clkbuf_sel); 715 716 sdhci_get_of_property(pdev); 717 718 return 0; 719 } 720 721 static const struct of_device_id sdhci_am654_of_match[] = { 722 { 723 .compatible = "ti,am654-sdhci-5.1", 724 .data = &sdhci_am654_drvdata, 725 }, 726 { 727 .compatible = "ti,j721e-sdhci-8bit", 728 .data = &sdhci_j721e_8bit_drvdata, 729 }, 730 { 731 .compatible = "ti,j721e-sdhci-4bit", 732 .data = &sdhci_j721e_4bit_drvdata, 733 }, 734 { /* sentinel */ } 735 }; 736 737 static int sdhci_am654_probe(struct platform_device *pdev) 738 { 739 const struct sdhci_am654_driver_data *drvdata; 740 const struct soc_device_attribute *soc; 741 struct sdhci_pltfm_host *pltfm_host; 742 struct sdhci_am654_data *sdhci_am654; 743 const struct of_device_id *match; 744 struct sdhci_host *host; 745 struct clk *clk_xin; 746 struct device *dev = &pdev->dev; 747 void __iomem *base; 748 int ret; 749 750 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 751 drvdata = match->data; 752 753 /* Update drvdata based on SoC revision */ 754 soc = soc_device_match(sdhci_am654_devices); 755 if (soc && soc->data) 756 drvdata = soc->data; 757 758 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 759 if (IS_ERR(host)) 760 return PTR_ERR(host); 761 762 pltfm_host = sdhci_priv(host); 763 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 764 sdhci_am654->flags = drvdata->flags; 765 766 clk_xin = devm_clk_get(dev, "clk_xin"); 767 if (IS_ERR(clk_xin)) { 768 dev_err(dev, "clk_xin clock not found.\n"); 769 ret = PTR_ERR(clk_xin); 770 goto err_pltfm_free; 771 } 772 773 pltfm_host->clk = clk_xin; 774 775 /* Clocks are enabled using pm_runtime */ 776 pm_runtime_enable(dev); 777 ret = pm_runtime_get_sync(dev); 778 if (ret < 0) { 779 pm_runtime_put_noidle(dev); 780 goto pm_runtime_disable; 781 } 782 783 base = devm_platform_ioremap_resource(pdev, 1); 784 if (IS_ERR(base)) { 785 ret = PTR_ERR(base); 786 goto pm_runtime_put; 787 } 788 789 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 790 &sdhci_am654_regmap_config); 791 if (IS_ERR(sdhci_am654->base)) { 792 dev_err(dev, "Failed to initialize regmap\n"); 793 ret = PTR_ERR(sdhci_am654->base); 794 goto pm_runtime_put; 795 } 796 797 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 798 if (ret) 799 goto pm_runtime_put; 800 801 ret = mmc_of_parse(host->mmc); 802 if (ret) { 803 dev_err(dev, "parsing dt failed (%d)\n", ret); 804 goto pm_runtime_put; 805 } 806 807 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 808 809 ret = sdhci_am654_init(host); 810 if (ret) 811 goto pm_runtime_put; 812 813 return 0; 814 815 pm_runtime_put: 816 pm_runtime_put_sync(dev); 817 pm_runtime_disable: 818 pm_runtime_disable(dev); 819 err_pltfm_free: 820 sdhci_pltfm_free(pdev); 821 return ret; 822 } 823 824 static int sdhci_am654_remove(struct platform_device *pdev) 825 { 826 struct sdhci_host *host = platform_get_drvdata(pdev); 827 int ret; 828 829 sdhci_remove_host(host, true); 830 ret = pm_runtime_put_sync(&pdev->dev); 831 if (ret < 0) 832 return ret; 833 834 pm_runtime_disable(&pdev->dev); 835 sdhci_pltfm_free(pdev); 836 837 return 0; 838 } 839 840 static struct platform_driver sdhci_am654_driver = { 841 .driver = { 842 .name = "sdhci-am654", 843 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 844 .of_match_table = sdhci_am654_of_match, 845 }, 846 .probe = sdhci_am654_probe, 847 .remove = sdhci_am654_remove, 848 }; 849 850 module_platform_driver(sdhci_am654_driver); 851 852 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 853 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 854 MODULE_LICENSE("GPL"); 855