1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/iopoll.h> 10 #include <linux/of.h> 11 #include <linux/module.h> 12 #include <linux/pm_runtime.h> 13 #include <linux/property.h> 14 #include <linux/regmap.h> 15 #include <linux/sys_soc.h> 16 17 #include "cqhci.h" 18 #include "sdhci-pltfm.h" 19 20 /* CTL_CFG Registers */ 21 #define CTL_CFG_2 0x14 22 #define CTL_CFG_3 0x18 23 24 #define SLOTTYPE_MASK GENMASK(31, 30) 25 #define SLOTTYPE_EMBEDDED BIT(30) 26 #define TUNINGFORSDR50_MASK BIT(13) 27 28 /* PHY Registers */ 29 #define PHY_CTRL1 0x100 30 #define PHY_CTRL2 0x104 31 #define PHY_CTRL3 0x108 32 #define PHY_CTRL4 0x10C 33 #define PHY_CTRL5 0x110 34 #define PHY_CTRL6 0x114 35 #define PHY_STAT1 0x130 36 #define PHY_STAT2 0x134 37 38 #define IOMUX_ENABLE_SHIFT 31 39 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 40 #define OTAPDLYENA_SHIFT 20 41 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 42 #define OTAPDLYSEL_SHIFT 12 43 #define OTAPDLYSEL_MASK GENMASK(15, 12) 44 #define STRBSEL_SHIFT 24 45 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 46 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 47 #define SEL50_SHIFT 8 48 #define SEL50_MASK BIT(SEL50_SHIFT) 49 #define SEL100_SHIFT 9 50 #define SEL100_MASK BIT(SEL100_SHIFT) 51 #define FREQSEL_SHIFT 8 52 #define FREQSEL_MASK GENMASK(10, 8) 53 #define CLKBUFSEL_SHIFT 0 54 #define CLKBUFSEL_MASK GENMASK(2, 0) 55 #define DLL_TRIM_ICP_SHIFT 4 56 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 57 #define DR_TY_SHIFT 20 58 #define DR_TY_MASK GENMASK(22, 20) 59 #define ENDLL_SHIFT 1 60 #define ENDLL_MASK BIT(ENDLL_SHIFT) 61 #define DLLRDY_SHIFT 0 62 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 63 #define PDB_SHIFT 0 64 #define PDB_MASK BIT(PDB_SHIFT) 65 #define CALDONE_SHIFT 1 66 #define CALDONE_MASK BIT(CALDONE_SHIFT) 67 #define RETRIM_SHIFT 17 68 #define RETRIM_MASK BIT(RETRIM_SHIFT) 69 #define SELDLYTXCLK_SHIFT 17 70 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 71 #define SELDLYRXCLK_SHIFT 16 72 #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 73 #define ITAPDLYSEL_SHIFT 0 74 #define ITAPDLYSEL_MASK GENMASK(4, 0) 75 #define ITAPDLYENA_SHIFT 8 76 #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 77 #define ITAPCHGWIN_SHIFT 9 78 #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 79 80 #define DRIVER_STRENGTH_50_OHM 0x0 81 #define DRIVER_STRENGTH_33_OHM 0x1 82 #define DRIVER_STRENGTH_66_OHM 0x2 83 #define DRIVER_STRENGTH_100_OHM 0x3 84 #define DRIVER_STRENGTH_40_OHM 0x4 85 86 #define CLOCK_TOO_SLOW_HZ 50000000 87 88 /* Command Queue Host Controller Interface Base address */ 89 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 90 91 static struct regmap_config sdhci_am654_regmap_config = { 92 .reg_bits = 32, 93 .val_bits = 32, 94 .reg_stride = 4, 95 .fast_io = true, 96 }; 97 98 struct timing_data { 99 const char *otap_binding; 100 const char *itap_binding; 101 u32 capability; 102 }; 103 104 static const struct timing_data td[] = { 105 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 106 "ti,itap-del-sel-legacy", 107 0}, 108 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 109 "ti,itap-del-sel-mmc-hs", 110 MMC_CAP_MMC_HIGHSPEED}, 111 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 112 "ti,itap-del-sel-sd-hs", 113 MMC_CAP_SD_HIGHSPEED}, 114 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 115 "ti,itap-del-sel-sdr12", 116 MMC_CAP_UHS_SDR12}, 117 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 118 "ti,itap-del-sel-sdr25", 119 MMC_CAP_UHS_SDR25}, 120 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 121 NULL, 122 MMC_CAP_UHS_SDR50}, 123 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 124 NULL, 125 MMC_CAP_UHS_SDR104}, 126 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 127 NULL, 128 MMC_CAP_UHS_DDR50}, 129 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 130 "ti,itap-del-sel-ddr52", 131 MMC_CAP_DDR}, 132 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 133 NULL, 134 MMC_CAP2_HS200}, 135 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 136 NULL, 137 MMC_CAP2_HS400}, 138 }; 139 140 struct sdhci_am654_data { 141 struct regmap *base; 142 bool legacy_otapdly; 143 int otap_del_sel[ARRAY_SIZE(td)]; 144 int itap_del_sel[ARRAY_SIZE(td)]; 145 int clkbuf_sel; 146 int trm_icp; 147 int drv_strength; 148 int strb_sel; 149 u32 flags; 150 }; 151 152 struct sdhci_am654_driver_data { 153 const struct sdhci_pltfm_data *pdata; 154 u32 flags; 155 #define IOMUX_PRESENT (1 << 0) 156 #define FREQSEL_2_BIT (1 << 1) 157 #define STRBSEL_4_BIT (1 << 2) 158 #define DLL_PRESENT (1 << 3) 159 #define DLL_CALIB (1 << 4) 160 }; 161 162 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 163 { 164 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 165 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 166 int sel50, sel100, freqsel; 167 u32 mask, val; 168 int ret; 169 170 /* Disable delay chain mode */ 171 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 172 SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 173 174 if (sdhci_am654->flags & FREQSEL_2_BIT) { 175 switch (clock) { 176 case 200000000: 177 sel50 = 0; 178 sel100 = 0; 179 break; 180 case 100000000: 181 sel50 = 0; 182 sel100 = 1; 183 break; 184 default: 185 sel50 = 1; 186 sel100 = 0; 187 } 188 189 /* Configure PHY DLL frequency */ 190 mask = SEL50_MASK | SEL100_MASK; 191 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 192 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 193 194 } else { 195 switch (clock) { 196 case 200000000: 197 freqsel = 0x0; 198 break; 199 default: 200 freqsel = 0x4; 201 } 202 203 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 204 freqsel << FREQSEL_SHIFT); 205 } 206 /* Configure DLL TRIM */ 207 mask = DLL_TRIM_ICP_MASK; 208 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 209 210 /* Configure DLL driver strength */ 211 mask |= DR_TY_MASK; 212 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 213 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 214 215 /* Enable DLL */ 216 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 217 0x1 << ENDLL_SHIFT); 218 /* 219 * Poll for DLL ready. Use a one second timeout. 220 * Works in all experiments done so far 221 */ 222 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 223 val & DLLRDY_MASK, 1000, 1000000); 224 if (ret) { 225 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 226 return; 227 } 228 } 229 230 static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 231 u32 itapdly) 232 { 233 /* Set ITAPCHGWIN before writing to ITAPDLY */ 234 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 235 1 << ITAPCHGWIN_SHIFT); 236 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 237 itapdly << ITAPDLYSEL_SHIFT); 238 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 239 } 240 241 static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 242 unsigned char timing) 243 { 244 u32 mask, val; 245 246 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 247 248 val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 249 mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 250 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 251 252 sdhci_am654_write_itapdly(sdhci_am654, 253 sdhci_am654->itap_del_sel[timing]); 254 } 255 256 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 257 { 258 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 259 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 260 unsigned char timing = host->mmc->ios.timing; 261 u32 otap_del_sel; 262 u32 otap_del_ena; 263 u32 mask, val; 264 265 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 266 267 sdhci_set_clock(host, clock); 268 269 /* Setup DLL Output TAP delay */ 270 if (sdhci_am654->legacy_otapdly) 271 otap_del_sel = sdhci_am654->otap_del_sel[0]; 272 else 273 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 274 275 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 276 277 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 278 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 279 (otap_del_sel << OTAPDLYSEL_SHIFT); 280 281 /* Write to STRBSEL for HS400 speed mode */ 282 if (timing == MMC_TIMING_MMC_HS400) { 283 if (sdhci_am654->flags & STRBSEL_4_BIT) 284 mask |= STRBSEL_4BIT_MASK; 285 else 286 mask |= STRBSEL_8BIT_MASK; 287 288 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 289 } 290 291 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 292 293 if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 294 sdhci_am654_setup_dll(host, clock); 295 else 296 sdhci_am654_setup_delay_chain(sdhci_am654, timing); 297 298 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 299 sdhci_am654->clkbuf_sel); 300 } 301 302 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 303 unsigned int clock) 304 { 305 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 306 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 307 unsigned char timing = host->mmc->ios.timing; 308 u32 otap_del_sel; 309 u32 mask, val; 310 311 /* Setup DLL Output TAP delay */ 312 if (sdhci_am654->legacy_otapdly) 313 otap_del_sel = sdhci_am654->otap_del_sel[0]; 314 else 315 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 316 317 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 318 val = (0x1 << OTAPDLYENA_SHIFT) | 319 (otap_del_sel << OTAPDLYSEL_SHIFT); 320 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 321 322 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 323 sdhci_am654->clkbuf_sel); 324 325 sdhci_set_clock(host, clock); 326 } 327 328 static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 329 { 330 writeb(val, host->ioaddr + reg); 331 usleep_range(1000, 10000); 332 return readb(host->ioaddr + reg); 333 } 334 335 #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 336 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 337 { 338 unsigned char timing = host->mmc->ios.timing; 339 u8 pwr; 340 int ret; 341 342 if (reg == SDHCI_HOST_CONTROL) { 343 switch (timing) { 344 /* 345 * According to the data manual, HISPD bit 346 * should not be set in these speed modes. 347 */ 348 case MMC_TIMING_SD_HS: 349 case MMC_TIMING_MMC_HS: 350 case MMC_TIMING_UHS_SDR12: 351 case MMC_TIMING_UHS_SDR25: 352 val &= ~SDHCI_CTRL_HISPD; 353 } 354 } 355 356 writeb(val, host->ioaddr + reg); 357 if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 358 /* 359 * Power on will not happen until the card detect debounce 360 * timer expires. Wait at least 1.5 seconds for the power on 361 * bit to be set 362 */ 363 ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 364 pwr & SDHCI_POWER_ON, 0, 365 MAX_POWER_ON_TIMEOUT, false, host, val, 366 reg); 367 if (ret) 368 dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 369 } 370 } 371 372 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 373 { 374 struct sdhci_host *host = mmc_priv(mmc); 375 int err = sdhci_execute_tuning(mmc, opcode); 376 377 if (err) 378 return err; 379 /* 380 * Tuning data remains in the buffer after tuning. 381 * Do a command and data reset to get rid of it 382 */ 383 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 384 385 return 0; 386 } 387 388 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 389 { 390 int cmd_error = 0; 391 int data_error = 0; 392 393 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 394 return intmask; 395 396 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 397 398 return 0; 399 } 400 401 #define ITAP_MAX 32 402 static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 403 u32 opcode) 404 { 405 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 406 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 407 int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; 408 u32 itap; 409 410 /* Enable ITAPDLY */ 411 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 412 1 << ITAPDLYENA_SHIFT); 413 414 for (itap = 0; itap < ITAP_MAX; itap++) { 415 sdhci_am654_write_itapdly(sdhci_am654, itap); 416 417 cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); 418 if (cur_val && !prev_val) 419 pass_window = itap; 420 421 if (!cur_val) 422 fail_len++; 423 424 prev_val = cur_val; 425 } 426 /* 427 * Having determined the length of the failing window and start of 428 * the passing window calculate the length of the passing window and 429 * set the final value halfway through it considering the range as a 430 * circular buffer 431 */ 432 pass_len = ITAP_MAX - fail_len; 433 itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; 434 sdhci_am654_write_itapdly(sdhci_am654, itap); 435 436 return 0; 437 } 438 439 static struct sdhci_ops sdhci_am654_ops = { 440 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 441 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 442 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 443 .set_uhs_signaling = sdhci_set_uhs_signaling, 444 .set_bus_width = sdhci_set_bus_width, 445 .set_power = sdhci_set_power_and_bus_voltage, 446 .set_clock = sdhci_am654_set_clock, 447 .write_b = sdhci_am654_write_b, 448 .irq = sdhci_am654_cqhci_irq, 449 .reset = sdhci_reset, 450 }; 451 452 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 453 .ops = &sdhci_am654_ops, 454 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 455 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 456 }; 457 458 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 459 .pdata = &sdhci_am654_pdata, 460 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 461 DLL_CALIB, 462 }; 463 464 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 465 .pdata = &sdhci_am654_pdata, 466 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 467 }; 468 469 static struct sdhci_ops sdhci_j721e_8bit_ops = { 470 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 471 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 472 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 473 .set_uhs_signaling = sdhci_set_uhs_signaling, 474 .set_bus_width = sdhci_set_bus_width, 475 .set_power = sdhci_set_power_and_bus_voltage, 476 .set_clock = sdhci_am654_set_clock, 477 .write_b = sdhci_am654_write_b, 478 .irq = sdhci_am654_cqhci_irq, 479 .reset = sdhci_reset, 480 }; 481 482 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 483 .ops = &sdhci_j721e_8bit_ops, 484 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 485 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 486 }; 487 488 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 489 .pdata = &sdhci_j721e_8bit_pdata, 490 .flags = DLL_PRESENT | DLL_CALIB, 491 }; 492 493 static struct sdhci_ops sdhci_j721e_4bit_ops = { 494 .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 495 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 496 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 497 .set_uhs_signaling = sdhci_set_uhs_signaling, 498 .set_bus_width = sdhci_set_bus_width, 499 .set_power = sdhci_set_power_and_bus_voltage, 500 .set_clock = sdhci_j721e_4bit_set_clock, 501 .write_b = sdhci_am654_write_b, 502 .irq = sdhci_am654_cqhci_irq, 503 .reset = sdhci_reset, 504 }; 505 506 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 507 .ops = &sdhci_j721e_4bit_ops, 508 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 509 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 510 }; 511 512 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 513 .pdata = &sdhci_j721e_4bit_pdata, 514 .flags = IOMUX_PRESENT, 515 }; 516 517 static const struct soc_device_attribute sdhci_am654_devices[] = { 518 { .family = "AM65X", 519 .revision = "SR1.0", 520 .data = &sdhci_am654_sr1_drvdata 521 }, 522 {/* sentinel */} 523 }; 524 525 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 526 { 527 sdhci_dumpregs(mmc_priv(mmc)); 528 } 529 530 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 531 .enable = sdhci_cqe_enable, 532 .disable = sdhci_cqe_disable, 533 .dumpregs = sdhci_am654_dumpregs, 534 }; 535 536 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 537 { 538 struct cqhci_host *cq_host; 539 int ret; 540 541 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 542 GFP_KERNEL); 543 if (!cq_host) 544 return -ENOMEM; 545 546 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 547 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 548 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 549 cq_host->ops = &sdhci_am654_cqhci_ops; 550 551 host->mmc->caps2 |= MMC_CAP2_CQE; 552 553 ret = cqhci_init(cq_host, host->mmc, 1); 554 555 return ret; 556 } 557 558 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 559 struct sdhci_am654_data *sdhci_am654) 560 { 561 struct device *dev = mmc_dev(host->mmc); 562 int i; 563 int ret; 564 565 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 566 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 567 if (ret) { 568 /* 569 * ti,otap-del-sel-legacy is mandatory, look for old binding 570 * if not found. 571 */ 572 ret = device_property_read_u32(dev, "ti,otap-del-sel", 573 &sdhci_am654->otap_del_sel[0]); 574 if (ret) { 575 dev_err(dev, "Couldn't find otap-del-sel\n"); 576 577 return ret; 578 } 579 580 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 581 sdhci_am654->legacy_otapdly = true; 582 583 return 0; 584 } 585 586 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 587 588 ret = device_property_read_u32(dev, td[i].otap_binding, 589 &sdhci_am654->otap_del_sel[i]); 590 if (ret) { 591 dev_dbg(dev, "Couldn't find %s\n", 592 td[i].otap_binding); 593 /* 594 * Remove the corresponding capability 595 * if an otap-del-sel value is not found 596 */ 597 if (i <= MMC_TIMING_MMC_DDR52) 598 host->mmc->caps &= ~td[i].capability; 599 else 600 host->mmc->caps2 &= ~td[i].capability; 601 } 602 603 if (td[i].itap_binding) 604 device_property_read_u32(dev, td[i].itap_binding, 605 &sdhci_am654->itap_del_sel[i]); 606 } 607 608 return 0; 609 } 610 611 static int sdhci_am654_init(struct sdhci_host *host) 612 { 613 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 614 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 615 u32 ctl_cfg_2 = 0; 616 u32 mask; 617 u32 val; 618 int ret; 619 620 /* Reset OTAP to default value */ 621 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 622 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 623 624 if (sdhci_am654->flags & DLL_CALIB) { 625 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 626 if (~val & CALDONE_MASK) { 627 /* Calibrate IO lines */ 628 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 629 PDB_MASK, PDB_MASK); 630 ret = regmap_read_poll_timeout(sdhci_am654->base, 631 PHY_STAT1, val, 632 val & CALDONE_MASK, 633 1, 20); 634 if (ret) 635 return ret; 636 } 637 } 638 639 /* Enable pins by setting IO mux to 0 */ 640 if (sdhci_am654->flags & IOMUX_PRESENT) 641 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 642 IOMUX_ENABLE_MASK, 0); 643 644 /* Set slot type based on SD or eMMC */ 645 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 646 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 647 648 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 649 ctl_cfg_2); 650 651 /* Enable tuning for SDR50 */ 652 regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 653 TUNINGFORSDR50_MASK); 654 655 ret = sdhci_setup_host(host); 656 if (ret) 657 return ret; 658 659 ret = sdhci_am654_cqe_add_host(host); 660 if (ret) 661 goto err_cleanup_host; 662 663 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 664 if (ret) 665 goto err_cleanup_host; 666 667 ret = __sdhci_add_host(host); 668 if (ret) 669 goto err_cleanup_host; 670 671 return 0; 672 673 err_cleanup_host: 674 sdhci_cleanup_host(host); 675 return ret; 676 } 677 678 static int sdhci_am654_get_of_property(struct platform_device *pdev, 679 struct sdhci_am654_data *sdhci_am654) 680 { 681 struct device *dev = &pdev->dev; 682 int drv_strength; 683 int ret; 684 685 if (sdhci_am654->flags & DLL_PRESENT) { 686 ret = device_property_read_u32(dev, "ti,trm-icp", 687 &sdhci_am654->trm_icp); 688 if (ret) 689 return ret; 690 691 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 692 &drv_strength); 693 if (ret) 694 return ret; 695 696 switch (drv_strength) { 697 case 50: 698 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 699 break; 700 case 33: 701 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 702 break; 703 case 66: 704 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 705 break; 706 case 100: 707 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 708 break; 709 case 40: 710 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 711 break; 712 default: 713 dev_err(dev, "Invalid driver strength\n"); 714 return -EINVAL; 715 } 716 } 717 718 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 719 device_property_read_u32(dev, "ti,clkbuf-sel", 720 &sdhci_am654->clkbuf_sel); 721 722 sdhci_get_of_property(pdev); 723 724 return 0; 725 } 726 727 static const struct of_device_id sdhci_am654_of_match[] = { 728 { 729 .compatible = "ti,am654-sdhci-5.1", 730 .data = &sdhci_am654_drvdata, 731 }, 732 { 733 .compatible = "ti,j721e-sdhci-8bit", 734 .data = &sdhci_j721e_8bit_drvdata, 735 }, 736 { 737 .compatible = "ti,j721e-sdhci-4bit", 738 .data = &sdhci_j721e_4bit_drvdata, 739 }, 740 { /* sentinel */ } 741 }; 742 MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 743 744 static int sdhci_am654_probe(struct platform_device *pdev) 745 { 746 const struct sdhci_am654_driver_data *drvdata; 747 const struct soc_device_attribute *soc; 748 struct sdhci_pltfm_host *pltfm_host; 749 struct sdhci_am654_data *sdhci_am654; 750 const struct of_device_id *match; 751 struct sdhci_host *host; 752 struct clk *clk_xin; 753 struct device *dev = &pdev->dev; 754 void __iomem *base; 755 int ret; 756 757 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 758 drvdata = match->data; 759 760 /* Update drvdata based on SoC revision */ 761 soc = soc_device_match(sdhci_am654_devices); 762 if (soc && soc->data) 763 drvdata = soc->data; 764 765 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 766 if (IS_ERR(host)) 767 return PTR_ERR(host); 768 769 pltfm_host = sdhci_priv(host); 770 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 771 sdhci_am654->flags = drvdata->flags; 772 773 clk_xin = devm_clk_get(dev, "clk_xin"); 774 if (IS_ERR(clk_xin)) { 775 dev_err(dev, "clk_xin clock not found.\n"); 776 ret = PTR_ERR(clk_xin); 777 goto err_pltfm_free; 778 } 779 780 pltfm_host->clk = clk_xin; 781 782 /* Clocks are enabled using pm_runtime */ 783 pm_runtime_enable(dev); 784 ret = pm_runtime_get_sync(dev); 785 if (ret < 0) { 786 pm_runtime_put_noidle(dev); 787 goto pm_runtime_disable; 788 } 789 790 base = devm_platform_ioremap_resource(pdev, 1); 791 if (IS_ERR(base)) { 792 ret = PTR_ERR(base); 793 goto pm_runtime_put; 794 } 795 796 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 797 &sdhci_am654_regmap_config); 798 if (IS_ERR(sdhci_am654->base)) { 799 dev_err(dev, "Failed to initialize regmap\n"); 800 ret = PTR_ERR(sdhci_am654->base); 801 goto pm_runtime_put; 802 } 803 804 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 805 if (ret) 806 goto pm_runtime_put; 807 808 ret = mmc_of_parse(host->mmc); 809 if (ret) { 810 dev_err(dev, "parsing dt failed (%d)\n", ret); 811 goto pm_runtime_put; 812 } 813 814 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 815 816 ret = sdhci_am654_init(host); 817 if (ret) 818 goto pm_runtime_put; 819 820 return 0; 821 822 pm_runtime_put: 823 pm_runtime_put_sync(dev); 824 pm_runtime_disable: 825 pm_runtime_disable(dev); 826 err_pltfm_free: 827 sdhci_pltfm_free(pdev); 828 return ret; 829 } 830 831 static int sdhci_am654_remove(struct platform_device *pdev) 832 { 833 struct sdhci_host *host = platform_get_drvdata(pdev); 834 int ret; 835 836 sdhci_remove_host(host, true); 837 ret = pm_runtime_put_sync(&pdev->dev); 838 if (ret < 0) 839 return ret; 840 841 pm_runtime_disable(&pdev->dev); 842 sdhci_pltfm_free(pdev); 843 844 return 0; 845 } 846 847 static struct platform_driver sdhci_am654_driver = { 848 .driver = { 849 .name = "sdhci-am654", 850 .probe_type = PROBE_PREFER_ASYNCHRONOUS, 851 .of_match_table = sdhci_am654_of_match, 852 }, 853 .probe = sdhci_am654_probe, 854 .remove = sdhci_am654_remove, 855 }; 856 857 module_platform_driver(sdhci_am654_driver); 858 859 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 860 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 861 MODULE_LICENSE("GPL"); 862