1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 4 * 5 * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 6 * 7 */ 8 #include <linux/clk.h> 9 #include <linux/of.h> 10 #include <linux/module.h> 11 #include <linux/pm_runtime.h> 12 #include <linux/property.h> 13 #include <linux/regmap.h> 14 #include <linux/sys_soc.h> 15 16 #include "cqhci.h" 17 #include "sdhci-pltfm.h" 18 19 /* CTL_CFG Registers */ 20 #define CTL_CFG_2 0x14 21 22 #define SLOTTYPE_MASK GENMASK(31, 30) 23 #define SLOTTYPE_EMBEDDED BIT(30) 24 25 /* PHY Registers */ 26 #define PHY_CTRL1 0x100 27 #define PHY_CTRL2 0x104 28 #define PHY_CTRL3 0x108 29 #define PHY_CTRL4 0x10C 30 #define PHY_CTRL5 0x110 31 #define PHY_CTRL6 0x114 32 #define PHY_STAT1 0x130 33 #define PHY_STAT2 0x134 34 35 #define IOMUX_ENABLE_SHIFT 31 36 #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 37 #define OTAPDLYENA_SHIFT 20 38 #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 39 #define OTAPDLYSEL_SHIFT 12 40 #define OTAPDLYSEL_MASK GENMASK(15, 12) 41 #define STRBSEL_SHIFT 24 42 #define STRBSEL_4BIT_MASK GENMASK(27, 24) 43 #define STRBSEL_8BIT_MASK GENMASK(31, 24) 44 #define SEL50_SHIFT 8 45 #define SEL50_MASK BIT(SEL50_SHIFT) 46 #define SEL100_SHIFT 9 47 #define SEL100_MASK BIT(SEL100_SHIFT) 48 #define FREQSEL_SHIFT 8 49 #define FREQSEL_MASK GENMASK(10, 8) 50 #define DLL_TRIM_ICP_SHIFT 4 51 #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 52 #define DR_TY_SHIFT 20 53 #define DR_TY_MASK GENMASK(22, 20) 54 #define ENDLL_SHIFT 1 55 #define ENDLL_MASK BIT(ENDLL_SHIFT) 56 #define DLLRDY_SHIFT 0 57 #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 58 #define PDB_SHIFT 0 59 #define PDB_MASK BIT(PDB_SHIFT) 60 #define CALDONE_SHIFT 1 61 #define CALDONE_MASK BIT(CALDONE_SHIFT) 62 #define RETRIM_SHIFT 17 63 #define RETRIM_MASK BIT(RETRIM_SHIFT) 64 #define SELDLYTXCLK_SHIFT 17 65 #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 66 67 #define DRIVER_STRENGTH_50_OHM 0x0 68 #define DRIVER_STRENGTH_33_OHM 0x1 69 #define DRIVER_STRENGTH_66_OHM 0x2 70 #define DRIVER_STRENGTH_100_OHM 0x3 71 #define DRIVER_STRENGTH_40_OHM 0x4 72 73 #define CLOCK_TOO_SLOW_HZ 400000 74 75 /* Command Queue Host Controller Interface Base address */ 76 #define SDHCI_AM654_CQE_BASE_ADDR 0x200 77 78 static struct regmap_config sdhci_am654_regmap_config = { 79 .reg_bits = 32, 80 .val_bits = 32, 81 .reg_stride = 4, 82 .fast_io = true, 83 }; 84 85 struct sdhci_am654_data { 86 struct regmap *base; 87 bool legacy_otapdly; 88 int otap_del_sel[11]; 89 int trm_icp; 90 int drv_strength; 91 bool dll_on; 92 int strb_sel; 93 u32 flags; 94 }; 95 96 struct sdhci_am654_driver_data { 97 const struct sdhci_pltfm_data *pdata; 98 u32 flags; 99 #define IOMUX_PRESENT (1 << 0) 100 #define FREQSEL_2_BIT (1 << 1) 101 #define STRBSEL_4_BIT (1 << 2) 102 #define DLL_PRESENT (1 << 3) 103 #define DLL_CALIB (1 << 4) 104 }; 105 106 struct timing_data { 107 const char *binding; 108 u32 capability; 109 }; 110 111 static const struct timing_data td[] = { 112 [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0}, 113 [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED}, 114 [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED}, 115 [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12}, 116 [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25}, 117 [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50}, 118 [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 119 MMC_CAP_UHS_SDR104}, 120 [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50}, 121 [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR}, 122 [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200}, 123 [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400}, 124 }; 125 126 static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 127 { 128 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 129 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 130 int sel50, sel100, freqsel; 131 u32 mask, val; 132 int ret; 133 134 if (sdhci_am654->flags & FREQSEL_2_BIT) { 135 switch (clock) { 136 case 200000000: 137 sel50 = 0; 138 sel100 = 0; 139 break; 140 case 100000000: 141 sel50 = 0; 142 sel100 = 1; 143 break; 144 default: 145 sel50 = 1; 146 sel100 = 0; 147 } 148 149 /* Configure PHY DLL frequency */ 150 mask = SEL50_MASK | SEL100_MASK; 151 val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 152 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 153 154 } else { 155 switch (clock) { 156 case 200000000: 157 freqsel = 0x0; 158 break; 159 default: 160 freqsel = 0x4; 161 } 162 163 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 164 freqsel << FREQSEL_SHIFT); 165 } 166 /* Configure DLL TRIM */ 167 mask = DLL_TRIM_ICP_MASK; 168 val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 169 170 /* Configure DLL driver strength */ 171 mask |= DR_TY_MASK; 172 val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 173 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 174 175 /* Enable DLL */ 176 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 177 0x1 << ENDLL_SHIFT); 178 /* 179 * Poll for DLL ready. Use a one second timeout. 180 * Works in all experiments done so far 181 */ 182 ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 183 val & DLLRDY_MASK, 1000, 1000000); 184 if (ret) { 185 dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 186 return; 187 } 188 189 sdhci_am654->dll_on = true; 190 } 191 192 static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 193 { 194 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 195 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 196 unsigned char timing = host->mmc->ios.timing; 197 u32 otap_del_sel; 198 u32 otap_del_ena; 199 u32 mask, val; 200 201 if (sdhci_am654->dll_on) { 202 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 203 204 sdhci_am654->dll_on = false; 205 } 206 207 sdhci_set_clock(host, clock); 208 209 /* Setup DLL Output TAP delay */ 210 if (sdhci_am654->legacy_otapdly) 211 otap_del_sel = sdhci_am654->otap_del_sel[0]; 212 else 213 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 214 215 otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 216 217 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 218 val = (otap_del_ena << OTAPDLYENA_SHIFT) | 219 (otap_del_sel << OTAPDLYSEL_SHIFT); 220 221 /* Write to STRBSEL for HS400 speed mode */ 222 if (timing == MMC_TIMING_MMC_HS400) { 223 if (sdhci_am654->flags & STRBSEL_4_BIT) 224 mask |= STRBSEL_4BIT_MASK; 225 else 226 mask |= STRBSEL_8BIT_MASK; 227 228 val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 229 } 230 231 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 232 233 if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) { 234 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 235 SELDLYTXCLK_MASK, 0); 236 sdhci_am654_setup_dll(host, clock); 237 } else { 238 regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 239 SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT); 240 } 241 } 242 243 static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 244 unsigned int clock) 245 { 246 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 247 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 248 unsigned char timing = host->mmc->ios.timing; 249 u32 otap_del_sel; 250 u32 mask, val; 251 252 /* Setup DLL Output TAP delay */ 253 if (sdhci_am654->legacy_otapdly) 254 otap_del_sel = sdhci_am654->otap_del_sel[0]; 255 else 256 otap_del_sel = sdhci_am654->otap_del_sel[timing]; 257 258 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 259 val = (0x1 << OTAPDLYENA_SHIFT) | 260 (otap_del_sel << OTAPDLYSEL_SHIFT); 261 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 262 263 sdhci_set_clock(host, clock); 264 } 265 266 static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 267 { 268 unsigned char timing = host->mmc->ios.timing; 269 270 if (reg == SDHCI_HOST_CONTROL) { 271 switch (timing) { 272 /* 273 * According to the data manual, HISPD bit 274 * should not be set in these speed modes. 275 */ 276 case MMC_TIMING_SD_HS: 277 case MMC_TIMING_MMC_HS: 278 case MMC_TIMING_UHS_SDR12: 279 case MMC_TIMING_UHS_SDR25: 280 val &= ~SDHCI_CTRL_HISPD; 281 } 282 } 283 284 writeb(val, host->ioaddr + reg); 285 } 286 287 static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 288 { 289 struct sdhci_host *host = mmc_priv(mmc); 290 int err = sdhci_execute_tuning(mmc, opcode); 291 292 if (err) 293 return err; 294 /* 295 * Tuning data remains in the buffer after tuning. 296 * Do a command and data reset to get rid of it 297 */ 298 sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 299 300 return 0; 301 } 302 303 static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 304 { 305 int cmd_error = 0; 306 int data_error = 0; 307 308 if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 309 return intmask; 310 311 cqhci_irq(host->mmc, intmask, cmd_error, data_error); 312 313 return 0; 314 } 315 316 static struct sdhci_ops sdhci_am654_ops = { 317 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 318 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 319 .set_uhs_signaling = sdhci_set_uhs_signaling, 320 .set_bus_width = sdhci_set_bus_width, 321 .set_power = sdhci_set_power_and_bus_voltage, 322 .set_clock = sdhci_am654_set_clock, 323 .write_b = sdhci_am654_write_b, 324 .irq = sdhci_am654_cqhci_irq, 325 .reset = sdhci_reset, 326 }; 327 328 static const struct sdhci_pltfm_data sdhci_am654_pdata = { 329 .ops = &sdhci_am654_ops, 330 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 331 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 332 }; 333 334 static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 335 .pdata = &sdhci_am654_pdata, 336 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 337 DLL_CALIB, 338 }; 339 340 static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 341 .pdata = &sdhci_am654_pdata, 342 .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 343 }; 344 345 static struct sdhci_ops sdhci_j721e_8bit_ops = { 346 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 347 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 348 .set_uhs_signaling = sdhci_set_uhs_signaling, 349 .set_bus_width = sdhci_set_bus_width, 350 .set_power = sdhci_set_power_and_bus_voltage, 351 .set_clock = sdhci_am654_set_clock, 352 .write_b = sdhci_am654_write_b, 353 .irq = sdhci_am654_cqhci_irq, 354 .reset = sdhci_reset, 355 }; 356 357 static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 358 .ops = &sdhci_j721e_8bit_ops, 359 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 360 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 361 }; 362 363 static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 364 .pdata = &sdhci_j721e_8bit_pdata, 365 .flags = DLL_PRESENT | DLL_CALIB, 366 }; 367 368 static struct sdhci_ops sdhci_j721e_4bit_ops = { 369 .get_max_clock = sdhci_pltfm_clk_get_max_clock, 370 .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 371 .set_uhs_signaling = sdhci_set_uhs_signaling, 372 .set_bus_width = sdhci_set_bus_width, 373 .set_power = sdhci_set_power_and_bus_voltage, 374 .set_clock = sdhci_j721e_4bit_set_clock, 375 .write_b = sdhci_am654_write_b, 376 .irq = sdhci_am654_cqhci_irq, 377 .reset = sdhci_reset, 378 }; 379 380 static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 381 .ops = &sdhci_j721e_4bit_ops, 382 .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 383 .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 384 }; 385 386 static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 387 .pdata = &sdhci_j721e_4bit_pdata, 388 .flags = IOMUX_PRESENT, 389 }; 390 391 static const struct soc_device_attribute sdhci_am654_devices[] = { 392 { .family = "AM65X", 393 .revision = "SR1.0", 394 .data = &sdhci_am654_sr1_drvdata 395 }, 396 {/* sentinel */} 397 }; 398 399 static void sdhci_am654_dumpregs(struct mmc_host *mmc) 400 { 401 sdhci_dumpregs(mmc_priv(mmc)); 402 } 403 404 static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 405 .enable = sdhci_cqe_enable, 406 .disable = sdhci_cqe_disable, 407 .dumpregs = sdhci_am654_dumpregs, 408 }; 409 410 static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 411 { 412 struct cqhci_host *cq_host; 413 int ret; 414 415 cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 416 GFP_KERNEL); 417 if (!cq_host) 418 return -ENOMEM; 419 420 cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 421 cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 422 cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 423 cq_host->ops = &sdhci_am654_cqhci_ops; 424 425 host->mmc->caps2 |= MMC_CAP2_CQE; 426 427 ret = cqhci_init(cq_host, host->mmc, 1); 428 429 return ret; 430 } 431 432 static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 433 struct sdhci_am654_data *sdhci_am654) 434 { 435 struct device *dev = mmc_dev(host->mmc); 436 int i; 437 int ret; 438 439 ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding, 440 &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 441 if (ret) { 442 /* 443 * ti,otap-del-sel-legacy is mandatory, look for old binding 444 * if not found. 445 */ 446 ret = device_property_read_u32(dev, "ti,otap-del-sel", 447 &sdhci_am654->otap_del_sel[0]); 448 if (ret) { 449 dev_err(dev, "Couldn't find otap-del-sel\n"); 450 451 return ret; 452 } 453 454 dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 455 sdhci_am654->legacy_otapdly = true; 456 457 return 0; 458 } 459 460 for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 461 462 ret = device_property_read_u32(dev, td[i].binding, 463 &sdhci_am654->otap_del_sel[i]); 464 if (ret) { 465 dev_dbg(dev, "Couldn't find %s\n", 466 td[i].binding); 467 /* 468 * Remove the corresponding capability 469 * if an otap-del-sel value is not found 470 */ 471 if (i <= MMC_TIMING_MMC_DDR52) 472 host->mmc->caps &= ~td[i].capability; 473 else 474 host->mmc->caps2 &= ~td[i].capability; 475 } 476 } 477 478 return 0; 479 } 480 481 static int sdhci_am654_init(struct sdhci_host *host) 482 { 483 struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 484 struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 485 u32 ctl_cfg_2 = 0; 486 u32 mask; 487 u32 val; 488 int ret; 489 490 /* Reset OTAP to default value */ 491 mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 492 regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 493 494 if (sdhci_am654->flags & DLL_CALIB) { 495 regmap_read(sdhci_am654->base, PHY_STAT1, &val); 496 if (~val & CALDONE_MASK) { 497 /* Calibrate IO lines */ 498 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 499 PDB_MASK, PDB_MASK); 500 ret = regmap_read_poll_timeout(sdhci_am654->base, 501 PHY_STAT1, val, 502 val & CALDONE_MASK, 503 1, 20); 504 if (ret) 505 return ret; 506 } 507 } 508 509 /* Enable pins by setting IO mux to 0 */ 510 if (sdhci_am654->flags & IOMUX_PRESENT) 511 regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 512 IOMUX_ENABLE_MASK, 0); 513 514 /* Set slot type based on SD or eMMC */ 515 if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 516 ctl_cfg_2 = SLOTTYPE_EMBEDDED; 517 518 regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 519 ctl_cfg_2); 520 521 ret = sdhci_setup_host(host); 522 if (ret) 523 return ret; 524 525 ret = sdhci_am654_cqe_add_host(host); 526 if (ret) 527 goto err_cleanup_host; 528 529 ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 530 if (ret) 531 goto err_cleanup_host; 532 533 ret = __sdhci_add_host(host); 534 if (ret) 535 goto err_cleanup_host; 536 537 return 0; 538 539 err_cleanup_host: 540 sdhci_cleanup_host(host); 541 return ret; 542 } 543 544 static int sdhci_am654_get_of_property(struct platform_device *pdev, 545 struct sdhci_am654_data *sdhci_am654) 546 { 547 struct device *dev = &pdev->dev; 548 int drv_strength; 549 int ret; 550 551 if (sdhci_am654->flags & DLL_PRESENT) { 552 ret = device_property_read_u32(dev, "ti,trm-icp", 553 &sdhci_am654->trm_icp); 554 if (ret) 555 return ret; 556 557 ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 558 &drv_strength); 559 if (ret) 560 return ret; 561 562 switch (drv_strength) { 563 case 50: 564 sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 565 break; 566 case 33: 567 sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 568 break; 569 case 66: 570 sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 571 break; 572 case 100: 573 sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 574 break; 575 case 40: 576 sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 577 break; 578 default: 579 dev_err(dev, "Invalid driver strength\n"); 580 return -EINVAL; 581 } 582 } 583 584 device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 585 586 sdhci_get_of_property(pdev); 587 588 return 0; 589 } 590 591 static const struct of_device_id sdhci_am654_of_match[] = { 592 { 593 .compatible = "ti,am654-sdhci-5.1", 594 .data = &sdhci_am654_drvdata, 595 }, 596 { 597 .compatible = "ti,j721e-sdhci-8bit", 598 .data = &sdhci_j721e_8bit_drvdata, 599 }, 600 { 601 .compatible = "ti,j721e-sdhci-4bit", 602 .data = &sdhci_j721e_4bit_drvdata, 603 }, 604 { /* sentinel */ } 605 }; 606 607 static int sdhci_am654_probe(struct platform_device *pdev) 608 { 609 const struct sdhci_am654_driver_data *drvdata; 610 const struct soc_device_attribute *soc; 611 struct sdhci_pltfm_host *pltfm_host; 612 struct sdhci_am654_data *sdhci_am654; 613 const struct of_device_id *match; 614 struct sdhci_host *host; 615 struct clk *clk_xin; 616 struct device *dev = &pdev->dev; 617 void __iomem *base; 618 int ret; 619 620 match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 621 drvdata = match->data; 622 623 /* Update drvdata based on SoC revision */ 624 soc = soc_device_match(sdhci_am654_devices); 625 if (soc && soc->data) 626 drvdata = soc->data; 627 628 host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 629 if (IS_ERR(host)) 630 return PTR_ERR(host); 631 632 pltfm_host = sdhci_priv(host); 633 sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 634 sdhci_am654->flags = drvdata->flags; 635 636 clk_xin = devm_clk_get(dev, "clk_xin"); 637 if (IS_ERR(clk_xin)) { 638 dev_err(dev, "clk_xin clock not found.\n"); 639 ret = PTR_ERR(clk_xin); 640 goto err_pltfm_free; 641 } 642 643 pltfm_host->clk = clk_xin; 644 645 /* Clocks are enabled using pm_runtime */ 646 pm_runtime_enable(dev); 647 ret = pm_runtime_get_sync(dev); 648 if (ret < 0) { 649 pm_runtime_put_noidle(dev); 650 goto pm_runtime_disable; 651 } 652 653 base = devm_platform_ioremap_resource(pdev, 1); 654 if (IS_ERR(base)) { 655 ret = PTR_ERR(base); 656 goto pm_runtime_put; 657 } 658 659 sdhci_am654->base = devm_regmap_init_mmio(dev, base, 660 &sdhci_am654_regmap_config); 661 if (IS_ERR(sdhci_am654->base)) { 662 dev_err(dev, "Failed to initialize regmap\n"); 663 ret = PTR_ERR(sdhci_am654->base); 664 goto pm_runtime_put; 665 } 666 667 ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 668 if (ret) 669 goto pm_runtime_put; 670 671 ret = mmc_of_parse(host->mmc); 672 if (ret) { 673 dev_err(dev, "parsing dt failed (%d)\n", ret); 674 goto pm_runtime_put; 675 } 676 677 host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 678 679 ret = sdhci_am654_init(host); 680 if (ret) 681 goto pm_runtime_put; 682 683 return 0; 684 685 pm_runtime_put: 686 pm_runtime_put_sync(dev); 687 pm_runtime_disable: 688 pm_runtime_disable(dev); 689 err_pltfm_free: 690 sdhci_pltfm_free(pdev); 691 return ret; 692 } 693 694 static int sdhci_am654_remove(struct platform_device *pdev) 695 { 696 struct sdhci_host *host = platform_get_drvdata(pdev); 697 int ret; 698 699 sdhci_remove_host(host, true); 700 ret = pm_runtime_put_sync(&pdev->dev); 701 if (ret < 0) 702 return ret; 703 704 pm_runtime_disable(&pdev->dev); 705 sdhci_pltfm_free(pdev); 706 707 return 0; 708 } 709 710 static struct platform_driver sdhci_am654_driver = { 711 .driver = { 712 .name = "sdhci-am654", 713 .of_match_table = sdhci_am654_of_match, 714 }, 715 .probe = sdhci_am654_probe, 716 .remove = sdhci_am654_remove, 717 }; 718 719 module_platform_driver(sdhci_am654_driver); 720 721 MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 722 MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 723 MODULE_LICENSE("GPL"); 724