141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 59481b45cSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 97ca0f166SFaiz Abbas #include <linux/iopoll.h> 1099909b55SFaiz Abbas #include <linux/of.h> 1141fd4caeSFaiz Abbas #include <linux/module.h> 1241fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1341fd4caeSFaiz Abbas #include <linux/property.h> 1441fd4caeSFaiz Abbas #include <linux/regmap.h> 1509db9943SFaiz Abbas #include <linux/sys_soc.h> 1641fd4caeSFaiz Abbas 17f545702bSFaiz Abbas #include "cqhci.h" 18162503fdSBrian Norris #include "sdhci-cqhci.h" 1941fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 2041fd4caeSFaiz Abbas 2141fd4caeSFaiz Abbas /* CTL_CFG Registers */ 2241fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 23764384d0SFaiz Abbas #define CTL_CFG_3 0x18 2441fd4caeSFaiz Abbas 2541fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2641fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 27764384d0SFaiz Abbas #define TUNINGFORSDR50_MASK BIT(13) 2841fd4caeSFaiz Abbas 2941fd4caeSFaiz Abbas /* PHY Registers */ 3041fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 3141fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 3241fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 3341fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 3441fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3541fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3641fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3741fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3841fd4caeSFaiz Abbas 3941fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 4041fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 4141fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 4241fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 4341fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 4441fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4541fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4699909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4799909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4841fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4941fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 5041fd4caeSFaiz Abbas #define SEL100_SHIFT 9 5141fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 5299909b55SFaiz Abbas #define FREQSEL_SHIFT 8 5399909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 5461d9c4aaSFaiz Abbas #define CLKBUFSEL_SHIFT 0 5561d9c4aaSFaiz Abbas #define CLKBUFSEL_MASK GENMASK(2, 0) 5641fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5741fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5841fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5941fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 6041fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 6141fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 6241fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 6341fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 6441fd4caeSFaiz Abbas #define PDB_SHIFT 0 6541fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 6641fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6741fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6841fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6941fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 700003417dSFaiz Abbas #define SELDLYTXCLK_SHIFT 17 710003417dSFaiz Abbas #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 72a0a62497SFaiz Abbas #define SELDLYRXCLK_SHIFT 16 73a0a62497SFaiz Abbas #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 74a0a62497SFaiz Abbas #define ITAPDLYSEL_SHIFT 0 75a0a62497SFaiz Abbas #define ITAPDLYSEL_MASK GENMASK(4, 0) 76a0a62497SFaiz Abbas #define ITAPDLYENA_SHIFT 8 77a0a62497SFaiz Abbas #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 78a0a62497SFaiz Abbas #define ITAPCHGWIN_SHIFT 9 79a0a62497SFaiz Abbas #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 8041fd4caeSFaiz Abbas 8141fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 8241fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 8341fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 8441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 8541fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 8641fd4caeSFaiz Abbas 87a0a62497SFaiz Abbas #define CLOCK_TOO_SLOW_HZ 50000000 889d2e77ffSAswath Govindraju #define SDHCI_AM654_AUTOSUSPEND_DELAY -1 8941fd4caeSFaiz Abbas 90f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 91f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 92f545702bSFaiz Abbas 9341fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 9441fd4caeSFaiz Abbas .reg_bits = 32, 9541fd4caeSFaiz Abbas .val_bits = 32, 9641fd4caeSFaiz Abbas .reg_stride = 4, 9741fd4caeSFaiz Abbas .fast_io = true, 9841fd4caeSFaiz Abbas }; 9941fd4caeSFaiz Abbas 1008ee5fc0eSFaiz Abbas struct timing_data { 101a0a62497SFaiz Abbas const char *otap_binding; 102a0a62497SFaiz Abbas const char *itap_binding; 1038ee5fc0eSFaiz Abbas u32 capability; 1048ee5fc0eSFaiz Abbas }; 1058ee5fc0eSFaiz Abbas 1068ee5fc0eSFaiz Abbas static const struct timing_data td[] = { 107a0a62497SFaiz Abbas [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 108a0a62497SFaiz Abbas "ti,itap-del-sel-legacy", 109a0a62497SFaiz Abbas 0}, 110a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 111a0a62497SFaiz Abbas "ti,itap-del-sel-mmc-hs", 112a0a62497SFaiz Abbas MMC_CAP_MMC_HIGHSPEED}, 113a0a62497SFaiz Abbas [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 114a0a62497SFaiz Abbas "ti,itap-del-sel-sd-hs", 115a0a62497SFaiz Abbas MMC_CAP_SD_HIGHSPEED}, 116a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 117a0a62497SFaiz Abbas "ti,itap-del-sel-sdr12", 118a0a62497SFaiz Abbas MMC_CAP_UHS_SDR12}, 119a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 120a0a62497SFaiz Abbas "ti,itap-del-sel-sdr25", 121a0a62497SFaiz Abbas MMC_CAP_UHS_SDR25}, 122a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 123a0a62497SFaiz Abbas NULL, 124a0a62497SFaiz Abbas MMC_CAP_UHS_SDR50}, 1258ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 126a0a62497SFaiz Abbas NULL, 1278ee5fc0eSFaiz Abbas MMC_CAP_UHS_SDR104}, 128a0a62497SFaiz Abbas [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 129a0a62497SFaiz Abbas NULL, 130a0a62497SFaiz Abbas MMC_CAP_UHS_DDR50}, 131a0a62497SFaiz Abbas [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 132a0a62497SFaiz Abbas "ti,itap-del-sel-ddr52", 133a0a62497SFaiz Abbas MMC_CAP_DDR}, 134a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 135a0a62497SFaiz Abbas NULL, 136a0a62497SFaiz Abbas MMC_CAP2_HS200}, 137a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 138a0a62497SFaiz Abbas NULL, 139a0a62497SFaiz Abbas MMC_CAP2_HS400}, 1408ee5fc0eSFaiz Abbas }; 1418ee5fc0eSFaiz Abbas 1421e753dbbSFaiz Abbas struct sdhci_am654_data { 1431e753dbbSFaiz Abbas struct regmap *base; 1441e753dbbSFaiz Abbas bool legacy_otapdly; 1451e753dbbSFaiz Abbas int otap_del_sel[ARRAY_SIZE(td)]; 146a0a62497SFaiz Abbas int itap_del_sel[ARRAY_SIZE(td)]; 1471e753dbbSFaiz Abbas int clkbuf_sel; 1481e753dbbSFaiz Abbas int trm_icp; 1491e753dbbSFaiz Abbas int drv_strength; 1501e753dbbSFaiz Abbas int strb_sel; 1511e753dbbSFaiz Abbas u32 flags; 152c7666240SVignesh Raghavendra u32 quirks; 153c7666240SVignesh Raghavendra 154c7666240SVignesh Raghavendra #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 1551e753dbbSFaiz Abbas }; 1561e753dbbSFaiz Abbas 1571e753dbbSFaiz Abbas struct sdhci_am654_driver_data { 1581e753dbbSFaiz Abbas const struct sdhci_pltfm_data *pdata; 1591e753dbbSFaiz Abbas u32 flags; 1601e753dbbSFaiz Abbas #define IOMUX_PRESENT (1 << 0) 1611e753dbbSFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 1621e753dbbSFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 1631e753dbbSFaiz Abbas #define DLL_PRESENT (1 << 3) 1641e753dbbSFaiz Abbas #define DLL_CALIB (1 << 4) 1651e753dbbSFaiz Abbas }; 1661e753dbbSFaiz Abbas 167a161c45fSFaiz Abbas static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 168a161c45fSFaiz Abbas { 169a161c45fSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 170a161c45fSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 171a161c45fSFaiz Abbas int sel50, sel100, freqsel; 172a161c45fSFaiz Abbas u32 mask, val; 173a161c45fSFaiz Abbas int ret; 174a161c45fSFaiz Abbas 175a0a62497SFaiz Abbas /* Disable delay chain mode */ 176a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 177a0a62497SFaiz Abbas SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 178a0a62497SFaiz Abbas 179a161c45fSFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 180a161c45fSFaiz Abbas switch (clock) { 181a161c45fSFaiz Abbas case 200000000: 182a161c45fSFaiz Abbas sel50 = 0; 183a161c45fSFaiz Abbas sel100 = 0; 184a161c45fSFaiz Abbas break; 185a161c45fSFaiz Abbas case 100000000: 186a161c45fSFaiz Abbas sel50 = 0; 187a161c45fSFaiz Abbas sel100 = 1; 188a161c45fSFaiz Abbas break; 189a161c45fSFaiz Abbas default: 190a161c45fSFaiz Abbas sel50 = 1; 191a161c45fSFaiz Abbas sel100 = 0; 192a161c45fSFaiz Abbas } 193a161c45fSFaiz Abbas 194a161c45fSFaiz Abbas /* Configure PHY DLL frequency */ 195a161c45fSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 196a161c45fSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 197a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 198a161c45fSFaiz Abbas 199a161c45fSFaiz Abbas } else { 200a161c45fSFaiz Abbas switch (clock) { 201a161c45fSFaiz Abbas case 200000000: 202a161c45fSFaiz Abbas freqsel = 0x0; 203a161c45fSFaiz Abbas break; 204a161c45fSFaiz Abbas default: 205a161c45fSFaiz Abbas freqsel = 0x4; 206a161c45fSFaiz Abbas } 207a161c45fSFaiz Abbas 208a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 209a161c45fSFaiz Abbas freqsel << FREQSEL_SHIFT); 210a161c45fSFaiz Abbas } 211a161c45fSFaiz Abbas /* Configure DLL TRIM */ 212a161c45fSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 213a161c45fSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 214a161c45fSFaiz Abbas 215a161c45fSFaiz Abbas /* Configure DLL driver strength */ 216a161c45fSFaiz Abbas mask |= DR_TY_MASK; 217a161c45fSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 218a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 219a161c45fSFaiz Abbas 220a161c45fSFaiz Abbas /* Enable DLL */ 221a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 222a161c45fSFaiz Abbas 0x1 << ENDLL_SHIFT); 223a161c45fSFaiz Abbas /* 224a161c45fSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 225a161c45fSFaiz Abbas * Works in all experiments done so far 226a161c45fSFaiz Abbas */ 227a161c45fSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 228a161c45fSFaiz Abbas val & DLLRDY_MASK, 1000, 1000000); 229a161c45fSFaiz Abbas if (ret) { 230a161c45fSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 231a161c45fSFaiz Abbas return; 232a161c45fSFaiz Abbas } 233a0a62497SFaiz Abbas } 234a161c45fSFaiz Abbas 235a0a62497SFaiz Abbas static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 236a0a62497SFaiz Abbas u32 itapdly) 237a0a62497SFaiz Abbas { 238a0a62497SFaiz Abbas /* Set ITAPCHGWIN before writing to ITAPDLY */ 239a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 240a0a62497SFaiz Abbas 1 << ITAPCHGWIN_SHIFT); 241a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 242a0a62497SFaiz Abbas itapdly << ITAPDLYSEL_SHIFT); 243a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 244a0a62497SFaiz Abbas } 245a0a62497SFaiz Abbas 246a0a62497SFaiz Abbas static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 247a0a62497SFaiz Abbas unsigned char timing) 248a0a62497SFaiz Abbas { 249a0a62497SFaiz Abbas u32 mask, val; 250a0a62497SFaiz Abbas 251a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 252a0a62497SFaiz Abbas 253a0a62497SFaiz Abbas val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 254a0a62497SFaiz Abbas mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 255a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 256a0a62497SFaiz Abbas 257a0a62497SFaiz Abbas sdhci_am654_write_itapdly(sdhci_am654, 258a0a62497SFaiz Abbas sdhci_am654->itap_del_sel[timing]); 259a161c45fSFaiz Abbas } 260a161c45fSFaiz Abbas 26141fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 26241fd4caeSFaiz Abbas { 26341fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 26441fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2658ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2668ee5fc0eSFaiz Abbas u32 otap_del_sel; 2678ee5fc0eSFaiz Abbas u32 otap_del_ena; 26841fd4caeSFaiz Abbas u32 mask, val; 26941fd4caeSFaiz Abbas 2708023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 27141fd4caeSFaiz Abbas 27241fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 27341fd4caeSFaiz Abbas 27441fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 2758ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 2768ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 27799909b55SFaiz Abbas else 2788ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 27999909b55SFaiz Abbas 2808ee5fc0eSFaiz Abbas otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 2818ee5fc0eSFaiz Abbas 2828ee5fc0eSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2838ee5fc0eSFaiz Abbas val = (otap_del_ena << OTAPDLYENA_SHIFT) | 2848ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2858ee5fc0eSFaiz Abbas 2868ee5fc0eSFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 2878ee5fc0eSFaiz Abbas if (timing == MMC_TIMING_MMC_HS400) { 2888ee5fc0eSFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 2898ee5fc0eSFaiz Abbas mask |= STRBSEL_4BIT_MASK; 2908ee5fc0eSFaiz Abbas else 2918ee5fc0eSFaiz Abbas mask |= STRBSEL_8BIT_MASK; 2928ee5fc0eSFaiz Abbas 2938ee5fc0eSFaiz Abbas val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 29499909b55SFaiz Abbas } 29599909b55SFaiz Abbas 2968ee5fc0eSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2978ee5fc0eSFaiz Abbas 298a0a62497SFaiz Abbas if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 299a161c45fSFaiz Abbas sdhci_am654_setup_dll(host, clock); 300a0a62497SFaiz Abbas else 301a0a62497SFaiz Abbas sdhci_am654_setup_delay_chain(sdhci_am654, timing); 30261d9c4aaSFaiz Abbas 30361d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 30461d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 30541fd4caeSFaiz Abbas } 30641fd4caeSFaiz Abbas 3078751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 3088751c8bdSYueHaibing unsigned int clock) 3091accbcedSFaiz Abbas { 3101accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3111accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 3128ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3138ee5fc0eSFaiz Abbas u32 otap_del_sel; 3148ee5fc0eSFaiz Abbas u32 mask, val; 3158ee5fc0eSFaiz Abbas 3168ee5fc0eSFaiz Abbas /* Setup DLL Output TAP delay */ 3178ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 3188ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 3198ee5fc0eSFaiz Abbas else 3208ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 3211accbcedSFaiz Abbas 3221accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 3238ee5fc0eSFaiz Abbas val = (0x1 << OTAPDLYENA_SHIFT) | 3248ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 3251accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 3261accbcedSFaiz Abbas 32761d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 32861d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 32961d9c4aaSFaiz Abbas 3301accbcedSFaiz Abbas sdhci_set_clock(host, clock); 3311accbcedSFaiz Abbas } 3321accbcedSFaiz Abbas 3337ca0f166SFaiz Abbas static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 3347ca0f166SFaiz Abbas { 3357ca0f166SFaiz Abbas writeb(val, host->ioaddr + reg); 3367ca0f166SFaiz Abbas usleep_range(1000, 10000); 3377ca0f166SFaiz Abbas return readb(host->ioaddr + reg); 3387ca0f166SFaiz Abbas } 3397ca0f166SFaiz Abbas 3407ca0f166SFaiz Abbas #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 341e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 342e374e875SFaiz Abbas { 343e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3447ca0f166SFaiz Abbas u8 pwr; 3457ca0f166SFaiz Abbas int ret; 346e374e875SFaiz Abbas 347e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 348e374e875SFaiz Abbas switch (timing) { 349e374e875SFaiz Abbas /* 350e374e875SFaiz Abbas * According to the data manual, HISPD bit 351e374e875SFaiz Abbas * should not be set in these speed modes. 352e374e875SFaiz Abbas */ 353e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 354e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 355e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 356e374e875SFaiz Abbas } 357e374e875SFaiz Abbas } 358e374e875SFaiz Abbas 359e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 3607ca0f166SFaiz Abbas if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 3617ca0f166SFaiz Abbas /* 3627ca0f166SFaiz Abbas * Power on will not happen until the card detect debounce 3637ca0f166SFaiz Abbas * timer expires. Wait at least 1.5 seconds for the power on 3647ca0f166SFaiz Abbas * bit to be set 3657ca0f166SFaiz Abbas */ 3667ca0f166SFaiz Abbas ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 3677ca0f166SFaiz Abbas pwr & SDHCI_POWER_ON, 0, 3687ca0f166SFaiz Abbas MAX_POWER_ON_TIMEOUT, false, host, val, 3697ca0f166SFaiz Abbas reg); 3707ca0f166SFaiz Abbas if (ret) 37111440da7SFrancesco Dolcini dev_info(mmc_dev(host->mmc), "Power on failed\n"); 3727ca0f166SFaiz Abbas } 373e374e875SFaiz Abbas } 374e374e875SFaiz Abbas 375c7666240SVignesh Raghavendra static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 376c7666240SVignesh Raghavendra { 377c7666240SVignesh Raghavendra u8 ctrl; 378c7666240SVignesh Raghavendra struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 379c7666240SVignesh Raghavendra struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 380c7666240SVignesh Raghavendra 381162503fdSBrian Norris sdhci_and_cqhci_reset(host, mask); 382c7666240SVignesh Raghavendra 383c7666240SVignesh Raghavendra if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 384c7666240SVignesh Raghavendra ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 385c7666240SVignesh Raghavendra ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 386c7666240SVignesh Raghavendra sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 387c7666240SVignesh Raghavendra } 388c7666240SVignesh Raghavendra } 389c7666240SVignesh Raghavendra 390de31f6abSFaiz Abbas static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 391de31f6abSFaiz Abbas { 392de31f6abSFaiz Abbas struct sdhci_host *host = mmc_priv(mmc); 393de31f6abSFaiz Abbas int err = sdhci_execute_tuning(mmc, opcode); 39441fd4caeSFaiz Abbas 395de31f6abSFaiz Abbas if (err) 396de31f6abSFaiz Abbas return err; 397de31f6abSFaiz Abbas /* 398de31f6abSFaiz Abbas * Tuning data remains in the buffer after tuning. 399de31f6abSFaiz Abbas * Do a command and data reset to get rid of it 400de31f6abSFaiz Abbas */ 401de31f6abSFaiz Abbas sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 40241fd4caeSFaiz Abbas 403de31f6abSFaiz Abbas return 0; 404de31f6abSFaiz Abbas } 40599909b55SFaiz Abbas 406f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 407f545702bSFaiz Abbas { 408f545702bSFaiz Abbas int cmd_error = 0; 409f545702bSFaiz Abbas int data_error = 0; 410f545702bSFaiz Abbas 411f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 412f545702bSFaiz Abbas return intmask; 413f545702bSFaiz Abbas 414f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 415f545702bSFaiz Abbas 416f545702bSFaiz Abbas return 0; 417f545702bSFaiz Abbas } 418f545702bSFaiz Abbas 41913ebeae6SFaiz Abbas #define ITAP_MAX 32 42013ebeae6SFaiz Abbas static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 42113ebeae6SFaiz Abbas u32 opcode) 42213ebeae6SFaiz Abbas { 42313ebeae6SFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 42413ebeae6SFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 42513ebeae6SFaiz Abbas int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; 42613ebeae6SFaiz Abbas u32 itap; 42713ebeae6SFaiz Abbas 42813ebeae6SFaiz Abbas /* Enable ITAPDLY */ 42913ebeae6SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 43013ebeae6SFaiz Abbas 1 << ITAPDLYENA_SHIFT); 43113ebeae6SFaiz Abbas 43213ebeae6SFaiz Abbas for (itap = 0; itap < ITAP_MAX; itap++) { 43313ebeae6SFaiz Abbas sdhci_am654_write_itapdly(sdhci_am654, itap); 43413ebeae6SFaiz Abbas 43513ebeae6SFaiz Abbas cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); 43613ebeae6SFaiz Abbas if (cur_val && !prev_val) 43713ebeae6SFaiz Abbas pass_window = itap; 43813ebeae6SFaiz Abbas 43913ebeae6SFaiz Abbas if (!cur_val) 44013ebeae6SFaiz Abbas fail_len++; 44113ebeae6SFaiz Abbas 44213ebeae6SFaiz Abbas prev_val = cur_val; 44313ebeae6SFaiz Abbas } 44413ebeae6SFaiz Abbas /* 44513ebeae6SFaiz Abbas * Having determined the length of the failing window and start of 44613ebeae6SFaiz Abbas * the passing window calculate the length of the passing window and 44713ebeae6SFaiz Abbas * set the final value halfway through it considering the range as a 44813ebeae6SFaiz Abbas * circular buffer 44913ebeae6SFaiz Abbas */ 45013ebeae6SFaiz Abbas pass_len = ITAP_MAX - fail_len; 45113ebeae6SFaiz Abbas itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; 45213ebeae6SFaiz Abbas sdhci_am654_write_itapdly(sdhci_am654, itap); 45313ebeae6SFaiz Abbas 45413ebeae6SFaiz Abbas return 0; 45513ebeae6SFaiz Abbas } 45613ebeae6SFaiz Abbas 45741fd4caeSFaiz Abbas static struct sdhci_ops sdhci_am654_ops = { 45813ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 45941fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 46041fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 46141fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 46241fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4639d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 46441fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 46541fd4caeSFaiz Abbas .write_b = sdhci_am654_write_b, 46627f4e1e9SFaiz Abbas .irq = sdhci_am654_cqhci_irq, 467162503fdSBrian Norris .reset = sdhci_and_cqhci_reset, 46841fd4caeSFaiz Abbas }; 46941fd4caeSFaiz Abbas 47041fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 47141fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 4724d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 47341fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 47441fd4caeSFaiz Abbas }; 47541fd4caeSFaiz Abbas 47609db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 47741fd4caeSFaiz Abbas .pdata = &sdhci_am654_pdata, 47823514731SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 47923514731SFaiz Abbas DLL_CALIB, 48041fd4caeSFaiz Abbas }; 48141fd4caeSFaiz Abbas 48209db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 48309db9943SFaiz Abbas .pdata = &sdhci_am654_pdata, 48409db9943SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 48509db9943SFaiz Abbas }; 48609db9943SFaiz Abbas 4878751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 48813ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 48999909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 49099909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 49199909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 49299909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4939d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 49499909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 49599909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 496f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 497162503fdSBrian Norris .reset = sdhci_and_cqhci_reset, 49899909b55SFaiz Abbas }; 49999909b55SFaiz Abbas 50099909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 50199909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 5024d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 50399909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 50499909b55SFaiz Abbas }; 50599909b55SFaiz Abbas 50699909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 50799909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 50823514731SFaiz Abbas .flags = DLL_PRESENT | DLL_CALIB, 50999909b55SFaiz Abbas }; 51099909b55SFaiz Abbas 5118751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 51213ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 5131accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 5141accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 5151accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 5161accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5179d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 5181accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 5191accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 520f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 521c7666240SVignesh Raghavendra .reset = sdhci_am654_reset, 5221accbcedSFaiz Abbas }; 5231accbcedSFaiz Abbas 5241accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 5251accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 5264d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 5271accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 5281accbcedSFaiz Abbas }; 5291accbcedSFaiz Abbas 5301accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 5311accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 5321accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 5331accbcedSFaiz Abbas }; 534f545702bSFaiz Abbas 53509db9943SFaiz Abbas static const struct soc_device_attribute sdhci_am654_devices[] = { 53609db9943SFaiz Abbas { .family = "AM65X", 53709db9943SFaiz Abbas .revision = "SR1.0", 53809db9943SFaiz Abbas .data = &sdhci_am654_sr1_drvdata 53909db9943SFaiz Abbas }, 54009db9943SFaiz Abbas {/* sentinel */} 54109db9943SFaiz Abbas }; 54209db9943SFaiz Abbas 543f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 544f545702bSFaiz Abbas { 545f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 546f545702bSFaiz Abbas } 547f545702bSFaiz Abbas 548f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 549f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 550f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 551f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 552f545702bSFaiz Abbas }; 553f545702bSFaiz Abbas 554f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 555f545702bSFaiz Abbas { 556f545702bSFaiz Abbas struct cqhci_host *cq_host; 557f545702bSFaiz Abbas 558bac53336SJisheng Zhang cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 559f545702bSFaiz Abbas GFP_KERNEL); 560f545702bSFaiz Abbas if (!cq_host) 561f545702bSFaiz Abbas return -ENOMEM; 562f545702bSFaiz Abbas 563f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 564f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 565f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 566f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 567f545702bSFaiz Abbas 568f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 569f545702bSFaiz Abbas 570c0470f43Sye xingchen return cqhci_init(cq_host, host->mmc, 1); 571f545702bSFaiz Abbas } 572f545702bSFaiz Abbas 5738ee5fc0eSFaiz Abbas static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 5748ee5fc0eSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 5758ee5fc0eSFaiz Abbas { 5768ee5fc0eSFaiz Abbas struct device *dev = mmc_dev(host->mmc); 5778ee5fc0eSFaiz Abbas int i; 5788ee5fc0eSFaiz Abbas int ret; 5798ee5fc0eSFaiz Abbas 580a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 5818ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 5828ee5fc0eSFaiz Abbas if (ret) { 5838ee5fc0eSFaiz Abbas /* 5848ee5fc0eSFaiz Abbas * ti,otap-del-sel-legacy is mandatory, look for old binding 5858ee5fc0eSFaiz Abbas * if not found. 5868ee5fc0eSFaiz Abbas */ 5878ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 5888ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[0]); 5898ee5fc0eSFaiz Abbas if (ret) { 5908ee5fc0eSFaiz Abbas dev_err(dev, "Couldn't find otap-del-sel\n"); 5918ee5fc0eSFaiz Abbas 5928ee5fc0eSFaiz Abbas return ret; 5938ee5fc0eSFaiz Abbas } 5948ee5fc0eSFaiz Abbas 5958ee5fc0eSFaiz Abbas dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 5968ee5fc0eSFaiz Abbas sdhci_am654->legacy_otapdly = true; 5978ee5fc0eSFaiz Abbas 5988ee5fc0eSFaiz Abbas return 0; 5998ee5fc0eSFaiz Abbas } 6008ee5fc0eSFaiz Abbas 6018ee5fc0eSFaiz Abbas for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 6028ee5fc0eSFaiz Abbas 603a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[i].otap_binding, 6048ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[i]); 6058ee5fc0eSFaiz Abbas if (ret) { 6068ee5fc0eSFaiz Abbas dev_dbg(dev, "Couldn't find %s\n", 607a0a62497SFaiz Abbas td[i].otap_binding); 6088ee5fc0eSFaiz Abbas /* 6098ee5fc0eSFaiz Abbas * Remove the corresponding capability 6108ee5fc0eSFaiz Abbas * if an otap-del-sel value is not found 6118ee5fc0eSFaiz Abbas */ 6128ee5fc0eSFaiz Abbas if (i <= MMC_TIMING_MMC_DDR52) 6138ee5fc0eSFaiz Abbas host->mmc->caps &= ~td[i].capability; 6148ee5fc0eSFaiz Abbas else 6158ee5fc0eSFaiz Abbas host->mmc->caps2 &= ~td[i].capability; 6168ee5fc0eSFaiz Abbas } 617a0a62497SFaiz Abbas 618a0a62497SFaiz Abbas if (td[i].itap_binding) 619a0a62497SFaiz Abbas device_property_read_u32(dev, td[i].itap_binding, 620a0a62497SFaiz Abbas &sdhci_am654->itap_del_sel[i]); 6218ee5fc0eSFaiz Abbas } 6228ee5fc0eSFaiz Abbas 6238ee5fc0eSFaiz Abbas return 0; 6248ee5fc0eSFaiz Abbas } 6258ee5fc0eSFaiz Abbas 62641fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 62741fd4caeSFaiz Abbas { 62841fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 62941fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 63041fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 63141fd4caeSFaiz Abbas u32 mask; 63241fd4caeSFaiz Abbas u32 val; 63341fd4caeSFaiz Abbas int ret; 63441fd4caeSFaiz Abbas 63541fd4caeSFaiz Abbas /* Reset OTAP to default value */ 63641fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 6378023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 63841fd4caeSFaiz Abbas 63923514731SFaiz Abbas if (sdhci_am654->flags & DLL_CALIB) { 64041fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 64141fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 64241fd4caeSFaiz Abbas /* Calibrate IO lines */ 64341fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 64441fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 6451accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 6461accbcedSFaiz Abbas PHY_STAT1, val, 6471accbcedSFaiz Abbas val & CALDONE_MASK, 6481accbcedSFaiz Abbas 1, 20); 64941fd4caeSFaiz Abbas if (ret) 65041fd4caeSFaiz Abbas return ret; 65141fd4caeSFaiz Abbas } 6521accbcedSFaiz Abbas } 65341fd4caeSFaiz Abbas 65441fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 65599909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 65699909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 65799909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 65841fd4caeSFaiz Abbas 65941fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 66041fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 66141fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 66241fd4caeSFaiz Abbas 6638023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 6648023cf26SFaiz Abbas ctl_cfg_2); 66541fd4caeSFaiz Abbas 666764384d0SFaiz Abbas /* Enable tuning for SDR50 */ 667764384d0SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 668764384d0SFaiz Abbas TUNINGFORSDR50_MASK); 669764384d0SFaiz Abbas 670f545702bSFaiz Abbas ret = sdhci_setup_host(host); 671f545702bSFaiz Abbas if (ret) 672f545702bSFaiz Abbas return ret; 673f545702bSFaiz Abbas 674f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 675f545702bSFaiz Abbas if (ret) 676f545702bSFaiz Abbas goto err_cleanup_host; 677f545702bSFaiz Abbas 6788ee5fc0eSFaiz Abbas ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 6798ee5fc0eSFaiz Abbas if (ret) 6808ee5fc0eSFaiz Abbas goto err_cleanup_host; 6818ee5fc0eSFaiz Abbas 682f545702bSFaiz Abbas ret = __sdhci_add_host(host); 683f545702bSFaiz Abbas if (ret) 684f545702bSFaiz Abbas goto err_cleanup_host; 685f545702bSFaiz Abbas 686f545702bSFaiz Abbas return 0; 687f545702bSFaiz Abbas 688f545702bSFaiz Abbas err_cleanup_host: 689f545702bSFaiz Abbas sdhci_cleanup_host(host); 690f545702bSFaiz Abbas return ret; 69141fd4caeSFaiz Abbas } 69241fd4caeSFaiz Abbas 69341fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 69441fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 69541fd4caeSFaiz Abbas { 69641fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 69741fd4caeSFaiz Abbas int drv_strength; 69841fd4caeSFaiz Abbas int ret; 69941fd4caeSFaiz Abbas 7001accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 7011accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 7021accbcedSFaiz Abbas &sdhci_am654->trm_icp); 70341fd4caeSFaiz Abbas if (ret) 70441fd4caeSFaiz Abbas return ret; 70541fd4caeSFaiz Abbas 70641fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 70741fd4caeSFaiz Abbas &drv_strength); 70841fd4caeSFaiz Abbas if (ret) 70941fd4caeSFaiz Abbas return ret; 71041fd4caeSFaiz Abbas 71141fd4caeSFaiz Abbas switch (drv_strength) { 71241fd4caeSFaiz Abbas case 50: 71341fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 71441fd4caeSFaiz Abbas break; 71541fd4caeSFaiz Abbas case 33: 71641fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 71741fd4caeSFaiz Abbas break; 71841fd4caeSFaiz Abbas case 66: 71941fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 72041fd4caeSFaiz Abbas break; 72141fd4caeSFaiz Abbas case 100: 72241fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 72341fd4caeSFaiz Abbas break; 72441fd4caeSFaiz Abbas case 40: 72541fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 72641fd4caeSFaiz Abbas break; 72741fd4caeSFaiz Abbas default: 72841fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 72941fd4caeSFaiz Abbas return -EINVAL; 73041fd4caeSFaiz Abbas } 7311accbcedSFaiz Abbas } 73241fd4caeSFaiz Abbas 73399909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 73461d9c4aaSFaiz Abbas device_property_read_u32(dev, "ti,clkbuf-sel", 73561d9c4aaSFaiz Abbas &sdhci_am654->clkbuf_sel); 73699909b55SFaiz Abbas 737c7666240SVignesh Raghavendra if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 738c7666240SVignesh Raghavendra sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 739c7666240SVignesh Raghavendra 74041fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 74141fd4caeSFaiz Abbas 74241fd4caeSFaiz Abbas return 0; 74341fd4caeSFaiz Abbas } 74441fd4caeSFaiz Abbas 74599909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 74699909b55SFaiz Abbas { 74799909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 74899909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 74999909b55SFaiz Abbas }, 75099909b55SFaiz Abbas { 75199909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 75299909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 75399909b55SFaiz Abbas }, 7541accbcedSFaiz Abbas { 7551accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 7561accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 7571accbcedSFaiz Abbas }, 758754b7f2fSFaiz Abbas { 759754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-8bit", 7603b7340f1SAswath Govindraju .data = &sdhci_j721e_8bit_drvdata, 761754b7f2fSFaiz Abbas }, 762754b7f2fSFaiz Abbas { 763754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-4bit", 7643b7340f1SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 765754b7f2fSFaiz Abbas }, 76602538e45SAswath Govindraju { 76702538e45SAswath Govindraju .compatible = "ti,am62-sdhci", 76802538e45SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 76902538e45SAswath Govindraju }, 77099909b55SFaiz Abbas { /* sentinel */ } 77199909b55SFaiz Abbas }; 7721e23400fSFaiz Abbas MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 77399909b55SFaiz Abbas 77441fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 77541fd4caeSFaiz Abbas { 77699909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 77709db9943SFaiz Abbas const struct soc_device_attribute *soc; 77841fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 77941fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 78099909b55SFaiz Abbas const struct of_device_id *match; 78141fd4caeSFaiz Abbas struct sdhci_host *host; 78241fd4caeSFaiz Abbas struct clk *clk_xin; 78341fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 78441fd4caeSFaiz Abbas void __iomem *base; 78541fd4caeSFaiz Abbas int ret; 78641fd4caeSFaiz Abbas 78799909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 78899909b55SFaiz Abbas drvdata = match->data; 78909db9943SFaiz Abbas 79009db9943SFaiz Abbas /* Update drvdata based on SoC revision */ 79109db9943SFaiz Abbas soc = soc_device_match(sdhci_am654_devices); 79209db9943SFaiz Abbas if (soc && soc->data) 79309db9943SFaiz Abbas drvdata = soc->data; 79409db9943SFaiz Abbas 79599909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 79641fd4caeSFaiz Abbas if (IS_ERR(host)) 79741fd4caeSFaiz Abbas return PTR_ERR(host); 79841fd4caeSFaiz Abbas 79941fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 80041fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 80199909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 80241fd4caeSFaiz Abbas 80341fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 80441fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 80541fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 80641fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 80741fd4caeSFaiz Abbas goto err_pltfm_free; 80841fd4caeSFaiz Abbas } 80941fd4caeSFaiz Abbas 81041fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 81141fd4caeSFaiz Abbas 8124942ae0eSYangtao Li base = devm_platform_ioremap_resource(pdev, 1); 81341fd4caeSFaiz Abbas if (IS_ERR(base)) { 81441fd4caeSFaiz Abbas ret = PTR_ERR(base); 8159d2e77ffSAswath Govindraju goto err_pltfm_free; 81641fd4caeSFaiz Abbas } 81741fd4caeSFaiz Abbas 81841fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 81941fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 82041fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 82141fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 82241fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 8239d2e77ffSAswath Govindraju goto err_pltfm_free; 82441fd4caeSFaiz Abbas } 82541fd4caeSFaiz Abbas 82641fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 82741fd4caeSFaiz Abbas if (ret) 8289d2e77ffSAswath Govindraju goto err_pltfm_free; 82941fd4caeSFaiz Abbas 83041fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 83141fd4caeSFaiz Abbas if (ret) { 832654993b3SMatthias Schiffer dev_err_probe(dev, ret, "parsing dt failed\n"); 8339d2e77ffSAswath Govindraju goto err_pltfm_free; 83441fd4caeSFaiz Abbas } 83541fd4caeSFaiz Abbas 836de31f6abSFaiz Abbas host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 837de31f6abSFaiz Abbas 8389d2e77ffSAswath Govindraju pm_runtime_get_noresume(dev); 8399d2e77ffSAswath Govindraju ret = pm_runtime_set_active(dev); 8409d2e77ffSAswath Govindraju if (ret) 8419d2e77ffSAswath Govindraju goto pm_put; 8429d2e77ffSAswath Govindraju pm_runtime_enable(dev); 8439d2e77ffSAswath Govindraju ret = clk_prepare_enable(pltfm_host->clk); 8449d2e77ffSAswath Govindraju if (ret) 8459d2e77ffSAswath Govindraju goto pm_disable; 8469d2e77ffSAswath Govindraju 84741fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 84841fd4caeSFaiz Abbas if (ret) 8499d2e77ffSAswath Govindraju goto clk_disable; 85041fd4caeSFaiz Abbas 8519d2e77ffSAswath Govindraju /* Setting up autosuspend */ 8529d2e77ffSAswath Govindraju pm_runtime_set_autosuspend_delay(dev, SDHCI_AM654_AUTOSUSPEND_DELAY); 8539d2e77ffSAswath Govindraju pm_runtime_use_autosuspend(dev); 8549d2e77ffSAswath Govindraju pm_runtime_mark_last_busy(dev); 8559d2e77ffSAswath Govindraju pm_runtime_put_autosuspend(dev); 85641fd4caeSFaiz Abbas return 0; 85741fd4caeSFaiz Abbas 8589d2e77ffSAswath Govindraju clk_disable: 8599d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 8609d2e77ffSAswath Govindraju pm_disable: 86141fd4caeSFaiz Abbas pm_runtime_disable(dev); 8629d2e77ffSAswath Govindraju pm_put: 8639d2e77ffSAswath Govindraju pm_runtime_put_noidle(dev); 86441fd4caeSFaiz Abbas err_pltfm_free: 86541fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 86641fd4caeSFaiz Abbas return ret; 86741fd4caeSFaiz Abbas } 86841fd4caeSFaiz Abbas 869*de29ade4SYangtao Li static void sdhci_am654_remove(struct platform_device *pdev) 87041fd4caeSFaiz Abbas { 87141fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 8729d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 873854034e2SYangtao Li struct device *dev = &pdev->dev; 87441fd4caeSFaiz Abbas int ret; 87541fd4caeSFaiz Abbas 876854034e2SYangtao Li ret = pm_runtime_get_sync(dev); 87741fd4caeSFaiz Abbas if (ret < 0) 878854034e2SYangtao Li dev_err(dev, "pm_runtime_get_sync() Failed\n"); 87941fd4caeSFaiz Abbas 8809d2e77ffSAswath Govindraju sdhci_remove_host(host, true); 8819d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 882854034e2SYangtao Li pm_runtime_disable(dev); 883854034e2SYangtao Li pm_runtime_put_noidle(dev); 88441fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 8859d2e77ffSAswath Govindraju } 8869d2e77ffSAswath Govindraju 8879d2e77ffSAswath Govindraju #ifdef CONFIG_PM 8889d2e77ffSAswath Govindraju static int sdhci_am654_restore(struct sdhci_host *host) 8899d2e77ffSAswath Govindraju { 8909d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 8919d2e77ffSAswath Govindraju struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 8929d2e77ffSAswath Govindraju u32 ctl_cfg_2 = 0; 8939d2e77ffSAswath Govindraju u32 val; 8949d2e77ffSAswath Govindraju int ret; 8959d2e77ffSAswath Govindraju 8969d2e77ffSAswath Govindraju if (sdhci_am654->flags & DLL_CALIB) { 8979d2e77ffSAswath Govindraju regmap_read(sdhci_am654->base, PHY_STAT1, &val); 8989d2e77ffSAswath Govindraju if (~val & CALDONE_MASK) { 8999d2e77ffSAswath Govindraju /* Calibrate IO lines */ 9009d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 9019d2e77ffSAswath Govindraju PDB_MASK, PDB_MASK); 9029d2e77ffSAswath Govindraju ret = regmap_read_poll_timeout(sdhci_am654->base, 9039d2e77ffSAswath Govindraju PHY_STAT1, val, 9049d2e77ffSAswath Govindraju val & CALDONE_MASK, 9059d2e77ffSAswath Govindraju 1, 20); 9069d2e77ffSAswath Govindraju if (ret) 9079d2e77ffSAswath Govindraju return ret; 9089d2e77ffSAswath Govindraju } 9099d2e77ffSAswath Govindraju } 9109d2e77ffSAswath Govindraju 9119d2e77ffSAswath Govindraju /* Enable pins by setting IO mux to 0 */ 9129d2e77ffSAswath Govindraju if (sdhci_am654->flags & IOMUX_PRESENT) 9139d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 9149d2e77ffSAswath Govindraju IOMUX_ENABLE_MASK, 0); 9159d2e77ffSAswath Govindraju 9169d2e77ffSAswath Govindraju /* Set slot type based on SD or eMMC */ 9179d2e77ffSAswath Govindraju if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 9189d2e77ffSAswath Govindraju ctl_cfg_2 = SLOTTYPE_EMBEDDED; 9199d2e77ffSAswath Govindraju 9209d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 9219d2e77ffSAswath Govindraju ctl_cfg_2); 9229d2e77ffSAswath Govindraju 9239d2e77ffSAswath Govindraju regmap_read(sdhci_am654->base, CTL_CFG_3, &val); 9249d2e77ffSAswath Govindraju if (~val & TUNINGFORSDR50_MASK) 9259d2e77ffSAswath Govindraju /* Enable tuning for SDR50 */ 9269d2e77ffSAswath Govindraju regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 9279d2e77ffSAswath Govindraju TUNINGFORSDR50_MASK); 92841fd4caeSFaiz Abbas 92941fd4caeSFaiz Abbas return 0; 93041fd4caeSFaiz Abbas } 93141fd4caeSFaiz Abbas 9329d2e77ffSAswath Govindraju static int sdhci_am654_runtime_suspend(struct device *dev) 9339d2e77ffSAswath Govindraju { 9349d2e77ffSAswath Govindraju struct sdhci_host *host = dev_get_drvdata(dev); 9359d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 9369d2e77ffSAswath Govindraju int ret; 9379d2e77ffSAswath Govindraju 9389d2e77ffSAswath Govindraju if (host->tuning_mode != SDHCI_TUNING_MODE_3) 9399d2e77ffSAswath Govindraju mmc_retune_needed(host->mmc); 9409d2e77ffSAswath Govindraju 9419d2e77ffSAswath Govindraju ret = cqhci_suspend(host->mmc); 9429d2e77ffSAswath Govindraju if (ret) 9439d2e77ffSAswath Govindraju return ret; 9449d2e77ffSAswath Govindraju 9459d2e77ffSAswath Govindraju ret = sdhci_runtime_suspend_host(host); 9469d2e77ffSAswath Govindraju if (ret) 9479d2e77ffSAswath Govindraju return ret; 9489d2e77ffSAswath Govindraju 9499d2e77ffSAswath Govindraju /* disable the clock */ 9509d2e77ffSAswath Govindraju clk_disable_unprepare(pltfm_host->clk); 9519d2e77ffSAswath Govindraju return 0; 9529d2e77ffSAswath Govindraju } 9539d2e77ffSAswath Govindraju 9549d2e77ffSAswath Govindraju static int sdhci_am654_runtime_resume(struct device *dev) 9559d2e77ffSAswath Govindraju { 9569d2e77ffSAswath Govindraju struct sdhci_host *host = dev_get_drvdata(dev); 9579d2e77ffSAswath Govindraju struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 9589d2e77ffSAswath Govindraju int ret; 9599d2e77ffSAswath Govindraju 9609d2e77ffSAswath Govindraju /* Enable the clock */ 9619d2e77ffSAswath Govindraju ret = clk_prepare_enable(pltfm_host->clk); 9629d2e77ffSAswath Govindraju if (ret) 9639d2e77ffSAswath Govindraju return ret; 9649d2e77ffSAswath Govindraju 9659d2e77ffSAswath Govindraju ret = sdhci_am654_restore(host); 9669d2e77ffSAswath Govindraju if (ret) 9679d2e77ffSAswath Govindraju return ret; 9689d2e77ffSAswath Govindraju 9699d2e77ffSAswath Govindraju ret = sdhci_runtime_resume_host(host, 0); 9709d2e77ffSAswath Govindraju if (ret) 9719d2e77ffSAswath Govindraju return ret; 9729d2e77ffSAswath Govindraju 9739d2e77ffSAswath Govindraju ret = cqhci_resume(host->mmc); 9749d2e77ffSAswath Govindraju if (ret) 9759d2e77ffSAswath Govindraju return ret; 9769d2e77ffSAswath Govindraju 9779d2e77ffSAswath Govindraju return 0; 9789d2e77ffSAswath Govindraju } 9799d2e77ffSAswath Govindraju #endif 9809d2e77ffSAswath Govindraju 9819d2e77ffSAswath Govindraju static const struct dev_pm_ops sdhci_am654_dev_pm_ops = { 9829d2e77ffSAswath Govindraju SET_RUNTIME_PM_OPS(sdhci_am654_runtime_suspend, 9839d2e77ffSAswath Govindraju sdhci_am654_runtime_resume, NULL) 9849d2e77ffSAswath Govindraju SET_SYSTEM_SLEEP_PM_OPS(pm_runtime_force_suspend, 9859d2e77ffSAswath Govindraju pm_runtime_force_resume) 9869d2e77ffSAswath Govindraju }; 9879d2e77ffSAswath Govindraju 98841fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 98941fd4caeSFaiz Abbas .driver = { 99041fd4caeSFaiz Abbas .name = "sdhci-am654", 991d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 9929d2e77ffSAswath Govindraju .pm = &sdhci_am654_dev_pm_ops, 99341fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 99441fd4caeSFaiz Abbas }, 99541fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 996*de29ade4SYangtao Li .remove_new = sdhci_am654_remove, 99741fd4caeSFaiz Abbas }; 99841fd4caeSFaiz Abbas 99941fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 100041fd4caeSFaiz Abbas 100141fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 100241fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 100341fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 1004