141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 59481b45cSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 97ca0f166SFaiz Abbas #include <linux/iopoll.h> 1099909b55SFaiz Abbas #include <linux/of.h> 1141fd4caeSFaiz Abbas #include <linux/module.h> 1241fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1341fd4caeSFaiz Abbas #include <linux/property.h> 1441fd4caeSFaiz Abbas #include <linux/regmap.h> 1509db9943SFaiz Abbas #include <linux/sys_soc.h> 1641fd4caeSFaiz Abbas 17f545702bSFaiz Abbas #include "cqhci.h" 1841fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 1941fd4caeSFaiz Abbas 2041fd4caeSFaiz Abbas /* CTL_CFG Registers */ 2141fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 22764384d0SFaiz Abbas #define CTL_CFG_3 0x18 2341fd4caeSFaiz Abbas 2441fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2541fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 26764384d0SFaiz Abbas #define TUNINGFORSDR50_MASK BIT(13) 2741fd4caeSFaiz Abbas 2841fd4caeSFaiz Abbas /* PHY Registers */ 2941fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 3041fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 3141fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 3241fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 3341fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3441fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3541fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3641fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3741fd4caeSFaiz Abbas 3841fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 3941fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 4041fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 4141fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 4241fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 4341fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4441fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4599909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4699909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4741fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4841fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 4941fd4caeSFaiz Abbas #define SEL100_SHIFT 9 5041fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 5199909b55SFaiz Abbas #define FREQSEL_SHIFT 8 5299909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 5361d9c4aaSFaiz Abbas #define CLKBUFSEL_SHIFT 0 5461d9c4aaSFaiz Abbas #define CLKBUFSEL_MASK GENMASK(2, 0) 5541fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5641fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5741fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5841fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 5941fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 6041fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 6141fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 6241fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 6341fd4caeSFaiz Abbas #define PDB_SHIFT 0 6441fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 6541fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6641fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6741fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6841fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 690003417dSFaiz Abbas #define SELDLYTXCLK_SHIFT 17 700003417dSFaiz Abbas #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 71a0a62497SFaiz Abbas #define SELDLYRXCLK_SHIFT 16 72a0a62497SFaiz Abbas #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 73a0a62497SFaiz Abbas #define ITAPDLYSEL_SHIFT 0 74a0a62497SFaiz Abbas #define ITAPDLYSEL_MASK GENMASK(4, 0) 75a0a62497SFaiz Abbas #define ITAPDLYENA_SHIFT 8 76a0a62497SFaiz Abbas #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 77a0a62497SFaiz Abbas #define ITAPCHGWIN_SHIFT 9 78a0a62497SFaiz Abbas #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 7941fd4caeSFaiz Abbas 8041fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 8141fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 8241fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 8341fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 8441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 8541fd4caeSFaiz Abbas 86a0a62497SFaiz Abbas #define CLOCK_TOO_SLOW_HZ 50000000 8741fd4caeSFaiz Abbas 88f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 89f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 90f545702bSFaiz Abbas 9141fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 9241fd4caeSFaiz Abbas .reg_bits = 32, 9341fd4caeSFaiz Abbas .val_bits = 32, 9441fd4caeSFaiz Abbas .reg_stride = 4, 9541fd4caeSFaiz Abbas .fast_io = true, 9641fd4caeSFaiz Abbas }; 9741fd4caeSFaiz Abbas 988ee5fc0eSFaiz Abbas struct timing_data { 99a0a62497SFaiz Abbas const char *otap_binding; 100a0a62497SFaiz Abbas const char *itap_binding; 1018ee5fc0eSFaiz Abbas u32 capability; 1028ee5fc0eSFaiz Abbas }; 1038ee5fc0eSFaiz Abbas 1048ee5fc0eSFaiz Abbas static const struct timing_data td[] = { 105a0a62497SFaiz Abbas [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 106a0a62497SFaiz Abbas "ti,itap-del-sel-legacy", 107a0a62497SFaiz Abbas 0}, 108a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 109a0a62497SFaiz Abbas "ti,itap-del-sel-mmc-hs", 110a0a62497SFaiz Abbas MMC_CAP_MMC_HIGHSPEED}, 111a0a62497SFaiz Abbas [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 112a0a62497SFaiz Abbas "ti,itap-del-sel-sd-hs", 113a0a62497SFaiz Abbas MMC_CAP_SD_HIGHSPEED}, 114a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 115a0a62497SFaiz Abbas "ti,itap-del-sel-sdr12", 116a0a62497SFaiz Abbas MMC_CAP_UHS_SDR12}, 117a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 118a0a62497SFaiz Abbas "ti,itap-del-sel-sdr25", 119a0a62497SFaiz Abbas MMC_CAP_UHS_SDR25}, 120a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 121a0a62497SFaiz Abbas NULL, 122a0a62497SFaiz Abbas MMC_CAP_UHS_SDR50}, 1238ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 124a0a62497SFaiz Abbas NULL, 1258ee5fc0eSFaiz Abbas MMC_CAP_UHS_SDR104}, 126a0a62497SFaiz Abbas [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 127a0a62497SFaiz Abbas NULL, 128a0a62497SFaiz Abbas MMC_CAP_UHS_DDR50}, 129a0a62497SFaiz Abbas [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 130a0a62497SFaiz Abbas "ti,itap-del-sel-ddr52", 131a0a62497SFaiz Abbas MMC_CAP_DDR}, 132a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 133a0a62497SFaiz Abbas NULL, 134a0a62497SFaiz Abbas MMC_CAP2_HS200}, 135a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 136a0a62497SFaiz Abbas NULL, 137a0a62497SFaiz Abbas MMC_CAP2_HS400}, 1388ee5fc0eSFaiz Abbas }; 1398ee5fc0eSFaiz Abbas 1401e753dbbSFaiz Abbas struct sdhci_am654_data { 1411e753dbbSFaiz Abbas struct regmap *base; 1421e753dbbSFaiz Abbas bool legacy_otapdly; 1431e753dbbSFaiz Abbas int otap_del_sel[ARRAY_SIZE(td)]; 144a0a62497SFaiz Abbas int itap_del_sel[ARRAY_SIZE(td)]; 1451e753dbbSFaiz Abbas int clkbuf_sel; 1461e753dbbSFaiz Abbas int trm_icp; 1471e753dbbSFaiz Abbas int drv_strength; 1481e753dbbSFaiz Abbas int strb_sel; 1491e753dbbSFaiz Abbas u32 flags; 150*c7666240SVignesh Raghavendra u32 quirks; 151*c7666240SVignesh Raghavendra 152*c7666240SVignesh Raghavendra #define SDHCI_AM654_QUIRK_FORCE_CDTEST BIT(0) 1531e753dbbSFaiz Abbas }; 1541e753dbbSFaiz Abbas 1551e753dbbSFaiz Abbas struct sdhci_am654_driver_data { 1561e753dbbSFaiz Abbas const struct sdhci_pltfm_data *pdata; 1571e753dbbSFaiz Abbas u32 flags; 1581e753dbbSFaiz Abbas #define IOMUX_PRESENT (1 << 0) 1591e753dbbSFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 1601e753dbbSFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 1611e753dbbSFaiz Abbas #define DLL_PRESENT (1 << 3) 1621e753dbbSFaiz Abbas #define DLL_CALIB (1 << 4) 1631e753dbbSFaiz Abbas }; 1641e753dbbSFaiz Abbas 165a161c45fSFaiz Abbas static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 166a161c45fSFaiz Abbas { 167a161c45fSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 168a161c45fSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 169a161c45fSFaiz Abbas int sel50, sel100, freqsel; 170a161c45fSFaiz Abbas u32 mask, val; 171a161c45fSFaiz Abbas int ret; 172a161c45fSFaiz Abbas 173a0a62497SFaiz Abbas /* Disable delay chain mode */ 174a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 175a0a62497SFaiz Abbas SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 176a0a62497SFaiz Abbas 177a161c45fSFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 178a161c45fSFaiz Abbas switch (clock) { 179a161c45fSFaiz Abbas case 200000000: 180a161c45fSFaiz Abbas sel50 = 0; 181a161c45fSFaiz Abbas sel100 = 0; 182a161c45fSFaiz Abbas break; 183a161c45fSFaiz Abbas case 100000000: 184a161c45fSFaiz Abbas sel50 = 0; 185a161c45fSFaiz Abbas sel100 = 1; 186a161c45fSFaiz Abbas break; 187a161c45fSFaiz Abbas default: 188a161c45fSFaiz Abbas sel50 = 1; 189a161c45fSFaiz Abbas sel100 = 0; 190a161c45fSFaiz Abbas } 191a161c45fSFaiz Abbas 192a161c45fSFaiz Abbas /* Configure PHY DLL frequency */ 193a161c45fSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 194a161c45fSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 195a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 196a161c45fSFaiz Abbas 197a161c45fSFaiz Abbas } else { 198a161c45fSFaiz Abbas switch (clock) { 199a161c45fSFaiz Abbas case 200000000: 200a161c45fSFaiz Abbas freqsel = 0x0; 201a161c45fSFaiz Abbas break; 202a161c45fSFaiz Abbas default: 203a161c45fSFaiz Abbas freqsel = 0x4; 204a161c45fSFaiz Abbas } 205a161c45fSFaiz Abbas 206a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 207a161c45fSFaiz Abbas freqsel << FREQSEL_SHIFT); 208a161c45fSFaiz Abbas } 209a161c45fSFaiz Abbas /* Configure DLL TRIM */ 210a161c45fSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 211a161c45fSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 212a161c45fSFaiz Abbas 213a161c45fSFaiz Abbas /* Configure DLL driver strength */ 214a161c45fSFaiz Abbas mask |= DR_TY_MASK; 215a161c45fSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 216a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 217a161c45fSFaiz Abbas 218a161c45fSFaiz Abbas /* Enable DLL */ 219a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 220a161c45fSFaiz Abbas 0x1 << ENDLL_SHIFT); 221a161c45fSFaiz Abbas /* 222a161c45fSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 223a161c45fSFaiz Abbas * Works in all experiments done so far 224a161c45fSFaiz Abbas */ 225a161c45fSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 226a161c45fSFaiz Abbas val & DLLRDY_MASK, 1000, 1000000); 227a161c45fSFaiz Abbas if (ret) { 228a161c45fSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 229a161c45fSFaiz Abbas return; 230a161c45fSFaiz Abbas } 231a0a62497SFaiz Abbas } 232a161c45fSFaiz Abbas 233a0a62497SFaiz Abbas static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 234a0a62497SFaiz Abbas u32 itapdly) 235a0a62497SFaiz Abbas { 236a0a62497SFaiz Abbas /* Set ITAPCHGWIN before writing to ITAPDLY */ 237a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 238a0a62497SFaiz Abbas 1 << ITAPCHGWIN_SHIFT); 239a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 240a0a62497SFaiz Abbas itapdly << ITAPDLYSEL_SHIFT); 241a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 242a0a62497SFaiz Abbas } 243a0a62497SFaiz Abbas 244a0a62497SFaiz Abbas static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 245a0a62497SFaiz Abbas unsigned char timing) 246a0a62497SFaiz Abbas { 247a0a62497SFaiz Abbas u32 mask, val; 248a0a62497SFaiz Abbas 249a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 250a0a62497SFaiz Abbas 251a0a62497SFaiz Abbas val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 252a0a62497SFaiz Abbas mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 253a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 254a0a62497SFaiz Abbas 255a0a62497SFaiz Abbas sdhci_am654_write_itapdly(sdhci_am654, 256a0a62497SFaiz Abbas sdhci_am654->itap_del_sel[timing]); 257a161c45fSFaiz Abbas } 258a161c45fSFaiz Abbas 25941fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 26041fd4caeSFaiz Abbas { 26141fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 26241fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2638ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2648ee5fc0eSFaiz Abbas u32 otap_del_sel; 2658ee5fc0eSFaiz Abbas u32 otap_del_ena; 26641fd4caeSFaiz Abbas u32 mask, val; 26741fd4caeSFaiz Abbas 2688023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 26941fd4caeSFaiz Abbas 27041fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 27141fd4caeSFaiz Abbas 27241fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 2738ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 2748ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 27599909b55SFaiz Abbas else 2768ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 27799909b55SFaiz Abbas 2788ee5fc0eSFaiz Abbas otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 2798ee5fc0eSFaiz Abbas 2808ee5fc0eSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2818ee5fc0eSFaiz Abbas val = (otap_del_ena << OTAPDLYENA_SHIFT) | 2828ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2838ee5fc0eSFaiz Abbas 2848ee5fc0eSFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 2858ee5fc0eSFaiz Abbas if (timing == MMC_TIMING_MMC_HS400) { 2868ee5fc0eSFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 2878ee5fc0eSFaiz Abbas mask |= STRBSEL_4BIT_MASK; 2888ee5fc0eSFaiz Abbas else 2898ee5fc0eSFaiz Abbas mask |= STRBSEL_8BIT_MASK; 2908ee5fc0eSFaiz Abbas 2918ee5fc0eSFaiz Abbas val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 29299909b55SFaiz Abbas } 29399909b55SFaiz Abbas 2948ee5fc0eSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2958ee5fc0eSFaiz Abbas 296a0a62497SFaiz Abbas if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 297a161c45fSFaiz Abbas sdhci_am654_setup_dll(host, clock); 298a0a62497SFaiz Abbas else 299a0a62497SFaiz Abbas sdhci_am654_setup_delay_chain(sdhci_am654, timing); 30061d9c4aaSFaiz Abbas 30161d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 30261d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 30341fd4caeSFaiz Abbas } 30441fd4caeSFaiz Abbas 3058751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 3068751c8bdSYueHaibing unsigned int clock) 3071accbcedSFaiz Abbas { 3081accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3091accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 3108ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3118ee5fc0eSFaiz Abbas u32 otap_del_sel; 3128ee5fc0eSFaiz Abbas u32 mask, val; 3138ee5fc0eSFaiz Abbas 3148ee5fc0eSFaiz Abbas /* Setup DLL Output TAP delay */ 3158ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 3168ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 3178ee5fc0eSFaiz Abbas else 3188ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 3191accbcedSFaiz Abbas 3201accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 3218ee5fc0eSFaiz Abbas val = (0x1 << OTAPDLYENA_SHIFT) | 3228ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 3231accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 3241accbcedSFaiz Abbas 32561d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 32661d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 32761d9c4aaSFaiz Abbas 3281accbcedSFaiz Abbas sdhci_set_clock(host, clock); 3291accbcedSFaiz Abbas } 3301accbcedSFaiz Abbas 3317ca0f166SFaiz Abbas static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 3327ca0f166SFaiz Abbas { 3337ca0f166SFaiz Abbas writeb(val, host->ioaddr + reg); 3347ca0f166SFaiz Abbas usleep_range(1000, 10000); 3357ca0f166SFaiz Abbas return readb(host->ioaddr + reg); 3367ca0f166SFaiz Abbas } 3377ca0f166SFaiz Abbas 3387ca0f166SFaiz Abbas #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 339e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 340e374e875SFaiz Abbas { 341e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3427ca0f166SFaiz Abbas u8 pwr; 3437ca0f166SFaiz Abbas int ret; 344e374e875SFaiz Abbas 345e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 346e374e875SFaiz Abbas switch (timing) { 347e374e875SFaiz Abbas /* 348e374e875SFaiz Abbas * According to the data manual, HISPD bit 349e374e875SFaiz Abbas * should not be set in these speed modes. 350e374e875SFaiz Abbas */ 351e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 352e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 353e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR12: 354e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR25: 355e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 356e374e875SFaiz Abbas } 357e374e875SFaiz Abbas } 358e374e875SFaiz Abbas 359e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 3607ca0f166SFaiz Abbas if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 3617ca0f166SFaiz Abbas /* 3627ca0f166SFaiz Abbas * Power on will not happen until the card detect debounce 3637ca0f166SFaiz Abbas * timer expires. Wait at least 1.5 seconds for the power on 3647ca0f166SFaiz Abbas * bit to be set 3657ca0f166SFaiz Abbas */ 3667ca0f166SFaiz Abbas ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 3677ca0f166SFaiz Abbas pwr & SDHCI_POWER_ON, 0, 3687ca0f166SFaiz Abbas MAX_POWER_ON_TIMEOUT, false, host, val, 3697ca0f166SFaiz Abbas reg); 3707ca0f166SFaiz Abbas if (ret) 3717ca0f166SFaiz Abbas dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 3727ca0f166SFaiz Abbas } 373e374e875SFaiz Abbas } 374e374e875SFaiz Abbas 375*c7666240SVignesh Raghavendra static void sdhci_am654_reset(struct sdhci_host *host, u8 mask) 376*c7666240SVignesh Raghavendra { 377*c7666240SVignesh Raghavendra u8 ctrl; 378*c7666240SVignesh Raghavendra struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 379*c7666240SVignesh Raghavendra struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 380*c7666240SVignesh Raghavendra 381*c7666240SVignesh Raghavendra sdhci_reset(host, mask); 382*c7666240SVignesh Raghavendra 383*c7666240SVignesh Raghavendra if (sdhci_am654->quirks & SDHCI_AM654_QUIRK_FORCE_CDTEST) { 384*c7666240SVignesh Raghavendra ctrl = sdhci_readb(host, SDHCI_HOST_CONTROL); 385*c7666240SVignesh Raghavendra ctrl |= SDHCI_CTRL_CDTEST_INS | SDHCI_CTRL_CDTEST_EN; 386*c7666240SVignesh Raghavendra sdhci_writeb(host, ctrl, SDHCI_HOST_CONTROL); 387*c7666240SVignesh Raghavendra } 388*c7666240SVignesh Raghavendra } 389*c7666240SVignesh Raghavendra 390de31f6abSFaiz Abbas static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 391de31f6abSFaiz Abbas { 392de31f6abSFaiz Abbas struct sdhci_host *host = mmc_priv(mmc); 393de31f6abSFaiz Abbas int err = sdhci_execute_tuning(mmc, opcode); 39441fd4caeSFaiz Abbas 395de31f6abSFaiz Abbas if (err) 396de31f6abSFaiz Abbas return err; 397de31f6abSFaiz Abbas /* 398de31f6abSFaiz Abbas * Tuning data remains in the buffer after tuning. 399de31f6abSFaiz Abbas * Do a command and data reset to get rid of it 400de31f6abSFaiz Abbas */ 401de31f6abSFaiz Abbas sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 40241fd4caeSFaiz Abbas 403de31f6abSFaiz Abbas return 0; 404de31f6abSFaiz Abbas } 40599909b55SFaiz Abbas 406f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 407f545702bSFaiz Abbas { 408f545702bSFaiz Abbas int cmd_error = 0; 409f545702bSFaiz Abbas int data_error = 0; 410f545702bSFaiz Abbas 411f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 412f545702bSFaiz Abbas return intmask; 413f545702bSFaiz Abbas 414f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 415f545702bSFaiz Abbas 416f545702bSFaiz Abbas return 0; 417f545702bSFaiz Abbas } 418f545702bSFaiz Abbas 41913ebeae6SFaiz Abbas #define ITAP_MAX 32 42013ebeae6SFaiz Abbas static int sdhci_am654_platform_execute_tuning(struct sdhci_host *host, 42113ebeae6SFaiz Abbas u32 opcode) 42213ebeae6SFaiz Abbas { 42313ebeae6SFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 42413ebeae6SFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 42513ebeae6SFaiz Abbas int cur_val, prev_val = 1, fail_len = 0, pass_window = 0, pass_len; 42613ebeae6SFaiz Abbas u32 itap; 42713ebeae6SFaiz Abbas 42813ebeae6SFaiz Abbas /* Enable ITAPDLY */ 42913ebeae6SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYENA_MASK, 43013ebeae6SFaiz Abbas 1 << ITAPDLYENA_SHIFT); 43113ebeae6SFaiz Abbas 43213ebeae6SFaiz Abbas for (itap = 0; itap < ITAP_MAX; itap++) { 43313ebeae6SFaiz Abbas sdhci_am654_write_itapdly(sdhci_am654, itap); 43413ebeae6SFaiz Abbas 43513ebeae6SFaiz Abbas cur_val = !mmc_send_tuning(host->mmc, opcode, NULL); 43613ebeae6SFaiz Abbas if (cur_val && !prev_val) 43713ebeae6SFaiz Abbas pass_window = itap; 43813ebeae6SFaiz Abbas 43913ebeae6SFaiz Abbas if (!cur_val) 44013ebeae6SFaiz Abbas fail_len++; 44113ebeae6SFaiz Abbas 44213ebeae6SFaiz Abbas prev_val = cur_val; 44313ebeae6SFaiz Abbas } 44413ebeae6SFaiz Abbas /* 44513ebeae6SFaiz Abbas * Having determined the length of the failing window and start of 44613ebeae6SFaiz Abbas * the passing window calculate the length of the passing window and 44713ebeae6SFaiz Abbas * set the final value halfway through it considering the range as a 44813ebeae6SFaiz Abbas * circular buffer 44913ebeae6SFaiz Abbas */ 45013ebeae6SFaiz Abbas pass_len = ITAP_MAX - fail_len; 45113ebeae6SFaiz Abbas itap = (pass_window + (pass_len >> 1)) % ITAP_MAX; 45213ebeae6SFaiz Abbas sdhci_am654_write_itapdly(sdhci_am654, itap); 45313ebeae6SFaiz Abbas 45413ebeae6SFaiz Abbas return 0; 45513ebeae6SFaiz Abbas } 45613ebeae6SFaiz Abbas 45741fd4caeSFaiz Abbas static struct sdhci_ops sdhci_am654_ops = { 45813ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 45941fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 46041fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 46141fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 46241fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4639d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 46441fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 46541fd4caeSFaiz Abbas .write_b = sdhci_am654_write_b, 46627f4e1e9SFaiz Abbas .irq = sdhci_am654_cqhci_irq, 46741fd4caeSFaiz Abbas .reset = sdhci_reset, 46841fd4caeSFaiz Abbas }; 46941fd4caeSFaiz Abbas 47041fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 47141fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 4724d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 47341fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 47441fd4caeSFaiz Abbas }; 47541fd4caeSFaiz Abbas 47609db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 47741fd4caeSFaiz Abbas .pdata = &sdhci_am654_pdata, 47823514731SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 47923514731SFaiz Abbas DLL_CALIB, 48041fd4caeSFaiz Abbas }; 48141fd4caeSFaiz Abbas 48209db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 48309db9943SFaiz Abbas .pdata = &sdhci_am654_pdata, 48409db9943SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 48509db9943SFaiz Abbas }; 48609db9943SFaiz Abbas 4878751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 48813ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 48999909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 49099909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 49199909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 49299909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4939d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 49499909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 49599909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 496f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 49799909b55SFaiz Abbas .reset = sdhci_reset, 49899909b55SFaiz Abbas }; 49999909b55SFaiz Abbas 50099909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 50199909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 5024d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 50399909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 50499909b55SFaiz Abbas }; 50599909b55SFaiz Abbas 50699909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 50799909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 50823514731SFaiz Abbas .flags = DLL_PRESENT | DLL_CALIB, 50999909b55SFaiz Abbas }; 51099909b55SFaiz Abbas 5118751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 51213ebeae6SFaiz Abbas .platform_execute_tuning = sdhci_am654_platform_execute_tuning, 5131accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 5141accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 5151accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 5161accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 5179d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 5181accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 5191accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 520f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 521*c7666240SVignesh Raghavendra .reset = sdhci_am654_reset, 5221accbcedSFaiz Abbas }; 5231accbcedSFaiz Abbas 5241accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 5251accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 5264d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 5271accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 5281accbcedSFaiz Abbas }; 5291accbcedSFaiz Abbas 5301accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 5311accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 5321accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 5331accbcedSFaiz Abbas }; 534f545702bSFaiz Abbas 53509db9943SFaiz Abbas static const struct soc_device_attribute sdhci_am654_devices[] = { 53609db9943SFaiz Abbas { .family = "AM65X", 53709db9943SFaiz Abbas .revision = "SR1.0", 53809db9943SFaiz Abbas .data = &sdhci_am654_sr1_drvdata 53909db9943SFaiz Abbas }, 54009db9943SFaiz Abbas {/* sentinel */} 54109db9943SFaiz Abbas }; 54209db9943SFaiz Abbas 543f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 544f545702bSFaiz Abbas { 545f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 546f545702bSFaiz Abbas } 547f545702bSFaiz Abbas 548f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 549f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 550f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 551f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 552f545702bSFaiz Abbas }; 553f545702bSFaiz Abbas 554f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 555f545702bSFaiz Abbas { 556f545702bSFaiz Abbas struct cqhci_host *cq_host; 557f545702bSFaiz Abbas int ret; 558f545702bSFaiz Abbas 559bac53336SJisheng Zhang cq_host = devm_kzalloc(mmc_dev(host->mmc), sizeof(struct cqhci_host), 560f545702bSFaiz Abbas GFP_KERNEL); 561f545702bSFaiz Abbas if (!cq_host) 562f545702bSFaiz Abbas return -ENOMEM; 563f545702bSFaiz Abbas 564f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 565f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 566f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 567f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 568f545702bSFaiz Abbas 569f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 570f545702bSFaiz Abbas 571f545702bSFaiz Abbas ret = cqhci_init(cq_host, host->mmc, 1); 572f545702bSFaiz Abbas 573f545702bSFaiz Abbas return ret; 574f545702bSFaiz Abbas } 575f545702bSFaiz Abbas 5768ee5fc0eSFaiz Abbas static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 5778ee5fc0eSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 5788ee5fc0eSFaiz Abbas { 5798ee5fc0eSFaiz Abbas struct device *dev = mmc_dev(host->mmc); 5808ee5fc0eSFaiz Abbas int i; 5818ee5fc0eSFaiz Abbas int ret; 5828ee5fc0eSFaiz Abbas 583a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 5848ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 5858ee5fc0eSFaiz Abbas if (ret) { 5868ee5fc0eSFaiz Abbas /* 5878ee5fc0eSFaiz Abbas * ti,otap-del-sel-legacy is mandatory, look for old binding 5888ee5fc0eSFaiz Abbas * if not found. 5898ee5fc0eSFaiz Abbas */ 5908ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 5918ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[0]); 5928ee5fc0eSFaiz Abbas if (ret) { 5938ee5fc0eSFaiz Abbas dev_err(dev, "Couldn't find otap-del-sel\n"); 5948ee5fc0eSFaiz Abbas 5958ee5fc0eSFaiz Abbas return ret; 5968ee5fc0eSFaiz Abbas } 5978ee5fc0eSFaiz Abbas 5988ee5fc0eSFaiz Abbas dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 5998ee5fc0eSFaiz Abbas sdhci_am654->legacy_otapdly = true; 6008ee5fc0eSFaiz Abbas 6018ee5fc0eSFaiz Abbas return 0; 6028ee5fc0eSFaiz Abbas } 6038ee5fc0eSFaiz Abbas 6048ee5fc0eSFaiz Abbas for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 6058ee5fc0eSFaiz Abbas 606a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[i].otap_binding, 6078ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[i]); 6088ee5fc0eSFaiz Abbas if (ret) { 6098ee5fc0eSFaiz Abbas dev_dbg(dev, "Couldn't find %s\n", 610a0a62497SFaiz Abbas td[i].otap_binding); 6118ee5fc0eSFaiz Abbas /* 6128ee5fc0eSFaiz Abbas * Remove the corresponding capability 6138ee5fc0eSFaiz Abbas * if an otap-del-sel value is not found 6148ee5fc0eSFaiz Abbas */ 6158ee5fc0eSFaiz Abbas if (i <= MMC_TIMING_MMC_DDR52) 6168ee5fc0eSFaiz Abbas host->mmc->caps &= ~td[i].capability; 6178ee5fc0eSFaiz Abbas else 6188ee5fc0eSFaiz Abbas host->mmc->caps2 &= ~td[i].capability; 6198ee5fc0eSFaiz Abbas } 620a0a62497SFaiz Abbas 621a0a62497SFaiz Abbas if (td[i].itap_binding) 622a0a62497SFaiz Abbas device_property_read_u32(dev, td[i].itap_binding, 623a0a62497SFaiz Abbas &sdhci_am654->itap_del_sel[i]); 6248ee5fc0eSFaiz Abbas } 6258ee5fc0eSFaiz Abbas 6268ee5fc0eSFaiz Abbas return 0; 6278ee5fc0eSFaiz Abbas } 6288ee5fc0eSFaiz Abbas 62941fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 63041fd4caeSFaiz Abbas { 63141fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 63241fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 63341fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 63441fd4caeSFaiz Abbas u32 mask; 63541fd4caeSFaiz Abbas u32 val; 63641fd4caeSFaiz Abbas int ret; 63741fd4caeSFaiz Abbas 63841fd4caeSFaiz Abbas /* Reset OTAP to default value */ 63941fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 6408023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 64141fd4caeSFaiz Abbas 64223514731SFaiz Abbas if (sdhci_am654->flags & DLL_CALIB) { 64341fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 64441fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 64541fd4caeSFaiz Abbas /* Calibrate IO lines */ 64641fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 64741fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 6481accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 6491accbcedSFaiz Abbas PHY_STAT1, val, 6501accbcedSFaiz Abbas val & CALDONE_MASK, 6511accbcedSFaiz Abbas 1, 20); 65241fd4caeSFaiz Abbas if (ret) 65341fd4caeSFaiz Abbas return ret; 65441fd4caeSFaiz Abbas } 6551accbcedSFaiz Abbas } 65641fd4caeSFaiz Abbas 65741fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 65899909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 65999909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 66099909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 66141fd4caeSFaiz Abbas 66241fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 66341fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 66441fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 66541fd4caeSFaiz Abbas 6668023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 6678023cf26SFaiz Abbas ctl_cfg_2); 66841fd4caeSFaiz Abbas 669764384d0SFaiz Abbas /* Enable tuning for SDR50 */ 670764384d0SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_3, TUNINGFORSDR50_MASK, 671764384d0SFaiz Abbas TUNINGFORSDR50_MASK); 672764384d0SFaiz Abbas 673f545702bSFaiz Abbas ret = sdhci_setup_host(host); 674f545702bSFaiz Abbas if (ret) 675f545702bSFaiz Abbas return ret; 676f545702bSFaiz Abbas 677f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 678f545702bSFaiz Abbas if (ret) 679f545702bSFaiz Abbas goto err_cleanup_host; 680f545702bSFaiz Abbas 6818ee5fc0eSFaiz Abbas ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 6828ee5fc0eSFaiz Abbas if (ret) 6838ee5fc0eSFaiz Abbas goto err_cleanup_host; 6848ee5fc0eSFaiz Abbas 685f545702bSFaiz Abbas ret = __sdhci_add_host(host); 686f545702bSFaiz Abbas if (ret) 687f545702bSFaiz Abbas goto err_cleanup_host; 688f545702bSFaiz Abbas 689f545702bSFaiz Abbas return 0; 690f545702bSFaiz Abbas 691f545702bSFaiz Abbas err_cleanup_host: 692f545702bSFaiz Abbas sdhci_cleanup_host(host); 693f545702bSFaiz Abbas return ret; 69441fd4caeSFaiz Abbas } 69541fd4caeSFaiz Abbas 69641fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 69741fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 69841fd4caeSFaiz Abbas { 69941fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 70041fd4caeSFaiz Abbas int drv_strength; 70141fd4caeSFaiz Abbas int ret; 70241fd4caeSFaiz Abbas 7031accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 7041accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 7051accbcedSFaiz Abbas &sdhci_am654->trm_icp); 70641fd4caeSFaiz Abbas if (ret) 70741fd4caeSFaiz Abbas return ret; 70841fd4caeSFaiz Abbas 70941fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 71041fd4caeSFaiz Abbas &drv_strength); 71141fd4caeSFaiz Abbas if (ret) 71241fd4caeSFaiz Abbas return ret; 71341fd4caeSFaiz Abbas 71441fd4caeSFaiz Abbas switch (drv_strength) { 71541fd4caeSFaiz Abbas case 50: 71641fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 71741fd4caeSFaiz Abbas break; 71841fd4caeSFaiz Abbas case 33: 71941fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 72041fd4caeSFaiz Abbas break; 72141fd4caeSFaiz Abbas case 66: 72241fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 72341fd4caeSFaiz Abbas break; 72441fd4caeSFaiz Abbas case 100: 72541fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 72641fd4caeSFaiz Abbas break; 72741fd4caeSFaiz Abbas case 40: 72841fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 72941fd4caeSFaiz Abbas break; 73041fd4caeSFaiz Abbas default: 73141fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 73241fd4caeSFaiz Abbas return -EINVAL; 73341fd4caeSFaiz Abbas } 7341accbcedSFaiz Abbas } 73541fd4caeSFaiz Abbas 73699909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 73761d9c4aaSFaiz Abbas device_property_read_u32(dev, "ti,clkbuf-sel", 73861d9c4aaSFaiz Abbas &sdhci_am654->clkbuf_sel); 73999909b55SFaiz Abbas 740*c7666240SVignesh Raghavendra if (device_property_read_bool(dev, "ti,fails-without-test-cd")) 741*c7666240SVignesh Raghavendra sdhci_am654->quirks |= SDHCI_AM654_QUIRK_FORCE_CDTEST; 742*c7666240SVignesh Raghavendra 74341fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 74441fd4caeSFaiz Abbas 74541fd4caeSFaiz Abbas return 0; 74641fd4caeSFaiz Abbas } 74741fd4caeSFaiz Abbas 74899909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 74999909b55SFaiz Abbas { 75099909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 75199909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 75299909b55SFaiz Abbas }, 75399909b55SFaiz Abbas { 75499909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 75599909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 75699909b55SFaiz Abbas }, 7571accbcedSFaiz Abbas { 7581accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 7591accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 7601accbcedSFaiz Abbas }, 761754b7f2fSFaiz Abbas { 762754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-8bit", 7633b7340f1SAswath Govindraju .data = &sdhci_j721e_8bit_drvdata, 764754b7f2fSFaiz Abbas }, 765754b7f2fSFaiz Abbas { 766754b7f2fSFaiz Abbas .compatible = "ti,am64-sdhci-4bit", 7673b7340f1SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 768754b7f2fSFaiz Abbas }, 76902538e45SAswath Govindraju { 77002538e45SAswath Govindraju .compatible = "ti,am62-sdhci", 77102538e45SAswath Govindraju .data = &sdhci_j721e_4bit_drvdata, 77202538e45SAswath Govindraju }, 77399909b55SFaiz Abbas { /* sentinel */ } 77499909b55SFaiz Abbas }; 7751e23400fSFaiz Abbas MODULE_DEVICE_TABLE(of, sdhci_am654_of_match); 77699909b55SFaiz Abbas 77741fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 77841fd4caeSFaiz Abbas { 77999909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 78009db9943SFaiz Abbas const struct soc_device_attribute *soc; 78141fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 78241fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 78399909b55SFaiz Abbas const struct of_device_id *match; 78441fd4caeSFaiz Abbas struct sdhci_host *host; 78541fd4caeSFaiz Abbas struct clk *clk_xin; 78641fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 78741fd4caeSFaiz Abbas void __iomem *base; 78841fd4caeSFaiz Abbas int ret; 78941fd4caeSFaiz Abbas 79099909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 79199909b55SFaiz Abbas drvdata = match->data; 79209db9943SFaiz Abbas 79309db9943SFaiz Abbas /* Update drvdata based on SoC revision */ 79409db9943SFaiz Abbas soc = soc_device_match(sdhci_am654_devices); 79509db9943SFaiz Abbas if (soc && soc->data) 79609db9943SFaiz Abbas drvdata = soc->data; 79709db9943SFaiz Abbas 79899909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 79941fd4caeSFaiz Abbas if (IS_ERR(host)) 80041fd4caeSFaiz Abbas return PTR_ERR(host); 80141fd4caeSFaiz Abbas 80241fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 80341fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 80499909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 80541fd4caeSFaiz Abbas 80641fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 80741fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 80841fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 80941fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 81041fd4caeSFaiz Abbas goto err_pltfm_free; 81141fd4caeSFaiz Abbas } 81241fd4caeSFaiz Abbas 81341fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 81441fd4caeSFaiz Abbas 81541fd4caeSFaiz Abbas /* Clocks are enabled using pm_runtime */ 81641fd4caeSFaiz Abbas pm_runtime_enable(dev); 81707e70346STian Tao ret = pm_runtime_resume_and_get(dev); 81807e70346STian Tao if (ret) 81941fd4caeSFaiz Abbas goto pm_runtime_disable; 82041fd4caeSFaiz Abbas 8214942ae0eSYangtao Li base = devm_platform_ioremap_resource(pdev, 1); 82241fd4caeSFaiz Abbas if (IS_ERR(base)) { 82341fd4caeSFaiz Abbas ret = PTR_ERR(base); 82441fd4caeSFaiz Abbas goto pm_runtime_put; 82541fd4caeSFaiz Abbas } 82641fd4caeSFaiz Abbas 82741fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 82841fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 82941fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 83041fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 83141fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 83241fd4caeSFaiz Abbas goto pm_runtime_put; 83341fd4caeSFaiz Abbas } 83441fd4caeSFaiz Abbas 83541fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 83641fd4caeSFaiz Abbas if (ret) 83741fd4caeSFaiz Abbas goto pm_runtime_put; 83841fd4caeSFaiz Abbas 83941fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 84041fd4caeSFaiz Abbas if (ret) { 84141fd4caeSFaiz Abbas dev_err(dev, "parsing dt failed (%d)\n", ret); 84241fd4caeSFaiz Abbas goto pm_runtime_put; 84341fd4caeSFaiz Abbas } 84441fd4caeSFaiz Abbas 845de31f6abSFaiz Abbas host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 846de31f6abSFaiz Abbas 84741fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 84841fd4caeSFaiz Abbas if (ret) 84941fd4caeSFaiz Abbas goto pm_runtime_put; 85041fd4caeSFaiz Abbas 85141fd4caeSFaiz Abbas return 0; 85241fd4caeSFaiz Abbas 85341fd4caeSFaiz Abbas pm_runtime_put: 85441fd4caeSFaiz Abbas pm_runtime_put_sync(dev); 85541fd4caeSFaiz Abbas pm_runtime_disable: 85641fd4caeSFaiz Abbas pm_runtime_disable(dev); 85741fd4caeSFaiz Abbas err_pltfm_free: 85841fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 85941fd4caeSFaiz Abbas return ret; 86041fd4caeSFaiz Abbas } 86141fd4caeSFaiz Abbas 86241fd4caeSFaiz Abbas static int sdhci_am654_remove(struct platform_device *pdev) 86341fd4caeSFaiz Abbas { 86441fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 86541fd4caeSFaiz Abbas int ret; 86641fd4caeSFaiz Abbas 86741fd4caeSFaiz Abbas sdhci_remove_host(host, true); 86841fd4caeSFaiz Abbas ret = pm_runtime_put_sync(&pdev->dev); 86941fd4caeSFaiz Abbas if (ret < 0) 87041fd4caeSFaiz Abbas return ret; 87141fd4caeSFaiz Abbas 87241fd4caeSFaiz Abbas pm_runtime_disable(&pdev->dev); 87341fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 87441fd4caeSFaiz Abbas 87541fd4caeSFaiz Abbas return 0; 87641fd4caeSFaiz Abbas } 87741fd4caeSFaiz Abbas 87841fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 87941fd4caeSFaiz Abbas .driver = { 88041fd4caeSFaiz Abbas .name = "sdhci-am654", 881d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 88241fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 88341fd4caeSFaiz Abbas }, 88441fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 88541fd4caeSFaiz Abbas .remove = sdhci_am654_remove, 88641fd4caeSFaiz Abbas }; 88741fd4caeSFaiz Abbas 88841fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 88941fd4caeSFaiz Abbas 89041fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 89141fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 89241fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 893