141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 59481b45cSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 97ca0f166SFaiz Abbas #include <linux/iopoll.h> 1099909b55SFaiz Abbas #include <linux/of.h> 1141fd4caeSFaiz Abbas #include <linux/module.h> 1241fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1341fd4caeSFaiz Abbas #include <linux/property.h> 1441fd4caeSFaiz Abbas #include <linux/regmap.h> 1509db9943SFaiz Abbas #include <linux/sys_soc.h> 1641fd4caeSFaiz Abbas 17f545702bSFaiz Abbas #include "cqhci.h" 1841fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 1941fd4caeSFaiz Abbas 2041fd4caeSFaiz Abbas /* CTL_CFG Registers */ 2141fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 2241fd4caeSFaiz Abbas 2341fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2441fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 2541fd4caeSFaiz Abbas 2641fd4caeSFaiz Abbas /* PHY Registers */ 2741fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 2841fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 2941fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 3041fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 3141fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3241fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3341fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3441fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3541fd4caeSFaiz Abbas 3641fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 3741fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 3841fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 3941fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 4041fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 4141fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4241fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4399909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4499909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4541fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4641fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 4741fd4caeSFaiz Abbas #define SEL100_SHIFT 9 4841fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 4999909b55SFaiz Abbas #define FREQSEL_SHIFT 8 5099909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 5161d9c4aaSFaiz Abbas #define CLKBUFSEL_SHIFT 0 5261d9c4aaSFaiz Abbas #define CLKBUFSEL_MASK GENMASK(2, 0) 5341fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5441fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5541fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5641fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 5741fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 5841fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 5941fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 6041fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 6141fd4caeSFaiz Abbas #define PDB_SHIFT 0 6241fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 6341fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6441fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6541fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6641fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 670003417dSFaiz Abbas #define SELDLYTXCLK_SHIFT 17 680003417dSFaiz Abbas #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 69a0a62497SFaiz Abbas #define SELDLYRXCLK_SHIFT 16 70a0a62497SFaiz Abbas #define SELDLYRXCLK_MASK BIT(SELDLYRXCLK_SHIFT) 71a0a62497SFaiz Abbas #define ITAPDLYSEL_SHIFT 0 72a0a62497SFaiz Abbas #define ITAPDLYSEL_MASK GENMASK(4, 0) 73a0a62497SFaiz Abbas #define ITAPDLYENA_SHIFT 8 74a0a62497SFaiz Abbas #define ITAPDLYENA_MASK BIT(ITAPDLYENA_SHIFT) 75a0a62497SFaiz Abbas #define ITAPCHGWIN_SHIFT 9 76a0a62497SFaiz Abbas #define ITAPCHGWIN_MASK BIT(ITAPCHGWIN_SHIFT) 7741fd4caeSFaiz Abbas 7841fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 7941fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 8041fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 8141fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 8241fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 8341fd4caeSFaiz Abbas 84a0a62497SFaiz Abbas #define CLOCK_TOO_SLOW_HZ 50000000 8541fd4caeSFaiz Abbas 86f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 87f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 88f545702bSFaiz Abbas 8941fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 9041fd4caeSFaiz Abbas .reg_bits = 32, 9141fd4caeSFaiz Abbas .val_bits = 32, 9241fd4caeSFaiz Abbas .reg_stride = 4, 9341fd4caeSFaiz Abbas .fast_io = true, 9441fd4caeSFaiz Abbas }; 9541fd4caeSFaiz Abbas 968ee5fc0eSFaiz Abbas struct timing_data { 97a0a62497SFaiz Abbas const char *otap_binding; 98a0a62497SFaiz Abbas const char *itap_binding; 998ee5fc0eSFaiz Abbas u32 capability; 1008ee5fc0eSFaiz Abbas }; 1018ee5fc0eSFaiz Abbas 1028ee5fc0eSFaiz Abbas static const struct timing_data td[] = { 103a0a62497SFaiz Abbas [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 104a0a62497SFaiz Abbas "ti,itap-del-sel-legacy", 105a0a62497SFaiz Abbas 0}, 106a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", 107a0a62497SFaiz Abbas "ti,itap-del-sel-mmc-hs", 108a0a62497SFaiz Abbas MMC_CAP_MMC_HIGHSPEED}, 109a0a62497SFaiz Abbas [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", 110a0a62497SFaiz Abbas "ti,itap-del-sel-sd-hs", 111a0a62497SFaiz Abbas MMC_CAP_SD_HIGHSPEED}, 112a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", 113a0a62497SFaiz Abbas "ti,itap-del-sel-sdr12", 114a0a62497SFaiz Abbas MMC_CAP_UHS_SDR12}, 115a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", 116a0a62497SFaiz Abbas "ti,itap-del-sel-sdr25", 117a0a62497SFaiz Abbas MMC_CAP_UHS_SDR25}, 118a0a62497SFaiz Abbas [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", 119a0a62497SFaiz Abbas NULL, 120a0a62497SFaiz Abbas MMC_CAP_UHS_SDR50}, 1218ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 122a0a62497SFaiz Abbas NULL, 1238ee5fc0eSFaiz Abbas MMC_CAP_UHS_SDR104}, 124a0a62497SFaiz Abbas [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", 125a0a62497SFaiz Abbas NULL, 126a0a62497SFaiz Abbas MMC_CAP_UHS_DDR50}, 127a0a62497SFaiz Abbas [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", 128a0a62497SFaiz Abbas "ti,itap-del-sel-ddr52", 129a0a62497SFaiz Abbas MMC_CAP_DDR}, 130a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", 131a0a62497SFaiz Abbas NULL, 132a0a62497SFaiz Abbas MMC_CAP2_HS200}, 133a0a62497SFaiz Abbas [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", 134a0a62497SFaiz Abbas NULL, 135a0a62497SFaiz Abbas MMC_CAP2_HS400}, 1368ee5fc0eSFaiz Abbas }; 1378ee5fc0eSFaiz Abbas 1381e753dbbSFaiz Abbas struct sdhci_am654_data { 1391e753dbbSFaiz Abbas struct regmap *base; 1401e753dbbSFaiz Abbas bool legacy_otapdly; 1411e753dbbSFaiz Abbas int otap_del_sel[ARRAY_SIZE(td)]; 142a0a62497SFaiz Abbas int itap_del_sel[ARRAY_SIZE(td)]; 1431e753dbbSFaiz Abbas int clkbuf_sel; 1441e753dbbSFaiz Abbas int trm_icp; 1451e753dbbSFaiz Abbas int drv_strength; 1461e753dbbSFaiz Abbas int strb_sel; 1471e753dbbSFaiz Abbas u32 flags; 1481e753dbbSFaiz Abbas }; 1491e753dbbSFaiz Abbas 1501e753dbbSFaiz Abbas struct sdhci_am654_driver_data { 1511e753dbbSFaiz Abbas const struct sdhci_pltfm_data *pdata; 1521e753dbbSFaiz Abbas u32 flags; 1531e753dbbSFaiz Abbas #define IOMUX_PRESENT (1 << 0) 1541e753dbbSFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 1551e753dbbSFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 1561e753dbbSFaiz Abbas #define DLL_PRESENT (1 << 3) 1571e753dbbSFaiz Abbas #define DLL_CALIB (1 << 4) 1581e753dbbSFaiz Abbas }; 1591e753dbbSFaiz Abbas 160a161c45fSFaiz Abbas static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 161a161c45fSFaiz Abbas { 162a161c45fSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 163a161c45fSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 164a161c45fSFaiz Abbas int sel50, sel100, freqsel; 165a161c45fSFaiz Abbas u32 mask, val; 166a161c45fSFaiz Abbas int ret; 167a161c45fSFaiz Abbas 168a0a62497SFaiz Abbas /* Disable delay chain mode */ 169a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 170a0a62497SFaiz Abbas SELDLYTXCLK_MASK | SELDLYRXCLK_MASK, 0); 171a0a62497SFaiz Abbas 172a161c45fSFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 173a161c45fSFaiz Abbas switch (clock) { 174a161c45fSFaiz Abbas case 200000000: 175a161c45fSFaiz Abbas sel50 = 0; 176a161c45fSFaiz Abbas sel100 = 0; 177a161c45fSFaiz Abbas break; 178a161c45fSFaiz Abbas case 100000000: 179a161c45fSFaiz Abbas sel50 = 0; 180a161c45fSFaiz Abbas sel100 = 1; 181a161c45fSFaiz Abbas break; 182a161c45fSFaiz Abbas default: 183a161c45fSFaiz Abbas sel50 = 1; 184a161c45fSFaiz Abbas sel100 = 0; 185a161c45fSFaiz Abbas } 186a161c45fSFaiz Abbas 187a161c45fSFaiz Abbas /* Configure PHY DLL frequency */ 188a161c45fSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 189a161c45fSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 190a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 191a161c45fSFaiz Abbas 192a161c45fSFaiz Abbas } else { 193a161c45fSFaiz Abbas switch (clock) { 194a161c45fSFaiz Abbas case 200000000: 195a161c45fSFaiz Abbas freqsel = 0x0; 196a161c45fSFaiz Abbas break; 197a161c45fSFaiz Abbas default: 198a161c45fSFaiz Abbas freqsel = 0x4; 199a161c45fSFaiz Abbas } 200a161c45fSFaiz Abbas 201a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 202a161c45fSFaiz Abbas freqsel << FREQSEL_SHIFT); 203a161c45fSFaiz Abbas } 204a161c45fSFaiz Abbas /* Configure DLL TRIM */ 205a161c45fSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 206a161c45fSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 207a161c45fSFaiz Abbas 208a161c45fSFaiz Abbas /* Configure DLL driver strength */ 209a161c45fSFaiz Abbas mask |= DR_TY_MASK; 210a161c45fSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 211a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 212a161c45fSFaiz Abbas 213a161c45fSFaiz Abbas /* Enable DLL */ 214a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 215a161c45fSFaiz Abbas 0x1 << ENDLL_SHIFT); 216a161c45fSFaiz Abbas /* 217a161c45fSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 218a161c45fSFaiz Abbas * Works in all experiments done so far 219a161c45fSFaiz Abbas */ 220a161c45fSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 221a161c45fSFaiz Abbas val & DLLRDY_MASK, 1000, 1000000); 222a161c45fSFaiz Abbas if (ret) { 223a161c45fSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 224a161c45fSFaiz Abbas return; 225a161c45fSFaiz Abbas } 226a0a62497SFaiz Abbas } 227a161c45fSFaiz Abbas 228a0a62497SFaiz Abbas static void sdhci_am654_write_itapdly(struct sdhci_am654_data *sdhci_am654, 229a0a62497SFaiz Abbas u32 itapdly) 230a0a62497SFaiz Abbas { 231a0a62497SFaiz Abbas /* Set ITAPCHGWIN before writing to ITAPDLY */ 232a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 233a0a62497SFaiz Abbas 1 << ITAPCHGWIN_SHIFT); 234a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPDLYSEL_MASK, 235a0a62497SFaiz Abbas itapdly << ITAPDLYSEL_SHIFT); 236a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, ITAPCHGWIN_MASK, 0); 237a0a62497SFaiz Abbas } 238a0a62497SFaiz Abbas 239a0a62497SFaiz Abbas static void sdhci_am654_setup_delay_chain(struct sdhci_am654_data *sdhci_am654, 240a0a62497SFaiz Abbas unsigned char timing) 241a0a62497SFaiz Abbas { 242a0a62497SFaiz Abbas u32 mask, val; 243a0a62497SFaiz Abbas 244a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 245a0a62497SFaiz Abbas 246a0a62497SFaiz Abbas val = 1 << SELDLYTXCLK_SHIFT | 1 << SELDLYRXCLK_SHIFT; 247a0a62497SFaiz Abbas mask = SELDLYTXCLK_MASK | SELDLYRXCLK_MASK; 248a0a62497SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 249a0a62497SFaiz Abbas 250a0a62497SFaiz Abbas sdhci_am654_write_itapdly(sdhci_am654, 251a0a62497SFaiz Abbas sdhci_am654->itap_del_sel[timing]); 252a161c45fSFaiz Abbas } 253a161c45fSFaiz Abbas 25441fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 25541fd4caeSFaiz Abbas { 25641fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 25741fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2588ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2598ee5fc0eSFaiz Abbas u32 otap_del_sel; 2608ee5fc0eSFaiz Abbas u32 otap_del_ena; 26141fd4caeSFaiz Abbas u32 mask, val; 26241fd4caeSFaiz Abbas 2638023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 26441fd4caeSFaiz Abbas 26541fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 26641fd4caeSFaiz Abbas 26741fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 2688ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 2698ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 27099909b55SFaiz Abbas else 2718ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 27299909b55SFaiz Abbas 2738ee5fc0eSFaiz Abbas otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 2748ee5fc0eSFaiz Abbas 2758ee5fc0eSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2768ee5fc0eSFaiz Abbas val = (otap_del_ena << OTAPDLYENA_SHIFT) | 2778ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2788ee5fc0eSFaiz Abbas 2798ee5fc0eSFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 2808ee5fc0eSFaiz Abbas if (timing == MMC_TIMING_MMC_HS400) { 2818ee5fc0eSFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 2828ee5fc0eSFaiz Abbas mask |= STRBSEL_4BIT_MASK; 2838ee5fc0eSFaiz Abbas else 2848ee5fc0eSFaiz Abbas mask |= STRBSEL_8BIT_MASK; 2858ee5fc0eSFaiz Abbas 2868ee5fc0eSFaiz Abbas val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 28799909b55SFaiz Abbas } 28899909b55SFaiz Abbas 2898ee5fc0eSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2908ee5fc0eSFaiz Abbas 291a0a62497SFaiz Abbas if (timing > MMC_TIMING_UHS_SDR25 && clock >= CLOCK_TOO_SLOW_HZ) 292a161c45fSFaiz Abbas sdhci_am654_setup_dll(host, clock); 293a0a62497SFaiz Abbas else 294a0a62497SFaiz Abbas sdhci_am654_setup_delay_chain(sdhci_am654, timing); 29561d9c4aaSFaiz Abbas 29661d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 29761d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 29841fd4caeSFaiz Abbas } 29941fd4caeSFaiz Abbas 3008751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 3018751c8bdSYueHaibing unsigned int clock) 3021accbcedSFaiz Abbas { 3031accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 3041accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 3058ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3068ee5fc0eSFaiz Abbas u32 otap_del_sel; 3078ee5fc0eSFaiz Abbas u32 mask, val; 3088ee5fc0eSFaiz Abbas 3098ee5fc0eSFaiz Abbas /* Setup DLL Output TAP delay */ 3108ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 3118ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 3128ee5fc0eSFaiz Abbas else 3138ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 3141accbcedSFaiz Abbas 3151accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 3168ee5fc0eSFaiz Abbas val = (0x1 << OTAPDLYENA_SHIFT) | 3178ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 3181accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 3191accbcedSFaiz Abbas 32061d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 32161d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 32261d9c4aaSFaiz Abbas 3231accbcedSFaiz Abbas sdhci_set_clock(host, clock); 3241accbcedSFaiz Abbas } 3251accbcedSFaiz Abbas 3267ca0f166SFaiz Abbas static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 3277ca0f166SFaiz Abbas { 3287ca0f166SFaiz Abbas writeb(val, host->ioaddr + reg); 3297ca0f166SFaiz Abbas usleep_range(1000, 10000); 3307ca0f166SFaiz Abbas return readb(host->ioaddr + reg); 3317ca0f166SFaiz Abbas } 3327ca0f166SFaiz Abbas 3337ca0f166SFaiz Abbas #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 334e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 335e374e875SFaiz Abbas { 336e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 3377ca0f166SFaiz Abbas u8 pwr; 3387ca0f166SFaiz Abbas int ret; 339e374e875SFaiz Abbas 340e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 341e374e875SFaiz Abbas switch (timing) { 342e374e875SFaiz Abbas /* 343e374e875SFaiz Abbas * According to the data manual, HISPD bit 344e374e875SFaiz Abbas * should not be set in these speed modes. 345e374e875SFaiz Abbas */ 346e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 347e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 348e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR12: 349e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR25: 350e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 351e374e875SFaiz Abbas } 352e374e875SFaiz Abbas } 353e374e875SFaiz Abbas 354e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 3557ca0f166SFaiz Abbas if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 3567ca0f166SFaiz Abbas /* 3577ca0f166SFaiz Abbas * Power on will not happen until the card detect debounce 3587ca0f166SFaiz Abbas * timer expires. Wait at least 1.5 seconds for the power on 3597ca0f166SFaiz Abbas * bit to be set 3607ca0f166SFaiz Abbas */ 3617ca0f166SFaiz Abbas ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 3627ca0f166SFaiz Abbas pwr & SDHCI_POWER_ON, 0, 3637ca0f166SFaiz Abbas MAX_POWER_ON_TIMEOUT, false, host, val, 3647ca0f166SFaiz Abbas reg); 3657ca0f166SFaiz Abbas if (ret) 3667ca0f166SFaiz Abbas dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 3677ca0f166SFaiz Abbas } 368e374e875SFaiz Abbas } 369e374e875SFaiz Abbas 370de31f6abSFaiz Abbas static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 371de31f6abSFaiz Abbas { 372de31f6abSFaiz Abbas struct sdhci_host *host = mmc_priv(mmc); 373de31f6abSFaiz Abbas int err = sdhci_execute_tuning(mmc, opcode); 37441fd4caeSFaiz Abbas 375de31f6abSFaiz Abbas if (err) 376de31f6abSFaiz Abbas return err; 377de31f6abSFaiz Abbas /* 378de31f6abSFaiz Abbas * Tuning data remains in the buffer after tuning. 379de31f6abSFaiz Abbas * Do a command and data reset to get rid of it 380de31f6abSFaiz Abbas */ 381de31f6abSFaiz Abbas sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 38241fd4caeSFaiz Abbas 383de31f6abSFaiz Abbas return 0; 384de31f6abSFaiz Abbas } 38599909b55SFaiz Abbas 386f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 387f545702bSFaiz Abbas { 388f545702bSFaiz Abbas int cmd_error = 0; 389f545702bSFaiz Abbas int data_error = 0; 390f545702bSFaiz Abbas 391f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 392f545702bSFaiz Abbas return intmask; 393f545702bSFaiz Abbas 394f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 395f545702bSFaiz Abbas 396f545702bSFaiz Abbas return 0; 397f545702bSFaiz Abbas } 398f545702bSFaiz Abbas 39941fd4caeSFaiz Abbas static struct sdhci_ops sdhci_am654_ops = { 40041fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 40141fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 40241fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 40341fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4049d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 40541fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 40641fd4caeSFaiz Abbas .write_b = sdhci_am654_write_b, 40727f4e1e9SFaiz Abbas .irq = sdhci_am654_cqhci_irq, 40841fd4caeSFaiz Abbas .reset = sdhci_reset, 40941fd4caeSFaiz Abbas }; 41041fd4caeSFaiz Abbas 41141fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 41241fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 4134d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 41441fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 41541fd4caeSFaiz Abbas }; 41641fd4caeSFaiz Abbas 41709db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 41841fd4caeSFaiz Abbas .pdata = &sdhci_am654_pdata, 41923514731SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 42023514731SFaiz Abbas DLL_CALIB, 42141fd4caeSFaiz Abbas }; 42241fd4caeSFaiz Abbas 42309db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 42409db9943SFaiz Abbas .pdata = &sdhci_am654_pdata, 42509db9943SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 42609db9943SFaiz Abbas }; 42709db9943SFaiz Abbas 4288751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 42999909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 43099909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 43199909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 43299909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4339d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 43499909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 43599909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 436f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 43799909b55SFaiz Abbas .reset = sdhci_reset, 43899909b55SFaiz Abbas }; 43999909b55SFaiz Abbas 44099909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 44199909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 4424d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 44399909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 44499909b55SFaiz Abbas }; 44599909b55SFaiz Abbas 44699909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 44799909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 44823514731SFaiz Abbas .flags = DLL_PRESENT | DLL_CALIB, 44999909b55SFaiz Abbas }; 45099909b55SFaiz Abbas 4518751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 4521accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 4531accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 4541accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 4551accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4569d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 4571accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 4581accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 459f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 4601accbcedSFaiz Abbas .reset = sdhci_reset, 4611accbcedSFaiz Abbas }; 4621accbcedSFaiz Abbas 4631accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 4641accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 4654d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 4661accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 4671accbcedSFaiz Abbas }; 4681accbcedSFaiz Abbas 4691accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 4701accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 4711accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 4721accbcedSFaiz Abbas }; 473f545702bSFaiz Abbas 47409db9943SFaiz Abbas static const struct soc_device_attribute sdhci_am654_devices[] = { 47509db9943SFaiz Abbas { .family = "AM65X", 47609db9943SFaiz Abbas .revision = "SR1.0", 47709db9943SFaiz Abbas .data = &sdhci_am654_sr1_drvdata 47809db9943SFaiz Abbas }, 47909db9943SFaiz Abbas {/* sentinel */} 48009db9943SFaiz Abbas }; 48109db9943SFaiz Abbas 482f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 483f545702bSFaiz Abbas { 484f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 485f545702bSFaiz Abbas } 486f545702bSFaiz Abbas 487f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 488f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 489f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 490f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 491f545702bSFaiz Abbas }; 492f545702bSFaiz Abbas 493f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 494f545702bSFaiz Abbas { 495f545702bSFaiz Abbas struct cqhci_host *cq_host; 496f545702bSFaiz Abbas int ret; 497f545702bSFaiz Abbas 498f545702bSFaiz Abbas cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 499f545702bSFaiz Abbas GFP_KERNEL); 500f545702bSFaiz Abbas if (!cq_host) 501f545702bSFaiz Abbas return -ENOMEM; 502f545702bSFaiz Abbas 503f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 504f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 505f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 506f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 507f545702bSFaiz Abbas 508f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 509f545702bSFaiz Abbas 510f545702bSFaiz Abbas ret = cqhci_init(cq_host, host->mmc, 1); 511f545702bSFaiz Abbas 512f545702bSFaiz Abbas return ret; 513f545702bSFaiz Abbas } 514f545702bSFaiz Abbas 5158ee5fc0eSFaiz Abbas static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 5168ee5fc0eSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 5178ee5fc0eSFaiz Abbas { 5188ee5fc0eSFaiz Abbas struct device *dev = mmc_dev(host->mmc); 5198ee5fc0eSFaiz Abbas int i; 5208ee5fc0eSFaiz Abbas int ret; 5218ee5fc0eSFaiz Abbas 522a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].otap_binding, 5238ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 5248ee5fc0eSFaiz Abbas if (ret) { 5258ee5fc0eSFaiz Abbas /* 5268ee5fc0eSFaiz Abbas * ti,otap-del-sel-legacy is mandatory, look for old binding 5278ee5fc0eSFaiz Abbas * if not found. 5288ee5fc0eSFaiz Abbas */ 5298ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 5308ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[0]); 5318ee5fc0eSFaiz Abbas if (ret) { 5328ee5fc0eSFaiz Abbas dev_err(dev, "Couldn't find otap-del-sel\n"); 5338ee5fc0eSFaiz Abbas 5348ee5fc0eSFaiz Abbas return ret; 5358ee5fc0eSFaiz Abbas } 5368ee5fc0eSFaiz Abbas 5378ee5fc0eSFaiz Abbas dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 5388ee5fc0eSFaiz Abbas sdhci_am654->legacy_otapdly = true; 5398ee5fc0eSFaiz Abbas 5408ee5fc0eSFaiz Abbas return 0; 5418ee5fc0eSFaiz Abbas } 5428ee5fc0eSFaiz Abbas 5438ee5fc0eSFaiz Abbas for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 5448ee5fc0eSFaiz Abbas 545a0a62497SFaiz Abbas ret = device_property_read_u32(dev, td[i].otap_binding, 5468ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[i]); 5478ee5fc0eSFaiz Abbas if (ret) { 5488ee5fc0eSFaiz Abbas dev_dbg(dev, "Couldn't find %s\n", 549a0a62497SFaiz Abbas td[i].otap_binding); 5508ee5fc0eSFaiz Abbas /* 5518ee5fc0eSFaiz Abbas * Remove the corresponding capability 5528ee5fc0eSFaiz Abbas * if an otap-del-sel value is not found 5538ee5fc0eSFaiz Abbas */ 5548ee5fc0eSFaiz Abbas if (i <= MMC_TIMING_MMC_DDR52) 5558ee5fc0eSFaiz Abbas host->mmc->caps &= ~td[i].capability; 5568ee5fc0eSFaiz Abbas else 5578ee5fc0eSFaiz Abbas host->mmc->caps2 &= ~td[i].capability; 5588ee5fc0eSFaiz Abbas } 559a0a62497SFaiz Abbas 560a0a62497SFaiz Abbas if (td[i].itap_binding) 561a0a62497SFaiz Abbas device_property_read_u32(dev, td[i].itap_binding, 562a0a62497SFaiz Abbas &sdhci_am654->itap_del_sel[i]); 5638ee5fc0eSFaiz Abbas } 5648ee5fc0eSFaiz Abbas 5658ee5fc0eSFaiz Abbas return 0; 5668ee5fc0eSFaiz Abbas } 5678ee5fc0eSFaiz Abbas 56841fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 56941fd4caeSFaiz Abbas { 57041fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 57141fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 57241fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 57341fd4caeSFaiz Abbas u32 mask; 57441fd4caeSFaiz Abbas u32 val; 57541fd4caeSFaiz Abbas int ret; 57641fd4caeSFaiz Abbas 57741fd4caeSFaiz Abbas /* Reset OTAP to default value */ 57841fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 5798023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 58041fd4caeSFaiz Abbas 58123514731SFaiz Abbas if (sdhci_am654->flags & DLL_CALIB) { 58241fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 58341fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 58441fd4caeSFaiz Abbas /* Calibrate IO lines */ 58541fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 58641fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 5871accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 5881accbcedSFaiz Abbas PHY_STAT1, val, 5891accbcedSFaiz Abbas val & CALDONE_MASK, 5901accbcedSFaiz Abbas 1, 20); 59141fd4caeSFaiz Abbas if (ret) 59241fd4caeSFaiz Abbas return ret; 59341fd4caeSFaiz Abbas } 5941accbcedSFaiz Abbas } 59541fd4caeSFaiz Abbas 59641fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 59799909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 59899909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 59999909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 60041fd4caeSFaiz Abbas 60141fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 60241fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 60341fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 60441fd4caeSFaiz Abbas 6058023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 6068023cf26SFaiz Abbas ctl_cfg_2); 60741fd4caeSFaiz Abbas 608f545702bSFaiz Abbas ret = sdhci_setup_host(host); 609f545702bSFaiz Abbas if (ret) 610f545702bSFaiz Abbas return ret; 611f545702bSFaiz Abbas 612f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 613f545702bSFaiz Abbas if (ret) 614f545702bSFaiz Abbas goto err_cleanup_host; 615f545702bSFaiz Abbas 6168ee5fc0eSFaiz Abbas ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 6178ee5fc0eSFaiz Abbas if (ret) 6188ee5fc0eSFaiz Abbas goto err_cleanup_host; 6198ee5fc0eSFaiz Abbas 620f545702bSFaiz Abbas ret = __sdhci_add_host(host); 621f545702bSFaiz Abbas if (ret) 622f545702bSFaiz Abbas goto err_cleanup_host; 623f545702bSFaiz Abbas 624f545702bSFaiz Abbas return 0; 625f545702bSFaiz Abbas 626f545702bSFaiz Abbas err_cleanup_host: 627f545702bSFaiz Abbas sdhci_cleanup_host(host); 628f545702bSFaiz Abbas return ret; 62941fd4caeSFaiz Abbas } 63041fd4caeSFaiz Abbas 63141fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 63241fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 63341fd4caeSFaiz Abbas { 63441fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 63541fd4caeSFaiz Abbas int drv_strength; 63641fd4caeSFaiz Abbas int ret; 63741fd4caeSFaiz Abbas 6381accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 6391accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 6401accbcedSFaiz Abbas &sdhci_am654->trm_icp); 64141fd4caeSFaiz Abbas if (ret) 64241fd4caeSFaiz Abbas return ret; 64341fd4caeSFaiz Abbas 64441fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 64541fd4caeSFaiz Abbas &drv_strength); 64641fd4caeSFaiz Abbas if (ret) 64741fd4caeSFaiz Abbas return ret; 64841fd4caeSFaiz Abbas 64941fd4caeSFaiz Abbas switch (drv_strength) { 65041fd4caeSFaiz Abbas case 50: 65141fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 65241fd4caeSFaiz Abbas break; 65341fd4caeSFaiz Abbas case 33: 65441fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 65541fd4caeSFaiz Abbas break; 65641fd4caeSFaiz Abbas case 66: 65741fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 65841fd4caeSFaiz Abbas break; 65941fd4caeSFaiz Abbas case 100: 66041fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 66141fd4caeSFaiz Abbas break; 66241fd4caeSFaiz Abbas case 40: 66341fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 66441fd4caeSFaiz Abbas break; 66541fd4caeSFaiz Abbas default: 66641fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 66741fd4caeSFaiz Abbas return -EINVAL; 66841fd4caeSFaiz Abbas } 6691accbcedSFaiz Abbas } 67041fd4caeSFaiz Abbas 67199909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 67261d9c4aaSFaiz Abbas device_property_read_u32(dev, "ti,clkbuf-sel", 67361d9c4aaSFaiz Abbas &sdhci_am654->clkbuf_sel); 67499909b55SFaiz Abbas 67541fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 67641fd4caeSFaiz Abbas 67741fd4caeSFaiz Abbas return 0; 67841fd4caeSFaiz Abbas } 67941fd4caeSFaiz Abbas 68099909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 68199909b55SFaiz Abbas { 68299909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 68399909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 68499909b55SFaiz Abbas }, 68599909b55SFaiz Abbas { 68699909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 68799909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 68899909b55SFaiz Abbas }, 6891accbcedSFaiz Abbas { 6901accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 6911accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 6921accbcedSFaiz Abbas }, 69399909b55SFaiz Abbas { /* sentinel */ } 69499909b55SFaiz Abbas }; 69599909b55SFaiz Abbas 69641fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 69741fd4caeSFaiz Abbas { 69899909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 69909db9943SFaiz Abbas const struct soc_device_attribute *soc; 70041fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 70141fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 70299909b55SFaiz Abbas const struct of_device_id *match; 70341fd4caeSFaiz Abbas struct sdhci_host *host; 70441fd4caeSFaiz Abbas struct clk *clk_xin; 70541fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 70641fd4caeSFaiz Abbas void __iomem *base; 70741fd4caeSFaiz Abbas int ret; 70841fd4caeSFaiz Abbas 70999909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 71099909b55SFaiz Abbas drvdata = match->data; 71109db9943SFaiz Abbas 71209db9943SFaiz Abbas /* Update drvdata based on SoC revision */ 71309db9943SFaiz Abbas soc = soc_device_match(sdhci_am654_devices); 71409db9943SFaiz Abbas if (soc && soc->data) 71509db9943SFaiz Abbas drvdata = soc->data; 71609db9943SFaiz Abbas 71799909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 71841fd4caeSFaiz Abbas if (IS_ERR(host)) 71941fd4caeSFaiz Abbas return PTR_ERR(host); 72041fd4caeSFaiz Abbas 72141fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 72241fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 72399909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 72441fd4caeSFaiz Abbas 72541fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 72641fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 72741fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 72841fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 72941fd4caeSFaiz Abbas goto err_pltfm_free; 73041fd4caeSFaiz Abbas } 73141fd4caeSFaiz Abbas 73241fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 73341fd4caeSFaiz Abbas 73441fd4caeSFaiz Abbas /* Clocks are enabled using pm_runtime */ 73541fd4caeSFaiz Abbas pm_runtime_enable(dev); 73641fd4caeSFaiz Abbas ret = pm_runtime_get_sync(dev); 73741fd4caeSFaiz Abbas if (ret < 0) { 73841fd4caeSFaiz Abbas pm_runtime_put_noidle(dev); 73941fd4caeSFaiz Abbas goto pm_runtime_disable; 74041fd4caeSFaiz Abbas } 74141fd4caeSFaiz Abbas 7424942ae0eSYangtao Li base = devm_platform_ioremap_resource(pdev, 1); 74341fd4caeSFaiz Abbas if (IS_ERR(base)) { 74441fd4caeSFaiz Abbas ret = PTR_ERR(base); 74541fd4caeSFaiz Abbas goto pm_runtime_put; 74641fd4caeSFaiz Abbas } 74741fd4caeSFaiz Abbas 74841fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 74941fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 75041fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 75141fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 75241fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 75341fd4caeSFaiz Abbas goto pm_runtime_put; 75441fd4caeSFaiz Abbas } 75541fd4caeSFaiz Abbas 75641fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 75741fd4caeSFaiz Abbas if (ret) 75841fd4caeSFaiz Abbas goto pm_runtime_put; 75941fd4caeSFaiz Abbas 76041fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 76141fd4caeSFaiz Abbas if (ret) { 76241fd4caeSFaiz Abbas dev_err(dev, "parsing dt failed (%d)\n", ret); 76341fd4caeSFaiz Abbas goto pm_runtime_put; 76441fd4caeSFaiz Abbas } 76541fd4caeSFaiz Abbas 766de31f6abSFaiz Abbas host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 767de31f6abSFaiz Abbas 76841fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 76941fd4caeSFaiz Abbas if (ret) 77041fd4caeSFaiz Abbas goto pm_runtime_put; 77141fd4caeSFaiz Abbas 77241fd4caeSFaiz Abbas return 0; 77341fd4caeSFaiz Abbas 77441fd4caeSFaiz Abbas pm_runtime_put: 77541fd4caeSFaiz Abbas pm_runtime_put_sync(dev); 77641fd4caeSFaiz Abbas pm_runtime_disable: 77741fd4caeSFaiz Abbas pm_runtime_disable(dev); 77841fd4caeSFaiz Abbas err_pltfm_free: 77941fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 78041fd4caeSFaiz Abbas return ret; 78141fd4caeSFaiz Abbas } 78241fd4caeSFaiz Abbas 78341fd4caeSFaiz Abbas static int sdhci_am654_remove(struct platform_device *pdev) 78441fd4caeSFaiz Abbas { 78541fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 78641fd4caeSFaiz Abbas int ret; 78741fd4caeSFaiz Abbas 78841fd4caeSFaiz Abbas sdhci_remove_host(host, true); 78941fd4caeSFaiz Abbas ret = pm_runtime_put_sync(&pdev->dev); 79041fd4caeSFaiz Abbas if (ret < 0) 79141fd4caeSFaiz Abbas return ret; 79241fd4caeSFaiz Abbas 79341fd4caeSFaiz Abbas pm_runtime_disable(&pdev->dev); 79441fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 79541fd4caeSFaiz Abbas 79641fd4caeSFaiz Abbas return 0; 79741fd4caeSFaiz Abbas } 79841fd4caeSFaiz Abbas 79941fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 80041fd4caeSFaiz Abbas .driver = { 80141fd4caeSFaiz Abbas .name = "sdhci-am654", 802d86472aeSDouglas Anderson .probe_type = PROBE_PREFER_ASYNCHRONOUS, 80341fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 80441fd4caeSFaiz Abbas }, 80541fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 80641fd4caeSFaiz Abbas .remove = sdhci_am654_remove, 80741fd4caeSFaiz Abbas }; 80841fd4caeSFaiz Abbas 80941fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 81041fd4caeSFaiz Abbas 81141fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 81241fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 81341fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 814