141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 541fd4caeSFaiz Abbas * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 999909b55SFaiz Abbas #include <linux/of.h> 1041fd4caeSFaiz Abbas #include <linux/module.h> 1141fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1241fd4caeSFaiz Abbas #include <linux/property.h> 1341fd4caeSFaiz Abbas #include <linux/regmap.h> 1441fd4caeSFaiz Abbas 15f545702bSFaiz Abbas #include "cqhci.h" 1641fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 1741fd4caeSFaiz Abbas 1841fd4caeSFaiz Abbas /* CTL_CFG Registers */ 1941fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 2041fd4caeSFaiz Abbas 2141fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2241fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 2341fd4caeSFaiz Abbas 2441fd4caeSFaiz Abbas /* PHY Registers */ 2541fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 2641fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 2741fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 2841fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 2941fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3041fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3141fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3241fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3341fd4caeSFaiz Abbas 3441fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 3541fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 3641fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 3741fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 3841fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 3941fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4041fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4199909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4299909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4341fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4441fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 4541fd4caeSFaiz Abbas #define SEL100_SHIFT 9 4641fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 4799909b55SFaiz Abbas #define FREQSEL_SHIFT 8 4899909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 4941fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5041fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5141fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5241fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 5341fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 5441fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 5541fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 5641fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 5741fd4caeSFaiz Abbas #define PDB_SHIFT 0 5841fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 5941fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6041fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6141fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6241fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 6341fd4caeSFaiz Abbas 6441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 6541fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 6641fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 6741fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 6841fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 6941fd4caeSFaiz Abbas 7041fd4caeSFaiz Abbas #define CLOCK_TOO_SLOW_HZ 400000 7141fd4caeSFaiz Abbas 72f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 73f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 74f545702bSFaiz Abbas 7541fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 7641fd4caeSFaiz Abbas .reg_bits = 32, 7741fd4caeSFaiz Abbas .val_bits = 32, 7841fd4caeSFaiz Abbas .reg_stride = 4, 7941fd4caeSFaiz Abbas .fast_io = true, 8041fd4caeSFaiz Abbas }; 8141fd4caeSFaiz Abbas 8241fd4caeSFaiz Abbas struct sdhci_am654_data { 8341fd4caeSFaiz Abbas struct regmap *base; 848ee5fc0eSFaiz Abbas bool legacy_otapdly; 858ee5fc0eSFaiz Abbas int otap_del_sel[11]; 8641fd4caeSFaiz Abbas int trm_icp; 8741fd4caeSFaiz Abbas int drv_strength; 8841fd4caeSFaiz Abbas bool dll_on; 8999909b55SFaiz Abbas int strb_sel; 9099909b55SFaiz Abbas u32 flags; 9199909b55SFaiz Abbas }; 9299909b55SFaiz Abbas 9399909b55SFaiz Abbas struct sdhci_am654_driver_data { 9499909b55SFaiz Abbas const struct sdhci_pltfm_data *pdata; 9599909b55SFaiz Abbas u32 flags; 9699909b55SFaiz Abbas #define IOMUX_PRESENT (1 << 0) 9799909b55SFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 9899909b55SFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 991accbcedSFaiz Abbas #define DLL_PRESENT (1 << 3) 10041fd4caeSFaiz Abbas }; 10141fd4caeSFaiz Abbas 1028ee5fc0eSFaiz Abbas struct timing_data { 1038ee5fc0eSFaiz Abbas const char *binding; 1048ee5fc0eSFaiz Abbas u32 capability; 1058ee5fc0eSFaiz Abbas }; 1068ee5fc0eSFaiz Abbas 1078ee5fc0eSFaiz Abbas static const struct timing_data td[] = { 1088ee5fc0eSFaiz Abbas [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0}, 1098ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED}, 1108ee5fc0eSFaiz Abbas [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED}, 1118ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12}, 1128ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25}, 1138ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50}, 1148ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 1158ee5fc0eSFaiz Abbas MMC_CAP_UHS_SDR104}, 1168ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50}, 1178ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR}, 1188ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200}, 1198ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400}, 1208ee5fc0eSFaiz Abbas }; 1218ee5fc0eSFaiz Abbas 12241fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 12341fd4caeSFaiz Abbas { 12441fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 12541fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 1268ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 12799909b55SFaiz Abbas int sel50, sel100, freqsel; 1288ee5fc0eSFaiz Abbas u32 otap_del_sel; 1298ee5fc0eSFaiz Abbas u32 otap_del_ena; 13041fd4caeSFaiz Abbas u32 mask, val; 13141fd4caeSFaiz Abbas int ret; 13241fd4caeSFaiz Abbas 13341fd4caeSFaiz Abbas if (sdhci_am654->dll_on) { 1348023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 13541fd4caeSFaiz Abbas 13641fd4caeSFaiz Abbas sdhci_am654->dll_on = false; 13741fd4caeSFaiz Abbas } 13841fd4caeSFaiz Abbas 13941fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 14041fd4caeSFaiz Abbas 14141fd4caeSFaiz Abbas if (clock > CLOCK_TOO_SLOW_HZ) { 14241fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 1438ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 1448ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 14599909b55SFaiz Abbas else 1468ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 14799909b55SFaiz Abbas 1488ee5fc0eSFaiz Abbas otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 1498ee5fc0eSFaiz Abbas 1508ee5fc0eSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 1518ee5fc0eSFaiz Abbas val = (otap_del_ena << OTAPDLYENA_SHIFT) | 1528ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 1538ee5fc0eSFaiz Abbas 1548ee5fc0eSFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 1558ee5fc0eSFaiz Abbas if (timing == MMC_TIMING_MMC_HS400) { 1568ee5fc0eSFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 1578ee5fc0eSFaiz Abbas mask |= STRBSEL_4BIT_MASK; 1588ee5fc0eSFaiz Abbas else 1598ee5fc0eSFaiz Abbas mask |= STRBSEL_8BIT_MASK; 1608ee5fc0eSFaiz Abbas 1618ee5fc0eSFaiz Abbas val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 16299909b55SFaiz Abbas } 16399909b55SFaiz Abbas 1648ee5fc0eSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 1658ee5fc0eSFaiz Abbas 16699909b55SFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 16741fd4caeSFaiz Abbas switch (clock) { 16841fd4caeSFaiz Abbas case 200000000: 16941fd4caeSFaiz Abbas sel50 = 0; 17041fd4caeSFaiz Abbas sel100 = 0; 17141fd4caeSFaiz Abbas break; 17241fd4caeSFaiz Abbas case 100000000: 17341fd4caeSFaiz Abbas sel50 = 0; 17441fd4caeSFaiz Abbas sel100 = 1; 17541fd4caeSFaiz Abbas break; 17641fd4caeSFaiz Abbas default: 17741fd4caeSFaiz Abbas sel50 = 1; 17841fd4caeSFaiz Abbas sel100 = 0; 17941fd4caeSFaiz Abbas } 18041fd4caeSFaiz Abbas 18141fd4caeSFaiz Abbas /* Configure PHY DLL frequency */ 18241fd4caeSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 18341fd4caeSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 18499909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, 18599909b55SFaiz Abbas val); 18699909b55SFaiz Abbas } else { 18799909b55SFaiz Abbas switch (clock) { 18899909b55SFaiz Abbas case 200000000: 18999909b55SFaiz Abbas freqsel = 0x0; 19099909b55SFaiz Abbas break; 19199909b55SFaiz Abbas default: 19299909b55SFaiz Abbas freqsel = 0x4; 19399909b55SFaiz Abbas } 19499909b55SFaiz Abbas 19599909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 19699909b55SFaiz Abbas FREQSEL_MASK, 19799909b55SFaiz Abbas freqsel << FREQSEL_SHIFT); 19899909b55SFaiz Abbas } 19999909b55SFaiz Abbas 20041fd4caeSFaiz Abbas /* Configure DLL TRIM */ 20141fd4caeSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 20241fd4caeSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 20341fd4caeSFaiz Abbas 20441fd4caeSFaiz Abbas /* Configure DLL driver strength */ 20541fd4caeSFaiz Abbas mask |= DR_TY_MASK; 20641fd4caeSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 2078023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 20841fd4caeSFaiz Abbas /* Enable DLL */ 2098023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 2108023cf26SFaiz Abbas 0x1 << ENDLL_SHIFT); 21141fd4caeSFaiz Abbas /* 21241fd4caeSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 21341fd4caeSFaiz Abbas * Works in all experiments done so far 21441fd4caeSFaiz Abbas */ 2158023cf26SFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 2168023cf26SFaiz Abbas val, val & DLLRDY_MASK, 1000, 2178023cf26SFaiz Abbas 1000000); 2187e24e28bSFaiz Abbas if (ret) { 2197e24e28bSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 2207e24e28bSFaiz Abbas return; 2217e24e28bSFaiz Abbas } 2227e24e28bSFaiz Abbas 22341fd4caeSFaiz Abbas sdhci_am654->dll_on = true; 22441fd4caeSFaiz Abbas } 22541fd4caeSFaiz Abbas } 22641fd4caeSFaiz Abbas 2278751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 2288751c8bdSYueHaibing unsigned int clock) 2291accbcedSFaiz Abbas { 2301accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2311accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2328ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2338ee5fc0eSFaiz Abbas u32 otap_del_sel; 2348ee5fc0eSFaiz Abbas u32 mask, val; 2358ee5fc0eSFaiz Abbas 2368ee5fc0eSFaiz Abbas /* Setup DLL Output TAP delay */ 2378ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 2388ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 2398ee5fc0eSFaiz Abbas else 2408ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 2411accbcedSFaiz Abbas 2421accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2438ee5fc0eSFaiz Abbas val = (0x1 << OTAPDLYENA_SHIFT) | 2448ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2451accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2461accbcedSFaiz Abbas 2471accbcedSFaiz Abbas sdhci_set_clock(host, clock); 2481accbcedSFaiz Abbas } 2491accbcedSFaiz Abbas 25041fd4caeSFaiz Abbas static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 25141fd4caeSFaiz Abbas unsigned short vdd) 25241fd4caeSFaiz Abbas { 25341fd4caeSFaiz Abbas if (!IS_ERR(host->mmc->supply.vmmc)) { 25441fd4caeSFaiz Abbas struct mmc_host *mmc = host->mmc; 25541fd4caeSFaiz Abbas 25641fd4caeSFaiz Abbas mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 25741fd4caeSFaiz Abbas } 25841fd4caeSFaiz Abbas sdhci_set_power_noreg(host, mode, vdd); 25941fd4caeSFaiz Abbas } 26041fd4caeSFaiz Abbas 261e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 262e374e875SFaiz Abbas { 263e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 264e374e875SFaiz Abbas 265e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 266e374e875SFaiz Abbas switch (timing) { 267e374e875SFaiz Abbas /* 268e374e875SFaiz Abbas * According to the data manual, HISPD bit 269e374e875SFaiz Abbas * should not be set in these speed modes. 270e374e875SFaiz Abbas */ 271e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 272e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 273e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR12: 274e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR25: 275e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 276e374e875SFaiz Abbas } 277e374e875SFaiz Abbas } 278e374e875SFaiz Abbas 279e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 280e374e875SFaiz Abbas } 281e374e875SFaiz Abbas 282de31f6abSFaiz Abbas static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 283de31f6abSFaiz Abbas { 284de31f6abSFaiz Abbas struct sdhci_host *host = mmc_priv(mmc); 285de31f6abSFaiz Abbas int err = sdhci_execute_tuning(mmc, opcode); 28641fd4caeSFaiz Abbas 287de31f6abSFaiz Abbas if (err) 288de31f6abSFaiz Abbas return err; 289de31f6abSFaiz Abbas /* 290de31f6abSFaiz Abbas * Tuning data remains in the buffer after tuning. 291de31f6abSFaiz Abbas * Do a command and data reset to get rid of it 292de31f6abSFaiz Abbas */ 293de31f6abSFaiz Abbas sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 29441fd4caeSFaiz Abbas 295de31f6abSFaiz Abbas return 0; 296de31f6abSFaiz Abbas } 29799909b55SFaiz Abbas 298f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 299f545702bSFaiz Abbas { 300f545702bSFaiz Abbas int cmd_error = 0; 301f545702bSFaiz Abbas int data_error = 0; 302f545702bSFaiz Abbas 303f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 304f545702bSFaiz Abbas return intmask; 305f545702bSFaiz Abbas 306f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 307f545702bSFaiz Abbas 308f545702bSFaiz Abbas return 0; 309f545702bSFaiz Abbas } 310f545702bSFaiz Abbas 31141fd4caeSFaiz Abbas static struct sdhci_ops sdhci_am654_ops = { 31241fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 31341fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 31441fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 31541fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 31641fd4caeSFaiz Abbas .set_power = sdhci_am654_set_power, 31741fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 31841fd4caeSFaiz Abbas .write_b = sdhci_am654_write_b, 31927f4e1e9SFaiz Abbas .irq = sdhci_am654_cqhci_irq, 32041fd4caeSFaiz Abbas .reset = sdhci_reset, 32141fd4caeSFaiz Abbas }; 32241fd4caeSFaiz Abbas 32341fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 32441fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 3254d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 32641fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 32741fd4caeSFaiz Abbas }; 32841fd4caeSFaiz Abbas 32941fd4caeSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 33041fd4caeSFaiz Abbas .pdata = &sdhci_am654_pdata, 33141fd4caeSFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 33241fd4caeSFaiz Abbas }; 33341fd4caeSFaiz Abbas 3348751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 33599909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 33699909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 33799909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 33899909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 33999909b55SFaiz Abbas .set_power = sdhci_am654_set_power, 34099909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 34199909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 342f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 34399909b55SFaiz Abbas .reset = sdhci_reset, 34499909b55SFaiz Abbas }; 34599909b55SFaiz Abbas 34699909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 34799909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 3484d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 34999909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 35099909b55SFaiz Abbas }; 35199909b55SFaiz Abbas 35299909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 35399909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 3541accbcedSFaiz Abbas .flags = DLL_PRESENT, 35599909b55SFaiz Abbas }; 35699909b55SFaiz Abbas 3578751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 3581accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 3591accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 3601accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 3611accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 3621accbcedSFaiz Abbas .set_power = sdhci_am654_set_power, 3631accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 3641accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 365f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 3661accbcedSFaiz Abbas .reset = sdhci_reset, 3671accbcedSFaiz Abbas }; 3681accbcedSFaiz Abbas 3691accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 3701accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 3714d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 3721accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 3731accbcedSFaiz Abbas }; 3741accbcedSFaiz Abbas 3751accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 3761accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 3771accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 3781accbcedSFaiz Abbas }; 379f545702bSFaiz Abbas 380f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 381f545702bSFaiz Abbas { 382f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 383f545702bSFaiz Abbas } 384f545702bSFaiz Abbas 385f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 386f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 387f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 388f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 389f545702bSFaiz Abbas }; 390f545702bSFaiz Abbas 391f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 392f545702bSFaiz Abbas { 393f545702bSFaiz Abbas struct cqhci_host *cq_host; 394f545702bSFaiz Abbas int ret; 395f545702bSFaiz Abbas 396f545702bSFaiz Abbas cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 397f545702bSFaiz Abbas GFP_KERNEL); 398f545702bSFaiz Abbas if (!cq_host) 399f545702bSFaiz Abbas return -ENOMEM; 400f545702bSFaiz Abbas 401f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 402f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 403f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 404f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 405f545702bSFaiz Abbas 406f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 407f545702bSFaiz Abbas 408f545702bSFaiz Abbas ret = cqhci_init(cq_host, host->mmc, 1); 409f545702bSFaiz Abbas 410f545702bSFaiz Abbas return ret; 411f545702bSFaiz Abbas } 412f545702bSFaiz Abbas 4138ee5fc0eSFaiz Abbas static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 4148ee5fc0eSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 4158ee5fc0eSFaiz Abbas { 4168ee5fc0eSFaiz Abbas struct device *dev = mmc_dev(host->mmc); 4178ee5fc0eSFaiz Abbas int i; 4188ee5fc0eSFaiz Abbas int ret; 4198ee5fc0eSFaiz Abbas 4208ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding, 4218ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 4228ee5fc0eSFaiz Abbas if (ret) { 4238ee5fc0eSFaiz Abbas /* 4248ee5fc0eSFaiz Abbas * ti,otap-del-sel-legacy is mandatory, look for old binding 4258ee5fc0eSFaiz Abbas * if not found. 4268ee5fc0eSFaiz Abbas */ 4278ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 4288ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[0]); 4298ee5fc0eSFaiz Abbas if (ret) { 4308ee5fc0eSFaiz Abbas dev_err(dev, "Couldn't find otap-del-sel\n"); 4318ee5fc0eSFaiz Abbas 4328ee5fc0eSFaiz Abbas return ret; 4338ee5fc0eSFaiz Abbas } 4348ee5fc0eSFaiz Abbas 4358ee5fc0eSFaiz Abbas dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 4368ee5fc0eSFaiz Abbas sdhci_am654->legacy_otapdly = true; 4378ee5fc0eSFaiz Abbas 4388ee5fc0eSFaiz Abbas return 0; 4398ee5fc0eSFaiz Abbas } 4408ee5fc0eSFaiz Abbas 4418ee5fc0eSFaiz Abbas for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 4428ee5fc0eSFaiz Abbas 4438ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, td[i].binding, 4448ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[i]); 4458ee5fc0eSFaiz Abbas if (ret) { 4468ee5fc0eSFaiz Abbas dev_dbg(dev, "Couldn't find %s\n", 4478ee5fc0eSFaiz Abbas td[i].binding); 4488ee5fc0eSFaiz Abbas /* 4498ee5fc0eSFaiz Abbas * Remove the corresponding capability 4508ee5fc0eSFaiz Abbas * if an otap-del-sel value is not found 4518ee5fc0eSFaiz Abbas */ 4528ee5fc0eSFaiz Abbas if (i <= MMC_TIMING_MMC_DDR52) 4538ee5fc0eSFaiz Abbas host->mmc->caps &= ~td[i].capability; 4548ee5fc0eSFaiz Abbas else 4558ee5fc0eSFaiz Abbas host->mmc->caps2 &= ~td[i].capability; 4568ee5fc0eSFaiz Abbas } 4578ee5fc0eSFaiz Abbas } 4588ee5fc0eSFaiz Abbas 4598ee5fc0eSFaiz Abbas return 0; 4608ee5fc0eSFaiz Abbas } 4618ee5fc0eSFaiz Abbas 46241fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 46341fd4caeSFaiz Abbas { 46441fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 46541fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 46641fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 46741fd4caeSFaiz Abbas u32 mask; 46841fd4caeSFaiz Abbas u32 val; 46941fd4caeSFaiz Abbas int ret; 47041fd4caeSFaiz Abbas 47141fd4caeSFaiz Abbas /* Reset OTAP to default value */ 47241fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 4738023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 47441fd4caeSFaiz Abbas 4751accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 47641fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 47741fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 47841fd4caeSFaiz Abbas /* Calibrate IO lines */ 47941fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 48041fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 4811accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 4821accbcedSFaiz Abbas PHY_STAT1, val, 4831accbcedSFaiz Abbas val & CALDONE_MASK, 4841accbcedSFaiz Abbas 1, 20); 48541fd4caeSFaiz Abbas if (ret) 48641fd4caeSFaiz Abbas return ret; 48741fd4caeSFaiz Abbas } 4881accbcedSFaiz Abbas } 48941fd4caeSFaiz Abbas 49041fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 49199909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 49299909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 49399909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 49441fd4caeSFaiz Abbas 49541fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 49641fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 49741fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 49841fd4caeSFaiz Abbas 4998023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 5008023cf26SFaiz Abbas ctl_cfg_2); 50141fd4caeSFaiz Abbas 502f545702bSFaiz Abbas ret = sdhci_setup_host(host); 503f545702bSFaiz Abbas if (ret) 504f545702bSFaiz Abbas return ret; 505f545702bSFaiz Abbas 506f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 507f545702bSFaiz Abbas if (ret) 508f545702bSFaiz Abbas goto err_cleanup_host; 509f545702bSFaiz Abbas 5108ee5fc0eSFaiz Abbas ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 5118ee5fc0eSFaiz Abbas if (ret) 5128ee5fc0eSFaiz Abbas goto err_cleanup_host; 5138ee5fc0eSFaiz Abbas 514f545702bSFaiz Abbas ret = __sdhci_add_host(host); 515f545702bSFaiz Abbas if (ret) 516f545702bSFaiz Abbas goto err_cleanup_host; 517f545702bSFaiz Abbas 518f545702bSFaiz Abbas return 0; 519f545702bSFaiz Abbas 520f545702bSFaiz Abbas err_cleanup_host: 521f545702bSFaiz Abbas sdhci_cleanup_host(host); 522f545702bSFaiz Abbas return ret; 52341fd4caeSFaiz Abbas } 52441fd4caeSFaiz Abbas 52541fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 52641fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 52741fd4caeSFaiz Abbas { 52841fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 52941fd4caeSFaiz Abbas int drv_strength; 53041fd4caeSFaiz Abbas int ret; 53141fd4caeSFaiz Abbas 5321accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 5331accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 5341accbcedSFaiz Abbas &sdhci_am654->trm_icp); 53541fd4caeSFaiz Abbas if (ret) 53641fd4caeSFaiz Abbas return ret; 53741fd4caeSFaiz Abbas 53841fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 53941fd4caeSFaiz Abbas &drv_strength); 54041fd4caeSFaiz Abbas if (ret) 54141fd4caeSFaiz Abbas return ret; 54241fd4caeSFaiz Abbas 54341fd4caeSFaiz Abbas switch (drv_strength) { 54441fd4caeSFaiz Abbas case 50: 54541fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 54641fd4caeSFaiz Abbas break; 54741fd4caeSFaiz Abbas case 33: 54841fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 54941fd4caeSFaiz Abbas break; 55041fd4caeSFaiz Abbas case 66: 55141fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 55241fd4caeSFaiz Abbas break; 55341fd4caeSFaiz Abbas case 100: 55441fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 55541fd4caeSFaiz Abbas break; 55641fd4caeSFaiz Abbas case 40: 55741fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 55841fd4caeSFaiz Abbas break; 55941fd4caeSFaiz Abbas default: 56041fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 56141fd4caeSFaiz Abbas return -EINVAL; 56241fd4caeSFaiz Abbas } 5631accbcedSFaiz Abbas } 56441fd4caeSFaiz Abbas 56599909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 56699909b55SFaiz Abbas 56741fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 56841fd4caeSFaiz Abbas 56941fd4caeSFaiz Abbas return 0; 57041fd4caeSFaiz Abbas } 57141fd4caeSFaiz Abbas 57299909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 57399909b55SFaiz Abbas { 57499909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 57599909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 57699909b55SFaiz Abbas }, 57799909b55SFaiz Abbas { 57899909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 57999909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 58099909b55SFaiz Abbas }, 5811accbcedSFaiz Abbas { 5821accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 5831accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 5841accbcedSFaiz Abbas }, 58599909b55SFaiz Abbas { /* sentinel */ } 58699909b55SFaiz Abbas }; 58799909b55SFaiz Abbas 58841fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 58941fd4caeSFaiz Abbas { 59099909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 59141fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 59241fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 59399909b55SFaiz Abbas const struct of_device_id *match; 59441fd4caeSFaiz Abbas struct sdhci_host *host; 59541fd4caeSFaiz Abbas struct clk *clk_xin; 59641fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 59741fd4caeSFaiz Abbas void __iomem *base; 59841fd4caeSFaiz Abbas int ret; 59941fd4caeSFaiz Abbas 60099909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 60199909b55SFaiz Abbas drvdata = match->data; 60299909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 60341fd4caeSFaiz Abbas if (IS_ERR(host)) 60441fd4caeSFaiz Abbas return PTR_ERR(host); 60541fd4caeSFaiz Abbas 60641fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 60741fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 60899909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 60941fd4caeSFaiz Abbas 61041fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 61141fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 61241fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 61341fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 61441fd4caeSFaiz Abbas goto err_pltfm_free; 61541fd4caeSFaiz Abbas } 61641fd4caeSFaiz Abbas 61741fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 61841fd4caeSFaiz Abbas 61941fd4caeSFaiz Abbas /* Clocks are enabled using pm_runtime */ 62041fd4caeSFaiz Abbas pm_runtime_enable(dev); 62141fd4caeSFaiz Abbas ret = pm_runtime_get_sync(dev); 62241fd4caeSFaiz Abbas if (ret < 0) { 62341fd4caeSFaiz Abbas pm_runtime_put_noidle(dev); 62441fd4caeSFaiz Abbas goto pm_runtime_disable; 62541fd4caeSFaiz Abbas } 62641fd4caeSFaiz Abbas 6274942ae0eSYangtao Li base = devm_platform_ioremap_resource(pdev, 1); 62841fd4caeSFaiz Abbas if (IS_ERR(base)) { 62941fd4caeSFaiz Abbas ret = PTR_ERR(base); 63041fd4caeSFaiz Abbas goto pm_runtime_put; 63141fd4caeSFaiz Abbas } 63241fd4caeSFaiz Abbas 63341fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 63441fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 63541fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 63641fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 63741fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 63841fd4caeSFaiz Abbas goto pm_runtime_put; 63941fd4caeSFaiz Abbas } 64041fd4caeSFaiz Abbas 64141fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 64241fd4caeSFaiz Abbas if (ret) 64341fd4caeSFaiz Abbas goto pm_runtime_put; 64441fd4caeSFaiz Abbas 64541fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 64641fd4caeSFaiz Abbas if (ret) { 64741fd4caeSFaiz Abbas dev_err(dev, "parsing dt failed (%d)\n", ret); 64841fd4caeSFaiz Abbas goto pm_runtime_put; 64941fd4caeSFaiz Abbas } 65041fd4caeSFaiz Abbas 651de31f6abSFaiz Abbas host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 652de31f6abSFaiz Abbas 65341fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 65441fd4caeSFaiz Abbas if (ret) 65541fd4caeSFaiz Abbas goto pm_runtime_put; 65641fd4caeSFaiz Abbas 65741fd4caeSFaiz Abbas return 0; 65841fd4caeSFaiz Abbas 65941fd4caeSFaiz Abbas pm_runtime_put: 66041fd4caeSFaiz Abbas pm_runtime_put_sync(dev); 66141fd4caeSFaiz Abbas pm_runtime_disable: 66241fd4caeSFaiz Abbas pm_runtime_disable(dev); 66341fd4caeSFaiz Abbas err_pltfm_free: 66441fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 66541fd4caeSFaiz Abbas return ret; 66641fd4caeSFaiz Abbas } 66741fd4caeSFaiz Abbas 66841fd4caeSFaiz Abbas static int sdhci_am654_remove(struct platform_device *pdev) 66941fd4caeSFaiz Abbas { 67041fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 67141fd4caeSFaiz Abbas int ret; 67241fd4caeSFaiz Abbas 67341fd4caeSFaiz Abbas sdhci_remove_host(host, true); 67441fd4caeSFaiz Abbas ret = pm_runtime_put_sync(&pdev->dev); 67541fd4caeSFaiz Abbas if (ret < 0) 67641fd4caeSFaiz Abbas return ret; 67741fd4caeSFaiz Abbas 67841fd4caeSFaiz Abbas pm_runtime_disable(&pdev->dev); 67941fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 68041fd4caeSFaiz Abbas 68141fd4caeSFaiz Abbas return 0; 68241fd4caeSFaiz Abbas } 68341fd4caeSFaiz Abbas 68441fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 68541fd4caeSFaiz Abbas .driver = { 68641fd4caeSFaiz Abbas .name = "sdhci-am654", 68741fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 68841fd4caeSFaiz Abbas }, 68941fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 69041fd4caeSFaiz Abbas .remove = sdhci_am654_remove, 69141fd4caeSFaiz Abbas }; 69241fd4caeSFaiz Abbas 69341fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 69441fd4caeSFaiz Abbas 69541fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 69641fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 69741fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 698