141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 541fd4caeSFaiz Abbas * Copyright (C) 2018 Texas Instruments Incorporated - http://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 941fd4caeSFaiz Abbas #include <linux/module.h> 1041fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1141fd4caeSFaiz Abbas #include <linux/property.h> 1241fd4caeSFaiz Abbas #include <linux/regmap.h> 1341fd4caeSFaiz Abbas 1441fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 1541fd4caeSFaiz Abbas 1641fd4caeSFaiz Abbas /* CTL_CFG Registers */ 1741fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 1841fd4caeSFaiz Abbas 1941fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2041fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 2141fd4caeSFaiz Abbas 2241fd4caeSFaiz Abbas /* PHY Registers */ 2341fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 2441fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 2541fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 2641fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 2741fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 2841fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 2941fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3041fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3141fd4caeSFaiz Abbas 3241fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 3341fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 3441fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 3541fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 3641fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 3741fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 3841fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 3941fd4caeSFaiz Abbas #define STRBSEL_MASK GENMASK(27, 24) 4041fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4141fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 4241fd4caeSFaiz Abbas #define SEL100_SHIFT 9 4341fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 4441fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 4541fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 4641fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 4741fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 4841fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 4941fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 5041fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 5141fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 5241fd4caeSFaiz Abbas #define PDB_SHIFT 0 5341fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 5441fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 5541fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 5641fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 5741fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 5841fd4caeSFaiz Abbas 5941fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 6041fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 6141fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 6241fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 6341fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 6441fd4caeSFaiz Abbas 6541fd4caeSFaiz Abbas #define CLOCK_TOO_SLOW_HZ 400000 6641fd4caeSFaiz Abbas 6741fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 6841fd4caeSFaiz Abbas .reg_bits = 32, 6941fd4caeSFaiz Abbas .val_bits = 32, 7041fd4caeSFaiz Abbas .reg_stride = 4, 7141fd4caeSFaiz Abbas .fast_io = true, 7241fd4caeSFaiz Abbas }; 7341fd4caeSFaiz Abbas 7441fd4caeSFaiz Abbas struct sdhci_am654_data { 7541fd4caeSFaiz Abbas struct regmap *base; 7641fd4caeSFaiz Abbas int otap_del_sel; 7741fd4caeSFaiz Abbas int trm_icp; 7841fd4caeSFaiz Abbas int drv_strength; 7941fd4caeSFaiz Abbas bool dll_on; 8041fd4caeSFaiz Abbas }; 8141fd4caeSFaiz Abbas 8241fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 8341fd4caeSFaiz Abbas { 8441fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 8541fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 8641fd4caeSFaiz Abbas int sel50, sel100; 8741fd4caeSFaiz Abbas u32 mask, val; 8841fd4caeSFaiz Abbas int ret; 8941fd4caeSFaiz Abbas 9041fd4caeSFaiz Abbas if (sdhci_am654->dll_on) { 918023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 9241fd4caeSFaiz Abbas 9341fd4caeSFaiz Abbas sdhci_am654->dll_on = false; 9441fd4caeSFaiz Abbas } 9541fd4caeSFaiz Abbas 9641fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 9741fd4caeSFaiz Abbas 9841fd4caeSFaiz Abbas if (clock > CLOCK_TOO_SLOW_HZ) { 9941fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 10041fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 10141fd4caeSFaiz Abbas val = (1 << OTAPDLYENA_SHIFT) | 10241fd4caeSFaiz Abbas (sdhci_am654->otap_del_sel << OTAPDLYSEL_SHIFT); 1038023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 10441fd4caeSFaiz Abbas switch (clock) { 10541fd4caeSFaiz Abbas case 200000000: 10641fd4caeSFaiz Abbas sel50 = 0; 10741fd4caeSFaiz Abbas sel100 = 0; 10841fd4caeSFaiz Abbas break; 10941fd4caeSFaiz Abbas case 100000000: 11041fd4caeSFaiz Abbas sel50 = 0; 11141fd4caeSFaiz Abbas sel100 = 1; 11241fd4caeSFaiz Abbas break; 11341fd4caeSFaiz Abbas default: 11441fd4caeSFaiz Abbas sel50 = 1; 11541fd4caeSFaiz Abbas sel100 = 0; 11641fd4caeSFaiz Abbas } 11741fd4caeSFaiz Abbas 11841fd4caeSFaiz Abbas /* Configure PHY DLL frequency */ 11941fd4caeSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 12041fd4caeSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 1218023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 12241fd4caeSFaiz Abbas /* Configure DLL TRIM */ 12341fd4caeSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 12441fd4caeSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 12541fd4caeSFaiz Abbas 12641fd4caeSFaiz Abbas /* Configure DLL driver strength */ 12741fd4caeSFaiz Abbas mask |= DR_TY_MASK; 12841fd4caeSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 1298023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 13041fd4caeSFaiz Abbas /* Enable DLL */ 1318023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 1328023cf26SFaiz Abbas 0x1 << ENDLL_SHIFT); 13341fd4caeSFaiz Abbas /* 13441fd4caeSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 13541fd4caeSFaiz Abbas * Works in all experiments done so far 13641fd4caeSFaiz Abbas */ 1378023cf26SFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 1388023cf26SFaiz Abbas val, val & DLLRDY_MASK, 1000, 1398023cf26SFaiz Abbas 1000000); 14041fd4caeSFaiz Abbas sdhci_am654->dll_on = true; 14141fd4caeSFaiz Abbas } 14241fd4caeSFaiz Abbas } 14341fd4caeSFaiz Abbas 14441fd4caeSFaiz Abbas static void sdhci_am654_set_power(struct sdhci_host *host, unsigned char mode, 14541fd4caeSFaiz Abbas unsigned short vdd) 14641fd4caeSFaiz Abbas { 14741fd4caeSFaiz Abbas if (!IS_ERR(host->mmc->supply.vmmc)) { 14841fd4caeSFaiz Abbas struct mmc_host *mmc = host->mmc; 14941fd4caeSFaiz Abbas 15041fd4caeSFaiz Abbas mmc_regulator_set_ocr(mmc, mmc->supply.vmmc, vdd); 15141fd4caeSFaiz Abbas } 15241fd4caeSFaiz Abbas sdhci_set_power_noreg(host, mode, vdd); 15341fd4caeSFaiz Abbas } 15441fd4caeSFaiz Abbas 155e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 156e374e875SFaiz Abbas { 157e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 158e374e875SFaiz Abbas 159e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 160e374e875SFaiz Abbas switch (timing) { 161e374e875SFaiz Abbas /* 162e374e875SFaiz Abbas * According to the data manual, HISPD bit 163e374e875SFaiz Abbas * should not be set in these speed modes. 164e374e875SFaiz Abbas */ 165e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 166e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 167e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR12: 168e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR25: 169e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 170e374e875SFaiz Abbas } 171e374e875SFaiz Abbas } 172e374e875SFaiz Abbas 173e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 174e374e875SFaiz Abbas } 175e374e875SFaiz Abbas 1764e47345aSWei Yongjun static struct sdhci_ops sdhci_am654_ops = { 17741fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 17841fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 17941fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 18041fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 18141fd4caeSFaiz Abbas .set_power = sdhci_am654_set_power, 18241fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 183e374e875SFaiz Abbas .write_b = sdhci_am654_write_b, 18441fd4caeSFaiz Abbas .reset = sdhci_reset, 18541fd4caeSFaiz Abbas }; 18641fd4caeSFaiz Abbas 18741fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 18841fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 18941fd4caeSFaiz Abbas .quirks = SDHCI_QUIRK_INVERTED_WRITE_PROTECT | 19041fd4caeSFaiz Abbas SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 19141fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 19241fd4caeSFaiz Abbas }; 19341fd4caeSFaiz Abbas 19441fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 19541fd4caeSFaiz Abbas { 19641fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 19741fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 19841fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 19941fd4caeSFaiz Abbas u32 mask; 20041fd4caeSFaiz Abbas u32 val; 20141fd4caeSFaiz Abbas int ret; 20241fd4caeSFaiz Abbas 20341fd4caeSFaiz Abbas /* Reset OTAP to default value */ 20441fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2058023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 20641fd4caeSFaiz Abbas 20741fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 20841fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 20941fd4caeSFaiz Abbas /* Calibrate IO lines */ 21041fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 21141fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 21241fd4caeSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, 21341fd4caeSFaiz Abbas val, val & CALDONE_MASK, 1, 20); 21441fd4caeSFaiz Abbas if (ret) 21541fd4caeSFaiz Abbas return ret; 21641fd4caeSFaiz Abbas } 21741fd4caeSFaiz Abbas 21841fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 2198023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, IOMUX_ENABLE_MASK, 0); 22041fd4caeSFaiz Abbas 22141fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 22241fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 22341fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 22441fd4caeSFaiz Abbas 2258023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 2268023cf26SFaiz Abbas ctl_cfg_2); 22741fd4caeSFaiz Abbas 22841fd4caeSFaiz Abbas return sdhci_add_host(host); 22941fd4caeSFaiz Abbas } 23041fd4caeSFaiz Abbas 23141fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 23241fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 23341fd4caeSFaiz Abbas { 23441fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 23541fd4caeSFaiz Abbas int drv_strength; 23641fd4caeSFaiz Abbas int ret; 23741fd4caeSFaiz Abbas 23841fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 23941fd4caeSFaiz Abbas &sdhci_am654->trm_icp); 24041fd4caeSFaiz Abbas if (ret) 24141fd4caeSFaiz Abbas return ret; 24241fd4caeSFaiz Abbas 24341fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 24441fd4caeSFaiz Abbas &sdhci_am654->otap_del_sel); 24541fd4caeSFaiz Abbas if (ret) 24641fd4caeSFaiz Abbas return ret; 24741fd4caeSFaiz Abbas 24841fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 24941fd4caeSFaiz Abbas &drv_strength); 25041fd4caeSFaiz Abbas if (ret) 25141fd4caeSFaiz Abbas return ret; 25241fd4caeSFaiz Abbas 25341fd4caeSFaiz Abbas switch (drv_strength) { 25441fd4caeSFaiz Abbas case 50: 25541fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 25641fd4caeSFaiz Abbas break; 25741fd4caeSFaiz Abbas case 33: 25841fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 25941fd4caeSFaiz Abbas break; 26041fd4caeSFaiz Abbas case 66: 26141fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 26241fd4caeSFaiz Abbas break; 26341fd4caeSFaiz Abbas case 100: 26441fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 26541fd4caeSFaiz Abbas break; 26641fd4caeSFaiz Abbas case 40: 26741fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 26841fd4caeSFaiz Abbas break; 26941fd4caeSFaiz Abbas default: 27041fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 27141fd4caeSFaiz Abbas return -EINVAL; 27241fd4caeSFaiz Abbas } 27341fd4caeSFaiz Abbas 27441fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 27541fd4caeSFaiz Abbas 27641fd4caeSFaiz Abbas return 0; 27741fd4caeSFaiz Abbas } 27841fd4caeSFaiz Abbas 27941fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 28041fd4caeSFaiz Abbas { 28141fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 28241fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 28341fd4caeSFaiz Abbas struct sdhci_host *host; 28441fd4caeSFaiz Abbas struct resource *res; 28541fd4caeSFaiz Abbas struct clk *clk_xin; 28641fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 28741fd4caeSFaiz Abbas void __iomem *base; 28841fd4caeSFaiz Abbas int ret; 28941fd4caeSFaiz Abbas 29041fd4caeSFaiz Abbas host = sdhci_pltfm_init(pdev, &sdhci_am654_pdata, sizeof(*sdhci_am654)); 29141fd4caeSFaiz Abbas if (IS_ERR(host)) 29241fd4caeSFaiz Abbas return PTR_ERR(host); 29341fd4caeSFaiz Abbas 29441fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 29541fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 29641fd4caeSFaiz Abbas 29741fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 29841fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 29941fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 30041fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 30141fd4caeSFaiz Abbas goto err_pltfm_free; 30241fd4caeSFaiz Abbas } 30341fd4caeSFaiz Abbas 30441fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 30541fd4caeSFaiz Abbas 30641fd4caeSFaiz Abbas /* Clocks are enabled using pm_runtime */ 30741fd4caeSFaiz Abbas pm_runtime_enable(dev); 30841fd4caeSFaiz Abbas ret = pm_runtime_get_sync(dev); 30941fd4caeSFaiz Abbas if (ret < 0) { 31041fd4caeSFaiz Abbas pm_runtime_put_noidle(dev); 31141fd4caeSFaiz Abbas goto pm_runtime_disable; 31241fd4caeSFaiz Abbas } 31341fd4caeSFaiz Abbas 31441fd4caeSFaiz Abbas res = platform_get_resource(pdev, IORESOURCE_MEM, 1); 31541fd4caeSFaiz Abbas base = devm_ioremap_resource(dev, res); 31641fd4caeSFaiz Abbas if (IS_ERR(base)) { 31741fd4caeSFaiz Abbas ret = PTR_ERR(base); 31841fd4caeSFaiz Abbas goto pm_runtime_put; 31941fd4caeSFaiz Abbas } 32041fd4caeSFaiz Abbas 32141fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 32241fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 32341fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 32441fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 32541fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 32641fd4caeSFaiz Abbas goto pm_runtime_put; 32741fd4caeSFaiz Abbas } 32841fd4caeSFaiz Abbas 32941fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 33041fd4caeSFaiz Abbas if (ret) 33141fd4caeSFaiz Abbas goto pm_runtime_put; 33241fd4caeSFaiz Abbas 33341fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 33441fd4caeSFaiz Abbas if (ret) { 33541fd4caeSFaiz Abbas dev_err(dev, "parsing dt failed (%d)\n", ret); 33641fd4caeSFaiz Abbas goto pm_runtime_put; 33741fd4caeSFaiz Abbas } 33841fd4caeSFaiz Abbas 33941fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 34041fd4caeSFaiz Abbas if (ret) 34141fd4caeSFaiz Abbas goto pm_runtime_put; 34241fd4caeSFaiz Abbas 34341fd4caeSFaiz Abbas return 0; 34441fd4caeSFaiz Abbas 34541fd4caeSFaiz Abbas pm_runtime_put: 34641fd4caeSFaiz Abbas pm_runtime_put_sync(dev); 34741fd4caeSFaiz Abbas pm_runtime_disable: 34841fd4caeSFaiz Abbas pm_runtime_disable(dev); 34941fd4caeSFaiz Abbas err_pltfm_free: 35041fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 35141fd4caeSFaiz Abbas return ret; 35241fd4caeSFaiz Abbas } 35341fd4caeSFaiz Abbas 35441fd4caeSFaiz Abbas static int sdhci_am654_remove(struct platform_device *pdev) 35541fd4caeSFaiz Abbas { 35641fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 35741fd4caeSFaiz Abbas int ret; 35841fd4caeSFaiz Abbas 35941fd4caeSFaiz Abbas sdhci_remove_host(host, true); 36041fd4caeSFaiz Abbas ret = pm_runtime_put_sync(&pdev->dev); 36141fd4caeSFaiz Abbas if (ret < 0) 36241fd4caeSFaiz Abbas return ret; 36341fd4caeSFaiz Abbas 36441fd4caeSFaiz Abbas pm_runtime_disable(&pdev->dev); 36541fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 36641fd4caeSFaiz Abbas 36741fd4caeSFaiz Abbas return 0; 36841fd4caeSFaiz Abbas } 36941fd4caeSFaiz Abbas 37041fd4caeSFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 37141fd4caeSFaiz Abbas { .compatible = "ti,am654-sdhci-5.1" }, 37241fd4caeSFaiz Abbas { /* sentinel */ } 37341fd4caeSFaiz Abbas }; 37441fd4caeSFaiz Abbas 37541fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 37641fd4caeSFaiz Abbas .driver = { 37741fd4caeSFaiz Abbas .name = "sdhci-am654", 37841fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 37941fd4caeSFaiz Abbas }, 38041fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 38141fd4caeSFaiz Abbas .remove = sdhci_am654_remove, 38241fd4caeSFaiz Abbas }; 38341fd4caeSFaiz Abbas 38441fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 38541fd4caeSFaiz Abbas 38641fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 38741fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 38841fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 389