141fd4caeSFaiz Abbas // SPDX-License-Identifier: GPL-2.0 241fd4caeSFaiz Abbas /* 341fd4caeSFaiz Abbas * sdhci_am654.c - SDHCI driver for TI's AM654 SOCs 441fd4caeSFaiz Abbas * 59481b45cSAlexander A. Klimov * Copyright (C) 2018 Texas Instruments Incorporated - https://www.ti.com 641fd4caeSFaiz Abbas * 741fd4caeSFaiz Abbas */ 841fd4caeSFaiz Abbas #include <linux/clk.h> 97ca0f166SFaiz Abbas #include <linux/iopoll.h> 1099909b55SFaiz Abbas #include <linux/of.h> 1141fd4caeSFaiz Abbas #include <linux/module.h> 1241fd4caeSFaiz Abbas #include <linux/pm_runtime.h> 1341fd4caeSFaiz Abbas #include <linux/property.h> 1441fd4caeSFaiz Abbas #include <linux/regmap.h> 1509db9943SFaiz Abbas #include <linux/sys_soc.h> 1641fd4caeSFaiz Abbas 17f545702bSFaiz Abbas #include "cqhci.h" 1841fd4caeSFaiz Abbas #include "sdhci-pltfm.h" 1941fd4caeSFaiz Abbas 2041fd4caeSFaiz Abbas /* CTL_CFG Registers */ 2141fd4caeSFaiz Abbas #define CTL_CFG_2 0x14 2241fd4caeSFaiz Abbas 2341fd4caeSFaiz Abbas #define SLOTTYPE_MASK GENMASK(31, 30) 2441fd4caeSFaiz Abbas #define SLOTTYPE_EMBEDDED BIT(30) 2541fd4caeSFaiz Abbas 2641fd4caeSFaiz Abbas /* PHY Registers */ 2741fd4caeSFaiz Abbas #define PHY_CTRL1 0x100 2841fd4caeSFaiz Abbas #define PHY_CTRL2 0x104 2941fd4caeSFaiz Abbas #define PHY_CTRL3 0x108 3041fd4caeSFaiz Abbas #define PHY_CTRL4 0x10C 3141fd4caeSFaiz Abbas #define PHY_CTRL5 0x110 3241fd4caeSFaiz Abbas #define PHY_CTRL6 0x114 3341fd4caeSFaiz Abbas #define PHY_STAT1 0x130 3441fd4caeSFaiz Abbas #define PHY_STAT2 0x134 3541fd4caeSFaiz Abbas 3641fd4caeSFaiz Abbas #define IOMUX_ENABLE_SHIFT 31 3741fd4caeSFaiz Abbas #define IOMUX_ENABLE_MASK BIT(IOMUX_ENABLE_SHIFT) 3841fd4caeSFaiz Abbas #define OTAPDLYENA_SHIFT 20 3941fd4caeSFaiz Abbas #define OTAPDLYENA_MASK BIT(OTAPDLYENA_SHIFT) 4041fd4caeSFaiz Abbas #define OTAPDLYSEL_SHIFT 12 4141fd4caeSFaiz Abbas #define OTAPDLYSEL_MASK GENMASK(15, 12) 4241fd4caeSFaiz Abbas #define STRBSEL_SHIFT 24 4399909b55SFaiz Abbas #define STRBSEL_4BIT_MASK GENMASK(27, 24) 4499909b55SFaiz Abbas #define STRBSEL_8BIT_MASK GENMASK(31, 24) 4541fd4caeSFaiz Abbas #define SEL50_SHIFT 8 4641fd4caeSFaiz Abbas #define SEL50_MASK BIT(SEL50_SHIFT) 4741fd4caeSFaiz Abbas #define SEL100_SHIFT 9 4841fd4caeSFaiz Abbas #define SEL100_MASK BIT(SEL100_SHIFT) 4999909b55SFaiz Abbas #define FREQSEL_SHIFT 8 5099909b55SFaiz Abbas #define FREQSEL_MASK GENMASK(10, 8) 5161d9c4aaSFaiz Abbas #define CLKBUFSEL_SHIFT 0 5261d9c4aaSFaiz Abbas #define CLKBUFSEL_MASK GENMASK(2, 0) 5341fd4caeSFaiz Abbas #define DLL_TRIM_ICP_SHIFT 4 5441fd4caeSFaiz Abbas #define DLL_TRIM_ICP_MASK GENMASK(7, 4) 5541fd4caeSFaiz Abbas #define DR_TY_SHIFT 20 5641fd4caeSFaiz Abbas #define DR_TY_MASK GENMASK(22, 20) 5741fd4caeSFaiz Abbas #define ENDLL_SHIFT 1 5841fd4caeSFaiz Abbas #define ENDLL_MASK BIT(ENDLL_SHIFT) 5941fd4caeSFaiz Abbas #define DLLRDY_SHIFT 0 6041fd4caeSFaiz Abbas #define DLLRDY_MASK BIT(DLLRDY_SHIFT) 6141fd4caeSFaiz Abbas #define PDB_SHIFT 0 6241fd4caeSFaiz Abbas #define PDB_MASK BIT(PDB_SHIFT) 6341fd4caeSFaiz Abbas #define CALDONE_SHIFT 1 6441fd4caeSFaiz Abbas #define CALDONE_MASK BIT(CALDONE_SHIFT) 6541fd4caeSFaiz Abbas #define RETRIM_SHIFT 17 6641fd4caeSFaiz Abbas #define RETRIM_MASK BIT(RETRIM_SHIFT) 670003417dSFaiz Abbas #define SELDLYTXCLK_SHIFT 17 680003417dSFaiz Abbas #define SELDLYTXCLK_MASK BIT(SELDLYTXCLK_SHIFT) 6941fd4caeSFaiz Abbas 7041fd4caeSFaiz Abbas #define DRIVER_STRENGTH_50_OHM 0x0 7141fd4caeSFaiz Abbas #define DRIVER_STRENGTH_33_OHM 0x1 7241fd4caeSFaiz Abbas #define DRIVER_STRENGTH_66_OHM 0x2 7341fd4caeSFaiz Abbas #define DRIVER_STRENGTH_100_OHM 0x3 7441fd4caeSFaiz Abbas #define DRIVER_STRENGTH_40_OHM 0x4 7541fd4caeSFaiz Abbas 7641fd4caeSFaiz Abbas #define CLOCK_TOO_SLOW_HZ 400000 7741fd4caeSFaiz Abbas 78f545702bSFaiz Abbas /* Command Queue Host Controller Interface Base address */ 79f545702bSFaiz Abbas #define SDHCI_AM654_CQE_BASE_ADDR 0x200 80f545702bSFaiz Abbas 8141fd4caeSFaiz Abbas static struct regmap_config sdhci_am654_regmap_config = { 8241fd4caeSFaiz Abbas .reg_bits = 32, 8341fd4caeSFaiz Abbas .val_bits = 32, 8441fd4caeSFaiz Abbas .reg_stride = 4, 8541fd4caeSFaiz Abbas .fast_io = true, 8641fd4caeSFaiz Abbas }; 8741fd4caeSFaiz Abbas 8841fd4caeSFaiz Abbas struct sdhci_am654_data { 8941fd4caeSFaiz Abbas struct regmap *base; 908ee5fc0eSFaiz Abbas bool legacy_otapdly; 918ee5fc0eSFaiz Abbas int otap_del_sel[11]; 9261d9c4aaSFaiz Abbas int clkbuf_sel; 9341fd4caeSFaiz Abbas int trm_icp; 9441fd4caeSFaiz Abbas int drv_strength; 9541fd4caeSFaiz Abbas bool dll_on; 9699909b55SFaiz Abbas int strb_sel; 9799909b55SFaiz Abbas u32 flags; 9899909b55SFaiz Abbas }; 9999909b55SFaiz Abbas 10099909b55SFaiz Abbas struct sdhci_am654_driver_data { 10199909b55SFaiz Abbas const struct sdhci_pltfm_data *pdata; 10299909b55SFaiz Abbas u32 flags; 10399909b55SFaiz Abbas #define IOMUX_PRESENT (1 << 0) 10499909b55SFaiz Abbas #define FREQSEL_2_BIT (1 << 1) 10599909b55SFaiz Abbas #define STRBSEL_4_BIT (1 << 2) 1061accbcedSFaiz Abbas #define DLL_PRESENT (1 << 3) 10723514731SFaiz Abbas #define DLL_CALIB (1 << 4) 10841fd4caeSFaiz Abbas }; 10941fd4caeSFaiz Abbas 1108ee5fc0eSFaiz Abbas struct timing_data { 1118ee5fc0eSFaiz Abbas const char *binding; 1128ee5fc0eSFaiz Abbas u32 capability; 1138ee5fc0eSFaiz Abbas }; 1148ee5fc0eSFaiz Abbas 1158ee5fc0eSFaiz Abbas static const struct timing_data td[] = { 1168ee5fc0eSFaiz Abbas [MMC_TIMING_LEGACY] = {"ti,otap-del-sel-legacy", 0}, 1178ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_HS] = {"ti,otap-del-sel-mmc-hs", MMC_CAP_MMC_HIGHSPEED}, 1188ee5fc0eSFaiz Abbas [MMC_TIMING_SD_HS] = {"ti,otap-del-sel-sd-hs", MMC_CAP_SD_HIGHSPEED}, 1198ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR12] = {"ti,otap-del-sel-sdr12", MMC_CAP_UHS_SDR12}, 1208ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR25] = {"ti,otap-del-sel-sdr25", MMC_CAP_UHS_SDR25}, 1218ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR50] = {"ti,otap-del-sel-sdr50", MMC_CAP_UHS_SDR50}, 1228ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_SDR104] = {"ti,otap-del-sel-sdr104", 1238ee5fc0eSFaiz Abbas MMC_CAP_UHS_SDR104}, 1248ee5fc0eSFaiz Abbas [MMC_TIMING_UHS_DDR50] = {"ti,otap-del-sel-ddr50", MMC_CAP_UHS_DDR50}, 1258ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_DDR52] = {"ti,otap-del-sel-ddr52", MMC_CAP_DDR}, 1268ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_HS200] = {"ti,otap-del-sel-hs200", MMC_CAP2_HS200}, 1278ee5fc0eSFaiz Abbas [MMC_TIMING_MMC_HS400] = {"ti,otap-del-sel-hs400", MMC_CAP2_HS400}, 1288ee5fc0eSFaiz Abbas }; 1298ee5fc0eSFaiz Abbas 130a161c45fSFaiz Abbas static void sdhci_am654_setup_dll(struct sdhci_host *host, unsigned int clock) 131a161c45fSFaiz Abbas { 132a161c45fSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 133a161c45fSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 134a161c45fSFaiz Abbas int sel50, sel100, freqsel; 135a161c45fSFaiz Abbas u32 mask, val; 136a161c45fSFaiz Abbas int ret; 137a161c45fSFaiz Abbas 138a161c45fSFaiz Abbas if (sdhci_am654->flags & FREQSEL_2_BIT) { 139a161c45fSFaiz Abbas switch (clock) { 140a161c45fSFaiz Abbas case 200000000: 141a161c45fSFaiz Abbas sel50 = 0; 142a161c45fSFaiz Abbas sel100 = 0; 143a161c45fSFaiz Abbas break; 144a161c45fSFaiz Abbas case 100000000: 145a161c45fSFaiz Abbas sel50 = 0; 146a161c45fSFaiz Abbas sel100 = 1; 147a161c45fSFaiz Abbas break; 148a161c45fSFaiz Abbas default: 149a161c45fSFaiz Abbas sel50 = 1; 150a161c45fSFaiz Abbas sel100 = 0; 151a161c45fSFaiz Abbas } 152a161c45fSFaiz Abbas 153a161c45fSFaiz Abbas /* Configure PHY DLL frequency */ 154a161c45fSFaiz Abbas mask = SEL50_MASK | SEL100_MASK; 155a161c45fSFaiz Abbas val = (sel50 << SEL50_SHIFT) | (sel100 << SEL100_SHIFT); 156a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, mask, val); 157a161c45fSFaiz Abbas 158a161c45fSFaiz Abbas } else { 159a161c45fSFaiz Abbas switch (clock) { 160a161c45fSFaiz Abbas case 200000000: 161a161c45fSFaiz Abbas freqsel = 0x0; 162a161c45fSFaiz Abbas break; 163a161c45fSFaiz Abbas default: 164a161c45fSFaiz Abbas freqsel = 0x4; 165a161c45fSFaiz Abbas } 166a161c45fSFaiz Abbas 167a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, FREQSEL_MASK, 168a161c45fSFaiz Abbas freqsel << FREQSEL_SHIFT); 169a161c45fSFaiz Abbas } 170a161c45fSFaiz Abbas /* Configure DLL TRIM */ 171a161c45fSFaiz Abbas mask = DLL_TRIM_ICP_MASK; 172a161c45fSFaiz Abbas val = sdhci_am654->trm_icp << DLL_TRIM_ICP_SHIFT; 173a161c45fSFaiz Abbas 174a161c45fSFaiz Abbas /* Configure DLL driver strength */ 175a161c45fSFaiz Abbas mask |= DR_TY_MASK; 176a161c45fSFaiz Abbas val |= sdhci_am654->drv_strength << DR_TY_SHIFT; 177a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, mask, val); 178a161c45fSFaiz Abbas 179a161c45fSFaiz Abbas /* Enable DLL */ 180a161c45fSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 181a161c45fSFaiz Abbas 0x1 << ENDLL_SHIFT); 182a161c45fSFaiz Abbas /* 183a161c45fSFaiz Abbas * Poll for DLL ready. Use a one second timeout. 184a161c45fSFaiz Abbas * Works in all experiments done so far 185a161c45fSFaiz Abbas */ 186a161c45fSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, PHY_STAT1, val, 187a161c45fSFaiz Abbas val & DLLRDY_MASK, 1000, 1000000); 188a161c45fSFaiz Abbas if (ret) { 189a161c45fSFaiz Abbas dev_err(mmc_dev(host->mmc), "DLL failed to relock\n"); 190a161c45fSFaiz Abbas return; 191a161c45fSFaiz Abbas } 192a161c45fSFaiz Abbas 193a161c45fSFaiz Abbas sdhci_am654->dll_on = true; 194a161c45fSFaiz Abbas } 195a161c45fSFaiz Abbas 19641fd4caeSFaiz Abbas static void sdhci_am654_set_clock(struct sdhci_host *host, unsigned int clock) 19741fd4caeSFaiz Abbas { 19841fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 19941fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2008ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2018ee5fc0eSFaiz Abbas u32 otap_del_sel; 2028ee5fc0eSFaiz Abbas u32 otap_del_ena; 20341fd4caeSFaiz Abbas u32 mask, val; 20441fd4caeSFaiz Abbas 20541fd4caeSFaiz Abbas if (sdhci_am654->dll_on) { 2068023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, ENDLL_MASK, 0); 20741fd4caeSFaiz Abbas 20841fd4caeSFaiz Abbas sdhci_am654->dll_on = false; 20941fd4caeSFaiz Abbas } 21041fd4caeSFaiz Abbas 21141fd4caeSFaiz Abbas sdhci_set_clock(host, clock); 21241fd4caeSFaiz Abbas 21341fd4caeSFaiz Abbas /* Setup DLL Output TAP delay */ 2148ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 2158ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 21699909b55SFaiz Abbas else 2178ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 21899909b55SFaiz Abbas 2198ee5fc0eSFaiz Abbas otap_del_ena = (timing > MMC_TIMING_UHS_SDR25) ? 1 : 0; 2208ee5fc0eSFaiz Abbas 2218ee5fc0eSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2228ee5fc0eSFaiz Abbas val = (otap_del_ena << OTAPDLYENA_SHIFT) | 2238ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2248ee5fc0eSFaiz Abbas 2258ee5fc0eSFaiz Abbas /* Write to STRBSEL for HS400 speed mode */ 2268ee5fc0eSFaiz Abbas if (timing == MMC_TIMING_MMC_HS400) { 2278ee5fc0eSFaiz Abbas if (sdhci_am654->flags & STRBSEL_4_BIT) 2288ee5fc0eSFaiz Abbas mask |= STRBSEL_4BIT_MASK; 2298ee5fc0eSFaiz Abbas else 2308ee5fc0eSFaiz Abbas mask |= STRBSEL_8BIT_MASK; 2318ee5fc0eSFaiz Abbas 2328ee5fc0eSFaiz Abbas val |= sdhci_am654->strb_sel << STRBSEL_SHIFT; 23399909b55SFaiz Abbas } 23499909b55SFaiz Abbas 2358ee5fc0eSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2368ee5fc0eSFaiz Abbas 2370003417dSFaiz Abbas if (timing > MMC_TIMING_UHS_SDR25 && clock > CLOCK_TOO_SLOW_HZ) { 2380003417dSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 2390003417dSFaiz Abbas SELDLYTXCLK_MASK, 0); 240a161c45fSFaiz Abbas sdhci_am654_setup_dll(host, clock); 2410003417dSFaiz Abbas } else { 2420003417dSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, 2430003417dSFaiz Abbas SELDLYTXCLK_MASK, 1 << SELDLYTXCLK_SHIFT); 2440003417dSFaiz Abbas } 24561d9c4aaSFaiz Abbas 24661d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 24761d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 24841fd4caeSFaiz Abbas } 24941fd4caeSFaiz Abbas 2508751c8bdSYueHaibing static void sdhci_j721e_4bit_set_clock(struct sdhci_host *host, 2518751c8bdSYueHaibing unsigned int clock) 2521accbcedSFaiz Abbas { 2531accbcedSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 2541accbcedSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 2558ee5fc0eSFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2568ee5fc0eSFaiz Abbas u32 otap_del_sel; 2578ee5fc0eSFaiz Abbas u32 mask, val; 2588ee5fc0eSFaiz Abbas 2598ee5fc0eSFaiz Abbas /* Setup DLL Output TAP delay */ 2608ee5fc0eSFaiz Abbas if (sdhci_am654->legacy_otapdly) 2618ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[0]; 2628ee5fc0eSFaiz Abbas else 2638ee5fc0eSFaiz Abbas otap_del_sel = sdhci_am654->otap_del_sel[timing]; 2641accbcedSFaiz Abbas 2651accbcedSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 2668ee5fc0eSFaiz Abbas val = (0x1 << OTAPDLYENA_SHIFT) | 2678ee5fc0eSFaiz Abbas (otap_del_sel << OTAPDLYSEL_SHIFT); 2681accbcedSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, val); 2691accbcedSFaiz Abbas 27061d9c4aaSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL5, CLKBUFSEL_MASK, 27161d9c4aaSFaiz Abbas sdhci_am654->clkbuf_sel); 27261d9c4aaSFaiz Abbas 2731accbcedSFaiz Abbas sdhci_set_clock(host, clock); 2741accbcedSFaiz Abbas } 2751accbcedSFaiz Abbas 2767ca0f166SFaiz Abbas static u8 sdhci_am654_write_power_on(struct sdhci_host *host, u8 val, int reg) 2777ca0f166SFaiz Abbas { 2787ca0f166SFaiz Abbas writeb(val, host->ioaddr + reg); 2797ca0f166SFaiz Abbas usleep_range(1000, 10000); 2807ca0f166SFaiz Abbas return readb(host->ioaddr + reg); 2817ca0f166SFaiz Abbas } 2827ca0f166SFaiz Abbas 2837ca0f166SFaiz Abbas #define MAX_POWER_ON_TIMEOUT 1500000 /* us */ 284e374e875SFaiz Abbas static void sdhci_am654_write_b(struct sdhci_host *host, u8 val, int reg) 285e374e875SFaiz Abbas { 286e374e875SFaiz Abbas unsigned char timing = host->mmc->ios.timing; 2877ca0f166SFaiz Abbas u8 pwr; 2887ca0f166SFaiz Abbas int ret; 289e374e875SFaiz Abbas 290e374e875SFaiz Abbas if (reg == SDHCI_HOST_CONTROL) { 291e374e875SFaiz Abbas switch (timing) { 292e374e875SFaiz Abbas /* 293e374e875SFaiz Abbas * According to the data manual, HISPD bit 294e374e875SFaiz Abbas * should not be set in these speed modes. 295e374e875SFaiz Abbas */ 296e374e875SFaiz Abbas case MMC_TIMING_SD_HS: 297e374e875SFaiz Abbas case MMC_TIMING_MMC_HS: 298e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR12: 299e374e875SFaiz Abbas case MMC_TIMING_UHS_SDR25: 300e374e875SFaiz Abbas val &= ~SDHCI_CTRL_HISPD; 301e374e875SFaiz Abbas } 302e374e875SFaiz Abbas } 303e374e875SFaiz Abbas 304e374e875SFaiz Abbas writeb(val, host->ioaddr + reg); 3057ca0f166SFaiz Abbas if (reg == SDHCI_POWER_CONTROL && (val & SDHCI_POWER_ON)) { 3067ca0f166SFaiz Abbas /* 3077ca0f166SFaiz Abbas * Power on will not happen until the card detect debounce 3087ca0f166SFaiz Abbas * timer expires. Wait at least 1.5 seconds for the power on 3097ca0f166SFaiz Abbas * bit to be set 3107ca0f166SFaiz Abbas */ 3117ca0f166SFaiz Abbas ret = read_poll_timeout(sdhci_am654_write_power_on, pwr, 3127ca0f166SFaiz Abbas pwr & SDHCI_POWER_ON, 0, 3137ca0f166SFaiz Abbas MAX_POWER_ON_TIMEOUT, false, host, val, 3147ca0f166SFaiz Abbas reg); 3157ca0f166SFaiz Abbas if (ret) 3167ca0f166SFaiz Abbas dev_warn(mmc_dev(host->mmc), "Power on failed\n"); 3177ca0f166SFaiz Abbas } 318e374e875SFaiz Abbas } 319e374e875SFaiz Abbas 320de31f6abSFaiz Abbas static int sdhci_am654_execute_tuning(struct mmc_host *mmc, u32 opcode) 321de31f6abSFaiz Abbas { 322de31f6abSFaiz Abbas struct sdhci_host *host = mmc_priv(mmc); 323de31f6abSFaiz Abbas int err = sdhci_execute_tuning(mmc, opcode); 32441fd4caeSFaiz Abbas 325de31f6abSFaiz Abbas if (err) 326de31f6abSFaiz Abbas return err; 327de31f6abSFaiz Abbas /* 328de31f6abSFaiz Abbas * Tuning data remains in the buffer after tuning. 329de31f6abSFaiz Abbas * Do a command and data reset to get rid of it 330de31f6abSFaiz Abbas */ 331de31f6abSFaiz Abbas sdhci_reset(host, SDHCI_RESET_CMD | SDHCI_RESET_DATA); 33241fd4caeSFaiz Abbas 333de31f6abSFaiz Abbas return 0; 334de31f6abSFaiz Abbas } 33599909b55SFaiz Abbas 336f545702bSFaiz Abbas static u32 sdhci_am654_cqhci_irq(struct sdhci_host *host, u32 intmask) 337f545702bSFaiz Abbas { 338f545702bSFaiz Abbas int cmd_error = 0; 339f545702bSFaiz Abbas int data_error = 0; 340f545702bSFaiz Abbas 341f545702bSFaiz Abbas if (!sdhci_cqe_irq(host, intmask, &cmd_error, &data_error)) 342f545702bSFaiz Abbas return intmask; 343f545702bSFaiz Abbas 344f545702bSFaiz Abbas cqhci_irq(host->mmc, intmask, cmd_error, data_error); 345f545702bSFaiz Abbas 346f545702bSFaiz Abbas return 0; 347f545702bSFaiz Abbas } 348f545702bSFaiz Abbas 34941fd4caeSFaiz Abbas static struct sdhci_ops sdhci_am654_ops = { 35041fd4caeSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 35141fd4caeSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 35241fd4caeSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 35341fd4caeSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 3549d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 35541fd4caeSFaiz Abbas .set_clock = sdhci_am654_set_clock, 35641fd4caeSFaiz Abbas .write_b = sdhci_am654_write_b, 35727f4e1e9SFaiz Abbas .irq = sdhci_am654_cqhci_irq, 35841fd4caeSFaiz Abbas .reset = sdhci_reset, 35941fd4caeSFaiz Abbas }; 36041fd4caeSFaiz Abbas 36141fd4caeSFaiz Abbas static const struct sdhci_pltfm_data sdhci_am654_pdata = { 36241fd4caeSFaiz Abbas .ops = &sdhci_am654_ops, 3634d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 36441fd4caeSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 36541fd4caeSFaiz Abbas }; 36641fd4caeSFaiz Abbas 36709db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_sr1_drvdata = { 36841fd4caeSFaiz Abbas .pdata = &sdhci_am654_pdata, 36923514731SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT | 37023514731SFaiz Abbas DLL_CALIB, 37141fd4caeSFaiz Abbas }; 37241fd4caeSFaiz Abbas 37309db9943SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_am654_drvdata = { 37409db9943SFaiz Abbas .pdata = &sdhci_am654_pdata, 37509db9943SFaiz Abbas .flags = IOMUX_PRESENT | FREQSEL_2_BIT | STRBSEL_4_BIT | DLL_PRESENT, 37609db9943SFaiz Abbas }; 37709db9943SFaiz Abbas 3788751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_8bit_ops = { 37999909b55SFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 38099909b55SFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 38199909b55SFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 38299909b55SFaiz Abbas .set_bus_width = sdhci_set_bus_width, 3839d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 38499909b55SFaiz Abbas .set_clock = sdhci_am654_set_clock, 38599909b55SFaiz Abbas .write_b = sdhci_am654_write_b, 386f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 38799909b55SFaiz Abbas .reset = sdhci_reset, 38899909b55SFaiz Abbas }; 38999909b55SFaiz Abbas 39099909b55SFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_8bit_pdata = { 39199909b55SFaiz Abbas .ops = &sdhci_j721e_8bit_ops, 3924d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 39399909b55SFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 39499909b55SFaiz Abbas }; 39599909b55SFaiz Abbas 39699909b55SFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_8bit_drvdata = { 39799909b55SFaiz Abbas .pdata = &sdhci_j721e_8bit_pdata, 39823514731SFaiz Abbas .flags = DLL_PRESENT | DLL_CALIB, 39999909b55SFaiz Abbas }; 40099909b55SFaiz Abbas 4018751c8bdSYueHaibing static struct sdhci_ops sdhci_j721e_4bit_ops = { 4021accbcedSFaiz Abbas .get_max_clock = sdhci_pltfm_clk_get_max_clock, 4031accbcedSFaiz Abbas .get_timeout_clock = sdhci_pltfm_clk_get_max_clock, 4041accbcedSFaiz Abbas .set_uhs_signaling = sdhci_set_uhs_signaling, 4051accbcedSFaiz Abbas .set_bus_width = sdhci_set_bus_width, 4069d8acdd3SNicolas Saenz Julienne .set_power = sdhci_set_power_and_bus_voltage, 4071accbcedSFaiz Abbas .set_clock = sdhci_j721e_4bit_set_clock, 4081accbcedSFaiz Abbas .write_b = sdhci_am654_write_b, 409f545702bSFaiz Abbas .irq = sdhci_am654_cqhci_irq, 4101accbcedSFaiz Abbas .reset = sdhci_reset, 4111accbcedSFaiz Abbas }; 4121accbcedSFaiz Abbas 4131accbcedSFaiz Abbas static const struct sdhci_pltfm_data sdhci_j721e_4bit_pdata = { 4141accbcedSFaiz Abbas .ops = &sdhci_j721e_4bit_ops, 4154d627c88SFaiz Abbas .quirks = SDHCI_QUIRK_MULTIBLOCK_READ_ACMD12, 4161accbcedSFaiz Abbas .quirks2 = SDHCI_QUIRK2_PRESET_VALUE_BROKEN, 4171accbcedSFaiz Abbas }; 4181accbcedSFaiz Abbas 4191accbcedSFaiz Abbas static const struct sdhci_am654_driver_data sdhci_j721e_4bit_drvdata = { 4201accbcedSFaiz Abbas .pdata = &sdhci_j721e_4bit_pdata, 4211accbcedSFaiz Abbas .flags = IOMUX_PRESENT, 4221accbcedSFaiz Abbas }; 423f545702bSFaiz Abbas 42409db9943SFaiz Abbas static const struct soc_device_attribute sdhci_am654_devices[] = { 42509db9943SFaiz Abbas { .family = "AM65X", 42609db9943SFaiz Abbas .revision = "SR1.0", 42709db9943SFaiz Abbas .data = &sdhci_am654_sr1_drvdata 42809db9943SFaiz Abbas }, 42909db9943SFaiz Abbas {/* sentinel */} 43009db9943SFaiz Abbas }; 43109db9943SFaiz Abbas 432f545702bSFaiz Abbas static void sdhci_am654_dumpregs(struct mmc_host *mmc) 433f545702bSFaiz Abbas { 434f545702bSFaiz Abbas sdhci_dumpregs(mmc_priv(mmc)); 435f545702bSFaiz Abbas } 436f545702bSFaiz Abbas 437f545702bSFaiz Abbas static const struct cqhci_host_ops sdhci_am654_cqhci_ops = { 438f545702bSFaiz Abbas .enable = sdhci_cqe_enable, 439f545702bSFaiz Abbas .disable = sdhci_cqe_disable, 440f545702bSFaiz Abbas .dumpregs = sdhci_am654_dumpregs, 441f545702bSFaiz Abbas }; 442f545702bSFaiz Abbas 443f545702bSFaiz Abbas static int sdhci_am654_cqe_add_host(struct sdhci_host *host) 444f545702bSFaiz Abbas { 445f545702bSFaiz Abbas struct cqhci_host *cq_host; 446f545702bSFaiz Abbas int ret; 447f545702bSFaiz Abbas 448f545702bSFaiz Abbas cq_host = devm_kzalloc(host->mmc->parent, sizeof(struct cqhci_host), 449f545702bSFaiz Abbas GFP_KERNEL); 450f545702bSFaiz Abbas if (!cq_host) 451f545702bSFaiz Abbas return -ENOMEM; 452f545702bSFaiz Abbas 453f545702bSFaiz Abbas cq_host->mmio = host->ioaddr + SDHCI_AM654_CQE_BASE_ADDR; 454f545702bSFaiz Abbas cq_host->quirks |= CQHCI_QUIRK_SHORT_TXFR_DESC_SZ; 455f545702bSFaiz Abbas cq_host->caps |= CQHCI_TASK_DESC_SZ_128; 456f545702bSFaiz Abbas cq_host->ops = &sdhci_am654_cqhci_ops; 457f545702bSFaiz Abbas 458f545702bSFaiz Abbas host->mmc->caps2 |= MMC_CAP2_CQE; 459f545702bSFaiz Abbas 460f545702bSFaiz Abbas ret = cqhci_init(cq_host, host->mmc, 1); 461f545702bSFaiz Abbas 462f545702bSFaiz Abbas return ret; 463f545702bSFaiz Abbas } 464f545702bSFaiz Abbas 4658ee5fc0eSFaiz Abbas static int sdhci_am654_get_otap_delay(struct sdhci_host *host, 4668ee5fc0eSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 4678ee5fc0eSFaiz Abbas { 4688ee5fc0eSFaiz Abbas struct device *dev = mmc_dev(host->mmc); 4698ee5fc0eSFaiz Abbas int i; 4708ee5fc0eSFaiz Abbas int ret; 4718ee5fc0eSFaiz Abbas 4728ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, td[MMC_TIMING_LEGACY].binding, 4738ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[MMC_TIMING_LEGACY]); 4748ee5fc0eSFaiz Abbas if (ret) { 4758ee5fc0eSFaiz Abbas /* 4768ee5fc0eSFaiz Abbas * ti,otap-del-sel-legacy is mandatory, look for old binding 4778ee5fc0eSFaiz Abbas * if not found. 4788ee5fc0eSFaiz Abbas */ 4798ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, "ti,otap-del-sel", 4808ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[0]); 4818ee5fc0eSFaiz Abbas if (ret) { 4828ee5fc0eSFaiz Abbas dev_err(dev, "Couldn't find otap-del-sel\n"); 4838ee5fc0eSFaiz Abbas 4848ee5fc0eSFaiz Abbas return ret; 4858ee5fc0eSFaiz Abbas } 4868ee5fc0eSFaiz Abbas 4878ee5fc0eSFaiz Abbas dev_info(dev, "Using legacy binding ti,otap-del-sel\n"); 4888ee5fc0eSFaiz Abbas sdhci_am654->legacy_otapdly = true; 4898ee5fc0eSFaiz Abbas 4908ee5fc0eSFaiz Abbas return 0; 4918ee5fc0eSFaiz Abbas } 4928ee5fc0eSFaiz Abbas 4938ee5fc0eSFaiz Abbas for (i = MMC_TIMING_MMC_HS; i <= MMC_TIMING_MMC_HS400; i++) { 4948ee5fc0eSFaiz Abbas 4958ee5fc0eSFaiz Abbas ret = device_property_read_u32(dev, td[i].binding, 4968ee5fc0eSFaiz Abbas &sdhci_am654->otap_del_sel[i]); 4978ee5fc0eSFaiz Abbas if (ret) { 4988ee5fc0eSFaiz Abbas dev_dbg(dev, "Couldn't find %s\n", 4998ee5fc0eSFaiz Abbas td[i].binding); 5008ee5fc0eSFaiz Abbas /* 5018ee5fc0eSFaiz Abbas * Remove the corresponding capability 5028ee5fc0eSFaiz Abbas * if an otap-del-sel value is not found 5038ee5fc0eSFaiz Abbas */ 5048ee5fc0eSFaiz Abbas if (i <= MMC_TIMING_MMC_DDR52) 5058ee5fc0eSFaiz Abbas host->mmc->caps &= ~td[i].capability; 5068ee5fc0eSFaiz Abbas else 5078ee5fc0eSFaiz Abbas host->mmc->caps2 &= ~td[i].capability; 5088ee5fc0eSFaiz Abbas } 5098ee5fc0eSFaiz Abbas } 5108ee5fc0eSFaiz Abbas 5118ee5fc0eSFaiz Abbas return 0; 5128ee5fc0eSFaiz Abbas } 5138ee5fc0eSFaiz Abbas 51441fd4caeSFaiz Abbas static int sdhci_am654_init(struct sdhci_host *host) 51541fd4caeSFaiz Abbas { 51641fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host); 51741fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 51841fd4caeSFaiz Abbas u32 ctl_cfg_2 = 0; 51941fd4caeSFaiz Abbas u32 mask; 52041fd4caeSFaiz Abbas u32 val; 52141fd4caeSFaiz Abbas int ret; 52241fd4caeSFaiz Abbas 52341fd4caeSFaiz Abbas /* Reset OTAP to default value */ 52441fd4caeSFaiz Abbas mask = OTAPDLYENA_MASK | OTAPDLYSEL_MASK; 5258023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL4, mask, 0x0); 52641fd4caeSFaiz Abbas 52723514731SFaiz Abbas if (sdhci_am654->flags & DLL_CALIB) { 52841fd4caeSFaiz Abbas regmap_read(sdhci_am654->base, PHY_STAT1, &val); 52941fd4caeSFaiz Abbas if (~val & CALDONE_MASK) { 53041fd4caeSFaiz Abbas /* Calibrate IO lines */ 53141fd4caeSFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 53241fd4caeSFaiz Abbas PDB_MASK, PDB_MASK); 5331accbcedSFaiz Abbas ret = regmap_read_poll_timeout(sdhci_am654->base, 5341accbcedSFaiz Abbas PHY_STAT1, val, 5351accbcedSFaiz Abbas val & CALDONE_MASK, 5361accbcedSFaiz Abbas 1, 20); 53741fd4caeSFaiz Abbas if (ret) 53841fd4caeSFaiz Abbas return ret; 53941fd4caeSFaiz Abbas } 5401accbcedSFaiz Abbas } 54141fd4caeSFaiz Abbas 54241fd4caeSFaiz Abbas /* Enable pins by setting IO mux to 0 */ 54399909b55SFaiz Abbas if (sdhci_am654->flags & IOMUX_PRESENT) 54499909b55SFaiz Abbas regmap_update_bits(sdhci_am654->base, PHY_CTRL1, 54599909b55SFaiz Abbas IOMUX_ENABLE_MASK, 0); 54641fd4caeSFaiz Abbas 54741fd4caeSFaiz Abbas /* Set slot type based on SD or eMMC */ 54841fd4caeSFaiz Abbas if (host->mmc->caps & MMC_CAP_NONREMOVABLE) 54941fd4caeSFaiz Abbas ctl_cfg_2 = SLOTTYPE_EMBEDDED; 55041fd4caeSFaiz Abbas 5518023cf26SFaiz Abbas regmap_update_bits(sdhci_am654->base, CTL_CFG_2, SLOTTYPE_MASK, 5528023cf26SFaiz Abbas ctl_cfg_2); 55341fd4caeSFaiz Abbas 554f545702bSFaiz Abbas ret = sdhci_setup_host(host); 555f545702bSFaiz Abbas if (ret) 556f545702bSFaiz Abbas return ret; 557f545702bSFaiz Abbas 558f545702bSFaiz Abbas ret = sdhci_am654_cqe_add_host(host); 559f545702bSFaiz Abbas if (ret) 560f545702bSFaiz Abbas goto err_cleanup_host; 561f545702bSFaiz Abbas 5628ee5fc0eSFaiz Abbas ret = sdhci_am654_get_otap_delay(host, sdhci_am654); 5638ee5fc0eSFaiz Abbas if (ret) 5648ee5fc0eSFaiz Abbas goto err_cleanup_host; 5658ee5fc0eSFaiz Abbas 566f545702bSFaiz Abbas ret = __sdhci_add_host(host); 567f545702bSFaiz Abbas if (ret) 568f545702bSFaiz Abbas goto err_cleanup_host; 569f545702bSFaiz Abbas 570f545702bSFaiz Abbas return 0; 571f545702bSFaiz Abbas 572f545702bSFaiz Abbas err_cleanup_host: 573f545702bSFaiz Abbas sdhci_cleanup_host(host); 574f545702bSFaiz Abbas return ret; 57541fd4caeSFaiz Abbas } 57641fd4caeSFaiz Abbas 57741fd4caeSFaiz Abbas static int sdhci_am654_get_of_property(struct platform_device *pdev, 57841fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654) 57941fd4caeSFaiz Abbas { 58041fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 58141fd4caeSFaiz Abbas int drv_strength; 58241fd4caeSFaiz Abbas int ret; 58341fd4caeSFaiz Abbas 5841accbcedSFaiz Abbas if (sdhci_am654->flags & DLL_PRESENT) { 5851accbcedSFaiz Abbas ret = device_property_read_u32(dev, "ti,trm-icp", 5861accbcedSFaiz Abbas &sdhci_am654->trm_icp); 58741fd4caeSFaiz Abbas if (ret) 58841fd4caeSFaiz Abbas return ret; 58941fd4caeSFaiz Abbas 59041fd4caeSFaiz Abbas ret = device_property_read_u32(dev, "ti,driver-strength-ohm", 59141fd4caeSFaiz Abbas &drv_strength); 59241fd4caeSFaiz Abbas if (ret) 59341fd4caeSFaiz Abbas return ret; 59441fd4caeSFaiz Abbas 59541fd4caeSFaiz Abbas switch (drv_strength) { 59641fd4caeSFaiz Abbas case 50: 59741fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_50_OHM; 59841fd4caeSFaiz Abbas break; 59941fd4caeSFaiz Abbas case 33: 60041fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_33_OHM; 60141fd4caeSFaiz Abbas break; 60241fd4caeSFaiz Abbas case 66: 60341fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_66_OHM; 60441fd4caeSFaiz Abbas break; 60541fd4caeSFaiz Abbas case 100: 60641fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_100_OHM; 60741fd4caeSFaiz Abbas break; 60841fd4caeSFaiz Abbas case 40: 60941fd4caeSFaiz Abbas sdhci_am654->drv_strength = DRIVER_STRENGTH_40_OHM; 61041fd4caeSFaiz Abbas break; 61141fd4caeSFaiz Abbas default: 61241fd4caeSFaiz Abbas dev_err(dev, "Invalid driver strength\n"); 61341fd4caeSFaiz Abbas return -EINVAL; 61441fd4caeSFaiz Abbas } 6151accbcedSFaiz Abbas } 61641fd4caeSFaiz Abbas 61799909b55SFaiz Abbas device_property_read_u32(dev, "ti,strobe-sel", &sdhci_am654->strb_sel); 61861d9c4aaSFaiz Abbas device_property_read_u32(dev, "ti,clkbuf-sel", 61961d9c4aaSFaiz Abbas &sdhci_am654->clkbuf_sel); 62099909b55SFaiz Abbas 62141fd4caeSFaiz Abbas sdhci_get_of_property(pdev); 62241fd4caeSFaiz Abbas 62341fd4caeSFaiz Abbas return 0; 62441fd4caeSFaiz Abbas } 62541fd4caeSFaiz Abbas 62699909b55SFaiz Abbas static const struct of_device_id sdhci_am654_of_match[] = { 62799909b55SFaiz Abbas { 62899909b55SFaiz Abbas .compatible = "ti,am654-sdhci-5.1", 62999909b55SFaiz Abbas .data = &sdhci_am654_drvdata, 63099909b55SFaiz Abbas }, 63199909b55SFaiz Abbas { 63299909b55SFaiz Abbas .compatible = "ti,j721e-sdhci-8bit", 63399909b55SFaiz Abbas .data = &sdhci_j721e_8bit_drvdata, 63499909b55SFaiz Abbas }, 6351accbcedSFaiz Abbas { 6361accbcedSFaiz Abbas .compatible = "ti,j721e-sdhci-4bit", 6371accbcedSFaiz Abbas .data = &sdhci_j721e_4bit_drvdata, 6381accbcedSFaiz Abbas }, 63999909b55SFaiz Abbas { /* sentinel */ } 64099909b55SFaiz Abbas }; 64199909b55SFaiz Abbas 64241fd4caeSFaiz Abbas static int sdhci_am654_probe(struct platform_device *pdev) 64341fd4caeSFaiz Abbas { 64499909b55SFaiz Abbas const struct sdhci_am654_driver_data *drvdata; 64509db9943SFaiz Abbas const struct soc_device_attribute *soc; 64641fd4caeSFaiz Abbas struct sdhci_pltfm_host *pltfm_host; 64741fd4caeSFaiz Abbas struct sdhci_am654_data *sdhci_am654; 64899909b55SFaiz Abbas const struct of_device_id *match; 64941fd4caeSFaiz Abbas struct sdhci_host *host; 65041fd4caeSFaiz Abbas struct clk *clk_xin; 65141fd4caeSFaiz Abbas struct device *dev = &pdev->dev; 65241fd4caeSFaiz Abbas void __iomem *base; 65341fd4caeSFaiz Abbas int ret; 65441fd4caeSFaiz Abbas 65599909b55SFaiz Abbas match = of_match_node(sdhci_am654_of_match, pdev->dev.of_node); 65699909b55SFaiz Abbas drvdata = match->data; 65709db9943SFaiz Abbas 65809db9943SFaiz Abbas /* Update drvdata based on SoC revision */ 65909db9943SFaiz Abbas soc = soc_device_match(sdhci_am654_devices); 66009db9943SFaiz Abbas if (soc && soc->data) 66109db9943SFaiz Abbas drvdata = soc->data; 66209db9943SFaiz Abbas 66399909b55SFaiz Abbas host = sdhci_pltfm_init(pdev, drvdata->pdata, sizeof(*sdhci_am654)); 66441fd4caeSFaiz Abbas if (IS_ERR(host)) 66541fd4caeSFaiz Abbas return PTR_ERR(host); 66641fd4caeSFaiz Abbas 66741fd4caeSFaiz Abbas pltfm_host = sdhci_priv(host); 66841fd4caeSFaiz Abbas sdhci_am654 = sdhci_pltfm_priv(pltfm_host); 66999909b55SFaiz Abbas sdhci_am654->flags = drvdata->flags; 67041fd4caeSFaiz Abbas 67141fd4caeSFaiz Abbas clk_xin = devm_clk_get(dev, "clk_xin"); 67241fd4caeSFaiz Abbas if (IS_ERR(clk_xin)) { 67341fd4caeSFaiz Abbas dev_err(dev, "clk_xin clock not found.\n"); 67441fd4caeSFaiz Abbas ret = PTR_ERR(clk_xin); 67541fd4caeSFaiz Abbas goto err_pltfm_free; 67641fd4caeSFaiz Abbas } 67741fd4caeSFaiz Abbas 67841fd4caeSFaiz Abbas pltfm_host->clk = clk_xin; 67941fd4caeSFaiz Abbas 68041fd4caeSFaiz Abbas /* Clocks are enabled using pm_runtime */ 68141fd4caeSFaiz Abbas pm_runtime_enable(dev); 68241fd4caeSFaiz Abbas ret = pm_runtime_get_sync(dev); 68341fd4caeSFaiz Abbas if (ret < 0) { 68441fd4caeSFaiz Abbas pm_runtime_put_noidle(dev); 68541fd4caeSFaiz Abbas goto pm_runtime_disable; 68641fd4caeSFaiz Abbas } 68741fd4caeSFaiz Abbas 6884942ae0eSYangtao Li base = devm_platform_ioremap_resource(pdev, 1); 68941fd4caeSFaiz Abbas if (IS_ERR(base)) { 69041fd4caeSFaiz Abbas ret = PTR_ERR(base); 69141fd4caeSFaiz Abbas goto pm_runtime_put; 69241fd4caeSFaiz Abbas } 69341fd4caeSFaiz Abbas 69441fd4caeSFaiz Abbas sdhci_am654->base = devm_regmap_init_mmio(dev, base, 69541fd4caeSFaiz Abbas &sdhci_am654_regmap_config); 69641fd4caeSFaiz Abbas if (IS_ERR(sdhci_am654->base)) { 69741fd4caeSFaiz Abbas dev_err(dev, "Failed to initialize regmap\n"); 69841fd4caeSFaiz Abbas ret = PTR_ERR(sdhci_am654->base); 69941fd4caeSFaiz Abbas goto pm_runtime_put; 70041fd4caeSFaiz Abbas } 70141fd4caeSFaiz Abbas 70241fd4caeSFaiz Abbas ret = sdhci_am654_get_of_property(pdev, sdhci_am654); 70341fd4caeSFaiz Abbas if (ret) 70441fd4caeSFaiz Abbas goto pm_runtime_put; 70541fd4caeSFaiz Abbas 70641fd4caeSFaiz Abbas ret = mmc_of_parse(host->mmc); 70741fd4caeSFaiz Abbas if (ret) { 70841fd4caeSFaiz Abbas dev_err(dev, "parsing dt failed (%d)\n", ret); 70941fd4caeSFaiz Abbas goto pm_runtime_put; 71041fd4caeSFaiz Abbas } 71141fd4caeSFaiz Abbas 712de31f6abSFaiz Abbas host->mmc_host_ops.execute_tuning = sdhci_am654_execute_tuning; 713de31f6abSFaiz Abbas 71441fd4caeSFaiz Abbas ret = sdhci_am654_init(host); 71541fd4caeSFaiz Abbas if (ret) 71641fd4caeSFaiz Abbas goto pm_runtime_put; 71741fd4caeSFaiz Abbas 71841fd4caeSFaiz Abbas return 0; 71941fd4caeSFaiz Abbas 72041fd4caeSFaiz Abbas pm_runtime_put: 72141fd4caeSFaiz Abbas pm_runtime_put_sync(dev); 72241fd4caeSFaiz Abbas pm_runtime_disable: 72341fd4caeSFaiz Abbas pm_runtime_disable(dev); 72441fd4caeSFaiz Abbas err_pltfm_free: 72541fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 72641fd4caeSFaiz Abbas return ret; 72741fd4caeSFaiz Abbas } 72841fd4caeSFaiz Abbas 72941fd4caeSFaiz Abbas static int sdhci_am654_remove(struct platform_device *pdev) 73041fd4caeSFaiz Abbas { 73141fd4caeSFaiz Abbas struct sdhci_host *host = platform_get_drvdata(pdev); 73241fd4caeSFaiz Abbas int ret; 73341fd4caeSFaiz Abbas 73441fd4caeSFaiz Abbas sdhci_remove_host(host, true); 73541fd4caeSFaiz Abbas ret = pm_runtime_put_sync(&pdev->dev); 73641fd4caeSFaiz Abbas if (ret < 0) 73741fd4caeSFaiz Abbas return ret; 73841fd4caeSFaiz Abbas 73941fd4caeSFaiz Abbas pm_runtime_disable(&pdev->dev); 74041fd4caeSFaiz Abbas sdhci_pltfm_free(pdev); 74141fd4caeSFaiz Abbas 74241fd4caeSFaiz Abbas return 0; 74341fd4caeSFaiz Abbas } 74441fd4caeSFaiz Abbas 74541fd4caeSFaiz Abbas static struct platform_driver sdhci_am654_driver = { 74641fd4caeSFaiz Abbas .driver = { 74741fd4caeSFaiz Abbas .name = "sdhci-am654", 74841fd4caeSFaiz Abbas .of_match_table = sdhci_am654_of_match, 74941fd4caeSFaiz Abbas }, 75041fd4caeSFaiz Abbas .probe = sdhci_am654_probe, 75141fd4caeSFaiz Abbas .remove = sdhci_am654_remove, 75241fd4caeSFaiz Abbas }; 75341fd4caeSFaiz Abbas 75441fd4caeSFaiz Abbas module_platform_driver(sdhci_am654_driver); 75541fd4caeSFaiz Abbas 75641fd4caeSFaiz Abbas MODULE_DESCRIPTION("Driver for SDHCI Controller on TI's AM654 devices"); 75741fd4caeSFaiz Abbas MODULE_AUTHOR("Faiz Abbas <faiz_abbas@ti.com>"); 75841fd4caeSFaiz Abbas MODULE_LICENSE("GPL"); 759